blob: 2db2db1235c70f05037edbf49dbcdebebf8ed48e [file] [log] [blame]
bellard420557e2004-09-30 22:13:50 +00001/*
bellard6f7e9ae2005-03-13 09:43:36 +00002 * QEMU TCX Frame buffer
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard6f7e9ae2005-03-13 09:43:36 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
ths5fafdf22007-09-16 21:08:06 +00005 *
bellard420557e2004-09-30 22:13:50 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Blue Swirlf40070c2009-07-12 19:21:36 +000024
pbrook87ecb682007-11-17 17:14:51 +000025#include "console.h"
blueswir194470842007-06-10 16:06:20 +000026#include "pixel_ops.h"
Blue Swirlf40070c2009-07-12 19:21:36 +000027#include "sysbus.h"
Gerd Hoffmannee6847d2009-07-15 13:43:31 +020028#include "qdev-addr.h"
bellard420557e2004-09-30 22:13:50 +000029
bellard420557e2004-09-30 22:13:50 +000030#define MAXX 1024
31#define MAXY 768
bellard6f7e9ae2005-03-13 09:43:36 +000032#define TCX_DAC_NREGS 16
blueswir18508b892007-05-06 17:39:55 +000033#define TCX_THC_NREGS_8 0x081c
34#define TCX_THC_NREGS_24 0x1000
35#define TCX_TEC_NREGS 0x1000
bellard420557e2004-09-30 22:13:50 +000036
bellard420557e2004-09-30 22:13:50 +000037typedef struct TCXState {
Blue Swirlf40070c2009-07-12 19:21:36 +000038 SysBusDevice busdev;
Anthony Liguoric227f092009-10-01 16:12:16 -050039 target_phys_addr_t addr;
bellard420557e2004-09-30 22:13:50 +000040 DisplayState *ds;
bellard8d5f07f2004-10-04 21:23:09 +000041 uint8_t *vram;
blueswir1eee0b832007-04-21 19:45:49 +000042 uint32_t *vram24, *cplane;
Avi Kivityd08151b2011-10-05 18:26:24 +020043 MemoryRegion vram_mem;
44 MemoryRegion vram_8bit;
45 MemoryRegion vram_24bit;
46 MemoryRegion vram_cplane;
47 MemoryRegion dac;
48 MemoryRegion tec;
49 MemoryRegion thc24;
50 MemoryRegion thc8;
51 ram_addr_t vram24_offset, cplane_offset;
Gerd Hoffmannee6847d2009-07-15 13:43:31 +020052 uint32_t vram_size;
bellard21206a12006-09-09 11:31:34 +000053 uint32_t palette[256];
Blue Swirl427a66c2011-08-07 19:13:24 +000054 uint8_t r[256], g[256], b[256];
55 uint16_t width, height, depth;
bellard6f7e9ae2005-03-13 09:43:36 +000056 uint8_t dac_index, dac_state;
bellard420557e2004-09-30 22:13:50 +000057} TCXState;
58
Luiz Capitulinod7098132012-05-21 16:41:37 -030059static void tcx_screen_dump(void *opaque, const char *filename, bool cswitch,
60 Error **errp);
61static void tcx24_screen_dump(void *opaque, const char *filename, bool cswitch,
62 Error **errp);
Blue Swirld3ffcaf2009-07-16 13:45:57 +000063
64static void tcx_set_dirty(TCXState *s)
65{
Blue Swirlfd4aa972011-10-16 16:04:59 +000066 memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY);
Blue Swirld3ffcaf2009-07-16 13:45:57 +000067}
68
69static void tcx24_set_dirty(TCXState *s)
70{
Blue Swirlfd4aa972011-10-16 16:04:59 +000071 memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4);
72 memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4);
Blue Swirld3ffcaf2009-07-16 13:45:57 +000073}
pbrook95219892006-04-09 01:06:34 +000074
bellard21206a12006-09-09 11:31:34 +000075static void update_palette_entries(TCXState *s, int start, int end)
76{
77 int i;
78 for(i = start; i < end; i++) {
aliguori0e1f5a02008-11-24 19:29:13 +000079 switch(ds_get_bits_per_pixel(s->ds)) {
bellard21206a12006-09-09 11:31:34 +000080 default:
81 case 8:
82 s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
83 break;
84 case 15:
aliguori8927bcf2009-01-15 22:07:16 +000085 s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
bellard21206a12006-09-09 11:31:34 +000086 break;
87 case 16:
aliguori8927bcf2009-01-15 22:07:16 +000088 s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
bellard21206a12006-09-09 11:31:34 +000089 break;
90 case 32:
aliguori7b5d76d2009-03-13 15:02:13 +000091 if (is_surface_bgr(s->ds->surface))
92 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
93 else
94 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
bellard21206a12006-09-09 11:31:34 +000095 break;
96 }
97 }
Blue Swirld3ffcaf2009-07-16 13:45:57 +000098 if (s->depth == 24) {
99 tcx24_set_dirty(s);
100 } else {
101 tcx_set_dirty(s);
102 }
bellard21206a12006-09-09 11:31:34 +0000103}
104
ths5fafdf22007-09-16 21:08:06 +0000105static void tcx_draw_line32(TCXState *s1, uint8_t *d,
blueswir1f930d072007-10-06 11:28:21 +0000106 const uint8_t *s, int width)
bellard420557e2004-09-30 22:13:50 +0000107{
bellarde80cfcf2004-12-19 23:18:01 +0000108 int x;
109 uint8_t val;
ths8bdc2152006-12-21 17:24:45 +0000110 uint32_t *p = (uint32_t *)d;
bellarde80cfcf2004-12-19 23:18:01 +0000111
112 for(x = 0; x < width; x++) {
blueswir1f930d072007-10-06 11:28:21 +0000113 val = *s++;
ths8bdc2152006-12-21 17:24:45 +0000114 *p++ = s1->palette[val];
bellarde80cfcf2004-12-19 23:18:01 +0000115 }
bellard420557e2004-09-30 22:13:50 +0000116}
117
ths5fafdf22007-09-16 21:08:06 +0000118static void tcx_draw_line16(TCXState *s1, uint8_t *d,
blueswir1f930d072007-10-06 11:28:21 +0000119 const uint8_t *s, int width)
bellarde80cfcf2004-12-19 23:18:01 +0000120{
121 int x;
122 uint8_t val;
ths8bdc2152006-12-21 17:24:45 +0000123 uint16_t *p = (uint16_t *)d;
bellard8d5f07f2004-10-04 21:23:09 +0000124
bellarde80cfcf2004-12-19 23:18:01 +0000125 for(x = 0; x < width; x++) {
blueswir1f930d072007-10-06 11:28:21 +0000126 val = *s++;
ths8bdc2152006-12-21 17:24:45 +0000127 *p++ = s1->palette[val];
bellarde80cfcf2004-12-19 23:18:01 +0000128 }
129}
130
ths5fafdf22007-09-16 21:08:06 +0000131static void tcx_draw_line8(TCXState *s1, uint8_t *d,
blueswir1f930d072007-10-06 11:28:21 +0000132 const uint8_t *s, int width)
bellarde80cfcf2004-12-19 23:18:01 +0000133{
134 int x;
135 uint8_t val;
136
137 for(x = 0; x < width; x++) {
blueswir1f930d072007-10-06 11:28:21 +0000138 val = *s++;
bellard21206a12006-09-09 11:31:34 +0000139 *d++ = s1->palette[val];
bellarde80cfcf2004-12-19 23:18:01 +0000140 }
141}
142
blueswir1688ea2e2008-07-24 11:26:38 +0000143/*
144 XXX Could be much more optimal:
145 * detect if line/page/whole screen is in 24 bit mode
146 * if destination is also BGR, use memcpy
147 */
blueswir1eee0b832007-04-21 19:45:49 +0000148static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
149 const uint8_t *s, int width,
150 const uint32_t *cplane,
151 const uint32_t *s24)
152{
aliguori7b5d76d2009-03-13 15:02:13 +0000153 int x, bgr, r, g, b;
blueswir1688ea2e2008-07-24 11:26:38 +0000154 uint8_t val, *p8;
blueswir1eee0b832007-04-21 19:45:49 +0000155 uint32_t *p = (uint32_t *)d;
156 uint32_t dval;
157
aliguori7b5d76d2009-03-13 15:02:13 +0000158 bgr = is_surface_bgr(s1->ds->surface);
blueswir1eee0b832007-04-21 19:45:49 +0000159 for(x = 0; x < width; x++, s++, s24++) {
blueswir1688ea2e2008-07-24 11:26:38 +0000160 if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
161 // 24-bit direct, BGR order
162 p8 = (uint8_t *)s24;
163 p8++;
164 b = *p8++;
165 g = *p8++;
Blue Swirlf7e683b2010-01-13 18:58:51 +0000166 r = *p8;
aliguori7b5d76d2009-03-13 15:02:13 +0000167 if (bgr)
168 dval = rgb_to_pixel32bgr(r, g, b);
169 else
170 dval = rgb_to_pixel32(r, g, b);
blueswir1eee0b832007-04-21 19:45:49 +0000171 } else {
172 val = *s;
173 dval = s1->palette[val];
174 }
175 *p++ = dval;
176 }
177}
178
Avi Kivityd08151b2011-10-05 18:26:24 +0200179static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24,
Anthony Liguoric227f092009-10-01 16:12:16 -0500180 ram_addr_t cpage)
blueswir1eee0b832007-04-21 19:45:49 +0000181{
182 int ret;
blueswir1eee0b832007-04-21 19:45:49 +0000183
Blue Swirlcd7a45c2012-01-22 16:38:21 +0000184 ret = memory_region_get_dirty(&s->vram_mem, page, TARGET_PAGE_SIZE,
185 DIRTY_MEMORY_VGA);
186 ret |= memory_region_get_dirty(&s->vram_mem, page24, TARGET_PAGE_SIZE * 4,
187 DIRTY_MEMORY_VGA);
188 ret |= memory_region_get_dirty(&s->vram_mem, cpage, TARGET_PAGE_SIZE * 4,
189 DIRTY_MEMORY_VGA);
blueswir1eee0b832007-04-21 19:45:49 +0000190 return ret;
191}
192
Anthony Liguoric227f092009-10-01 16:12:16 -0500193static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
194 ram_addr_t page_max, ram_addr_t page24,
195 ram_addr_t cpage)
blueswir1eee0b832007-04-21 19:45:49 +0000196{
Avi Kivityd08151b2011-10-05 18:26:24 +0200197 memory_region_reset_dirty(&ts->vram_mem,
198 page_min, page_max + TARGET_PAGE_SIZE,
199 DIRTY_MEMORY_VGA);
200 memory_region_reset_dirty(&ts->vram_mem,
201 page24 + page_min * 4,
202 page24 + page_max * 4 + TARGET_PAGE_SIZE,
203 DIRTY_MEMORY_VGA);
204 memory_region_reset_dirty(&ts->vram_mem,
205 cpage + page_min * 4,
206 cpage + page_max * 4 + TARGET_PAGE_SIZE,
207 DIRTY_MEMORY_VGA);
blueswir1eee0b832007-04-21 19:45:49 +0000208}
209
bellarde80cfcf2004-12-19 23:18:01 +0000210/* Fixed line length 1024 allows us to do nice tricks not possible on
211 VGA... */
pbrook95219892006-04-09 01:06:34 +0000212static void tcx_update_display(void *opaque)
bellarde80cfcf2004-12-19 23:18:01 +0000213{
214 TCXState *ts = opaque;
Anthony Liguoric227f092009-10-01 16:12:16 -0500215 ram_addr_t page, page_min, page_max;
bellard550be122006-08-02 22:19:33 +0000216 int y, y_start, dd, ds;
bellarde80cfcf2004-12-19 23:18:01 +0000217 uint8_t *d, *s;
blueswir1b3ceef22007-06-25 19:56:13 +0000218 void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
bellarde80cfcf2004-12-19 23:18:01 +0000219
aliguori0e1f5a02008-11-24 19:29:13 +0000220 if (ds_get_bits_per_pixel(ts->ds) == 0)
blueswir1f930d072007-10-06 11:28:21 +0000221 return;
Avi Kivityd08151b2011-10-05 18:26:24 +0200222 page = 0;
bellarde80cfcf2004-12-19 23:18:01 +0000223 y_start = -1;
Blue Swirlc0c440f2009-04-27 18:10:37 +0000224 page_min = -1;
bellard550be122006-08-02 22:19:33 +0000225 page_max = 0;
aliguori0e1f5a02008-11-24 19:29:13 +0000226 d = ds_get_data(ts->ds);
bellard6f7e9ae2005-03-13 09:43:36 +0000227 s = ts->vram;
aliguori0e1f5a02008-11-24 19:29:13 +0000228 dd = ds_get_linesize(ts->ds);
bellarde80cfcf2004-12-19 23:18:01 +0000229 ds = 1024;
230
aliguori0e1f5a02008-11-24 19:29:13 +0000231 switch (ds_get_bits_per_pixel(ts->ds)) {
bellarde80cfcf2004-12-19 23:18:01 +0000232 case 32:
blueswir1f930d072007-10-06 11:28:21 +0000233 f = tcx_draw_line32;
234 break;
bellard21206a12006-09-09 11:31:34 +0000235 case 15:
236 case 16:
blueswir1f930d072007-10-06 11:28:21 +0000237 f = tcx_draw_line16;
238 break;
bellarde80cfcf2004-12-19 23:18:01 +0000239 default:
240 case 8:
blueswir1f930d072007-10-06 11:28:21 +0000241 f = tcx_draw_line8;
242 break;
bellarde80cfcf2004-12-19 23:18:01 +0000243 case 0:
blueswir1f930d072007-10-06 11:28:21 +0000244 return;
bellarde80cfcf2004-12-19 23:18:01 +0000245 }
ths3b46e622007-09-17 08:09:54 +0000246
bellard6f7e9ae2005-03-13 09:43:36 +0000247 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
Blue Swirlcd7a45c2012-01-22 16:38:21 +0000248 if (memory_region_get_dirty(&ts->vram_mem, page, TARGET_PAGE_SIZE,
249 DIRTY_MEMORY_VGA)) {
blueswir1f930d072007-10-06 11:28:21 +0000250 if (y_start < 0)
bellarde80cfcf2004-12-19 23:18:01 +0000251 y_start = y;
252 if (page < page_min)
253 page_min = page;
254 if (page > page_max)
255 page_max = page;
blueswir1f930d072007-10-06 11:28:21 +0000256 f(ts, d, s, ts->width);
257 d += dd;
258 s += ds;
259 f(ts, d, s, ts->width);
260 d += dd;
261 s += ds;
262 f(ts, d, s, ts->width);
263 d += dd;
264 s += ds;
265 f(ts, d, s, ts->width);
266 d += dd;
267 s += ds;
268 } else {
bellarde80cfcf2004-12-19 23:18:01 +0000269 if (y_start >= 0) {
270 /* flush to display */
ths5fafdf22007-09-16 21:08:06 +0000271 dpy_update(ts->ds, 0, y_start,
bellard6f7e9ae2005-03-13 09:43:36 +0000272 ts->width, y - y_start);
bellarde80cfcf2004-12-19 23:18:01 +0000273 y_start = -1;
274 }
blueswir1f930d072007-10-06 11:28:21 +0000275 d += dd * 4;
276 s += ds * 4;
277 }
bellarde80cfcf2004-12-19 23:18:01 +0000278 }
279 if (y_start >= 0) {
blueswir1f930d072007-10-06 11:28:21 +0000280 /* flush to display */
281 dpy_update(ts->ds, 0, y_start,
282 ts->width, y - y_start);
bellarde80cfcf2004-12-19 23:18:01 +0000283 }
284 /* reset modified pages */
Blue Swirlc0c440f2009-04-27 18:10:37 +0000285 if (page_max >= page_min) {
Avi Kivityd08151b2011-10-05 18:26:24 +0200286 memory_region_reset_dirty(&ts->vram_mem,
287 page_min, page_max + TARGET_PAGE_SIZE,
288 DIRTY_MEMORY_VGA);
bellarde80cfcf2004-12-19 23:18:01 +0000289 }
290}
291
blueswir1eee0b832007-04-21 19:45:49 +0000292static void tcx24_update_display(void *opaque)
293{
294 TCXState *ts = opaque;
Anthony Liguoric227f092009-10-01 16:12:16 -0500295 ram_addr_t page, page_min, page_max, cpage, page24;
blueswir1eee0b832007-04-21 19:45:49 +0000296 int y, y_start, dd, ds;
297 uint8_t *d, *s;
298 uint32_t *cptr, *s24;
299
aliguori0e1f5a02008-11-24 19:29:13 +0000300 if (ds_get_bits_per_pixel(ts->ds) != 32)
blueswir1eee0b832007-04-21 19:45:49 +0000301 return;
Avi Kivityd08151b2011-10-05 18:26:24 +0200302 page = 0;
blueswir1eee0b832007-04-21 19:45:49 +0000303 page24 = ts->vram24_offset;
304 cpage = ts->cplane_offset;
305 y_start = -1;
Blue Swirlc0c440f2009-04-27 18:10:37 +0000306 page_min = -1;
blueswir1eee0b832007-04-21 19:45:49 +0000307 page_max = 0;
aliguori0e1f5a02008-11-24 19:29:13 +0000308 d = ds_get_data(ts->ds);
blueswir1eee0b832007-04-21 19:45:49 +0000309 s = ts->vram;
310 s24 = ts->vram24;
311 cptr = ts->cplane;
aliguori0e1f5a02008-11-24 19:29:13 +0000312 dd = ds_get_linesize(ts->ds);
blueswir1eee0b832007-04-21 19:45:49 +0000313 ds = 1024;
314
315 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
316 page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
Avi Kivityd08151b2011-10-05 18:26:24 +0200317 if (check_dirty(ts, page, page24, cpage)) {
blueswir1eee0b832007-04-21 19:45:49 +0000318 if (y_start < 0)
319 y_start = y;
320 if (page < page_min)
321 page_min = page;
322 if (page > page_max)
323 page_max = page;
324 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
325 d += dd;
326 s += ds;
327 cptr += ds;
328 s24 += ds;
329 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
330 d += dd;
331 s += ds;
332 cptr += ds;
333 s24 += ds;
334 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
335 d += dd;
336 s += ds;
337 cptr += ds;
338 s24 += ds;
339 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
340 d += dd;
341 s += ds;
342 cptr += ds;
343 s24 += ds;
344 } else {
345 if (y_start >= 0) {
346 /* flush to display */
347 dpy_update(ts->ds, 0, y_start,
348 ts->width, y - y_start);
349 y_start = -1;
350 }
351 d += dd * 4;
352 s += ds * 4;
353 cptr += ds * 4;
354 s24 += ds * 4;
355 }
356 }
357 if (y_start >= 0) {
358 /* flush to display */
359 dpy_update(ts->ds, 0, y_start,
360 ts->width, y - y_start);
361 }
362 /* reset modified pages */
Blue Swirlc0c440f2009-04-27 18:10:37 +0000363 if (page_max >= page_min) {
blueswir1eee0b832007-04-21 19:45:49 +0000364 reset_dirty(ts, page_min, page_max, page24, cpage);
365 }
366}
367
pbrook95219892006-04-09 01:06:34 +0000368static void tcx_invalidate_display(void *opaque)
bellard420557e2004-09-30 22:13:50 +0000369{
370 TCXState *s = opaque;
bellard420557e2004-09-30 22:13:50 +0000371
Blue Swirld3ffcaf2009-07-16 13:45:57 +0000372 tcx_set_dirty(s);
373 qemu_console_resize(s->ds, s->width, s->height);
bellarde80cfcf2004-12-19 23:18:01 +0000374}
375
blueswir1eee0b832007-04-21 19:45:49 +0000376static void tcx24_invalidate_display(void *opaque)
377{
378 TCXState *s = opaque;
blueswir1eee0b832007-04-21 19:45:49 +0000379
Blue Swirld3ffcaf2009-07-16 13:45:57 +0000380 tcx_set_dirty(s);
381 tcx24_set_dirty(s);
382 qemu_console_resize(s->ds, s->width, s->height);
blueswir1eee0b832007-04-21 19:45:49 +0000383}
384
Juan Quintelae59fb372009-09-29 22:48:21 +0200385static int vmstate_tcx_post_load(void *opaque, int version_id)
bellarde80cfcf2004-12-19 23:18:01 +0000386{
387 TCXState *s = opaque;
ths3b46e622007-09-17 08:09:54 +0000388
bellard21206a12006-09-09 11:31:34 +0000389 update_palette_entries(s, 0, 256);
Blue Swirld3ffcaf2009-07-16 13:45:57 +0000390 if (s->depth == 24) {
391 tcx24_set_dirty(s);
392 } else {
393 tcx_set_dirty(s);
394 }
blueswir15425a212007-04-13 19:24:07 +0000395
bellard420557e2004-09-30 22:13:50 +0000396 return 0;
397}
398
Blue Swirlc0c41a42009-08-28 20:43:01 +0000399static const VMStateDescription vmstate_tcx = {
400 .name ="tcx",
401 .version_id = 4,
402 .minimum_version_id = 4,
403 .minimum_version_id_old = 4,
Juan Quintela752ff2f2009-09-10 03:04:30 +0200404 .post_load = vmstate_tcx_post_load,
Blue Swirlc0c41a42009-08-28 20:43:01 +0000405 .fields = (VMStateField []) {
406 VMSTATE_UINT16(height, TCXState),
407 VMSTATE_UINT16(width, TCXState),
408 VMSTATE_UINT16(depth, TCXState),
409 VMSTATE_BUFFER(r, TCXState),
410 VMSTATE_BUFFER(g, TCXState),
411 VMSTATE_BUFFER(b, TCXState),
412 VMSTATE_UINT8(dac_index, TCXState),
413 VMSTATE_UINT8(dac_state, TCXState),
414 VMSTATE_END_OF_LIST()
415 }
416};
417
Michael S. Tsirkin7f23f812009-09-16 13:40:27 +0300418static void tcx_reset(DeviceState *d)
bellard420557e2004-09-30 22:13:50 +0000419{
Michael S. Tsirkin7f23f812009-09-16 13:40:27 +0300420 TCXState *s = container_of(d, TCXState, busdev.qdev);
bellard420557e2004-09-30 22:13:50 +0000421
bellarde80cfcf2004-12-19 23:18:01 +0000422 /* Initialize palette */
423 memset(s->r, 0, 256);
424 memset(s->g, 0, 256);
425 memset(s->b, 0, 256);
426 s->r[255] = s->g[255] = s->b[255] = 255;
bellard21206a12006-09-09 11:31:34 +0000427 update_palette_entries(s, 0, 256);
bellarde80cfcf2004-12-19 23:18:01 +0000428 memset(s->vram, 0, MAXX*MAXY);
Avi Kivityd08151b2011-10-05 18:26:24 +0200429 memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
430 DIRTY_MEMORY_VGA);
bellard6f7e9ae2005-03-13 09:43:36 +0000431 s->dac_index = 0;
432 s->dac_state = 0;
bellard420557e2004-09-30 22:13:50 +0000433}
434
Avi Kivityd08151b2011-10-05 18:26:24 +0200435static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr,
436 unsigned size)
bellard6f7e9ae2005-03-13 09:43:36 +0000437{
438 return 0;
439}
440
Avi Kivityd08151b2011-10-05 18:26:24 +0200441static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val,
442 unsigned size)
bellard6f7e9ae2005-03-13 09:43:36 +0000443{
444 TCXState *s = opaque;
bellard6f7e9ae2005-03-13 09:43:36 +0000445
blueswir1e64d7d52008-12-02 17:47:02 +0000446 switch (addr) {
bellard6f7e9ae2005-03-13 09:43:36 +0000447 case 0:
blueswir1f930d072007-10-06 11:28:21 +0000448 s->dac_index = val >> 24;
449 s->dac_state = 0;
450 break;
blueswir1e64d7d52008-12-02 17:47:02 +0000451 case 4:
blueswir1f930d072007-10-06 11:28:21 +0000452 switch (s->dac_state) {
453 case 0:
454 s->r[s->dac_index] = val >> 24;
bellard21206a12006-09-09 11:31:34 +0000455 update_palette_entries(s, s->dac_index, s->dac_index + 1);
blueswir1f930d072007-10-06 11:28:21 +0000456 s->dac_state++;
457 break;
458 case 1:
459 s->g[s->dac_index] = val >> 24;
bellard21206a12006-09-09 11:31:34 +0000460 update_palette_entries(s, s->dac_index, s->dac_index + 1);
blueswir1f930d072007-10-06 11:28:21 +0000461 s->dac_state++;
462 break;
463 case 2:
464 s->b[s->dac_index] = val >> 24;
bellard21206a12006-09-09 11:31:34 +0000465 update_palette_entries(s, s->dac_index, s->dac_index + 1);
blueswir15c8cdbf2007-04-17 19:42:21 +0000466 s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
blueswir1f930d072007-10-06 11:28:21 +0000467 default:
468 s->dac_state = 0;
469 break;
470 }
471 break;
bellard6f7e9ae2005-03-13 09:43:36 +0000472 default:
blueswir1f930d072007-10-06 11:28:21 +0000473 break;
bellard6f7e9ae2005-03-13 09:43:36 +0000474 }
bellard6f7e9ae2005-03-13 09:43:36 +0000475}
476
Avi Kivityd08151b2011-10-05 18:26:24 +0200477static const MemoryRegionOps tcx_dac_ops = {
478 .read = tcx_dac_readl,
479 .write = tcx_dac_writel,
480 .endianness = DEVICE_NATIVE_ENDIAN,
481 .valid = {
482 .min_access_size = 4,
483 .max_access_size = 4,
484 },
bellard6f7e9ae2005-03-13 09:43:36 +0000485};
486
Avi Kivityd08151b2011-10-05 18:26:24 +0200487static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr,
488 unsigned size)
blueswir18508b892007-05-06 17:39:55 +0000489{
490 return 0;
491}
492
Avi Kivityd08151b2011-10-05 18:26:24 +0200493static void dummy_writel(void *opaque, target_phys_addr_t addr,
494 uint64_t val, unsigned size)
blueswir18508b892007-05-06 17:39:55 +0000495{
496}
497
Avi Kivityd08151b2011-10-05 18:26:24 +0200498static const MemoryRegionOps dummy_ops = {
499 .read = dummy_readl,
500 .write = dummy_writel,
501 .endianness = DEVICE_NATIVE_ENDIAN,
502 .valid = {
503 .min_access_size = 4,
504 .max_access_size = 4,
505 },
blueswir18508b892007-05-06 17:39:55 +0000506};
507
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200508static int tcx_init1(SysBusDevice *dev)
Blue Swirlf40070c2009-07-12 19:21:36 +0000509{
510 TCXState *s = FROM_SYSBUS(TCXState, dev);
Avi Kivityd08151b2011-10-05 18:26:24 +0200511 ram_addr_t vram_offset = 0;
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200512 int size;
pbrookdc828ca2009-04-09 22:21:07 +0000513 uint8_t *vram_base;
514
Avi Kivityc5705a72011-12-20 15:59:12 +0200515 memory_region_init_ram(&s->vram_mem, "tcx.vram",
Avi Kivityd08151b2011-10-05 18:26:24 +0200516 s->vram_size * (1 + 4 + 4));
Avi Kivityc5705a72011-12-20 15:59:12 +0200517 vmstate_register_ram_global(&s->vram_mem);
Avi Kivityd08151b2011-10-05 18:26:24 +0200518 vram_base = memory_region_get_ram_ptr(&s->vram_mem);
bellarde80cfcf2004-12-19 23:18:01 +0000519
Blue Swirlf40070c2009-07-12 19:21:36 +0000520 /* 8-bit plane */
blueswir1eee0b832007-04-21 19:45:49 +0000521 s->vram = vram_base;
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200522 size = s->vram_size;
Avi Kivityd08151b2011-10-05 18:26:24 +0200523 memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit",
524 &s->vram_mem, vram_offset, size);
Avi Kivity750ecd42011-11-27 11:38:10 +0200525 sysbus_init_mmio(dev, &s->vram_8bit);
blueswir1eee0b832007-04-21 19:45:49 +0000526 vram_offset += size;
527 vram_base += size;
528
Blue Swirlf40070c2009-07-12 19:21:36 +0000529 /* DAC */
Avi Kivityd08151b2011-10-05 18:26:24 +0200530 memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
Avi Kivity750ecd42011-11-27 11:38:10 +0200531 sysbus_init_mmio(dev, &s->dac);
bellarde80cfcf2004-12-19 23:18:01 +0000532
Blue Swirlf40070c2009-07-12 19:21:36 +0000533 /* TEC (dummy) */
Avi Kivityd08151b2011-10-05 18:26:24 +0200534 memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
Avi Kivity750ecd42011-11-27 11:38:10 +0200535 sysbus_init_mmio(dev, &s->tec);
Blue Swirlf40070c2009-07-12 19:21:36 +0000536 /* THC: NetBSD writes here even with 8-bit display: dummy */
Avi Kivityd08151b2011-10-05 18:26:24 +0200537 memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24",
538 TCX_THC_NREGS_24);
Avi Kivity750ecd42011-11-27 11:38:10 +0200539 sysbus_init_mmio(dev, &s->thc24);
Blue Swirlf40070c2009-07-12 19:21:36 +0000540
541 if (s->depth == 24) {
542 /* 24-bit plane */
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200543 size = s->vram_size * 4;
blueswir1eee0b832007-04-21 19:45:49 +0000544 s->vram24 = (uint32_t *)vram_base;
545 s->vram24_offset = vram_offset;
Avi Kivityd08151b2011-10-05 18:26:24 +0200546 memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit",
547 &s->vram_mem, vram_offset, size);
Avi Kivity750ecd42011-11-27 11:38:10 +0200548 sysbus_init_mmio(dev, &s->vram_24bit);
blueswir1eee0b832007-04-21 19:45:49 +0000549 vram_offset += size;
550 vram_base += size;
551
Blue Swirlf40070c2009-07-12 19:21:36 +0000552 /* Control plane */
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200553 size = s->vram_size * 4;
blueswir1eee0b832007-04-21 19:45:49 +0000554 s->cplane = (uint32_t *)vram_base;
555 s->cplane_offset = vram_offset;
Avi Kivityd08151b2011-10-05 18:26:24 +0200556 memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane",
557 &s->vram_mem, vram_offset, size);
Avi Kivity750ecd42011-11-27 11:38:10 +0200558 sysbus_init_mmio(dev, &s->vram_cplane);
Blue Swirlf40070c2009-07-12 19:21:36 +0000559
aliguori3023f332009-01-16 19:04:14 +0000560 s->ds = graphic_console_init(tcx24_update_display,
561 tcx24_invalidate_display,
562 tcx24_screen_dump, NULL, s);
blueswir1eee0b832007-04-21 19:45:49 +0000563 } else {
Blue Swirlf40070c2009-07-12 19:21:36 +0000564 /* THC 8 bit (dummy) */
Avi Kivityd08151b2011-10-05 18:26:24 +0200565 memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
566 TCX_THC_NREGS_8);
Avi Kivity750ecd42011-11-27 11:38:10 +0200567 sysbus_init_mmio(dev, &s->thc8);
Blue Swirlf40070c2009-07-12 19:21:36 +0000568
aliguori3023f332009-01-16 19:04:14 +0000569 s->ds = graphic_console_init(tcx_update_display,
570 tcx_invalidate_display,
571 tcx_screen_dump, NULL, s);
blueswir1eee0b832007-04-21 19:45:49 +0000572 }
573
Blue Swirlf40070c2009-07-12 19:21:36 +0000574 qemu_console_resize(s->ds, s->width, s->height);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200575 return 0;
bellard420557e2004-09-30 22:13:50 +0000576}
577
Luiz Capitulinod7098132012-05-21 16:41:37 -0300578static void tcx_screen_dump(void *opaque, const char *filename, bool cswitch,
579 Error **errp)
bellard8d5f07f2004-10-04 21:23:09 +0000580{
bellarde80cfcf2004-12-19 23:18:01 +0000581 TCXState *s = opaque;
bellard8d5f07f2004-10-04 21:23:09 +0000582 FILE *f;
bellarde80cfcf2004-12-19 23:18:01 +0000583 uint8_t *d, *d1, v;
Luiz Capitulino0ab6b632012-05-24 11:33:25 -0300584 int ret, y, x;
bellard8d5f07f2004-10-04 21:23:09 +0000585
586 f = fopen(filename, "wb");
Luiz Capitulino0ab6b632012-05-24 11:33:25 -0300587 if (!f) {
588 error_setg(errp, "failed to open file '%s': %s", filename,
589 strerror(errno));
bellarde80cfcf2004-12-19 23:18:01 +0000590 return;
Luiz Capitulino0ab6b632012-05-24 11:33:25 -0300591 }
592 ret = fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
593 if (ret < 0) {
594 goto write_err;
595 }
bellard6f7e9ae2005-03-13 09:43:36 +0000596 d1 = s->vram;
597 for(y = 0; y < s->height; y++) {
bellard8d5f07f2004-10-04 21:23:09 +0000598 d = d1;
bellard6f7e9ae2005-03-13 09:43:36 +0000599 for(x = 0; x < s->width; x++) {
bellard8d5f07f2004-10-04 21:23:09 +0000600 v = *d;
Luiz Capitulino0ab6b632012-05-24 11:33:25 -0300601 ret = fputc(s->r[v], f);
602 if (ret == EOF) {
603 goto write_err;
604 }
605 ret = fputc(s->g[v], f);
606 if (ret == EOF) {
607 goto write_err;
608 }
609 ret = fputc(s->b[v], f);
610 if (ret == EOF) {
611 goto write_err;
612 }
bellard8d5f07f2004-10-04 21:23:09 +0000613 d++;
614 }
bellarde80cfcf2004-12-19 23:18:01 +0000615 d1 += MAXX;
bellard8d5f07f2004-10-04 21:23:09 +0000616 }
Luiz Capitulino0ab6b632012-05-24 11:33:25 -0300617
618out:
bellard8d5f07f2004-10-04 21:23:09 +0000619 fclose(f);
620 return;
Luiz Capitulino0ab6b632012-05-24 11:33:25 -0300621
622write_err:
623 error_setg(errp, "failed to write to file '%s': %s", filename,
624 strerror(errno));
625 unlink(filename);
626 goto out;
bellard8d5f07f2004-10-04 21:23:09 +0000627}
628
Luiz Capitulinod7098132012-05-21 16:41:37 -0300629static void tcx24_screen_dump(void *opaque, const char *filename, bool cswitch,
630 Error **errp)
blueswir1eee0b832007-04-21 19:45:49 +0000631{
632 TCXState *s = opaque;
633 FILE *f;
634 uint8_t *d, *d1, v;
635 uint32_t *s24, *cptr, dval;
Luiz Capitulino537f2d22012-05-24 11:30:40 -0300636 int ret, y, x;
bellard8d5f07f2004-10-04 21:23:09 +0000637
blueswir1eee0b832007-04-21 19:45:49 +0000638 f = fopen(filename, "wb");
Luiz Capitulino537f2d22012-05-24 11:30:40 -0300639 if (!f) {
640 error_setg(errp, "failed to open file '%s': %s", filename,
641 strerror(errno));
blueswir1eee0b832007-04-21 19:45:49 +0000642 return;
Luiz Capitulino537f2d22012-05-24 11:30:40 -0300643 }
644 ret = fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
645 if (ret < 0) {
646 goto write_err;
647 }
blueswir1eee0b832007-04-21 19:45:49 +0000648 d1 = s->vram;
649 s24 = s->vram24;
650 cptr = s->cplane;
651 for(y = 0; y < s->height; y++) {
652 d = d1;
653 for(x = 0; x < s->width; x++, d++, s24++) {
654 if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
655 dval = *s24 & 0x00ffffff;
Luiz Capitulino537f2d22012-05-24 11:30:40 -0300656 ret = fputc((dval >> 16) & 0xff, f);
657 if (ret == EOF) {
658 goto write_err;
659 }
660 ret = fputc((dval >> 8) & 0xff, f);
661 if (ret == EOF) {
662 goto write_err;
663 }
664 ret = fputc(dval & 0xff, f);
665 if (ret == EOF) {
666 goto write_err;
667 }
blueswir1eee0b832007-04-21 19:45:49 +0000668 } else {
669 v = *d;
Luiz Capitulino537f2d22012-05-24 11:30:40 -0300670 ret = fputc(s->r[v], f);
671 if (ret == EOF) {
672 goto write_err;
673 }
674 ret = fputc(s->g[v], f);
675 if (ret == EOF) {
676 goto write_err;
677 }
678 ret = fputc(s->b[v], f);
679 if (ret == EOF) {
680 goto write_err;
681 }
blueswir1eee0b832007-04-21 19:45:49 +0000682 }
683 }
684 d1 += MAXX;
685 }
Luiz Capitulino537f2d22012-05-24 11:30:40 -0300686
687out:
blueswir1eee0b832007-04-21 19:45:49 +0000688 fclose(f);
689 return;
Luiz Capitulino537f2d22012-05-24 11:30:40 -0300690
691write_err:
692 error_setg(errp, "failed to write to file '%s': %s", filename,
693 strerror(errno));
694 unlink(filename);
695 goto out;
blueswir1eee0b832007-04-21 19:45:49 +0000696}
Blue Swirlf40070c2009-07-12 19:21:36 +0000697
Anthony Liguori999e12b2012-01-24 13:12:29 -0600698static Property tcx_properties[] = {
699 DEFINE_PROP_TADDR("addr", TCXState, addr, -1),
700 DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1),
701 DEFINE_PROP_UINT16("width", TCXState, width, -1),
702 DEFINE_PROP_UINT16("height", TCXState, height, -1),
703 DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
704 DEFINE_PROP_END_OF_LIST(),
705};
706
707static void tcx_class_init(ObjectClass *klass, void *data)
708{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600709 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600710 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
711
712 k->init = tcx_init1;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600713 dc->reset = tcx_reset;
714 dc->vmsd = &vmstate_tcx;
715 dc->props = tcx_properties;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600716}
717
Anthony Liguori39bffca2011-12-07 21:34:16 -0600718static TypeInfo tcx_info = {
719 .name = "SUNW,tcx",
720 .parent = TYPE_SYS_BUS_DEVICE,
721 .instance_size = sizeof(TCXState),
722 .class_init = tcx_class_init,
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200723};
724
Andreas Färber83f7d432012-02-09 15:20:55 +0100725static void tcx_register_types(void)
Blue Swirlf40070c2009-07-12 19:21:36 +0000726{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600727 type_register_static(&tcx_info);
Blue Swirlf40070c2009-07-12 19:21:36 +0000728}
729
Andreas Färber83f7d432012-02-09 15:20:55 +0100730type_init(tcx_register_types)