Andreas Färber | b77f98c | 2012-04-12 02:17:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * QEMU MicroBlaze CPU |
| 3 | * |
Andreas Färber | 61b6208 | 2012-04-12 02:26:28 +0200 | [diff] [blame] | 4 | * Copyright (c) 2009 Edgar E. Iglesias |
| 5 | * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. |
Andreas Färber | b77f98c | 2012-04-12 02:17:53 +0200 | [diff] [blame] | 6 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
Alistair Francis | 73c6945 | 2014-01-13 13:35:26 +1000 | [diff] [blame] | 7 | * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. |
Andreas Färber | b77f98c | 2012-04-12 02:17:53 +0200 | [diff] [blame] | 8 | * |
| 9 | * This library is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU Lesser General Public |
| 11 | * License as published by the Free Software Foundation; either |
| 12 | * version 2.1 of the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This library is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 17 | * Lesser General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU Lesser General Public |
| 20 | * License along with this library; if not, see |
| 21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> |
| 22 | */ |
| 23 | |
| 24 | #include "cpu.h" |
| 25 | #include "qemu-common.h" |
Edgar E. Iglesias | a1bff71 | 2013-04-23 14:27:09 +0200 | [diff] [blame] | 26 | #include "hw/qdev-properties.h" |
Andreas Färber | 3ce8b2b | 2013-01-20 19:03:32 +0100 | [diff] [blame] | 27 | #include "migration/vmstate.h" |
Andreas Färber | b77f98c | 2012-04-12 02:17:53 +0200 | [diff] [blame] | 28 | |
| 29 | |
Andreas Färber | f45748f | 2013-06-21 19:09:18 +0200 | [diff] [blame] | 30 | static void mb_cpu_set_pc(CPUState *cs, vaddr value) |
| 31 | { |
| 32 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); |
| 33 | |
| 34 | cpu->env.sregs[SR_PC] = value; |
| 35 | } |
| 36 | |
Andreas Färber | 8c2e1b0 | 2013-08-25 18:53:55 +0200 | [diff] [blame] | 37 | static bool mb_cpu_has_work(CPUState *cs) |
| 38 | { |
| 39 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); |
| 40 | } |
| 41 | |
Alistair Francis | 73c6945 | 2014-01-13 13:35:26 +1000 | [diff] [blame] | 42 | #ifndef CONFIG_USER_ONLY |
| 43 | static void microblaze_cpu_set_irq(void *opaque, int irq, int level) |
| 44 | { |
| 45 | MicroBlazeCPU *cpu = opaque; |
| 46 | CPUState *cs = CPU(cpu); |
| 47 | int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; |
| 48 | |
| 49 | if (level) { |
| 50 | cpu_interrupt(cs, type); |
| 51 | } else { |
| 52 | cpu_reset_interrupt(cs, type); |
| 53 | } |
| 54 | } |
| 55 | #endif |
| 56 | |
Andreas Färber | b77f98c | 2012-04-12 02:17:53 +0200 | [diff] [blame] | 57 | /* CPUClass::reset() */ |
| 58 | static void mb_cpu_reset(CPUState *s) |
| 59 | { |
| 60 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); |
| 61 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); |
| 62 | CPUMBState *env = &cpu->env; |
| 63 | |
| 64 | mcc->parent_reset(s); |
| 65 | |
Andreas Färber | f0c3c50 | 2013-08-26 21:22:53 +0200 | [diff] [blame] | 66 | memset(env, 0, sizeof(CPUMBState)); |
Peter A. G. Crosthwaite | 8cc9b43 | 2012-06-01 13:23:28 +1000 | [diff] [blame] | 67 | env->res_addr = RES_ADDR_NONE; |
Andreas Färber | 00c8cb0 | 2013-09-04 02:19:44 +0200 | [diff] [blame] | 68 | tlb_flush(s, 1); |
Andreas Färber | 61b6208 | 2012-04-12 02:26:28 +0200 | [diff] [blame] | 69 | |
| 70 | /* Disable stack protector. */ |
| 71 | env->shr = ~0; |
| 72 | |
| 73 | env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ |
| 74 | | PVR0_USE_BARREL_MASK \ |
| 75 | | PVR0_USE_DIV_MASK \ |
| 76 | | PVR0_USE_HW_MUL_MASK \ |
| 77 | | PVR0_USE_EXC_MASK \ |
| 78 | | PVR0_USE_ICACHE_MASK \ |
| 79 | | PVR0_USE_DCACHE_MASK \ |
| 80 | | PVR0_USE_MMU \ |
| 81 | | (0xb << 8); |
| 82 | env->pvr.regs[2] = PVR2_D_OPB_MASK \ |
| 83 | | PVR2_D_LMB_MASK \ |
| 84 | | PVR2_I_OPB_MASK \ |
| 85 | | PVR2_I_LMB_MASK \ |
| 86 | | PVR2_USE_MSR_INSTR \ |
| 87 | | PVR2_USE_PCMP_INSTR \ |
| 88 | | PVR2_USE_BARREL_MASK \ |
| 89 | | PVR2_USE_DIV_MASK \ |
| 90 | | PVR2_USE_HW_MUL_MASK \ |
| 91 | | PVR2_USE_MUL64_MASK \ |
| 92 | | PVR2_USE_FPU_MASK \ |
| 93 | | PVR2_USE_FPU2_MASK \ |
| 94 | | PVR2_FPU_EXC_MASK \ |
| 95 | | 0; |
| 96 | env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ |
| 97 | env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); |
| 98 | |
Edgar E. Iglesias | 6d35556 | 2013-05-28 14:56:20 +0200 | [diff] [blame] | 99 | env->sregs[SR_PC] = cpu->base_vectors; |
| 100 | |
Andreas Färber | 61b6208 | 2012-04-12 02:26:28 +0200 | [diff] [blame] | 101 | #if defined(CONFIG_USER_ONLY) |
| 102 | /* start in user mode with interrupts enabled. */ |
| 103 | env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; |
| 104 | env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ |
| 105 | #else |
| 106 | env->sregs[SR_MSR] = 0; |
| 107 | mmu_init(&env->mmu); |
| 108 | env->mmu.c_mmu = 3; |
| 109 | env->mmu.c_mmu_tlb_access = 3; |
| 110 | env->mmu.c_mmu_zones = 16; |
| 111 | #endif |
Andreas Färber | b77f98c | 2012-04-12 02:17:53 +0200 | [diff] [blame] | 112 | } |
| 113 | |
Andreas Färber | 746b03b | 2013-01-05 15:27:31 +0100 | [diff] [blame] | 114 | static void mb_cpu_realizefn(DeviceState *dev, Error **errp) |
| 115 | { |
Andreas Färber | 14a10fc | 2013-07-27 02:53:25 +0200 | [diff] [blame] | 116 | CPUState *cs = CPU(dev); |
Andreas Färber | 746b03b | 2013-01-05 15:27:31 +0100 | [diff] [blame] | 117 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); |
| 118 | |
Andreas Färber | 14a10fc | 2013-07-27 02:53:25 +0200 | [diff] [blame] | 119 | cpu_reset(cs); |
| 120 | qemu_init_vcpu(cs); |
Andreas Färber | 746b03b | 2013-01-05 15:27:31 +0100 | [diff] [blame] | 121 | |
| 122 | mcc->parent_realize(dev, errp); |
| 123 | } |
| 124 | |
Andreas Färber | d0e71ef | 2012-04-12 02:34:40 +0200 | [diff] [blame] | 125 | static void mb_cpu_initfn(Object *obj) |
| 126 | { |
Andreas Färber | c05efcb | 2013-01-17 12:13:41 +0100 | [diff] [blame] | 127 | CPUState *cs = CPU(obj); |
Andreas Färber | d0e71ef | 2012-04-12 02:34:40 +0200 | [diff] [blame] | 128 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); |
| 129 | CPUMBState *env = &cpu->env; |
Andreas Färber | cd0c24f | 2013-01-20 01:10:52 +0100 | [diff] [blame] | 130 | static bool tcg_initialized; |
Andreas Färber | d0e71ef | 2012-04-12 02:34:40 +0200 | [diff] [blame] | 131 | |
Andreas Färber | c05efcb | 2013-01-17 12:13:41 +0100 | [diff] [blame] | 132 | cs->env_ptr = env; |
Andreas Färber | d0e71ef | 2012-04-12 02:34:40 +0200 | [diff] [blame] | 133 | cpu_exec_init(env); |
| 134 | |
| 135 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
Andreas Färber | cd0c24f | 2013-01-20 01:10:52 +0100 | [diff] [blame] | 136 | |
Alistair Francis | 73c6945 | 2014-01-13 13:35:26 +1000 | [diff] [blame] | 137 | #ifndef CONFIG_USER_ONLY |
| 138 | /* Inbound IRQ and FIR lines */ |
| 139 | qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); |
| 140 | #endif |
| 141 | |
Andreas Färber | cd0c24f | 2013-01-20 01:10:52 +0100 | [diff] [blame] | 142 | if (tcg_enabled() && !tcg_initialized) { |
| 143 | tcg_initialized = true; |
| 144 | mb_tcg_init(); |
| 145 | } |
Andreas Färber | d0e71ef | 2012-04-12 02:34:40 +0200 | [diff] [blame] | 146 | } |
| 147 | |
Andreas Färber | 3ce8b2b | 2013-01-20 19:03:32 +0100 | [diff] [blame] | 148 | static const VMStateDescription vmstate_mb_cpu = { |
| 149 | .name = "cpu", |
| 150 | .unmigratable = 1, |
| 151 | }; |
| 152 | |
Edgar E. Iglesias | a1bff71 | 2013-04-23 14:27:09 +0200 | [diff] [blame] | 153 | static Property mb_properties[] = { |
| 154 | DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0), |
| 155 | DEFINE_PROP_END_OF_LIST(), |
| 156 | }; |
| 157 | |
Andreas Färber | b77f98c | 2012-04-12 02:17:53 +0200 | [diff] [blame] | 158 | static void mb_cpu_class_init(ObjectClass *oc, void *data) |
| 159 | { |
Andreas Färber | 3ce8b2b | 2013-01-20 19:03:32 +0100 | [diff] [blame] | 160 | DeviceClass *dc = DEVICE_CLASS(oc); |
Andreas Färber | b77f98c | 2012-04-12 02:17:53 +0200 | [diff] [blame] | 161 | CPUClass *cc = CPU_CLASS(oc); |
| 162 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); |
| 163 | |
Andreas Färber | 746b03b | 2013-01-05 15:27:31 +0100 | [diff] [blame] | 164 | mcc->parent_realize = dc->realize; |
| 165 | dc->realize = mb_cpu_realizefn; |
| 166 | |
Andreas Färber | b77f98c | 2012-04-12 02:17:53 +0200 | [diff] [blame] | 167 | mcc->parent_reset = cc->reset; |
| 168 | cc->reset = mb_cpu_reset; |
Andreas Färber | 3ce8b2b | 2013-01-20 19:03:32 +0100 | [diff] [blame] | 169 | |
Andreas Färber | 8c2e1b0 | 2013-08-25 18:53:55 +0200 | [diff] [blame] | 170 | cc->has_work = mb_cpu_has_work; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 171 | cc->do_interrupt = mb_cpu_do_interrupt; |
Richard Henderson | 29cd33d | 2014-09-13 09:45:30 -0700 | [diff] [blame] | 172 | cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; |
Andreas Färber | 878096e | 2013-05-27 01:33:50 +0200 | [diff] [blame] | 173 | cc->dump_state = mb_cpu_dump_state; |
Andreas Färber | f45748f | 2013-06-21 19:09:18 +0200 | [diff] [blame] | 174 | cc->set_pc = mb_cpu_set_pc; |
Andreas Färber | 5b50e79 | 2013-06-29 04:18:45 +0200 | [diff] [blame] | 175 | cc->gdb_read_register = mb_cpu_gdb_read_register; |
| 176 | cc->gdb_write_register = mb_cpu_gdb_write_register; |
Andreas Färber | 7510454 | 2013-08-26 03:01:33 +0200 | [diff] [blame] | 177 | #ifdef CONFIG_USER_ONLY |
| 178 | cc->handle_mmu_fault = mb_cpu_handle_mmu_fault; |
| 179 | #else |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 180 | cc->do_unassigned_access = mb_cpu_unassigned_access; |
| 181 | cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; |
| 182 | #endif |
Andreas Färber | 3ce8b2b | 2013-01-20 19:03:32 +0100 | [diff] [blame] | 183 | dc->vmsd = &vmstate_mb_cpu; |
Edgar E. Iglesias | a1bff71 | 2013-04-23 14:27:09 +0200 | [diff] [blame] | 184 | dc->props = mb_properties; |
Andreas Färber | a0e372f | 2013-06-28 23:18:47 +0200 | [diff] [blame] | 185 | cc->gdb_num_core_regs = 32 + 5; |
Andreas Färber | b77f98c | 2012-04-12 02:17:53 +0200 | [diff] [blame] | 186 | } |
| 187 | |
| 188 | static const TypeInfo mb_cpu_type_info = { |
| 189 | .name = TYPE_MICROBLAZE_CPU, |
| 190 | .parent = TYPE_CPU, |
| 191 | .instance_size = sizeof(MicroBlazeCPU), |
Andreas Färber | d0e71ef | 2012-04-12 02:34:40 +0200 | [diff] [blame] | 192 | .instance_init = mb_cpu_initfn, |
Andreas Färber | b77f98c | 2012-04-12 02:17:53 +0200 | [diff] [blame] | 193 | .class_size = sizeof(MicroBlazeCPUClass), |
| 194 | .class_init = mb_cpu_class_init, |
| 195 | }; |
| 196 | |
| 197 | static void mb_cpu_register_types(void) |
| 198 | { |
| 199 | type_register_static(&mb_cpu_type_info); |
| 200 | } |
| 201 | |
| 202 | type_init(mb_cpu_register_types) |