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pbrookaef445b2006-09-18 01:15:29 +00001/*
2 * Memory mapped access to ISA IO space.
3 *
4 * Copyright (c) 2006 Fabrice Bellard
ths5fafdf22007-09-16 21:08:06 +00005 *
pbrookaef445b2006-09-18 01:15:29 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
pbrook87ecb682007-11-17 17:14:51 +000025#include "hw.h"
26#include "isa.h"
pbrookaef445b2006-09-18 01:15:29 +000027
Anthony Liguoric227f092009-10-01 16:12:16 -050028static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
pbrookaef445b2006-09-18 01:15:29 +000029 uint32_t val)
30{
Blue Swirlafcea8c2009-09-20 16:05:47 +000031 cpu_outb(addr & IOPORTS_MASK, val);
pbrookaef445b2006-09-18 01:15:29 +000032}
33
Blue Swirl84108e12010-03-21 19:47:09 +000034static void isa_mmio_writew_be(void *opaque, target_phys_addr_t addr,
35 uint32_t val)
pbrookaef445b2006-09-18 01:15:29 +000036{
pbrookaef445b2006-09-18 01:15:29 +000037 val = bswap16(val);
Blue Swirlafcea8c2009-09-20 16:05:47 +000038 cpu_outw(addr & IOPORTS_MASK, val);
pbrookaef445b2006-09-18 01:15:29 +000039}
40
Blue Swirl84108e12010-03-21 19:47:09 +000041static void isa_mmio_writew_le(void *opaque, target_phys_addr_t addr,
42 uint32_t val)
pbrookaef445b2006-09-18 01:15:29 +000043{
Blue Swirl84108e12010-03-21 19:47:09 +000044 cpu_outw(addr & IOPORTS_MASK, val);
45}
46
47static void isa_mmio_writel_be(void *opaque, target_phys_addr_t addr,
48 uint32_t val)
49{
pbrookaef445b2006-09-18 01:15:29 +000050 val = bswap32(val);
Blue Swirl84108e12010-03-21 19:47:09 +000051 cpu_outl(addr & IOPORTS_MASK, val);
52}
53
54static void isa_mmio_writel_le(void *opaque, target_phys_addr_t addr,
55 uint32_t val)
56{
Blue Swirlafcea8c2009-09-20 16:05:47 +000057 cpu_outl(addr & IOPORTS_MASK, val);
pbrookaef445b2006-09-18 01:15:29 +000058}
59
Anthony Liguoric227f092009-10-01 16:12:16 -050060static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
pbrookaef445b2006-09-18 01:15:29 +000061{
62 uint32_t val;
63
Blue Swirlafcea8c2009-09-20 16:05:47 +000064 val = cpu_inb(addr & IOPORTS_MASK);
pbrookaef445b2006-09-18 01:15:29 +000065 return val;
66}
67
Blue Swirl84108e12010-03-21 19:47:09 +000068static uint32_t isa_mmio_readw_be(void *opaque, target_phys_addr_t addr)
pbrookaef445b2006-09-18 01:15:29 +000069{
70 uint32_t val;
71
Blue Swirlafcea8c2009-09-20 16:05:47 +000072 val = cpu_inw(addr & IOPORTS_MASK);
pbrookaef445b2006-09-18 01:15:29 +000073 val = bswap16(val);
pbrookaef445b2006-09-18 01:15:29 +000074 return val;
75}
76
Blue Swirl84108e12010-03-21 19:47:09 +000077static uint32_t isa_mmio_readw_le(void *opaque, target_phys_addr_t addr)
78{
79 uint32_t val;
80
81 val = cpu_inw(addr & IOPORTS_MASK);
82 return val;
83}
84
85static uint32_t isa_mmio_readl_be(void *opaque, target_phys_addr_t addr)
pbrookaef445b2006-09-18 01:15:29 +000086{
87 uint32_t val;
88
Blue Swirlafcea8c2009-09-20 16:05:47 +000089 val = cpu_inl(addr & IOPORTS_MASK);
pbrookaef445b2006-09-18 01:15:29 +000090 val = bswap32(val);
pbrookaef445b2006-09-18 01:15:29 +000091 return val;
92}
93
Blue Swirl84108e12010-03-21 19:47:09 +000094static uint32_t isa_mmio_readl_le(void *opaque, target_phys_addr_t addr)
95{
96 uint32_t val;
97
98 val = cpu_inl(addr & IOPORTS_MASK);
99 return val;
100}
101
102static CPUWriteMemoryFunc * const isa_mmio_write_be[] = {
pbrookaef445b2006-09-18 01:15:29 +0000103 &isa_mmio_writeb,
Blue Swirl84108e12010-03-21 19:47:09 +0000104 &isa_mmio_writew_be,
105 &isa_mmio_writel_be,
pbrookaef445b2006-09-18 01:15:29 +0000106};
107
Blue Swirl84108e12010-03-21 19:47:09 +0000108static CPUReadMemoryFunc * const isa_mmio_read_be[] = {
pbrookaef445b2006-09-18 01:15:29 +0000109 &isa_mmio_readb,
Blue Swirl84108e12010-03-21 19:47:09 +0000110 &isa_mmio_readw_be,
111 &isa_mmio_readl_be,
112};
113
114static CPUWriteMemoryFunc * const isa_mmio_write_le[] = {
115 &isa_mmio_writeb,
116 &isa_mmio_writew_le,
117 &isa_mmio_writel_le,
118};
119
120static CPUReadMemoryFunc * const isa_mmio_read_le[] = {
121 &isa_mmio_readb,
122 &isa_mmio_readw_le,
123 &isa_mmio_readl_le,
pbrookaef445b2006-09-18 01:15:29 +0000124};
125
126static int isa_mmio_iomemtype = 0;
127
Blue Swirl84108e12010-03-21 19:47:09 +0000128void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be)
pbrookaef445b2006-09-18 01:15:29 +0000129{
130 if (!isa_mmio_iomemtype) {
Blue Swirl84108e12010-03-21 19:47:09 +0000131 if (be) {
132 isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_be,
133 isa_mmio_write_be,
134 NULL);
135 } else {
136 isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_le,
137 isa_mmio_write_le,
138 NULL);
139 }
pbrookaef445b2006-09-18 01:15:29 +0000140 }
141 cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
142}