Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1 | /* |
| 2 | * QEMU RISC-V Disassembler |
| 3 | * |
| 4 | * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com> |
| 5 | * Copyright (c) 2017-2018 SiFive, Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms and conditions of the GNU General Public License, |
| 9 | * version 2 or later, as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
Markus Armbruster | 3979fca | 2019-04-17 21:18:04 +0200 | [diff] [blame] | 21 | #include "disas/dis-asm.h" |
Weiwei Li | 454c220 | 2023-05-23 17:35:34 +0800 | [diff] [blame] | 22 | #include "target/riscv/cpu_cfg.h" |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 23 | |
| 24 | /* types */ |
| 25 | |
| 26 | typedef uint64_t rv_inst; |
| 27 | typedef uint16_t rv_opcode; |
| 28 | |
| 29 | /* enums */ |
| 30 | |
| 31 | typedef enum { |
| 32 | rv32, |
| 33 | rv64, |
| 34 | rv128 |
| 35 | } rv_isa; |
| 36 | |
| 37 | typedef enum { |
| 38 | rv_rm_rne = 0, |
| 39 | rv_rm_rtz = 1, |
| 40 | rv_rm_rdn = 2, |
| 41 | rv_rm_rup = 3, |
| 42 | rv_rm_rmm = 4, |
| 43 | rv_rm_dyn = 7, |
| 44 | } rv_rm; |
| 45 | |
| 46 | typedef enum { |
| 47 | rv_fence_i = 8, |
| 48 | rv_fence_o = 4, |
| 49 | rv_fence_r = 2, |
| 50 | rv_fence_w = 1, |
| 51 | } rv_fence; |
| 52 | |
| 53 | typedef enum { |
| 54 | rv_ireg_zero, |
| 55 | rv_ireg_ra, |
| 56 | rv_ireg_sp, |
| 57 | rv_ireg_gp, |
| 58 | rv_ireg_tp, |
| 59 | rv_ireg_t0, |
| 60 | rv_ireg_t1, |
| 61 | rv_ireg_t2, |
| 62 | rv_ireg_s0, |
| 63 | rv_ireg_s1, |
| 64 | rv_ireg_a0, |
| 65 | rv_ireg_a1, |
| 66 | rv_ireg_a2, |
| 67 | rv_ireg_a3, |
| 68 | rv_ireg_a4, |
| 69 | rv_ireg_a5, |
| 70 | rv_ireg_a6, |
| 71 | rv_ireg_a7, |
| 72 | rv_ireg_s2, |
| 73 | rv_ireg_s3, |
| 74 | rv_ireg_s4, |
| 75 | rv_ireg_s5, |
| 76 | rv_ireg_s6, |
| 77 | rv_ireg_s7, |
| 78 | rv_ireg_s8, |
| 79 | rv_ireg_s9, |
| 80 | rv_ireg_s10, |
| 81 | rv_ireg_s11, |
| 82 | rv_ireg_t3, |
| 83 | rv_ireg_t4, |
| 84 | rv_ireg_t5, |
| 85 | rv_ireg_t6, |
| 86 | } rv_ireg; |
| 87 | |
| 88 | typedef enum { |
| 89 | rvc_end, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 90 | rvc_rd_eq_ra, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 91 | rvc_rd_eq_x0, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 92 | rvc_rs1_eq_x0, |
| 93 | rvc_rs2_eq_x0, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 94 | rvc_rs2_eq_rs1, |
| 95 | rvc_rs1_eq_ra, |
| 96 | rvc_imm_eq_zero, |
| 97 | rvc_imm_eq_n1, |
| 98 | rvc_imm_eq_p1, |
| 99 | rvc_csr_eq_0x001, |
| 100 | rvc_csr_eq_0x002, |
| 101 | rvc_csr_eq_0x003, |
| 102 | rvc_csr_eq_0xc00, |
| 103 | rvc_csr_eq_0xc01, |
| 104 | rvc_csr_eq_0xc02, |
| 105 | rvc_csr_eq_0xc80, |
| 106 | rvc_csr_eq_0xc81, |
| 107 | rvc_csr_eq_0xc82, |
| 108 | } rvc_constraint; |
| 109 | |
| 110 | typedef enum { |
| 111 | rv_codec_illegal, |
| 112 | rv_codec_none, |
| 113 | rv_codec_u, |
| 114 | rv_codec_uj, |
| 115 | rv_codec_i, |
| 116 | rv_codec_i_sh5, |
| 117 | rv_codec_i_sh6, |
| 118 | rv_codec_i_sh7, |
| 119 | rv_codec_i_csr, |
| 120 | rv_codec_s, |
| 121 | rv_codec_sb, |
| 122 | rv_codec_r, |
| 123 | rv_codec_r_m, |
| 124 | rv_codec_r4_m, |
| 125 | rv_codec_r_a, |
| 126 | rv_codec_r_l, |
| 127 | rv_codec_r_f, |
| 128 | rv_codec_cb, |
| 129 | rv_codec_cb_imm, |
| 130 | rv_codec_cb_sh5, |
| 131 | rv_codec_cb_sh6, |
| 132 | rv_codec_ci, |
| 133 | rv_codec_ci_sh5, |
| 134 | rv_codec_ci_sh6, |
| 135 | rv_codec_ci_16sp, |
| 136 | rv_codec_ci_lwsp, |
| 137 | rv_codec_ci_ldsp, |
| 138 | rv_codec_ci_lqsp, |
| 139 | rv_codec_ci_li, |
| 140 | rv_codec_ci_lui, |
| 141 | rv_codec_ci_none, |
| 142 | rv_codec_ciw_4spn, |
| 143 | rv_codec_cj, |
| 144 | rv_codec_cj_jal, |
| 145 | rv_codec_cl_lw, |
| 146 | rv_codec_cl_ld, |
| 147 | rv_codec_cl_lq, |
| 148 | rv_codec_cr, |
| 149 | rv_codec_cr_mv, |
| 150 | rv_codec_cr_jalr, |
| 151 | rv_codec_cr_jr, |
| 152 | rv_codec_cs, |
| 153 | rv_codec_cs_sw, |
| 154 | rv_codec_cs_sd, |
| 155 | rv_codec_cs_sq, |
| 156 | rv_codec_css_swsp, |
| 157 | rv_codec_css_sdsp, |
| 158 | rv_codec_css_sqsp, |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 159 | rv_codec_k_bs, |
| 160 | rv_codec_k_rnum, |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 161 | rv_codec_v_r, |
| 162 | rv_codec_v_ldst, |
| 163 | rv_codec_v_i, |
| 164 | rv_codec_vsetvli, |
| 165 | rv_codec_vsetivli, |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 166 | rv_codec_zcb_ext, |
| 167 | rv_codec_zcb_mul, |
| 168 | rv_codec_zcb_lb, |
| 169 | rv_codec_zcb_lh, |
| 170 | rv_codec_zcmp_cm_pushpop, |
| 171 | rv_codec_zcmp_cm_mv, |
| 172 | rv_codec_zcmt_jt, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 173 | } rv_codec; |
| 174 | |
| 175 | typedef enum { |
| 176 | rv_op_illegal = 0, |
| 177 | rv_op_lui = 1, |
| 178 | rv_op_auipc = 2, |
| 179 | rv_op_jal = 3, |
| 180 | rv_op_jalr = 4, |
| 181 | rv_op_beq = 5, |
| 182 | rv_op_bne = 6, |
| 183 | rv_op_blt = 7, |
| 184 | rv_op_bge = 8, |
| 185 | rv_op_bltu = 9, |
| 186 | rv_op_bgeu = 10, |
| 187 | rv_op_lb = 11, |
| 188 | rv_op_lh = 12, |
| 189 | rv_op_lw = 13, |
| 190 | rv_op_lbu = 14, |
| 191 | rv_op_lhu = 15, |
| 192 | rv_op_sb = 16, |
| 193 | rv_op_sh = 17, |
| 194 | rv_op_sw = 18, |
| 195 | rv_op_addi = 19, |
| 196 | rv_op_slti = 20, |
| 197 | rv_op_sltiu = 21, |
| 198 | rv_op_xori = 22, |
| 199 | rv_op_ori = 23, |
| 200 | rv_op_andi = 24, |
| 201 | rv_op_slli = 25, |
| 202 | rv_op_srli = 26, |
| 203 | rv_op_srai = 27, |
| 204 | rv_op_add = 28, |
| 205 | rv_op_sub = 29, |
| 206 | rv_op_sll = 30, |
| 207 | rv_op_slt = 31, |
| 208 | rv_op_sltu = 32, |
| 209 | rv_op_xor = 33, |
| 210 | rv_op_srl = 34, |
| 211 | rv_op_sra = 35, |
| 212 | rv_op_or = 36, |
| 213 | rv_op_and = 37, |
| 214 | rv_op_fence = 38, |
| 215 | rv_op_fence_i = 39, |
| 216 | rv_op_lwu = 40, |
| 217 | rv_op_ld = 41, |
| 218 | rv_op_sd = 42, |
| 219 | rv_op_addiw = 43, |
| 220 | rv_op_slliw = 44, |
| 221 | rv_op_srliw = 45, |
| 222 | rv_op_sraiw = 46, |
| 223 | rv_op_addw = 47, |
| 224 | rv_op_subw = 48, |
| 225 | rv_op_sllw = 49, |
| 226 | rv_op_srlw = 50, |
| 227 | rv_op_sraw = 51, |
| 228 | rv_op_ldu = 52, |
| 229 | rv_op_lq = 53, |
| 230 | rv_op_sq = 54, |
| 231 | rv_op_addid = 55, |
| 232 | rv_op_sllid = 56, |
| 233 | rv_op_srlid = 57, |
| 234 | rv_op_sraid = 58, |
| 235 | rv_op_addd = 59, |
| 236 | rv_op_subd = 60, |
| 237 | rv_op_slld = 61, |
| 238 | rv_op_srld = 62, |
| 239 | rv_op_srad = 63, |
| 240 | rv_op_mul = 64, |
| 241 | rv_op_mulh = 65, |
| 242 | rv_op_mulhsu = 66, |
| 243 | rv_op_mulhu = 67, |
| 244 | rv_op_div = 68, |
| 245 | rv_op_divu = 69, |
| 246 | rv_op_rem = 70, |
| 247 | rv_op_remu = 71, |
| 248 | rv_op_mulw = 72, |
| 249 | rv_op_divw = 73, |
| 250 | rv_op_divuw = 74, |
| 251 | rv_op_remw = 75, |
| 252 | rv_op_remuw = 76, |
| 253 | rv_op_muld = 77, |
| 254 | rv_op_divd = 78, |
| 255 | rv_op_divud = 79, |
| 256 | rv_op_remd = 80, |
| 257 | rv_op_remud = 81, |
| 258 | rv_op_lr_w = 82, |
| 259 | rv_op_sc_w = 83, |
| 260 | rv_op_amoswap_w = 84, |
| 261 | rv_op_amoadd_w = 85, |
| 262 | rv_op_amoxor_w = 86, |
| 263 | rv_op_amoor_w = 87, |
| 264 | rv_op_amoand_w = 88, |
| 265 | rv_op_amomin_w = 89, |
| 266 | rv_op_amomax_w = 90, |
| 267 | rv_op_amominu_w = 91, |
| 268 | rv_op_amomaxu_w = 92, |
| 269 | rv_op_lr_d = 93, |
| 270 | rv_op_sc_d = 94, |
| 271 | rv_op_amoswap_d = 95, |
| 272 | rv_op_amoadd_d = 96, |
| 273 | rv_op_amoxor_d = 97, |
| 274 | rv_op_amoor_d = 98, |
| 275 | rv_op_amoand_d = 99, |
| 276 | rv_op_amomin_d = 100, |
| 277 | rv_op_amomax_d = 101, |
| 278 | rv_op_amominu_d = 102, |
| 279 | rv_op_amomaxu_d = 103, |
| 280 | rv_op_lr_q = 104, |
| 281 | rv_op_sc_q = 105, |
| 282 | rv_op_amoswap_q = 106, |
| 283 | rv_op_amoadd_q = 107, |
| 284 | rv_op_amoxor_q = 108, |
| 285 | rv_op_amoor_q = 109, |
| 286 | rv_op_amoand_q = 110, |
| 287 | rv_op_amomin_q = 111, |
| 288 | rv_op_amomax_q = 112, |
| 289 | rv_op_amominu_q = 113, |
| 290 | rv_op_amomaxu_q = 114, |
| 291 | rv_op_ecall = 115, |
| 292 | rv_op_ebreak = 116, |
| 293 | rv_op_uret = 117, |
| 294 | rv_op_sret = 118, |
| 295 | rv_op_hret = 119, |
| 296 | rv_op_mret = 120, |
| 297 | rv_op_dret = 121, |
| 298 | rv_op_sfence_vm = 122, |
| 299 | rv_op_sfence_vma = 123, |
| 300 | rv_op_wfi = 124, |
| 301 | rv_op_csrrw = 125, |
| 302 | rv_op_csrrs = 126, |
| 303 | rv_op_csrrc = 127, |
| 304 | rv_op_csrrwi = 128, |
| 305 | rv_op_csrrsi = 129, |
| 306 | rv_op_csrrci = 130, |
| 307 | rv_op_flw = 131, |
| 308 | rv_op_fsw = 132, |
| 309 | rv_op_fmadd_s = 133, |
| 310 | rv_op_fmsub_s = 134, |
| 311 | rv_op_fnmsub_s = 135, |
| 312 | rv_op_fnmadd_s = 136, |
| 313 | rv_op_fadd_s = 137, |
| 314 | rv_op_fsub_s = 138, |
| 315 | rv_op_fmul_s = 139, |
| 316 | rv_op_fdiv_s = 140, |
| 317 | rv_op_fsgnj_s = 141, |
| 318 | rv_op_fsgnjn_s = 142, |
| 319 | rv_op_fsgnjx_s = 143, |
| 320 | rv_op_fmin_s = 144, |
| 321 | rv_op_fmax_s = 145, |
| 322 | rv_op_fsqrt_s = 146, |
| 323 | rv_op_fle_s = 147, |
| 324 | rv_op_flt_s = 148, |
| 325 | rv_op_feq_s = 149, |
| 326 | rv_op_fcvt_w_s = 150, |
| 327 | rv_op_fcvt_wu_s = 151, |
| 328 | rv_op_fcvt_s_w = 152, |
| 329 | rv_op_fcvt_s_wu = 153, |
| 330 | rv_op_fmv_x_s = 154, |
| 331 | rv_op_fclass_s = 155, |
| 332 | rv_op_fmv_s_x = 156, |
| 333 | rv_op_fcvt_l_s = 157, |
| 334 | rv_op_fcvt_lu_s = 158, |
| 335 | rv_op_fcvt_s_l = 159, |
| 336 | rv_op_fcvt_s_lu = 160, |
| 337 | rv_op_fld = 161, |
| 338 | rv_op_fsd = 162, |
| 339 | rv_op_fmadd_d = 163, |
| 340 | rv_op_fmsub_d = 164, |
| 341 | rv_op_fnmsub_d = 165, |
| 342 | rv_op_fnmadd_d = 166, |
| 343 | rv_op_fadd_d = 167, |
| 344 | rv_op_fsub_d = 168, |
| 345 | rv_op_fmul_d = 169, |
| 346 | rv_op_fdiv_d = 170, |
| 347 | rv_op_fsgnj_d = 171, |
| 348 | rv_op_fsgnjn_d = 172, |
| 349 | rv_op_fsgnjx_d = 173, |
| 350 | rv_op_fmin_d = 174, |
| 351 | rv_op_fmax_d = 175, |
| 352 | rv_op_fcvt_s_d = 176, |
| 353 | rv_op_fcvt_d_s = 177, |
| 354 | rv_op_fsqrt_d = 178, |
| 355 | rv_op_fle_d = 179, |
| 356 | rv_op_flt_d = 180, |
| 357 | rv_op_feq_d = 181, |
| 358 | rv_op_fcvt_w_d = 182, |
| 359 | rv_op_fcvt_wu_d = 183, |
| 360 | rv_op_fcvt_d_w = 184, |
| 361 | rv_op_fcvt_d_wu = 185, |
| 362 | rv_op_fclass_d = 186, |
| 363 | rv_op_fcvt_l_d = 187, |
| 364 | rv_op_fcvt_lu_d = 188, |
| 365 | rv_op_fmv_x_d = 189, |
| 366 | rv_op_fcvt_d_l = 190, |
| 367 | rv_op_fcvt_d_lu = 191, |
| 368 | rv_op_fmv_d_x = 192, |
| 369 | rv_op_flq = 193, |
| 370 | rv_op_fsq = 194, |
| 371 | rv_op_fmadd_q = 195, |
| 372 | rv_op_fmsub_q = 196, |
| 373 | rv_op_fnmsub_q = 197, |
| 374 | rv_op_fnmadd_q = 198, |
| 375 | rv_op_fadd_q = 199, |
| 376 | rv_op_fsub_q = 200, |
| 377 | rv_op_fmul_q = 201, |
| 378 | rv_op_fdiv_q = 202, |
| 379 | rv_op_fsgnj_q = 203, |
| 380 | rv_op_fsgnjn_q = 204, |
| 381 | rv_op_fsgnjx_q = 205, |
| 382 | rv_op_fmin_q = 206, |
| 383 | rv_op_fmax_q = 207, |
| 384 | rv_op_fcvt_s_q = 208, |
| 385 | rv_op_fcvt_q_s = 209, |
| 386 | rv_op_fcvt_d_q = 210, |
| 387 | rv_op_fcvt_q_d = 211, |
| 388 | rv_op_fsqrt_q = 212, |
| 389 | rv_op_fle_q = 213, |
| 390 | rv_op_flt_q = 214, |
| 391 | rv_op_feq_q = 215, |
| 392 | rv_op_fcvt_w_q = 216, |
| 393 | rv_op_fcvt_wu_q = 217, |
| 394 | rv_op_fcvt_q_w = 218, |
| 395 | rv_op_fcvt_q_wu = 219, |
| 396 | rv_op_fclass_q = 220, |
| 397 | rv_op_fcvt_l_q = 221, |
| 398 | rv_op_fcvt_lu_q = 222, |
| 399 | rv_op_fcvt_q_l = 223, |
| 400 | rv_op_fcvt_q_lu = 224, |
| 401 | rv_op_fmv_x_q = 225, |
| 402 | rv_op_fmv_q_x = 226, |
| 403 | rv_op_c_addi4spn = 227, |
| 404 | rv_op_c_fld = 228, |
| 405 | rv_op_c_lw = 229, |
| 406 | rv_op_c_flw = 230, |
| 407 | rv_op_c_fsd = 231, |
| 408 | rv_op_c_sw = 232, |
| 409 | rv_op_c_fsw = 233, |
| 410 | rv_op_c_nop = 234, |
| 411 | rv_op_c_addi = 235, |
| 412 | rv_op_c_jal = 236, |
| 413 | rv_op_c_li = 237, |
| 414 | rv_op_c_addi16sp = 238, |
| 415 | rv_op_c_lui = 239, |
| 416 | rv_op_c_srli = 240, |
| 417 | rv_op_c_srai = 241, |
| 418 | rv_op_c_andi = 242, |
| 419 | rv_op_c_sub = 243, |
| 420 | rv_op_c_xor = 244, |
| 421 | rv_op_c_or = 245, |
| 422 | rv_op_c_and = 246, |
| 423 | rv_op_c_subw = 247, |
| 424 | rv_op_c_addw = 248, |
| 425 | rv_op_c_j = 249, |
| 426 | rv_op_c_beqz = 250, |
| 427 | rv_op_c_bnez = 251, |
| 428 | rv_op_c_slli = 252, |
| 429 | rv_op_c_fldsp = 253, |
| 430 | rv_op_c_lwsp = 254, |
| 431 | rv_op_c_flwsp = 255, |
| 432 | rv_op_c_jr = 256, |
| 433 | rv_op_c_mv = 257, |
| 434 | rv_op_c_ebreak = 258, |
| 435 | rv_op_c_jalr = 259, |
| 436 | rv_op_c_add = 260, |
| 437 | rv_op_c_fsdsp = 261, |
| 438 | rv_op_c_swsp = 262, |
| 439 | rv_op_c_fswsp = 263, |
| 440 | rv_op_c_ld = 264, |
| 441 | rv_op_c_sd = 265, |
| 442 | rv_op_c_addiw = 266, |
| 443 | rv_op_c_ldsp = 267, |
| 444 | rv_op_c_sdsp = 268, |
| 445 | rv_op_c_lq = 269, |
| 446 | rv_op_c_sq = 270, |
| 447 | rv_op_c_lqsp = 271, |
| 448 | rv_op_c_sqsp = 272, |
| 449 | rv_op_nop = 273, |
| 450 | rv_op_mv = 274, |
| 451 | rv_op_not = 275, |
| 452 | rv_op_neg = 276, |
| 453 | rv_op_negw = 277, |
| 454 | rv_op_sext_w = 278, |
| 455 | rv_op_seqz = 279, |
| 456 | rv_op_snez = 280, |
| 457 | rv_op_sltz = 281, |
| 458 | rv_op_sgtz = 282, |
| 459 | rv_op_fmv_s = 283, |
| 460 | rv_op_fabs_s = 284, |
| 461 | rv_op_fneg_s = 285, |
| 462 | rv_op_fmv_d = 286, |
| 463 | rv_op_fabs_d = 287, |
| 464 | rv_op_fneg_d = 288, |
| 465 | rv_op_fmv_q = 289, |
| 466 | rv_op_fabs_q = 290, |
| 467 | rv_op_fneg_q = 291, |
| 468 | rv_op_beqz = 292, |
| 469 | rv_op_bnez = 293, |
| 470 | rv_op_blez = 294, |
| 471 | rv_op_bgez = 295, |
| 472 | rv_op_bltz = 296, |
| 473 | rv_op_bgtz = 297, |
| 474 | rv_op_ble = 298, |
| 475 | rv_op_bleu = 299, |
| 476 | rv_op_bgt = 300, |
| 477 | rv_op_bgtu = 301, |
| 478 | rv_op_j = 302, |
| 479 | rv_op_ret = 303, |
| 480 | rv_op_jr = 304, |
| 481 | rv_op_rdcycle = 305, |
| 482 | rv_op_rdtime = 306, |
| 483 | rv_op_rdinstret = 307, |
| 484 | rv_op_rdcycleh = 308, |
| 485 | rv_op_rdtimeh = 309, |
| 486 | rv_op_rdinstreth = 310, |
| 487 | rv_op_frcsr = 311, |
| 488 | rv_op_frrm = 312, |
| 489 | rv_op_frflags = 313, |
| 490 | rv_op_fscsr = 314, |
| 491 | rv_op_fsrm = 315, |
| 492 | rv_op_fsflags = 316, |
| 493 | rv_op_fsrmi = 317, |
| 494 | rv_op_fsflagsi = 318, |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 495 | rv_op_bseti = 319, |
| 496 | rv_op_bclri = 320, |
| 497 | rv_op_binvi = 321, |
| 498 | rv_op_bexti = 322, |
| 499 | rv_op_rori = 323, |
| 500 | rv_op_clz = 324, |
| 501 | rv_op_ctz = 325, |
| 502 | rv_op_cpop = 326, |
| 503 | rv_op_sext_h = 327, |
| 504 | rv_op_sext_b = 328, |
| 505 | rv_op_xnor = 329, |
| 506 | rv_op_orn = 330, |
| 507 | rv_op_andn = 331, |
| 508 | rv_op_rol = 332, |
| 509 | rv_op_ror = 333, |
| 510 | rv_op_sh1add = 334, |
| 511 | rv_op_sh2add = 335, |
| 512 | rv_op_sh3add = 336, |
| 513 | rv_op_sh1add_uw = 337, |
| 514 | rv_op_sh2add_uw = 338, |
| 515 | rv_op_sh3add_uw = 339, |
| 516 | rv_op_clmul = 340, |
| 517 | rv_op_clmulr = 341, |
| 518 | rv_op_clmulh = 342, |
| 519 | rv_op_min = 343, |
| 520 | rv_op_minu = 344, |
| 521 | rv_op_max = 345, |
| 522 | rv_op_maxu = 346, |
| 523 | rv_op_clzw = 347, |
| 524 | rv_op_ctzw = 348, |
| 525 | rv_op_cpopw = 349, |
| 526 | rv_op_slli_uw = 350, |
| 527 | rv_op_add_uw = 351, |
| 528 | rv_op_rolw = 352, |
| 529 | rv_op_rorw = 353, |
| 530 | rv_op_rev8 = 354, |
| 531 | rv_op_zext_h = 355, |
| 532 | rv_op_roriw = 356, |
| 533 | rv_op_orc_b = 357, |
| 534 | rv_op_bset = 358, |
| 535 | rv_op_bclr = 359, |
| 536 | rv_op_binv = 360, |
| 537 | rv_op_bext = 361, |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 538 | rv_op_aes32esmi = 362, |
| 539 | rv_op_aes32esi = 363, |
| 540 | rv_op_aes32dsmi = 364, |
| 541 | rv_op_aes32dsi = 365, |
| 542 | rv_op_aes64ks1i = 366, |
| 543 | rv_op_aes64ks2 = 367, |
| 544 | rv_op_aes64im = 368, |
| 545 | rv_op_aes64esm = 369, |
| 546 | rv_op_aes64es = 370, |
| 547 | rv_op_aes64dsm = 371, |
| 548 | rv_op_aes64ds = 372, |
| 549 | rv_op_sha256sig0 = 373, |
| 550 | rv_op_sha256sig1 = 374, |
| 551 | rv_op_sha256sum0 = 375, |
| 552 | rv_op_sha256sum1 = 376, |
| 553 | rv_op_sha512sig0 = 377, |
| 554 | rv_op_sha512sig1 = 378, |
| 555 | rv_op_sha512sum0 = 379, |
| 556 | rv_op_sha512sum1 = 380, |
| 557 | rv_op_sha512sum0r = 381, |
| 558 | rv_op_sha512sum1r = 382, |
| 559 | rv_op_sha512sig0l = 383, |
| 560 | rv_op_sha512sig0h = 384, |
| 561 | rv_op_sha512sig1l = 385, |
| 562 | rv_op_sha512sig1h = 386, |
| 563 | rv_op_sm3p0 = 387, |
| 564 | rv_op_sm3p1 = 388, |
| 565 | rv_op_sm4ed = 389, |
| 566 | rv_op_sm4ks = 390, |
| 567 | rv_op_brev8 = 391, |
| 568 | rv_op_pack = 392, |
| 569 | rv_op_packh = 393, |
| 570 | rv_op_packw = 394, |
| 571 | rv_op_unzip = 395, |
| 572 | rv_op_zip = 396, |
| 573 | rv_op_xperm4 = 397, |
| 574 | rv_op_xperm8 = 398, |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 575 | rv_op_vle8_v = 399, |
| 576 | rv_op_vle16_v = 400, |
| 577 | rv_op_vle32_v = 401, |
| 578 | rv_op_vle64_v = 402, |
| 579 | rv_op_vse8_v = 403, |
| 580 | rv_op_vse16_v = 404, |
| 581 | rv_op_vse32_v = 405, |
| 582 | rv_op_vse64_v = 406, |
| 583 | rv_op_vlm_v = 407, |
| 584 | rv_op_vsm_v = 408, |
| 585 | rv_op_vlse8_v = 409, |
| 586 | rv_op_vlse16_v = 410, |
| 587 | rv_op_vlse32_v = 411, |
| 588 | rv_op_vlse64_v = 412, |
| 589 | rv_op_vsse8_v = 413, |
| 590 | rv_op_vsse16_v = 414, |
| 591 | rv_op_vsse32_v = 415, |
| 592 | rv_op_vsse64_v = 416, |
| 593 | rv_op_vluxei8_v = 417, |
| 594 | rv_op_vluxei16_v = 418, |
| 595 | rv_op_vluxei32_v = 419, |
| 596 | rv_op_vluxei64_v = 420, |
| 597 | rv_op_vloxei8_v = 421, |
| 598 | rv_op_vloxei16_v = 422, |
| 599 | rv_op_vloxei32_v = 423, |
| 600 | rv_op_vloxei64_v = 424, |
| 601 | rv_op_vsuxei8_v = 425, |
| 602 | rv_op_vsuxei16_v = 426, |
| 603 | rv_op_vsuxei32_v = 427, |
| 604 | rv_op_vsuxei64_v = 428, |
| 605 | rv_op_vsoxei8_v = 429, |
| 606 | rv_op_vsoxei16_v = 430, |
| 607 | rv_op_vsoxei32_v = 431, |
| 608 | rv_op_vsoxei64_v = 432, |
| 609 | rv_op_vle8ff_v = 433, |
| 610 | rv_op_vle16ff_v = 434, |
| 611 | rv_op_vle32ff_v = 435, |
| 612 | rv_op_vle64ff_v = 436, |
| 613 | rv_op_vl1re8_v = 437, |
| 614 | rv_op_vl1re16_v = 438, |
| 615 | rv_op_vl1re32_v = 439, |
| 616 | rv_op_vl1re64_v = 440, |
| 617 | rv_op_vl2re8_v = 441, |
| 618 | rv_op_vl2re16_v = 442, |
| 619 | rv_op_vl2re32_v = 443, |
| 620 | rv_op_vl2re64_v = 444, |
| 621 | rv_op_vl4re8_v = 445, |
| 622 | rv_op_vl4re16_v = 446, |
| 623 | rv_op_vl4re32_v = 447, |
| 624 | rv_op_vl4re64_v = 448, |
| 625 | rv_op_vl8re8_v = 449, |
| 626 | rv_op_vl8re16_v = 450, |
| 627 | rv_op_vl8re32_v = 451, |
| 628 | rv_op_vl8re64_v = 452, |
| 629 | rv_op_vs1r_v = 453, |
| 630 | rv_op_vs2r_v = 454, |
| 631 | rv_op_vs4r_v = 455, |
| 632 | rv_op_vs8r_v = 456, |
| 633 | rv_op_vadd_vv = 457, |
| 634 | rv_op_vadd_vx = 458, |
| 635 | rv_op_vadd_vi = 459, |
| 636 | rv_op_vsub_vv = 460, |
| 637 | rv_op_vsub_vx = 461, |
| 638 | rv_op_vrsub_vx = 462, |
| 639 | rv_op_vrsub_vi = 463, |
| 640 | rv_op_vwaddu_vv = 464, |
| 641 | rv_op_vwaddu_vx = 465, |
| 642 | rv_op_vwadd_vv = 466, |
| 643 | rv_op_vwadd_vx = 467, |
| 644 | rv_op_vwsubu_vv = 468, |
| 645 | rv_op_vwsubu_vx = 469, |
| 646 | rv_op_vwsub_vv = 470, |
| 647 | rv_op_vwsub_vx = 471, |
| 648 | rv_op_vwaddu_wv = 472, |
| 649 | rv_op_vwaddu_wx = 473, |
| 650 | rv_op_vwadd_wv = 474, |
| 651 | rv_op_vwadd_wx = 475, |
| 652 | rv_op_vwsubu_wv = 476, |
| 653 | rv_op_vwsubu_wx = 477, |
| 654 | rv_op_vwsub_wv = 478, |
| 655 | rv_op_vwsub_wx = 479, |
| 656 | rv_op_vadc_vvm = 480, |
| 657 | rv_op_vadc_vxm = 481, |
| 658 | rv_op_vadc_vim = 482, |
| 659 | rv_op_vmadc_vvm = 483, |
| 660 | rv_op_vmadc_vxm = 484, |
| 661 | rv_op_vmadc_vim = 485, |
| 662 | rv_op_vsbc_vvm = 486, |
| 663 | rv_op_vsbc_vxm = 487, |
| 664 | rv_op_vmsbc_vvm = 488, |
| 665 | rv_op_vmsbc_vxm = 489, |
| 666 | rv_op_vand_vv = 490, |
| 667 | rv_op_vand_vx = 491, |
| 668 | rv_op_vand_vi = 492, |
| 669 | rv_op_vor_vv = 493, |
| 670 | rv_op_vor_vx = 494, |
| 671 | rv_op_vor_vi = 495, |
| 672 | rv_op_vxor_vv = 496, |
| 673 | rv_op_vxor_vx = 497, |
| 674 | rv_op_vxor_vi = 498, |
| 675 | rv_op_vsll_vv = 499, |
| 676 | rv_op_vsll_vx = 500, |
| 677 | rv_op_vsll_vi = 501, |
| 678 | rv_op_vsrl_vv = 502, |
| 679 | rv_op_vsrl_vx = 503, |
| 680 | rv_op_vsrl_vi = 504, |
| 681 | rv_op_vsra_vv = 505, |
| 682 | rv_op_vsra_vx = 506, |
| 683 | rv_op_vsra_vi = 507, |
| 684 | rv_op_vnsrl_wv = 508, |
| 685 | rv_op_vnsrl_wx = 509, |
| 686 | rv_op_vnsrl_wi = 510, |
| 687 | rv_op_vnsra_wv = 511, |
| 688 | rv_op_vnsra_wx = 512, |
| 689 | rv_op_vnsra_wi = 513, |
| 690 | rv_op_vmseq_vv = 514, |
| 691 | rv_op_vmseq_vx = 515, |
| 692 | rv_op_vmseq_vi = 516, |
| 693 | rv_op_vmsne_vv = 517, |
| 694 | rv_op_vmsne_vx = 518, |
| 695 | rv_op_vmsne_vi = 519, |
| 696 | rv_op_vmsltu_vv = 520, |
| 697 | rv_op_vmsltu_vx = 521, |
| 698 | rv_op_vmslt_vv = 522, |
| 699 | rv_op_vmslt_vx = 523, |
| 700 | rv_op_vmsleu_vv = 524, |
| 701 | rv_op_vmsleu_vx = 525, |
| 702 | rv_op_vmsleu_vi = 526, |
| 703 | rv_op_vmsle_vv = 527, |
| 704 | rv_op_vmsle_vx = 528, |
| 705 | rv_op_vmsle_vi = 529, |
| 706 | rv_op_vmsgtu_vx = 530, |
| 707 | rv_op_vmsgtu_vi = 531, |
| 708 | rv_op_vmsgt_vx = 532, |
| 709 | rv_op_vmsgt_vi = 533, |
| 710 | rv_op_vminu_vv = 534, |
| 711 | rv_op_vminu_vx = 535, |
| 712 | rv_op_vmin_vv = 536, |
| 713 | rv_op_vmin_vx = 537, |
| 714 | rv_op_vmaxu_vv = 538, |
| 715 | rv_op_vmaxu_vx = 539, |
| 716 | rv_op_vmax_vv = 540, |
| 717 | rv_op_vmax_vx = 541, |
| 718 | rv_op_vmul_vv = 542, |
| 719 | rv_op_vmul_vx = 543, |
| 720 | rv_op_vmulh_vv = 544, |
| 721 | rv_op_vmulh_vx = 545, |
| 722 | rv_op_vmulhu_vv = 546, |
| 723 | rv_op_vmulhu_vx = 547, |
| 724 | rv_op_vmulhsu_vv = 548, |
| 725 | rv_op_vmulhsu_vx = 549, |
| 726 | rv_op_vdivu_vv = 550, |
| 727 | rv_op_vdivu_vx = 551, |
| 728 | rv_op_vdiv_vv = 552, |
| 729 | rv_op_vdiv_vx = 553, |
| 730 | rv_op_vremu_vv = 554, |
| 731 | rv_op_vremu_vx = 555, |
| 732 | rv_op_vrem_vv = 556, |
| 733 | rv_op_vrem_vx = 557, |
| 734 | rv_op_vwmulu_vv = 558, |
| 735 | rv_op_vwmulu_vx = 559, |
| 736 | rv_op_vwmulsu_vv = 560, |
| 737 | rv_op_vwmulsu_vx = 561, |
| 738 | rv_op_vwmul_vv = 562, |
| 739 | rv_op_vwmul_vx = 563, |
| 740 | rv_op_vmacc_vv = 564, |
| 741 | rv_op_vmacc_vx = 565, |
| 742 | rv_op_vnmsac_vv = 566, |
| 743 | rv_op_vnmsac_vx = 567, |
| 744 | rv_op_vmadd_vv = 568, |
| 745 | rv_op_vmadd_vx = 569, |
| 746 | rv_op_vnmsub_vv = 570, |
| 747 | rv_op_vnmsub_vx = 571, |
| 748 | rv_op_vwmaccu_vv = 572, |
| 749 | rv_op_vwmaccu_vx = 573, |
| 750 | rv_op_vwmacc_vv = 574, |
| 751 | rv_op_vwmacc_vx = 575, |
| 752 | rv_op_vwmaccsu_vv = 576, |
| 753 | rv_op_vwmaccsu_vx = 577, |
| 754 | rv_op_vwmaccus_vx = 578, |
| 755 | rv_op_vmv_v_v = 579, |
| 756 | rv_op_vmv_v_x = 580, |
| 757 | rv_op_vmv_v_i = 581, |
| 758 | rv_op_vmerge_vvm = 582, |
| 759 | rv_op_vmerge_vxm = 583, |
| 760 | rv_op_vmerge_vim = 584, |
| 761 | rv_op_vsaddu_vv = 585, |
| 762 | rv_op_vsaddu_vx = 586, |
| 763 | rv_op_vsaddu_vi = 587, |
| 764 | rv_op_vsadd_vv = 588, |
| 765 | rv_op_vsadd_vx = 589, |
| 766 | rv_op_vsadd_vi = 590, |
| 767 | rv_op_vssubu_vv = 591, |
| 768 | rv_op_vssubu_vx = 592, |
| 769 | rv_op_vssub_vv = 593, |
| 770 | rv_op_vssub_vx = 594, |
| 771 | rv_op_vaadd_vv = 595, |
| 772 | rv_op_vaadd_vx = 596, |
| 773 | rv_op_vaaddu_vv = 597, |
| 774 | rv_op_vaaddu_vx = 598, |
| 775 | rv_op_vasub_vv = 599, |
| 776 | rv_op_vasub_vx = 600, |
| 777 | rv_op_vasubu_vv = 601, |
| 778 | rv_op_vasubu_vx = 602, |
| 779 | rv_op_vsmul_vv = 603, |
| 780 | rv_op_vsmul_vx = 604, |
| 781 | rv_op_vssrl_vv = 605, |
| 782 | rv_op_vssrl_vx = 606, |
| 783 | rv_op_vssrl_vi = 607, |
| 784 | rv_op_vssra_vv = 608, |
| 785 | rv_op_vssra_vx = 609, |
| 786 | rv_op_vssra_vi = 610, |
| 787 | rv_op_vnclipu_wv = 611, |
| 788 | rv_op_vnclipu_wx = 612, |
| 789 | rv_op_vnclipu_wi = 613, |
| 790 | rv_op_vnclip_wv = 614, |
| 791 | rv_op_vnclip_wx = 615, |
| 792 | rv_op_vnclip_wi = 616, |
| 793 | rv_op_vfadd_vv = 617, |
| 794 | rv_op_vfadd_vf = 618, |
| 795 | rv_op_vfsub_vv = 619, |
| 796 | rv_op_vfsub_vf = 620, |
| 797 | rv_op_vfrsub_vf = 621, |
| 798 | rv_op_vfwadd_vv = 622, |
| 799 | rv_op_vfwadd_vf = 623, |
| 800 | rv_op_vfwadd_wv = 624, |
| 801 | rv_op_vfwadd_wf = 625, |
| 802 | rv_op_vfwsub_vv = 626, |
| 803 | rv_op_vfwsub_vf = 627, |
| 804 | rv_op_vfwsub_wv = 628, |
| 805 | rv_op_vfwsub_wf = 629, |
| 806 | rv_op_vfmul_vv = 630, |
| 807 | rv_op_vfmul_vf = 631, |
| 808 | rv_op_vfdiv_vv = 632, |
| 809 | rv_op_vfdiv_vf = 633, |
| 810 | rv_op_vfrdiv_vf = 634, |
| 811 | rv_op_vfwmul_vv = 635, |
| 812 | rv_op_vfwmul_vf = 636, |
| 813 | rv_op_vfmacc_vv = 637, |
| 814 | rv_op_vfmacc_vf = 638, |
| 815 | rv_op_vfnmacc_vv = 639, |
| 816 | rv_op_vfnmacc_vf = 640, |
| 817 | rv_op_vfmsac_vv = 641, |
| 818 | rv_op_vfmsac_vf = 642, |
| 819 | rv_op_vfnmsac_vv = 643, |
| 820 | rv_op_vfnmsac_vf = 644, |
| 821 | rv_op_vfmadd_vv = 645, |
| 822 | rv_op_vfmadd_vf = 646, |
| 823 | rv_op_vfnmadd_vv = 647, |
| 824 | rv_op_vfnmadd_vf = 648, |
| 825 | rv_op_vfmsub_vv = 649, |
| 826 | rv_op_vfmsub_vf = 650, |
| 827 | rv_op_vfnmsub_vv = 651, |
| 828 | rv_op_vfnmsub_vf = 652, |
| 829 | rv_op_vfwmacc_vv = 653, |
| 830 | rv_op_vfwmacc_vf = 654, |
| 831 | rv_op_vfwnmacc_vv = 655, |
| 832 | rv_op_vfwnmacc_vf = 656, |
| 833 | rv_op_vfwmsac_vv = 657, |
| 834 | rv_op_vfwmsac_vf = 658, |
| 835 | rv_op_vfwnmsac_vv = 659, |
| 836 | rv_op_vfwnmsac_vf = 660, |
| 837 | rv_op_vfsqrt_v = 661, |
| 838 | rv_op_vfrsqrt7_v = 662, |
| 839 | rv_op_vfrec7_v = 663, |
| 840 | rv_op_vfmin_vv = 664, |
| 841 | rv_op_vfmin_vf = 665, |
| 842 | rv_op_vfmax_vv = 666, |
| 843 | rv_op_vfmax_vf = 667, |
| 844 | rv_op_vfsgnj_vv = 668, |
| 845 | rv_op_vfsgnj_vf = 669, |
| 846 | rv_op_vfsgnjn_vv = 670, |
| 847 | rv_op_vfsgnjn_vf = 671, |
| 848 | rv_op_vfsgnjx_vv = 672, |
| 849 | rv_op_vfsgnjx_vf = 673, |
| 850 | rv_op_vfslide1up_vf = 674, |
| 851 | rv_op_vfslide1down_vf = 675, |
| 852 | rv_op_vmfeq_vv = 676, |
| 853 | rv_op_vmfeq_vf = 677, |
| 854 | rv_op_vmfne_vv = 678, |
| 855 | rv_op_vmfne_vf = 679, |
| 856 | rv_op_vmflt_vv = 680, |
| 857 | rv_op_vmflt_vf = 681, |
| 858 | rv_op_vmfle_vv = 682, |
| 859 | rv_op_vmfle_vf = 683, |
| 860 | rv_op_vmfgt_vf = 684, |
| 861 | rv_op_vmfge_vf = 685, |
| 862 | rv_op_vfclass_v = 686, |
| 863 | rv_op_vfmerge_vfm = 687, |
| 864 | rv_op_vfmv_v_f = 688, |
| 865 | rv_op_vfcvt_xu_f_v = 689, |
| 866 | rv_op_vfcvt_x_f_v = 690, |
| 867 | rv_op_vfcvt_f_xu_v = 691, |
| 868 | rv_op_vfcvt_f_x_v = 692, |
| 869 | rv_op_vfcvt_rtz_xu_f_v = 693, |
| 870 | rv_op_vfcvt_rtz_x_f_v = 694, |
| 871 | rv_op_vfwcvt_xu_f_v = 695, |
| 872 | rv_op_vfwcvt_x_f_v = 696, |
| 873 | rv_op_vfwcvt_f_xu_v = 697, |
| 874 | rv_op_vfwcvt_f_x_v = 698, |
| 875 | rv_op_vfwcvt_f_f_v = 699, |
| 876 | rv_op_vfwcvt_rtz_xu_f_v = 700, |
| 877 | rv_op_vfwcvt_rtz_x_f_v = 701, |
| 878 | rv_op_vfncvt_xu_f_w = 702, |
| 879 | rv_op_vfncvt_x_f_w = 703, |
| 880 | rv_op_vfncvt_f_xu_w = 704, |
| 881 | rv_op_vfncvt_f_x_w = 705, |
| 882 | rv_op_vfncvt_f_f_w = 706, |
| 883 | rv_op_vfncvt_rod_f_f_w = 707, |
| 884 | rv_op_vfncvt_rtz_xu_f_w = 708, |
| 885 | rv_op_vfncvt_rtz_x_f_w = 709, |
| 886 | rv_op_vredsum_vs = 710, |
| 887 | rv_op_vredand_vs = 711, |
| 888 | rv_op_vredor_vs = 712, |
| 889 | rv_op_vredxor_vs = 713, |
| 890 | rv_op_vredminu_vs = 714, |
| 891 | rv_op_vredmin_vs = 715, |
| 892 | rv_op_vredmaxu_vs = 716, |
| 893 | rv_op_vredmax_vs = 717, |
| 894 | rv_op_vwredsumu_vs = 718, |
| 895 | rv_op_vwredsum_vs = 719, |
| 896 | rv_op_vfredusum_vs = 720, |
| 897 | rv_op_vfredosum_vs = 721, |
| 898 | rv_op_vfredmin_vs = 722, |
| 899 | rv_op_vfredmax_vs = 723, |
| 900 | rv_op_vfwredusum_vs = 724, |
| 901 | rv_op_vfwredosum_vs = 725, |
| 902 | rv_op_vmand_mm = 726, |
| 903 | rv_op_vmnand_mm = 727, |
| 904 | rv_op_vmandn_mm = 728, |
| 905 | rv_op_vmxor_mm = 729, |
| 906 | rv_op_vmor_mm = 730, |
| 907 | rv_op_vmnor_mm = 731, |
| 908 | rv_op_vmorn_mm = 732, |
| 909 | rv_op_vmxnor_mm = 733, |
| 910 | rv_op_vcpop_m = 734, |
| 911 | rv_op_vfirst_m = 735, |
| 912 | rv_op_vmsbf_m = 736, |
| 913 | rv_op_vmsif_m = 737, |
| 914 | rv_op_vmsof_m = 738, |
| 915 | rv_op_viota_m = 739, |
| 916 | rv_op_vid_v = 740, |
| 917 | rv_op_vmv_x_s = 741, |
| 918 | rv_op_vmv_s_x = 742, |
| 919 | rv_op_vfmv_f_s = 743, |
| 920 | rv_op_vfmv_s_f = 744, |
| 921 | rv_op_vslideup_vx = 745, |
| 922 | rv_op_vslideup_vi = 746, |
| 923 | rv_op_vslide1up_vx = 747, |
| 924 | rv_op_vslidedown_vx = 748, |
| 925 | rv_op_vslidedown_vi = 749, |
| 926 | rv_op_vslide1down_vx = 750, |
| 927 | rv_op_vrgather_vv = 751, |
| 928 | rv_op_vrgatherei16_vv = 752, |
| 929 | rv_op_vrgather_vx = 753, |
| 930 | rv_op_vrgather_vi = 754, |
| 931 | rv_op_vcompress_vm = 755, |
| 932 | rv_op_vmv1r_v = 756, |
| 933 | rv_op_vmv2r_v = 757, |
| 934 | rv_op_vmv4r_v = 758, |
| 935 | rv_op_vmv8r_v = 759, |
| 936 | rv_op_vzext_vf2 = 760, |
| 937 | rv_op_vzext_vf4 = 761, |
| 938 | rv_op_vzext_vf8 = 762, |
| 939 | rv_op_vsext_vf2 = 763, |
| 940 | rv_op_vsext_vf4 = 764, |
| 941 | rv_op_vsext_vf8 = 765, |
| 942 | rv_op_vsetvli = 766, |
| 943 | rv_op_vsetivli = 767, |
| 944 | rv_op_vsetvl = 768, |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 945 | rv_op_c_zext_b = 769, |
| 946 | rv_op_c_sext_b = 770, |
| 947 | rv_op_c_zext_h = 771, |
| 948 | rv_op_c_sext_h = 772, |
| 949 | rv_op_c_zext_w = 773, |
| 950 | rv_op_c_not = 774, |
| 951 | rv_op_c_mul = 775, |
| 952 | rv_op_c_lbu = 776, |
| 953 | rv_op_c_lhu = 777, |
| 954 | rv_op_c_lh = 778, |
| 955 | rv_op_c_sb = 779, |
| 956 | rv_op_c_sh = 780, |
| 957 | rv_op_cm_push = 781, |
| 958 | rv_op_cm_pop = 782, |
| 959 | rv_op_cm_popret = 783, |
| 960 | rv_op_cm_popretz = 784, |
| 961 | rv_op_cm_mva01s = 785, |
| 962 | rv_op_cm_mvsa01 = 786, |
| 963 | rv_op_cm_jt = 787, |
| 964 | rv_op_cm_jalt = 788, |
Richard Henderson | d397be9 | 2023-04-26 13:33:05 +0100 | [diff] [blame] | 965 | rv_op_czero_eqz = 789, |
| 966 | rv_op_czero_nez = 790, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 967 | } rv_op; |
| 968 | |
| 969 | /* structures */ |
| 970 | |
| 971 | typedef struct { |
Weiwei Li | 454c220 | 2023-05-23 17:35:34 +0800 | [diff] [blame] | 972 | RISCVCPUConfig *cfg; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 973 | uint64_t pc; |
| 974 | uint64_t inst; |
| 975 | int32_t imm; |
| 976 | uint16_t op; |
| 977 | uint8_t codec; |
| 978 | uint8_t rd; |
| 979 | uint8_t rs1; |
| 980 | uint8_t rs2; |
| 981 | uint8_t rs3; |
| 982 | uint8_t rm; |
| 983 | uint8_t pred; |
| 984 | uint8_t succ; |
| 985 | uint8_t aq; |
| 986 | uint8_t rl; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 987 | uint8_t bs; |
| 988 | uint8_t rnum; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 989 | uint8_t vm; |
| 990 | uint32_t vzimm; |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 991 | uint8_t rlist; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 992 | } rv_decode; |
| 993 | |
| 994 | typedef struct { |
| 995 | const int op; |
| 996 | const rvc_constraint *constraints; |
| 997 | } rv_comp_data; |
| 998 | |
Michael Clark | f88222d | 2019-06-24 16:42:33 -0700 | [diff] [blame] | 999 | enum { |
| 1000 | rvcd_imm_nz = 0x1 |
| 1001 | }; |
| 1002 | |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1003 | typedef struct { |
| 1004 | const char * const name; |
| 1005 | const rv_codec codec; |
| 1006 | const char * const format; |
| 1007 | const rv_comp_data *pseudo; |
Michael Clark | f88222d | 2019-06-24 16:42:33 -0700 | [diff] [blame] | 1008 | const short decomp_rv32; |
| 1009 | const short decomp_rv64; |
| 1010 | const short decomp_rv128; |
| 1011 | const short decomp_data; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1012 | } rv_opcode_data; |
| 1013 | |
| 1014 | /* register names */ |
| 1015 | |
| 1016 | static const char rv_ireg_name_sym[32][5] = { |
| 1017 | "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", |
| 1018 | "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", |
| 1019 | "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", |
| 1020 | "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", |
| 1021 | }; |
| 1022 | |
| 1023 | static const char rv_freg_name_sym[32][5] = { |
| 1024 | "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", |
| 1025 | "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", |
| 1026 | "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", |
| 1027 | "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11", |
| 1028 | }; |
| 1029 | |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 1030 | static const char rv_vreg_name_sym[32][4] = { |
| 1031 | "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", |
| 1032 | "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", |
| 1033 | "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", |
| 1034 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" |
| 1035 | }; |
| 1036 | |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1037 | /* instruction formats */ |
| 1038 | |
| 1039 | #define rv_fmt_none "O\t" |
| 1040 | #define rv_fmt_rs1 "O\t1" |
| 1041 | #define rv_fmt_offset "O\to" |
| 1042 | #define rv_fmt_pred_succ "O\tp,s" |
| 1043 | #define rv_fmt_rs1_rs2 "O\t1,2" |
| 1044 | #define rv_fmt_rd_imm "O\t0,i" |
| 1045 | #define rv_fmt_rd_offset "O\t0,o" |
| 1046 | #define rv_fmt_rd_rs1_rs2 "O\t0,1,2" |
| 1047 | #define rv_fmt_frd_rs1 "O\t3,1" |
Mikhail Tyutin | 0d58150 | 2023-03-10 21:58:45 +0300 | [diff] [blame] | 1048 | #define rv_fmt_frd_frs1 "O\t3,4" |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1049 | #define rv_fmt_rd_frs1 "O\t0,4" |
| 1050 | #define rv_fmt_rd_frs1_frs2 "O\t0,4,5" |
| 1051 | #define rv_fmt_frd_frs1_frs2 "O\t3,4,5" |
| 1052 | #define rv_fmt_rm_frd_frs1 "O\tr,3,4" |
| 1053 | #define rv_fmt_rm_frd_rs1 "O\tr,3,1" |
| 1054 | #define rv_fmt_rm_rd_frs1 "O\tr,0,4" |
| 1055 | #define rv_fmt_rm_frd_frs1_frs2 "O\tr,3,4,5" |
| 1056 | #define rv_fmt_rm_frd_frs1_frs2_frs3 "O\tr,3,4,5,6" |
| 1057 | #define rv_fmt_rd_rs1_imm "O\t0,1,i" |
| 1058 | #define rv_fmt_rd_rs1_offset "O\t0,1,i" |
| 1059 | #define rv_fmt_rd_offset_rs1 "O\t0,i(1)" |
| 1060 | #define rv_fmt_frd_offset_rs1 "O\t3,i(1)" |
| 1061 | #define rv_fmt_rd_csr_rs1 "O\t0,c,1" |
| 1062 | #define rv_fmt_rd_csr_zimm "O\t0,c,7" |
| 1063 | #define rv_fmt_rs2_offset_rs1 "O\t2,i(1)" |
| 1064 | #define rv_fmt_frs2_offset_rs1 "O\t5,i(1)" |
| 1065 | #define rv_fmt_rs1_rs2_offset "O\t1,2,o" |
| 1066 | #define rv_fmt_rs2_rs1_offset "O\t2,1,o" |
| 1067 | #define rv_fmt_aqrl_rd_rs2_rs1 "OAR\t0,2,(1)" |
| 1068 | #define rv_fmt_aqrl_rd_rs1 "OAR\t0,(1)" |
| 1069 | #define rv_fmt_rd "O\t0" |
| 1070 | #define rv_fmt_rd_zimm "O\t0,7" |
| 1071 | #define rv_fmt_rd_rs1 "O\t0,1" |
| 1072 | #define rv_fmt_rd_rs2 "O\t0,2" |
| 1073 | #define rv_fmt_rs1_offset "O\t1,o" |
| 1074 | #define rv_fmt_rs2_offset "O\t2,o" |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 1075 | #define rv_fmt_rs1_rs2_bs "O\t1,2,b" |
| 1076 | #define rv_fmt_rd_rs1_rnum "O\t0,1,n" |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 1077 | #define rv_fmt_ldst_vd_rs1_vm "O\tD,(1)m" |
| 1078 | #define rv_fmt_ldst_vd_rs1_rs2_vm "O\tD,(1),2m" |
| 1079 | #define rv_fmt_ldst_vd_rs1_vs2_vm "O\tD,(1),Fm" |
| 1080 | #define rv_fmt_vd_vs2_vs1 "O\tD,F,E" |
| 1081 | #define rv_fmt_vd_vs2_vs1_vl "O\tD,F,El" |
| 1082 | #define rv_fmt_vd_vs2_vs1_vm "O\tD,F,Em" |
| 1083 | #define rv_fmt_vd_vs2_rs1_vl "O\tD,F,1l" |
| 1084 | #define rv_fmt_vd_vs2_fs1_vl "O\tD,F,4l" |
| 1085 | #define rv_fmt_vd_vs2_rs1_vm "O\tD,F,1m" |
| 1086 | #define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m" |
| 1087 | #define rv_fmt_vd_vs2_imm_vl "O\tD,F,il" |
| 1088 | #define rv_fmt_vd_vs2_imm_vm "O\tD,F,im" |
| 1089 | #define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um" |
| 1090 | #define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm" |
| 1091 | #define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm" |
| 1092 | #define rv_fmt_vd_fs1_vs2_vm "O\tD,4,Fm" |
| 1093 | #define rv_fmt_vd_vs1 "O\tD,E" |
| 1094 | #define rv_fmt_vd_rs1 "O\tD,1" |
| 1095 | #define rv_fmt_vd_fs1 "O\tD,4" |
| 1096 | #define rv_fmt_vd_imm "O\tD,i" |
| 1097 | #define rv_fmt_vd_vs2 "O\tD,F" |
| 1098 | #define rv_fmt_vd_vs2_vm "O\tD,Fm" |
| 1099 | #define rv_fmt_rd_vs2_vm "O\t0,Fm" |
| 1100 | #define rv_fmt_rd_vs2 "O\t0,F" |
| 1101 | #define rv_fmt_fd_vs2 "O\t3,F" |
| 1102 | #define rv_fmt_vd_vm "O\tDm" |
| 1103 | #define rv_fmt_vsetvli "O\t0,1,v" |
| 1104 | #define rv_fmt_vsetivli "O\t0,u,v" |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 1105 | #define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)" |
| 1106 | #define rv_fmt_push_rlist "O\tx,-i" |
| 1107 | #define rv_fmt_pop_rlist "O\tx,i" |
| 1108 | #define rv_fmt_zcmt_index "O\ti" |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1109 | |
| 1110 | /* pseudo-instruction constraints */ |
| 1111 | |
| 1112 | static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end }; |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 1113 | static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, |
| 1114 | rvc_end }; |
| 1115 | static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, |
| 1116 | rvc_imm_eq_zero, rvc_end }; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1117 | static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end }; |
| 1118 | static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end }; |
| 1119 | static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end }; |
| 1120 | static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end }; |
Michael Clark | 33b4f85 | 2018-03-23 01:07:01 -0700 | [diff] [blame] | 1121 | static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end }; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1122 | static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end }; |
| 1123 | static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end }; |
| 1124 | static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end }; |
| 1125 | static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end }; |
| 1126 | static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end }; |
| 1127 | static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end }; |
| 1128 | static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end }; |
| 1129 | static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end }; |
| 1130 | static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end }; |
| 1131 | static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end }; |
| 1132 | static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end }; |
| 1133 | static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end }; |
| 1134 | static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end }; |
| 1135 | static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end }; |
| 1136 | static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end }; |
| 1137 | static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end }; |
| 1138 | static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end }; |
| 1139 | static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end }; |
| 1140 | static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end }; |
| 1141 | static const rvc_constraint rvcc_ble[] = { rvc_end }; |
| 1142 | static const rvc_constraint rvcc_bleu[] = { rvc_end }; |
| 1143 | static const rvc_constraint rvcc_bgt[] = { rvc_end }; |
| 1144 | static const rvc_constraint rvcc_bgtu[] = { rvc_end }; |
| 1145 | static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end }; |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 1146 | static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, |
| 1147 | rvc_end }; |
| 1148 | static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, |
| 1149 | rvc_end }; |
| 1150 | static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, |
| 1151 | rvc_end }; |
| 1152 | static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, |
| 1153 | rvc_end }; |
| 1154 | static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, |
| 1155 | rvc_csr_eq_0xc02, rvc_end }; |
| 1156 | static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, |
| 1157 | rvc_csr_eq_0xc80, rvc_end }; |
| 1158 | static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, |
| 1159 | rvc_end }; |
Wladimir J. van der Laan | 2e3df91 | 2019-06-27 02:34:54 -0700 | [diff] [blame] | 1160 | static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, |
| 1161 | rvc_csr_eq_0xc82, rvc_end }; |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 1162 | static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, |
| 1163 | rvc_end }; |
| 1164 | static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, |
| 1165 | rvc_end }; |
| 1166 | static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, |
| 1167 | rvc_end }; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1168 | static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end }; |
| 1169 | static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end }; |
| 1170 | static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end }; |
| 1171 | static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end }; |
| 1172 | static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end }; |
| 1173 | |
| 1174 | /* pseudo-instruction metadata */ |
| 1175 | |
| 1176 | static const rv_comp_data rvcp_jal[] = { |
| 1177 | { rv_op_j, rvcc_j }, |
| 1178 | { rv_op_jal, rvcc_jal }, |
| 1179 | { rv_op_illegal, NULL } |
| 1180 | }; |
| 1181 | |
| 1182 | static const rv_comp_data rvcp_jalr[] = { |
| 1183 | { rv_op_ret, rvcc_ret }, |
| 1184 | { rv_op_jr, rvcc_jr }, |
| 1185 | { rv_op_jalr, rvcc_jalr }, |
| 1186 | { rv_op_illegal, NULL } |
| 1187 | }; |
| 1188 | |
| 1189 | static const rv_comp_data rvcp_beq[] = { |
| 1190 | { rv_op_beqz, rvcc_beqz }, |
| 1191 | { rv_op_illegal, NULL } |
| 1192 | }; |
| 1193 | |
| 1194 | static const rv_comp_data rvcp_bne[] = { |
| 1195 | { rv_op_bnez, rvcc_bnez }, |
| 1196 | { rv_op_illegal, NULL } |
| 1197 | }; |
| 1198 | |
| 1199 | static const rv_comp_data rvcp_blt[] = { |
| 1200 | { rv_op_bltz, rvcc_bltz }, |
| 1201 | { rv_op_bgtz, rvcc_bgtz }, |
| 1202 | { rv_op_bgt, rvcc_bgt }, |
| 1203 | { rv_op_illegal, NULL } |
| 1204 | }; |
| 1205 | |
| 1206 | static const rv_comp_data rvcp_bge[] = { |
| 1207 | { rv_op_blez, rvcc_blez }, |
| 1208 | { rv_op_bgez, rvcc_bgez }, |
| 1209 | { rv_op_ble, rvcc_ble }, |
| 1210 | { rv_op_illegal, NULL } |
| 1211 | }; |
| 1212 | |
| 1213 | static const rv_comp_data rvcp_bltu[] = { |
| 1214 | { rv_op_bgtu, rvcc_bgtu }, |
| 1215 | { rv_op_illegal, NULL } |
| 1216 | }; |
| 1217 | |
| 1218 | static const rv_comp_data rvcp_bgeu[] = { |
| 1219 | { rv_op_bleu, rvcc_bleu }, |
| 1220 | { rv_op_illegal, NULL } |
| 1221 | }; |
| 1222 | |
| 1223 | static const rv_comp_data rvcp_addi[] = { |
| 1224 | { rv_op_nop, rvcc_nop }, |
| 1225 | { rv_op_mv, rvcc_mv }, |
| 1226 | { rv_op_illegal, NULL } |
| 1227 | }; |
| 1228 | |
| 1229 | static const rv_comp_data rvcp_sltiu[] = { |
| 1230 | { rv_op_seqz, rvcc_seqz }, |
| 1231 | { rv_op_illegal, NULL } |
| 1232 | }; |
| 1233 | |
| 1234 | static const rv_comp_data rvcp_xori[] = { |
| 1235 | { rv_op_not, rvcc_not }, |
| 1236 | { rv_op_illegal, NULL } |
| 1237 | }; |
| 1238 | |
| 1239 | static const rv_comp_data rvcp_sub[] = { |
| 1240 | { rv_op_neg, rvcc_neg }, |
| 1241 | { rv_op_illegal, NULL } |
| 1242 | }; |
| 1243 | |
| 1244 | static const rv_comp_data rvcp_slt[] = { |
| 1245 | { rv_op_sltz, rvcc_sltz }, |
| 1246 | { rv_op_sgtz, rvcc_sgtz }, |
| 1247 | { rv_op_illegal, NULL } |
| 1248 | }; |
| 1249 | |
| 1250 | static const rv_comp_data rvcp_sltu[] = { |
| 1251 | { rv_op_snez, rvcc_snez }, |
| 1252 | { rv_op_illegal, NULL } |
| 1253 | }; |
| 1254 | |
| 1255 | static const rv_comp_data rvcp_addiw[] = { |
| 1256 | { rv_op_sext_w, rvcc_sext_w }, |
| 1257 | { rv_op_illegal, NULL } |
| 1258 | }; |
| 1259 | |
| 1260 | static const rv_comp_data rvcp_subw[] = { |
| 1261 | { rv_op_negw, rvcc_negw }, |
| 1262 | { rv_op_illegal, NULL } |
| 1263 | }; |
| 1264 | |
| 1265 | static const rv_comp_data rvcp_csrrw[] = { |
| 1266 | { rv_op_fscsr, rvcc_fscsr }, |
| 1267 | { rv_op_fsrm, rvcc_fsrm }, |
| 1268 | { rv_op_fsflags, rvcc_fsflags }, |
| 1269 | { rv_op_illegal, NULL } |
| 1270 | }; |
| 1271 | |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 1272 | |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1273 | static const rv_comp_data rvcp_csrrs[] = { |
| 1274 | { rv_op_rdcycle, rvcc_rdcycle }, |
| 1275 | { rv_op_rdtime, rvcc_rdtime }, |
| 1276 | { rv_op_rdinstret, rvcc_rdinstret }, |
| 1277 | { rv_op_rdcycleh, rvcc_rdcycleh }, |
| 1278 | { rv_op_rdtimeh, rvcc_rdtimeh }, |
| 1279 | { rv_op_rdinstreth, rvcc_rdinstreth }, |
| 1280 | { rv_op_frcsr, rvcc_frcsr }, |
| 1281 | { rv_op_frrm, rvcc_frrm }, |
| 1282 | { rv_op_frflags, rvcc_frflags }, |
| 1283 | { rv_op_illegal, NULL } |
| 1284 | }; |
| 1285 | |
| 1286 | static const rv_comp_data rvcp_csrrwi[] = { |
| 1287 | { rv_op_fsrmi, rvcc_fsrmi }, |
| 1288 | { rv_op_fsflagsi, rvcc_fsflagsi }, |
| 1289 | { rv_op_illegal, NULL } |
| 1290 | }; |
| 1291 | |
| 1292 | static const rv_comp_data rvcp_fsgnj_s[] = { |
| 1293 | { rv_op_fmv_s, rvcc_fmv_s }, |
| 1294 | { rv_op_illegal, NULL } |
| 1295 | }; |
| 1296 | |
| 1297 | static const rv_comp_data rvcp_fsgnjn_s[] = { |
| 1298 | { rv_op_fneg_s, rvcc_fneg_s }, |
| 1299 | { rv_op_illegal, NULL } |
| 1300 | }; |
| 1301 | |
| 1302 | static const rv_comp_data rvcp_fsgnjx_s[] = { |
| 1303 | { rv_op_fabs_s, rvcc_fabs_s }, |
| 1304 | { rv_op_illegal, NULL } |
| 1305 | }; |
| 1306 | |
| 1307 | static const rv_comp_data rvcp_fsgnj_d[] = { |
| 1308 | { rv_op_fmv_d, rvcc_fmv_d }, |
| 1309 | { rv_op_illegal, NULL } |
| 1310 | }; |
| 1311 | |
| 1312 | static const rv_comp_data rvcp_fsgnjn_d[] = { |
| 1313 | { rv_op_fneg_d, rvcc_fneg_d }, |
| 1314 | { rv_op_illegal, NULL } |
| 1315 | }; |
| 1316 | |
| 1317 | static const rv_comp_data rvcp_fsgnjx_d[] = { |
| 1318 | { rv_op_fabs_d, rvcc_fabs_d }, |
| 1319 | { rv_op_illegal, NULL } |
| 1320 | }; |
| 1321 | |
| 1322 | static const rv_comp_data rvcp_fsgnj_q[] = { |
| 1323 | { rv_op_fmv_q, rvcc_fmv_q }, |
| 1324 | { rv_op_illegal, NULL } |
| 1325 | }; |
| 1326 | |
| 1327 | static const rv_comp_data rvcp_fsgnjn_q[] = { |
| 1328 | { rv_op_fneg_q, rvcc_fneg_q }, |
| 1329 | { rv_op_illegal, NULL } |
| 1330 | }; |
| 1331 | |
| 1332 | static const rv_comp_data rvcp_fsgnjx_q[] = { |
| 1333 | { rv_op_fabs_q, rvcc_fabs_q }, |
| 1334 | { rv_op_illegal, NULL } |
| 1335 | }; |
| 1336 | |
| 1337 | /* instruction metadata */ |
| 1338 | |
| 1339 | const rv_opcode_data opcode_data[] = { |
| 1340 | { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, |
| 1341 | { "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 }, |
| 1342 | { "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 }, |
| 1343 | { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 }, |
| 1344 | { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 }, |
| 1345 | { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 }, |
| 1346 | { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 }, |
| 1347 | { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 }, |
| 1348 | { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 }, |
| 1349 | { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 }, |
| 1350 | { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 }, |
| 1351 | { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, |
| 1352 | { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, |
| 1353 | { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, |
| 1354 | { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, |
| 1355 | { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, |
| 1356 | { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, |
| 1357 | { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, |
| 1358 | { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, |
| 1359 | { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 }, |
| 1360 | { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1361 | { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 }, |
| 1362 | { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 }, |
| 1363 | { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1364 | { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1365 | { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1366 | { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1367 | { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1368 | { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1369 | { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 }, |
| 1370 | { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1371 | { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 }, |
| 1372 | { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 }, |
| 1373 | { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1374 | { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1375 | { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1376 | { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1377 | { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1378 | { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 }, |
| 1379 | { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, |
| 1380 | { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, |
| 1381 | { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, |
| 1382 | { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, |
| 1383 | { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 }, |
| 1384 | { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1385 | { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1386 | { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1387 | { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1388 | { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 }, |
| 1389 | { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1390 | { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1391 | { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1392 | { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, |
| 1393 | { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, |
| 1394 | { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, |
| 1395 | { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1396 | { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1397 | { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1398 | { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1399 | { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1400 | { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1401 | { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1402 | { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1403 | { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1404 | { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1405 | { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1406 | { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1407 | { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1408 | { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1409 | { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1410 | { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1411 | { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1412 | { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1413 | { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1414 | { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1415 | { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1416 | { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1417 | { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1418 | { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1419 | { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1420 | { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1421 | { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1422 | { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, |
| 1423 | { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1424 | { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1425 | { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1426 | { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1427 | { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1428 | { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1429 | { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1430 | { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1431 | { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1432 | { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1433 | { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, |
| 1434 | { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1435 | { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1436 | { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1437 | { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1438 | { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1439 | { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1440 | { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1441 | { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1442 | { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1443 | { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1444 | { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, |
| 1445 | { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1446 | { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1447 | { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1448 | { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1449 | { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1450 | { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1451 | { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1452 | { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1453 | { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1454 | { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, |
| 1455 | { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, |
| 1456 | { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, |
| 1457 | { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, |
| 1458 | { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, |
| 1459 | { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, |
| 1460 | { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, |
| 1461 | { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, |
| 1462 | { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, |
| 1463 | { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 }, |
| 1464 | { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, |
| 1465 | { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 }, |
| 1466 | { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 }, |
| 1467 | { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 }, |
| 1468 | { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 }, |
| 1469 | { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, |
| 1470 | { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, |
| 1471 | { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, |
| 1472 | { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, |
| 1473 | { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, |
| 1474 | { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, |
| 1475 | { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, |
| 1476 | { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, |
| 1477 | { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1478 | { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1479 | { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1480 | { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1481 | { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 }, |
| 1482 | { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 }, |
| 1483 | { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 }, |
| 1484 | { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1485 | { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1486 | { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, |
| 1487 | { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1488 | { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1489 | { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1490 | { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, |
| 1491 | { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, |
| 1492 | { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, |
| 1493 | { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, |
| 1494 | { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, |
| 1495 | { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, |
| 1496 | { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, |
| 1497 | { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, |
| 1498 | { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, |
| 1499 | { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, |
| 1500 | { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, |
| 1501 | { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, |
| 1502 | { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, |
| 1503 | { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, |
| 1504 | { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, |
| 1505 | { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, |
| 1506 | { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, |
| 1507 | { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1508 | { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1509 | { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1510 | { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1511 | { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 }, |
| 1512 | { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 }, |
| 1513 | { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 }, |
| 1514 | { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1515 | { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1516 | { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, |
| 1517 | { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, |
| 1518 | { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, |
| 1519 | { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1520 | { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1521 | { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1522 | { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, |
| 1523 | { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, |
| 1524 | { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, |
| 1525 | { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, |
| 1526 | { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, |
| 1527 | { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, |
| 1528 | { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, |
| 1529 | { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, |
| 1530 | { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, |
| 1531 | { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, |
| 1532 | { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, |
| 1533 | { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, |
| 1534 | { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, |
| 1535 | { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, |
| 1536 | { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, |
| 1537 | { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, |
| 1538 | { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, |
| 1539 | { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1540 | { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1541 | { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1542 | { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1543 | { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 }, |
| 1544 | { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 }, |
| 1545 | { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 }, |
| 1546 | { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1547 | { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1548 | { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, |
| 1549 | { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, |
| 1550 | { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, |
| 1551 | { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, |
| 1552 | { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, |
| 1553 | { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1554 | { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1555 | { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, |
| 1556 | { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, |
| 1557 | { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, |
| 1558 | { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, |
| 1559 | { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, |
| 1560 | { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, |
| 1561 | { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, |
| 1562 | { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, |
| 1563 | { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, |
| 1564 | { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, |
| 1565 | { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, |
| 1566 | { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, |
Michael Clark | f88222d | 2019-06-24 16:42:33 -0700 | [diff] [blame] | 1567 | { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, |
| 1568 | rv_op_addi, rv_op_addi, rvcd_imm_nz }, |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 1569 | { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, |
| 1570 | rv_op_fld, 0 }, |
| 1571 | { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, |
| 1572 | rv_op_lw }, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1573 | { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 1574 | { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, |
| 1575 | rv_op_fsd, 0 }, |
| 1576 | { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, |
| 1577 | rv_op_sw }, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1578 | { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 1579 | { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, |
| 1580 | rv_op_addi }, |
Michael Clark | f88222d | 2019-06-24 16:42:33 -0700 | [diff] [blame] | 1581 | { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, |
| 1582 | rv_op_addi, rvcd_imm_nz }, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1583 | { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 }, |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 1584 | { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, |
| 1585 | rv_op_addi }, |
Michael Clark | f88222d | 2019-06-24 16:42:33 -0700 | [diff] [blame] | 1586 | { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, |
| 1587 | rv_op_addi, rv_op_addi, rvcd_imm_nz }, |
| 1588 | { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, |
| 1589 | rv_op_lui, rvcd_imm_nz }, |
| 1590 | { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, |
| 1591 | rv_op_srli, rv_op_srli, rvcd_imm_nz }, |
| 1592 | { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, |
| 1593 | rv_op_srai, rv_op_srai, rvcd_imm_nz }, |
| 1594 | { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, |
Wladimir J. van der Laan | 2e3df91 | 2019-06-27 02:34:54 -0700 | [diff] [blame] | 1595 | rv_op_andi, rv_op_andi }, |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 1596 | { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, |
| 1597 | rv_op_sub }, |
| 1598 | { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, |
| 1599 | rv_op_xor }, |
| 1600 | { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, |
| 1601 | rv_op_or }, |
| 1602 | { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, |
| 1603 | rv_op_and }, |
| 1604 | { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, |
| 1605 | rv_op_subw }, |
| 1606 | { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, |
| 1607 | rv_op_addw }, |
| 1608 | { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, |
| 1609 | rv_op_jal }, |
| 1610 | { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, |
| 1611 | rv_op_beq }, |
| 1612 | { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, |
| 1613 | rv_op_bne }, |
Michael Clark | f88222d | 2019-06-24 16:42:33 -0700 | [diff] [blame] | 1614 | { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, |
| 1615 | rv_op_slli, rv_op_slli, rvcd_imm_nz }, |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 1616 | { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, |
| 1617 | rv_op_fld, rv_op_fld }, |
| 1618 | { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, |
| 1619 | rv_op_lw, rv_op_lw }, |
| 1620 | { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, |
| 1621 | 0 }, |
| 1622 | { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, |
| 1623 | rv_op_jalr, rv_op_jalr }, |
| 1624 | { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, |
| 1625 | rv_op_addi }, |
| 1626 | { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, |
| 1627 | rv_op_ebreak, rv_op_ebreak }, |
| 1628 | { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, |
| 1629 | rv_op_jalr, rv_op_jalr }, |
| 1630 | { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, |
| 1631 | rv_op_add }, |
| 1632 | { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, |
| 1633 | rv_op_fsd, rv_op_fsd }, |
| 1634 | { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, |
| 1635 | rv_op_sw, rv_op_sw }, |
| 1636 | { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, |
| 1637 | 0 }, |
| 1638 | { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, |
| 1639 | rv_op_ld }, |
| 1640 | { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, |
| 1641 | rv_op_sd }, |
| 1642 | { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, |
| 1643 | rv_op_addiw }, |
| 1644 | { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, |
| 1645 | rv_op_ld }, |
| 1646 | { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, |
| 1647 | rv_op_sd }, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1648 | { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, |
| 1649 | { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq }, |
| 1650 | { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 1651 | { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, |
| 1652 | rv_op_sq }, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1653 | { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, |
| 1654 | { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1655 | { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1656 | { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, |
| 1657 | { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, |
| 1658 | { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1659 | { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1660 | { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, |
| 1661 | { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1662 | { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, |
Mikhail Tyutin | 0d58150 | 2023-03-10 21:58:45 +0300 | [diff] [blame] | 1663 | { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, |
| 1664 | { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, |
| 1665 | { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, |
| 1666 | { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, |
| 1667 | { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, |
| 1668 | { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, |
| 1669 | { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, |
| 1670 | { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, |
| 1671 | { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 1672 | { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, |
| 1673 | { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, |
| 1674 | { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, |
| 1675 | { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, |
| 1676 | { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, |
| 1677 | { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, |
| 1678 | { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, |
| 1679 | { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, |
| 1680 | { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, |
| 1681 | { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, |
| 1682 | { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 }, |
| 1683 | { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, |
| 1684 | { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 }, |
| 1685 | { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, |
| 1686 | { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, |
| 1687 | { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, |
| 1688 | { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, |
| 1689 | { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, |
| 1690 | { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, |
| 1691 | { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, |
| 1692 | { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, |
| 1693 | { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, |
| 1694 | { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1695 | { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1696 | { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1697 | { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, |
| 1698 | { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 1699 | { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1700 | { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1701 | { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1702 | { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1703 | { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1704 | { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1705 | { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1706 | { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1707 | { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1708 | { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
Philipp Tomsich | 3de1fb7 | 2023-01-20 16:15:51 +0100 | [diff] [blame] | 1709 | { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1710 | { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1711 | { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 1712 | { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1713 | { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1714 | { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1715 | { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1716 | { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1717 | { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1718 | { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1719 | { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1720 | { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1721 | { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1722 | { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1723 | { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1724 | { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1725 | { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1726 | { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1727 | { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
Ivan Klokov | 2706290 | 2023-02-17 18:14:59 +0300 | [diff] [blame] | 1728 | { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 1729 | { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
Ivan Klokov | 13e269f | 2023-02-27 12:02:28 +0300 | [diff] [blame] | 1730 | { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 1731 | { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1732 | { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1733 | { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1734 | { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1735 | { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1736 | { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, |
| 1737 | { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1738 | { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1739 | { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1740 | { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1741 | { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 1742 | { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, |
| 1743 | { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, |
| 1744 | { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, |
| 1745 | { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, |
| 1746 | { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 }, |
| 1747 | { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1748 | { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, |
| 1749 | { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1750 | { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1751 | { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1752 | { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1753 | { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, |
| 1754 | { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, |
| 1755 | { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, |
| 1756 | { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, |
| 1757 | { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1758 | { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1759 | { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1760 | { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1761 | { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1762 | { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1763 | { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1764 | { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1765 | { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1766 | { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1767 | { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, |
| 1768 | { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, |
| 1769 | { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, |
| 1770 | { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, |
| 1771 | { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1772 | { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1773 | { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1774 | { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 1775 | { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1776 | { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
| 1777 | { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 1778 | { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, |
Weiwei Li | 8deb4756 | 2023-05-23 17:35:37 +0800 | [diff] [blame] | 1779 | { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1780 | { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1781 | { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1782 | { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1783 | { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1784 | { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1785 | { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1786 | { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1787 | { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1788 | { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1789 | { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, |
| 1790 | { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, |
| 1791 | { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, |
| 1792 | { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, |
| 1793 | { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, |
| 1794 | { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, |
| 1795 | { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, |
| 1796 | { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, |
| 1797 | { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1798 | { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1799 | { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1800 | { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1801 | { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1802 | { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1803 | { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1804 | { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1805 | { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1806 | { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1807 | { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1808 | { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1809 | { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1810 | { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1811 | { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1812 | { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1813 | { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1814 | { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1815 | { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1816 | { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1817 | { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1818 | { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1819 | { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1820 | { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1821 | { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1822 | { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1823 | { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1824 | { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1825 | { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1826 | { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1827 | { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1828 | { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1829 | { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1830 | { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1831 | { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1832 | { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1833 | { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1834 | { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1835 | { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1836 | { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, |
| 1837 | { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1838 | { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1839 | { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1840 | { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1841 | { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1842 | { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1843 | { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1844 | { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1845 | { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1846 | { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1847 | { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1848 | { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1849 | { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1850 | { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1851 | { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1852 | { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1853 | { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1854 | { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1855 | { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1856 | { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1857 | { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1858 | { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1859 | { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1860 | { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, |
| 1861 | { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, |
| 1862 | { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, |
| 1863 | { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, |
| 1864 | { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, |
| 1865 | { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, |
| 1866 | { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, |
| 1867 | { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, |
| 1868 | { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, |
| 1869 | { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, |
| 1870 | { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1871 | { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1872 | { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1873 | { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1874 | { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1875 | { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1876 | { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1877 | { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1878 | { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1879 | { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1880 | { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1881 | { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, |
| 1882 | { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1883 | { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1884 | { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, |
| 1885 | { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1886 | { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1887 | { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, |
| 1888 | { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1889 | { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1890 | { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, |
| 1891 | { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1892 | { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1893 | { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, |
| 1894 | { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1895 | { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1896 | { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1897 | { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1898 | { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1899 | { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1900 | { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1901 | { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1902 | { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1903 | { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1904 | { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1905 | { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1906 | { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1907 | { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1908 | { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1909 | { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1910 | { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1911 | { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1912 | { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1913 | { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1914 | { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1915 | { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1916 | { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1917 | { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1918 | { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1919 | { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1920 | { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1921 | { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1922 | { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1923 | { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1924 | { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1925 | { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1926 | { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1927 | { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1928 | { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1929 | { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1930 | { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1931 | { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1932 | { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1933 | { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1934 | { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1935 | { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1936 | { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1937 | { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1938 | { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1939 | { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1940 | { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1941 | { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1942 | { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1943 | { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1944 | { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1945 | { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1946 | { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1947 | { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1948 | { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1949 | { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1950 | { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1951 | { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1952 | { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1953 | { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1954 | { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1955 | { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1956 | { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1957 | { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1958 | { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, |
| 1959 | { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 }, |
| 1960 | { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, |
| 1961 | { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 }, |
| 1962 | { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, |
| 1963 | { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, |
| 1964 | { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, |
| 1965 | { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1966 | { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1967 | { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1968 | { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1969 | { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1970 | { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, |
| 1971 | { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1972 | { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1973 | { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1974 | { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1975 | { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1976 | { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1977 | { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1978 | { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1979 | { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1980 | { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1981 | { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1982 | { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1983 | { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1984 | { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1985 | { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1986 | { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1987 | { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, |
| 1988 | { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1989 | { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1990 | { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, |
| 1991 | { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1992 | { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1993 | { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, |
| 1994 | { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1995 | { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 1996 | { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, |
| 1997 | { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 1998 | { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 1999 | { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2000 | { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2001 | { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2002 | { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2003 | { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2004 | { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2005 | { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2006 | { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2007 | { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2008 | { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2009 | { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2010 | { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2011 | { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2012 | { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2013 | { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2014 | { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2015 | { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2016 | { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2017 | { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2018 | { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2019 | { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2020 | { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2021 | { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2022 | { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2023 | { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2024 | { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2025 | { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2026 | { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2027 | { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2028 | { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2029 | { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2030 | { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2031 | { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2032 | { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2033 | { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2034 | { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2035 | { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2036 | { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2037 | { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2038 | { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2039 | { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2040 | { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, |
| 2041 | { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, |
| 2042 | { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, |
| 2043 | { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, |
| 2044 | { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2045 | { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2046 | { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2047 | { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2048 | { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2049 | { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2050 | { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2051 | { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2052 | { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2053 | { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2054 | { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2055 | { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2056 | { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2057 | { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2058 | { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2059 | { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2060 | { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2061 | { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2062 | { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2063 | { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2064 | { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2065 | { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, |
| 2066 | { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2067 | { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 }, |
| 2068 | { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, |
| 2069 | { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2070 | { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2071 | { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2072 | { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2073 | { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2074 | { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2075 | { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2076 | { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2077 | { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2078 | { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2079 | { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2080 | { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2081 | { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2082 | { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2083 | { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2084 | { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2085 | { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2086 | { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2087 | { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2088 | { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2089 | { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2090 | { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2091 | { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2092 | { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2093 | { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2094 | { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2095 | { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2096 | { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2097 | { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2098 | { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2099 | { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2100 | { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2101 | { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2102 | { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2103 | { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2104 | { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2105 | { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2106 | { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2107 | { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2108 | { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2109 | { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2110 | { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2111 | { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2112 | { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2113 | { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2114 | { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, |
| 2115 | { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, |
| 2116 | { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2117 | { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2118 | { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2119 | { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2120 | { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 }, |
| 2121 | { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 }, |
| 2122 | { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, |
| 2123 | { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 }, |
| 2124 | { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, |
| 2125 | { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 2126 | { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, |
| 2127 | { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 2128 | { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 2129 | { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, |
| 2130 | { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 2131 | { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2132 | { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, |
| 2133 | { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, |
| 2134 | { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, |
| 2135 | { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, |
| 2136 | { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, |
| 2137 | { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, |
| 2138 | { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, |
| 2139 | { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, |
| 2140 | { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2141 | { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2142 | { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2143 | { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2144 | { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2145 | { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, |
| 2146 | { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 }, |
| 2147 | { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 }, |
| 2148 | { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 2149 | { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, |
| 2150 | { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, |
| 2151 | { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, |
| 2152 | { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, |
| 2153 | { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, |
| 2154 | { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, |
| 2155 | { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 }, |
| 2156 | { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, |
| 2157 | { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, |
| 2158 | { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, |
| 2159 | { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, |
| 2160 | { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, |
| 2161 | { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 }, |
| 2162 | { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, |
| 2163 | { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 }, |
| 2164 | { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, |
| 2165 | { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, |
| 2166 | { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, |
| 2167 | { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, |
| 2168 | { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, |
Richard Henderson | d397be9 | 2023-04-26 13:33:05 +0100 | [diff] [blame] | 2169 | { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
| 2170 | { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2171 | }; |
| 2172 | |
| 2173 | /* CSR names */ |
| 2174 | |
| 2175 | static const char *csr_name(int csrno) |
| 2176 | { |
| 2177 | switch (csrno) { |
| 2178 | case 0x0000: return "ustatus"; |
| 2179 | case 0x0001: return "fflags"; |
| 2180 | case 0x0002: return "frm"; |
| 2181 | case 0x0003: return "fcsr"; |
| 2182 | case 0x0004: return "uie"; |
| 2183 | case 0x0005: return "utvec"; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2184 | case 0x0008: return "vstart"; |
| 2185 | case 0x0009: return "vxsat"; |
| 2186 | case 0x000a: return "vxrm"; |
| 2187 | case 0x000f: return "vcsr"; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2188 | case 0x0015: return "seed"; |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 2189 | case 0x0017: return "jvt"; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2190 | case 0x0040: return "uscratch"; |
| 2191 | case 0x0041: return "uepc"; |
| 2192 | case 0x0042: return "ucause"; |
| 2193 | case 0x0043: return "utval"; |
| 2194 | case 0x0044: return "uip"; |
| 2195 | case 0x0100: return "sstatus"; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2196 | case 0x0104: return "sie"; |
| 2197 | case 0x0105: return "stvec"; |
| 2198 | case 0x0106: return "scounteren"; |
| 2199 | case 0x0140: return "sscratch"; |
| 2200 | case 0x0141: return "sepc"; |
| 2201 | case 0x0142: return "scause"; |
| 2202 | case 0x0143: return "stval"; |
| 2203 | case 0x0144: return "sip"; |
| 2204 | case 0x0180: return "satp"; |
| 2205 | case 0x0200: return "hstatus"; |
| 2206 | case 0x0202: return "hedeleg"; |
| 2207 | case 0x0203: return "hideleg"; |
| 2208 | case 0x0204: return "hie"; |
| 2209 | case 0x0205: return "htvec"; |
| 2210 | case 0x0240: return "hscratch"; |
| 2211 | case 0x0241: return "hepc"; |
| 2212 | case 0x0242: return "hcause"; |
| 2213 | case 0x0243: return "hbadaddr"; |
| 2214 | case 0x0244: return "hip"; |
| 2215 | case 0x0300: return "mstatus"; |
| 2216 | case 0x0301: return "misa"; |
| 2217 | case 0x0302: return "medeleg"; |
| 2218 | case 0x0303: return "mideleg"; |
| 2219 | case 0x0304: return "mie"; |
| 2220 | case 0x0305: return "mtvec"; |
| 2221 | case 0x0306: return "mcounteren"; |
| 2222 | case 0x0320: return "mucounteren"; |
| 2223 | case 0x0321: return "mscounteren"; |
| 2224 | case 0x0322: return "mhcounteren"; |
| 2225 | case 0x0323: return "mhpmevent3"; |
| 2226 | case 0x0324: return "mhpmevent4"; |
| 2227 | case 0x0325: return "mhpmevent5"; |
| 2228 | case 0x0326: return "mhpmevent6"; |
| 2229 | case 0x0327: return "mhpmevent7"; |
| 2230 | case 0x0328: return "mhpmevent8"; |
| 2231 | case 0x0329: return "mhpmevent9"; |
| 2232 | case 0x032a: return "mhpmevent10"; |
| 2233 | case 0x032b: return "mhpmevent11"; |
| 2234 | case 0x032c: return "mhpmevent12"; |
| 2235 | case 0x032d: return "mhpmevent13"; |
| 2236 | case 0x032e: return "mhpmevent14"; |
| 2237 | case 0x032f: return "mhpmevent15"; |
| 2238 | case 0x0330: return "mhpmevent16"; |
| 2239 | case 0x0331: return "mhpmevent17"; |
| 2240 | case 0x0332: return "mhpmevent18"; |
| 2241 | case 0x0333: return "mhpmevent19"; |
| 2242 | case 0x0334: return "mhpmevent20"; |
| 2243 | case 0x0335: return "mhpmevent21"; |
| 2244 | case 0x0336: return "mhpmevent22"; |
| 2245 | case 0x0337: return "mhpmevent23"; |
| 2246 | case 0x0338: return "mhpmevent24"; |
| 2247 | case 0x0339: return "mhpmevent25"; |
| 2248 | case 0x033a: return "mhpmevent26"; |
| 2249 | case 0x033b: return "mhpmevent27"; |
| 2250 | case 0x033c: return "mhpmevent28"; |
| 2251 | case 0x033d: return "mhpmevent29"; |
| 2252 | case 0x033e: return "mhpmevent30"; |
| 2253 | case 0x033f: return "mhpmevent31"; |
| 2254 | case 0x0340: return "mscratch"; |
| 2255 | case 0x0341: return "mepc"; |
| 2256 | case 0x0342: return "mcause"; |
| 2257 | case 0x0343: return "mtval"; |
| 2258 | case 0x0344: return "mip"; |
| 2259 | case 0x0380: return "mbase"; |
| 2260 | case 0x0381: return "mbound"; |
| 2261 | case 0x0382: return "mibase"; |
| 2262 | case 0x0383: return "mibound"; |
| 2263 | case 0x0384: return "mdbase"; |
| 2264 | case 0x0385: return "mdbound"; |
| 2265 | case 0x03a0: return "pmpcfg3"; |
| 2266 | case 0x03b0: return "pmpaddr0"; |
| 2267 | case 0x03b1: return "pmpaddr1"; |
| 2268 | case 0x03b2: return "pmpaddr2"; |
| 2269 | case 0x03b3: return "pmpaddr3"; |
| 2270 | case 0x03b4: return "pmpaddr4"; |
| 2271 | case 0x03b5: return "pmpaddr5"; |
| 2272 | case 0x03b6: return "pmpaddr6"; |
| 2273 | case 0x03b7: return "pmpaddr7"; |
| 2274 | case 0x03b8: return "pmpaddr8"; |
| 2275 | case 0x03b9: return "pmpaddr9"; |
| 2276 | case 0x03ba: return "pmpaddr10"; |
| 2277 | case 0x03bb: return "pmpaddr11"; |
| 2278 | case 0x03bc: return "pmpaddr12"; |
| 2279 | case 0x03bd: return "pmpaddr14"; |
| 2280 | case 0x03be: return "pmpaddr13"; |
| 2281 | case 0x03bf: return "pmpaddr15"; |
| 2282 | case 0x0780: return "mtohost"; |
| 2283 | case 0x0781: return "mfromhost"; |
| 2284 | case 0x0782: return "mreset"; |
| 2285 | case 0x0783: return "mipi"; |
| 2286 | case 0x0784: return "miobase"; |
| 2287 | case 0x07a0: return "tselect"; |
| 2288 | case 0x07a1: return "tdata1"; |
| 2289 | case 0x07a2: return "tdata2"; |
| 2290 | case 0x07a3: return "tdata3"; |
| 2291 | case 0x07b0: return "dcsr"; |
| 2292 | case 0x07b1: return "dpc"; |
| 2293 | case 0x07b2: return "dscratch"; |
| 2294 | case 0x0b00: return "mcycle"; |
| 2295 | case 0x0b01: return "mtime"; |
| 2296 | case 0x0b02: return "minstret"; |
| 2297 | case 0x0b03: return "mhpmcounter3"; |
| 2298 | case 0x0b04: return "mhpmcounter4"; |
| 2299 | case 0x0b05: return "mhpmcounter5"; |
| 2300 | case 0x0b06: return "mhpmcounter6"; |
| 2301 | case 0x0b07: return "mhpmcounter7"; |
| 2302 | case 0x0b08: return "mhpmcounter8"; |
| 2303 | case 0x0b09: return "mhpmcounter9"; |
| 2304 | case 0x0b0a: return "mhpmcounter10"; |
| 2305 | case 0x0b0b: return "mhpmcounter11"; |
| 2306 | case 0x0b0c: return "mhpmcounter12"; |
| 2307 | case 0x0b0d: return "mhpmcounter13"; |
| 2308 | case 0x0b0e: return "mhpmcounter14"; |
| 2309 | case 0x0b0f: return "mhpmcounter15"; |
| 2310 | case 0x0b10: return "mhpmcounter16"; |
| 2311 | case 0x0b11: return "mhpmcounter17"; |
| 2312 | case 0x0b12: return "mhpmcounter18"; |
| 2313 | case 0x0b13: return "mhpmcounter19"; |
| 2314 | case 0x0b14: return "mhpmcounter20"; |
| 2315 | case 0x0b15: return "mhpmcounter21"; |
| 2316 | case 0x0b16: return "mhpmcounter22"; |
| 2317 | case 0x0b17: return "mhpmcounter23"; |
| 2318 | case 0x0b18: return "mhpmcounter24"; |
| 2319 | case 0x0b19: return "mhpmcounter25"; |
| 2320 | case 0x0b1a: return "mhpmcounter26"; |
| 2321 | case 0x0b1b: return "mhpmcounter27"; |
| 2322 | case 0x0b1c: return "mhpmcounter28"; |
| 2323 | case 0x0b1d: return "mhpmcounter29"; |
| 2324 | case 0x0b1e: return "mhpmcounter30"; |
| 2325 | case 0x0b1f: return "mhpmcounter31"; |
| 2326 | case 0x0b80: return "mcycleh"; |
| 2327 | case 0x0b81: return "mtimeh"; |
| 2328 | case 0x0b82: return "minstreth"; |
| 2329 | case 0x0b83: return "mhpmcounter3h"; |
| 2330 | case 0x0b84: return "mhpmcounter4h"; |
| 2331 | case 0x0b85: return "mhpmcounter5h"; |
| 2332 | case 0x0b86: return "mhpmcounter6h"; |
| 2333 | case 0x0b87: return "mhpmcounter7h"; |
| 2334 | case 0x0b88: return "mhpmcounter8h"; |
| 2335 | case 0x0b89: return "mhpmcounter9h"; |
| 2336 | case 0x0b8a: return "mhpmcounter10h"; |
| 2337 | case 0x0b8b: return "mhpmcounter11h"; |
| 2338 | case 0x0b8c: return "mhpmcounter12h"; |
| 2339 | case 0x0b8d: return "mhpmcounter13h"; |
| 2340 | case 0x0b8e: return "mhpmcounter14h"; |
| 2341 | case 0x0b8f: return "mhpmcounter15h"; |
| 2342 | case 0x0b90: return "mhpmcounter16h"; |
| 2343 | case 0x0b91: return "mhpmcounter17h"; |
| 2344 | case 0x0b92: return "mhpmcounter18h"; |
| 2345 | case 0x0b93: return "mhpmcounter19h"; |
| 2346 | case 0x0b94: return "mhpmcounter20h"; |
| 2347 | case 0x0b95: return "mhpmcounter21h"; |
| 2348 | case 0x0b96: return "mhpmcounter22h"; |
| 2349 | case 0x0b97: return "mhpmcounter23h"; |
| 2350 | case 0x0b98: return "mhpmcounter24h"; |
| 2351 | case 0x0b99: return "mhpmcounter25h"; |
| 2352 | case 0x0b9a: return "mhpmcounter26h"; |
| 2353 | case 0x0b9b: return "mhpmcounter27h"; |
| 2354 | case 0x0b9c: return "mhpmcounter28h"; |
| 2355 | case 0x0b9d: return "mhpmcounter29h"; |
| 2356 | case 0x0b9e: return "mhpmcounter30h"; |
| 2357 | case 0x0b9f: return "mhpmcounter31h"; |
| 2358 | case 0x0c00: return "cycle"; |
| 2359 | case 0x0c01: return "time"; |
| 2360 | case 0x0c02: return "instret"; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2361 | case 0x0c20: return "vl"; |
| 2362 | case 0x0c21: return "vtype"; |
| 2363 | case 0x0c22: return "vlenb"; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2364 | case 0x0c80: return "cycleh"; |
| 2365 | case 0x0c81: return "timeh"; |
| 2366 | case 0x0c82: return "instreth"; |
| 2367 | case 0x0d00: return "scycle"; |
| 2368 | case 0x0d01: return "stime"; |
| 2369 | case 0x0d02: return "sinstret"; |
| 2370 | case 0x0d80: return "scycleh"; |
| 2371 | case 0x0d81: return "stimeh"; |
| 2372 | case 0x0d82: return "sinstreth"; |
| 2373 | case 0x0e00: return "hcycle"; |
| 2374 | case 0x0e01: return "htime"; |
| 2375 | case 0x0e02: return "hinstret"; |
| 2376 | case 0x0e80: return "hcycleh"; |
| 2377 | case 0x0e81: return "htimeh"; |
| 2378 | case 0x0e82: return "hinstreth"; |
| 2379 | case 0x0f11: return "mvendorid"; |
| 2380 | case 0x0f12: return "marchid"; |
| 2381 | case 0x0f13: return "mimpid"; |
| 2382 | case 0x0f14: return "mhartid"; |
| 2383 | default: return NULL; |
| 2384 | } |
| 2385 | } |
| 2386 | |
| 2387 | /* decode opcode */ |
| 2388 | |
| 2389 | static void decode_inst_opcode(rv_decode *dec, rv_isa isa) |
| 2390 | { |
| 2391 | rv_inst inst = dec->inst; |
| 2392 | rv_opcode op = rv_op_illegal; |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2393 | switch ((inst >> 0) & 0b11) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2394 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2395 | switch ((inst >> 13) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2396 | case 0: op = rv_op_c_addi4spn; break; |
| 2397 | case 1: |
| 2398 | if (isa == rv128) { |
| 2399 | op = rv_op_c_lq; |
| 2400 | } else { |
| 2401 | op = rv_op_c_fld; |
| 2402 | } |
| 2403 | break; |
| 2404 | case 2: op = rv_op_c_lw; break; |
| 2405 | case 3: |
| 2406 | if (isa == rv32) { |
| 2407 | op = rv_op_c_flw; |
| 2408 | } else { |
| 2409 | op = rv_op_c_ld; |
| 2410 | } |
| 2411 | break; |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 2412 | case 4: |
| 2413 | switch ((inst >> 10) & 0b111) { |
| 2414 | case 0: op = rv_op_c_lbu; break; |
| 2415 | case 1: |
| 2416 | if (((inst >> 6) & 1) == 0) { |
| 2417 | op = rv_op_c_lhu; |
| 2418 | } else { |
| 2419 | op = rv_op_c_lh; |
| 2420 | } |
| 2421 | break; |
| 2422 | case 2: op = rv_op_c_sb; break; |
| 2423 | case 3: |
| 2424 | if (((inst >> 6) & 1) == 0) { |
| 2425 | op = rv_op_c_sh; |
| 2426 | } |
| 2427 | break; |
| 2428 | } |
| 2429 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2430 | case 5: |
| 2431 | if (isa == rv128) { |
| 2432 | op = rv_op_c_sq; |
| 2433 | } else { |
| 2434 | op = rv_op_c_fsd; |
| 2435 | } |
| 2436 | break; |
| 2437 | case 6: op = rv_op_c_sw; break; |
| 2438 | case 7: |
| 2439 | if (isa == rv32) { |
| 2440 | op = rv_op_c_fsw; |
| 2441 | } else { |
| 2442 | op = rv_op_c_sd; |
| 2443 | } |
| 2444 | break; |
| 2445 | } |
| 2446 | break; |
| 2447 | case 1: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2448 | switch ((inst >> 13) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2449 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2450 | switch ((inst >> 2) & 0b11111111111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2451 | case 0: op = rv_op_c_nop; break; |
| 2452 | default: op = rv_op_c_addi; break; |
| 2453 | } |
| 2454 | break; |
| 2455 | case 1: |
| 2456 | if (isa == rv32) { |
| 2457 | op = rv_op_c_jal; |
| 2458 | } else { |
| 2459 | op = rv_op_c_addiw; |
| 2460 | } |
| 2461 | break; |
| 2462 | case 2: op = rv_op_c_li; break; |
| 2463 | case 3: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2464 | switch ((inst >> 7) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2465 | case 2: op = rv_op_c_addi16sp; break; |
| 2466 | default: op = rv_op_c_lui; break; |
| 2467 | } |
| 2468 | break; |
| 2469 | case 4: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2470 | switch ((inst >> 10) & 0b11) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2471 | case 0: |
| 2472 | op = rv_op_c_srli; |
| 2473 | break; |
| 2474 | case 1: |
| 2475 | op = rv_op_c_srai; |
| 2476 | break; |
| 2477 | case 2: op = rv_op_c_andi; break; |
| 2478 | case 3: |
| 2479 | switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) { |
| 2480 | case 0: op = rv_op_c_sub; break; |
| 2481 | case 1: op = rv_op_c_xor; break; |
| 2482 | case 2: op = rv_op_c_or; break; |
| 2483 | case 3: op = rv_op_c_and; break; |
| 2484 | case 4: op = rv_op_c_subw; break; |
| 2485 | case 5: op = rv_op_c_addw; break; |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 2486 | case 6: op = rv_op_c_mul; break; |
| 2487 | case 7: |
| 2488 | switch ((inst >> 2) & 0b111) { |
| 2489 | case 0: op = rv_op_c_zext_b; break; |
| 2490 | case 1: op = rv_op_c_sext_b; break; |
| 2491 | case 2: op = rv_op_c_zext_h; break; |
| 2492 | case 3: op = rv_op_c_sext_h; break; |
| 2493 | case 4: op = rv_op_c_zext_w; break; |
| 2494 | case 5: op = rv_op_c_not; break; |
| 2495 | } |
| 2496 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2497 | } |
| 2498 | break; |
| 2499 | } |
| 2500 | break; |
| 2501 | case 5: op = rv_op_c_j; break; |
| 2502 | case 6: op = rv_op_c_beqz; break; |
| 2503 | case 7: op = rv_op_c_bnez; break; |
| 2504 | } |
| 2505 | break; |
| 2506 | case 2: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2507 | switch ((inst >> 13) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2508 | case 0: |
| 2509 | op = rv_op_c_slli; |
| 2510 | break; |
| 2511 | case 1: |
| 2512 | if (isa == rv128) { |
| 2513 | op = rv_op_c_lqsp; |
| 2514 | } else { |
| 2515 | op = rv_op_c_fldsp; |
| 2516 | } |
| 2517 | break; |
| 2518 | case 2: op = rv_op_c_lwsp; break; |
| 2519 | case 3: |
| 2520 | if (isa == rv32) { |
| 2521 | op = rv_op_c_flwsp; |
| 2522 | } else { |
| 2523 | op = rv_op_c_ldsp; |
| 2524 | } |
| 2525 | break; |
| 2526 | case 4: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2527 | switch ((inst >> 12) & 0b1) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2528 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2529 | switch ((inst >> 2) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2530 | case 0: op = rv_op_c_jr; break; |
| 2531 | default: op = rv_op_c_mv; break; |
| 2532 | } |
| 2533 | break; |
| 2534 | case 1: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2535 | switch ((inst >> 2) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2536 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2537 | switch ((inst >> 7) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2538 | case 0: op = rv_op_c_ebreak; break; |
| 2539 | default: op = rv_op_c_jalr; break; |
| 2540 | } |
| 2541 | break; |
| 2542 | default: op = rv_op_c_add; break; |
| 2543 | } |
| 2544 | break; |
| 2545 | } |
| 2546 | break; |
| 2547 | case 5: |
| 2548 | if (isa == rv128) { |
| 2549 | op = rv_op_c_sqsp; |
| 2550 | } else { |
Michael Clark | 1dc34be | 2018-04-30 11:06:31 +1200 | [diff] [blame] | 2551 | op = rv_op_c_fsdsp; |
Weiwei Li | 2a2b221 | 2023-05-23 17:35:35 +0800 | [diff] [blame] | 2552 | if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 2553 | switch ((inst >> 8) & 0b01111) { |
| 2554 | case 8: |
| 2555 | if (((inst >> 4) & 0b01111) >= 4) { |
| 2556 | op = rv_op_cm_push; |
| 2557 | } |
| 2558 | break; |
| 2559 | case 10: |
| 2560 | if (((inst >> 4) & 0b01111) >= 4) { |
| 2561 | op = rv_op_cm_pop; |
| 2562 | } |
| 2563 | break; |
| 2564 | case 12: |
| 2565 | if (((inst >> 4) & 0b01111) >= 4) { |
| 2566 | op = rv_op_cm_popretz; |
| 2567 | } |
| 2568 | break; |
| 2569 | case 14: |
| 2570 | if (((inst >> 4) & 0b01111) >= 4) { |
| 2571 | op = rv_op_cm_popret; |
| 2572 | } |
| 2573 | break; |
| 2574 | } |
| 2575 | } else { |
| 2576 | switch ((inst >> 10) & 0b011) { |
| 2577 | case 0: |
Weiwei Li | 2a2b221 | 2023-05-23 17:35:35 +0800 | [diff] [blame] | 2578 | if (!dec->cfg->ext_zcmt) { |
| 2579 | break; |
| 2580 | } |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 2581 | if (((inst >> 2) & 0xFF) >= 32) { |
| 2582 | op = rv_op_cm_jalt; |
| 2583 | } else { |
| 2584 | op = rv_op_cm_jt; |
| 2585 | } |
| 2586 | break; |
| 2587 | case 3: |
Weiwei Li | 2a2b221 | 2023-05-23 17:35:35 +0800 | [diff] [blame] | 2588 | if (!dec->cfg->ext_zcmp) { |
| 2589 | break; |
| 2590 | } |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 2591 | switch ((inst >> 5) & 0b011) { |
| 2592 | case 1: op = rv_op_cm_mvsa01; break; |
| 2593 | case 3: op = rv_op_cm_mva01s; break; |
| 2594 | } |
| 2595 | break; |
| 2596 | } |
| 2597 | } |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2598 | } |
Michael Clark | 1dc34be | 2018-04-30 11:06:31 +1200 | [diff] [blame] | 2599 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2600 | case 6: op = rv_op_c_swsp; break; |
| 2601 | case 7: |
| 2602 | if (isa == rv32) { |
| 2603 | op = rv_op_c_fswsp; |
| 2604 | } else { |
| 2605 | op = rv_op_c_sdsp; |
| 2606 | } |
| 2607 | break; |
| 2608 | } |
| 2609 | break; |
| 2610 | case 3: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2611 | switch ((inst >> 2) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2612 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2613 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2614 | case 0: op = rv_op_lb; break; |
| 2615 | case 1: op = rv_op_lh; break; |
| 2616 | case 2: op = rv_op_lw; break; |
| 2617 | case 3: op = rv_op_ld; break; |
| 2618 | case 4: op = rv_op_lbu; break; |
| 2619 | case 5: op = rv_op_lhu; break; |
| 2620 | case 6: op = rv_op_lwu; break; |
| 2621 | case 7: op = rv_op_ldu; break; |
| 2622 | } |
| 2623 | break; |
| 2624 | case 1: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2625 | switch ((inst >> 12) & 0b111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2626 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2627 | switch ((inst >> 20) & 0b111111111111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2628 | case 40: op = rv_op_vl1re8_v; break; |
| 2629 | case 552: op = rv_op_vl2re8_v; break; |
| 2630 | case 1576: op = rv_op_vl4re8_v; break; |
| 2631 | case 3624: op = rv_op_vl8re8_v; break; |
| 2632 | } |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2633 | switch ((inst >> 26) & 0b111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2634 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2635 | switch ((inst >> 20) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2636 | case 0: op = rv_op_vle8_v; break; |
| 2637 | case 11: op = rv_op_vlm_v; break; |
| 2638 | case 16: op = rv_op_vle8ff_v; break; |
| 2639 | } |
| 2640 | break; |
| 2641 | case 1: op = rv_op_vluxei8_v; break; |
| 2642 | case 2: op = rv_op_vlse8_v; break; |
| 2643 | case 3: op = rv_op_vloxei8_v; break; |
| 2644 | } |
| 2645 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2646 | case 2: op = rv_op_flw; break; |
| 2647 | case 3: op = rv_op_fld; break; |
| 2648 | case 4: op = rv_op_flq; break; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2649 | case 5: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2650 | switch ((inst >> 20) & 0b111111111111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2651 | case 40: op = rv_op_vl1re16_v; break; |
| 2652 | case 552: op = rv_op_vl2re16_v; break; |
| 2653 | case 1576: op = rv_op_vl4re16_v; break; |
| 2654 | case 3624: op = rv_op_vl8re16_v; break; |
| 2655 | } |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2656 | switch ((inst >> 26) & 0b111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2657 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2658 | switch ((inst >> 20) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2659 | case 0: op = rv_op_vle16_v; break; |
| 2660 | case 16: op = rv_op_vle16ff_v; break; |
| 2661 | } |
| 2662 | break; |
| 2663 | case 1: op = rv_op_vluxei16_v; break; |
| 2664 | case 2: op = rv_op_vlse16_v; break; |
| 2665 | case 3: op = rv_op_vloxei16_v; break; |
| 2666 | } |
| 2667 | break; |
| 2668 | case 6: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2669 | switch ((inst >> 20) & 0b111111111111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2670 | case 40: op = rv_op_vl1re32_v; break; |
| 2671 | case 552: op = rv_op_vl2re32_v; break; |
| 2672 | case 1576: op = rv_op_vl4re32_v; break; |
| 2673 | case 3624: op = rv_op_vl8re32_v; break; |
| 2674 | } |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2675 | switch ((inst >> 26) & 0b111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2676 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2677 | switch ((inst >> 20) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2678 | case 0: op = rv_op_vle32_v; break; |
| 2679 | case 16: op = rv_op_vle32ff_v; break; |
| 2680 | } |
| 2681 | break; |
| 2682 | case 1: op = rv_op_vluxei32_v; break; |
| 2683 | case 2: op = rv_op_vlse32_v; break; |
| 2684 | case 3: op = rv_op_vloxei32_v; break; |
| 2685 | } |
| 2686 | break; |
| 2687 | case 7: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2688 | switch ((inst >> 20) & 0b111111111111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2689 | case 40: op = rv_op_vl1re64_v; break; |
| 2690 | case 552: op = rv_op_vl2re64_v; break; |
| 2691 | case 1576: op = rv_op_vl4re64_v; break; |
| 2692 | case 3624: op = rv_op_vl8re64_v; break; |
| 2693 | } |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2694 | switch ((inst >> 26) & 0b111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2695 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2696 | switch ((inst >> 20) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2697 | case 0: op = rv_op_vle64_v; break; |
| 2698 | case 16: op = rv_op_vle64ff_v; break; |
| 2699 | } |
| 2700 | break; |
| 2701 | case 1: op = rv_op_vluxei64_v; break; |
| 2702 | case 2: op = rv_op_vlse64_v; break; |
| 2703 | case 3: op = rv_op_vloxei64_v; break; |
| 2704 | } |
| 2705 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2706 | } |
| 2707 | break; |
| 2708 | case 3: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2709 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2710 | case 0: op = rv_op_fence; break; |
| 2711 | case 1: op = rv_op_fence_i; break; |
| 2712 | case 2: op = rv_op_lq; break; |
| 2713 | } |
| 2714 | break; |
| 2715 | case 4: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2716 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2717 | case 0: op = rv_op_addi; break; |
| 2718 | case 1: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2719 | switch ((inst >> 27) & 0b11111) { |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2720 | case 0b00000: op = rv_op_slli; break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2721 | case 0b00001: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2722 | switch ((inst >> 20) & 0b1111111) { |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2723 | case 0b0001111: op = rv_op_zip; break; |
| 2724 | } |
| 2725 | break; |
| 2726 | case 0b00010: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2727 | switch ((inst >> 20) & 0b1111111) { |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2728 | case 0b0000000: op = rv_op_sha256sum0; break; |
| 2729 | case 0b0000001: op = rv_op_sha256sum1; break; |
| 2730 | case 0b0000010: op = rv_op_sha256sig0; break; |
| 2731 | case 0b0000011: op = rv_op_sha256sig1; break; |
| 2732 | case 0b0000100: op = rv_op_sha512sum0; break; |
| 2733 | case 0b0000101: op = rv_op_sha512sum1; break; |
| 2734 | case 0b0000110: op = rv_op_sha512sig0; break; |
| 2735 | case 0b0000111: op = rv_op_sha512sig1; break; |
| 2736 | case 0b0001000: op = rv_op_sm3p0; break; |
| 2737 | case 0b0001001: op = rv_op_sm3p1; break; |
| 2738 | } |
| 2739 | break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2740 | case 0b00101: op = rv_op_bseti; break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2741 | case 0b00110: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2742 | switch ((inst >> 20) & 0b1111111) { |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2743 | case 0b0000000: op = rv_op_aes64im; break; |
| 2744 | default: |
| 2745 | if (((inst >> 24) & 0b0111) == 0b001) { |
| 2746 | op = rv_op_aes64ks1i; |
| 2747 | } |
| 2748 | break; |
| 2749 | } |
| 2750 | break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2751 | case 0b01001: op = rv_op_bclri; break; |
| 2752 | case 0b01101: op = rv_op_binvi; break; |
| 2753 | case 0b01100: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2754 | switch ((inst >> 20) & 0b1111111) { |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2755 | case 0b0000000: op = rv_op_clz; break; |
| 2756 | case 0b0000001: op = rv_op_ctz; break; |
| 2757 | case 0b0000010: op = rv_op_cpop; break; |
| 2758 | /* 0b0000011 */ |
| 2759 | case 0b0000100: op = rv_op_sext_b; break; |
| 2760 | case 0b0000101: op = rv_op_sext_h; break; |
| 2761 | } |
| 2762 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2763 | } |
| 2764 | break; |
| 2765 | case 2: op = rv_op_slti; break; |
| 2766 | case 3: op = rv_op_sltiu; break; |
| 2767 | case 4: op = rv_op_xori; break; |
| 2768 | case 5: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2769 | switch ((inst >> 27) & 0b11111) { |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2770 | case 0b00000: op = rv_op_srli; break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2771 | case 0b00001: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2772 | switch ((inst >> 20) & 0b1111111) { |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2773 | case 0b0001111: op = rv_op_unzip; break; |
| 2774 | } |
| 2775 | break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2776 | case 0b00101: op = rv_op_orc_b; break; |
| 2777 | case 0b01000: op = rv_op_srai; break; |
| 2778 | case 0b01001: op = rv_op_bexti; break; |
| 2779 | case 0b01100: op = rv_op_rori; break; |
| 2780 | case 0b01101: |
| 2781 | switch ((inst >> 20) & 0b1111111) { |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2782 | case 0b0011000: op = rv_op_rev8; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2783 | case 0b0111000: op = rv_op_rev8; break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2784 | case 0b0000111: op = rv_op_brev8; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2785 | } |
| 2786 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2787 | } |
| 2788 | break; |
| 2789 | case 6: op = rv_op_ori; break; |
| 2790 | case 7: op = rv_op_andi; break; |
| 2791 | } |
| 2792 | break; |
| 2793 | case 5: op = rv_op_auipc; break; |
| 2794 | case 6: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2795 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2796 | case 0: op = rv_op_addiw; break; |
| 2797 | case 1: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2798 | switch ((inst >> 26) & 0b111111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2799 | case 0: op = rv_op_slliw; break; |
Ivan Klokov | 13e269f | 2023-02-27 12:02:28 +0300 | [diff] [blame] | 2800 | case 2: op = rv_op_slli_uw; break; |
| 2801 | case 24: |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2802 | switch ((inst >> 20) & 0b11111) { |
| 2803 | case 0b00000: op = rv_op_clzw; break; |
| 2804 | case 0b00001: op = rv_op_ctzw; break; |
| 2805 | case 0b00010: op = rv_op_cpopw; break; |
| 2806 | } |
| 2807 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2808 | } |
| 2809 | break; |
| 2810 | case 5: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2811 | switch ((inst >> 25) & 0b1111111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2812 | case 0: op = rv_op_srliw; break; |
| 2813 | case 32: op = rv_op_sraiw; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2814 | case 48: op = rv_op_roriw; break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2815 | } |
| 2816 | break; |
| 2817 | } |
| 2818 | break; |
| 2819 | case 8: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2820 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2821 | case 0: op = rv_op_sb; break; |
| 2822 | case 1: op = rv_op_sh; break; |
| 2823 | case 2: op = rv_op_sw; break; |
| 2824 | case 3: op = rv_op_sd; break; |
| 2825 | case 4: op = rv_op_sq; break; |
| 2826 | } |
| 2827 | break; |
| 2828 | case 9: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2829 | switch ((inst >> 12) & 0b111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2830 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2831 | switch ((inst >> 20) & 0b111111111111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2832 | case 40: op = rv_op_vs1r_v; break; |
| 2833 | case 552: op = rv_op_vs2r_v; break; |
| 2834 | case 1576: op = rv_op_vs4r_v; break; |
| 2835 | case 3624: op = rv_op_vs8r_v; break; |
| 2836 | } |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2837 | switch ((inst >> 26) & 0b111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2838 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2839 | switch ((inst >> 20) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2840 | case 0: op = rv_op_vse8_v; break; |
| 2841 | case 11: op = rv_op_vsm_v; break; |
| 2842 | } |
| 2843 | break; |
| 2844 | case 1: op = rv_op_vsuxei8_v; break; |
| 2845 | case 2: op = rv_op_vsse8_v; break; |
| 2846 | case 3: op = rv_op_vsoxei8_v; break; |
| 2847 | } |
| 2848 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2849 | case 2: op = rv_op_fsw; break; |
| 2850 | case 3: op = rv_op_fsd; break; |
| 2851 | case 4: op = rv_op_fsq; break; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2852 | case 5: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2853 | switch ((inst >> 26) & 0b111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2854 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2855 | switch ((inst >> 20) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2856 | case 0: op = rv_op_vse16_v; break; |
| 2857 | } |
| 2858 | break; |
| 2859 | case 1: op = rv_op_vsuxei16_v; break; |
| 2860 | case 2: op = rv_op_vsse16_v; break; |
| 2861 | case 3: op = rv_op_vsoxei16_v; break; |
| 2862 | } |
| 2863 | break; |
| 2864 | case 6: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2865 | switch ((inst >> 26) & 0b111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2866 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2867 | switch ((inst >> 20) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2868 | case 0: op = rv_op_vse32_v; break; |
| 2869 | } |
| 2870 | break; |
| 2871 | case 1: op = rv_op_vsuxei32_v; break; |
| 2872 | case 2: op = rv_op_vsse32_v; break; |
| 2873 | case 3: op = rv_op_vsoxei32_v; break; |
| 2874 | } |
| 2875 | break; |
| 2876 | case 7: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2877 | switch ((inst >> 26) & 0b111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2878 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2879 | switch ((inst >> 20) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 2880 | case 0: op = rv_op_vse64_v; break; |
| 2881 | } |
| 2882 | break; |
| 2883 | case 1: op = rv_op_vsuxei64_v; break; |
| 2884 | case 2: op = rv_op_vsse64_v; break; |
| 2885 | case 3: op = rv_op_vsoxei64_v; break; |
| 2886 | } |
| 2887 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2888 | } |
| 2889 | break; |
| 2890 | case 11: |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 2891 | switch (((inst >> 24) & 0b11111000) | |
| 2892 | ((inst >> 12) & 0b00000111)) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2893 | case 2: op = rv_op_amoadd_w; break; |
| 2894 | case 3: op = rv_op_amoadd_d; break; |
| 2895 | case 4: op = rv_op_amoadd_q; break; |
| 2896 | case 10: op = rv_op_amoswap_w; break; |
| 2897 | case 11: op = rv_op_amoswap_d; break; |
| 2898 | case 12: op = rv_op_amoswap_q; break; |
| 2899 | case 18: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2900 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2901 | case 0: op = rv_op_lr_w; break; |
| 2902 | } |
| 2903 | break; |
| 2904 | case 19: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2905 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2906 | case 0: op = rv_op_lr_d; break; |
| 2907 | } |
| 2908 | break; |
| 2909 | case 20: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 2910 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2911 | case 0: op = rv_op_lr_q; break; |
| 2912 | } |
| 2913 | break; |
| 2914 | case 26: op = rv_op_sc_w; break; |
| 2915 | case 27: op = rv_op_sc_d; break; |
| 2916 | case 28: op = rv_op_sc_q; break; |
| 2917 | case 34: op = rv_op_amoxor_w; break; |
| 2918 | case 35: op = rv_op_amoxor_d; break; |
| 2919 | case 36: op = rv_op_amoxor_q; break; |
| 2920 | case 66: op = rv_op_amoor_w; break; |
| 2921 | case 67: op = rv_op_amoor_d; break; |
| 2922 | case 68: op = rv_op_amoor_q; break; |
| 2923 | case 98: op = rv_op_amoand_w; break; |
| 2924 | case 99: op = rv_op_amoand_d; break; |
| 2925 | case 100: op = rv_op_amoand_q; break; |
| 2926 | case 130: op = rv_op_amomin_w; break; |
| 2927 | case 131: op = rv_op_amomin_d; break; |
| 2928 | case 132: op = rv_op_amomin_q; break; |
| 2929 | case 162: op = rv_op_amomax_w; break; |
| 2930 | case 163: op = rv_op_amomax_d; break; |
| 2931 | case 164: op = rv_op_amomax_q; break; |
| 2932 | case 194: op = rv_op_amominu_w; break; |
| 2933 | case 195: op = rv_op_amominu_d; break; |
| 2934 | case 196: op = rv_op_amominu_q; break; |
| 2935 | case 226: op = rv_op_amomaxu_w; break; |
| 2936 | case 227: op = rv_op_amomaxu_d; break; |
| 2937 | case 228: op = rv_op_amomaxu_q; break; |
| 2938 | } |
| 2939 | break; |
| 2940 | case 12: |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 2941 | switch (((inst >> 22) & 0b1111111000) | |
| 2942 | ((inst >> 12) & 0b0000000111)) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2943 | case 0: op = rv_op_add; break; |
| 2944 | case 1: op = rv_op_sll; break; |
| 2945 | case 2: op = rv_op_slt; break; |
| 2946 | case 3: op = rv_op_sltu; break; |
| 2947 | case 4: op = rv_op_xor; break; |
| 2948 | case 5: op = rv_op_srl; break; |
| 2949 | case 6: op = rv_op_or; break; |
| 2950 | case 7: op = rv_op_and; break; |
| 2951 | case 8: op = rv_op_mul; break; |
| 2952 | case 9: op = rv_op_mulh; break; |
| 2953 | case 10: op = rv_op_mulhsu; break; |
| 2954 | case 11: op = rv_op_mulhu; break; |
| 2955 | case 12: op = rv_op_div; break; |
| 2956 | case 13: op = rv_op_divu; break; |
| 2957 | case 14: op = rv_op_rem; break; |
| 2958 | case 15: op = rv_op_remu; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2959 | case 36: |
| 2960 | switch ((inst >> 20) & 0b11111) { |
| 2961 | case 0: op = rv_op_zext_h; break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2962 | default: op = rv_op_pack; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2963 | } |
| 2964 | break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2965 | case 39: op = rv_op_packh; break; |
| 2966 | |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2967 | case 41: op = rv_op_clmul; break; |
| 2968 | case 42: op = rv_op_clmulr; break; |
| 2969 | case 43: op = rv_op_clmulh; break; |
| 2970 | case 44: op = rv_op_min; break; |
| 2971 | case 45: op = rv_op_minu; break; |
| 2972 | case 46: op = rv_op_max; break; |
| 2973 | case 47: op = rv_op_maxu; break; |
Richard Henderson | d397be9 | 2023-04-26 13:33:05 +0100 | [diff] [blame] | 2974 | case 075: op = rv_op_czero_eqz; break; |
| 2975 | case 077: op = rv_op_czero_nez; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2976 | case 130: op = rv_op_sh1add; break; |
| 2977 | case 132: op = rv_op_sh2add; break; |
| 2978 | case 134: op = rv_op_sh3add; break; |
| 2979 | case 161: op = rv_op_bset; break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2980 | case 162: op = rv_op_xperm4; break; |
| 2981 | case 164: op = rv_op_xperm8; break; |
| 2982 | case 200: op = rv_op_aes64es; break; |
| 2983 | case 216: op = rv_op_aes64esm; break; |
| 2984 | case 232: op = rv_op_aes64ds; break; |
| 2985 | case 248: op = rv_op_aes64dsm; break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2986 | case 256: op = rv_op_sub; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2987 | case 260: op = rv_op_xnor; break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 2988 | case 261: op = rv_op_sra; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2989 | case 262: op = rv_op_orn; break; |
| 2990 | case 263: op = rv_op_andn; break; |
| 2991 | case 289: op = rv_op_bclr; break; |
| 2992 | case 293: op = rv_op_bext; break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 2993 | case 320: op = rv_op_sha512sum0r; break; |
| 2994 | case 328: op = rv_op_sha512sum1r; break; |
| 2995 | case 336: op = rv_op_sha512sig0l; break; |
| 2996 | case 344: op = rv_op_sha512sig1l; break; |
| 2997 | case 368: op = rv_op_sha512sig0h; break; |
| 2998 | case 376: op = rv_op_sha512sig1h; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 2999 | case 385: op = rv_op_rol; break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 3000 | case 389: op = rv_op_ror; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 3001 | case 417: op = rv_op_binv; break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 3002 | case 504: op = rv_op_aes64ks2; break; |
| 3003 | } |
| 3004 | switch ((inst >> 25) & 0b0011111) { |
| 3005 | case 17: op = rv_op_aes32esi; break; |
| 3006 | case 19: op = rv_op_aes32esmi; break; |
| 3007 | case 21: op = rv_op_aes32dsi; break; |
| 3008 | case 23: op = rv_op_aes32dsmi; break; |
| 3009 | case 24: op = rv_op_sm4ed; break; |
| 3010 | case 26: op = rv_op_sm4ks; break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3011 | } |
| 3012 | break; |
| 3013 | case 13: op = rv_op_lui; break; |
| 3014 | case 14: |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3015 | switch (((inst >> 22) & 0b1111111000) | |
| 3016 | ((inst >> 12) & 0b0000000111)) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3017 | case 0: op = rv_op_addw; break; |
| 3018 | case 1: op = rv_op_sllw; break; |
| 3019 | case 5: op = rv_op_srlw; break; |
| 3020 | case 8: op = rv_op_mulw; break; |
| 3021 | case 12: op = rv_op_divw; break; |
| 3022 | case 13: op = rv_op_divuw; break; |
| 3023 | case 14: op = rv_op_remw; break; |
| 3024 | case 15: op = rv_op_remuw; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 3025 | case 32: op = rv_op_add_uw; break; |
| 3026 | case 36: |
| 3027 | switch ((inst >> 20) & 0b11111) { |
| 3028 | case 0: op = rv_op_zext_h; break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 3029 | default: op = rv_op_packw; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 3030 | } |
| 3031 | break; |
| 3032 | case 130: op = rv_op_sh1add_uw; break; |
| 3033 | case 132: op = rv_op_sh2add_uw; break; |
| 3034 | case 134: op = rv_op_sh3add_uw; break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3035 | case 256: op = rv_op_subw; break; |
| 3036 | case 261: op = rv_op_sraw; break; |
Philipp Tomsich | 02c1b56 | 2021-09-11 16:00:16 +0200 | [diff] [blame] | 3037 | case 385: op = rv_op_rolw; break; |
| 3038 | case 389: op = rv_op_rorw; break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3039 | } |
| 3040 | break; |
| 3041 | case 16: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3042 | switch ((inst >> 25) & 0b11) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3043 | case 0: op = rv_op_fmadd_s; break; |
| 3044 | case 1: op = rv_op_fmadd_d; break; |
| 3045 | case 3: op = rv_op_fmadd_q; break; |
| 3046 | } |
| 3047 | break; |
| 3048 | case 17: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3049 | switch ((inst >> 25) & 0b11) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3050 | case 0: op = rv_op_fmsub_s; break; |
| 3051 | case 1: op = rv_op_fmsub_d; break; |
| 3052 | case 3: op = rv_op_fmsub_q; break; |
| 3053 | } |
| 3054 | break; |
| 3055 | case 18: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3056 | switch ((inst >> 25) & 0b11) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3057 | case 0: op = rv_op_fnmsub_s; break; |
| 3058 | case 1: op = rv_op_fnmsub_d; break; |
| 3059 | case 3: op = rv_op_fnmsub_q; break; |
| 3060 | } |
| 3061 | break; |
| 3062 | case 19: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3063 | switch ((inst >> 25) & 0b11) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3064 | case 0: op = rv_op_fnmadd_s; break; |
| 3065 | case 1: op = rv_op_fnmadd_d; break; |
| 3066 | case 3: op = rv_op_fnmadd_q; break; |
| 3067 | } |
| 3068 | break; |
| 3069 | case 20: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3070 | switch ((inst >> 25) & 0b1111111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3071 | case 0: op = rv_op_fadd_s; break; |
| 3072 | case 1: op = rv_op_fadd_d; break; |
| 3073 | case 3: op = rv_op_fadd_q; break; |
| 3074 | case 4: op = rv_op_fsub_s; break; |
| 3075 | case 5: op = rv_op_fsub_d; break; |
| 3076 | case 7: op = rv_op_fsub_q; break; |
| 3077 | case 8: op = rv_op_fmul_s; break; |
| 3078 | case 9: op = rv_op_fmul_d; break; |
| 3079 | case 11: op = rv_op_fmul_q; break; |
| 3080 | case 12: op = rv_op_fdiv_s; break; |
| 3081 | case 13: op = rv_op_fdiv_d; break; |
| 3082 | case 15: op = rv_op_fdiv_q; break; |
| 3083 | case 16: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3084 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3085 | case 0: op = rv_op_fsgnj_s; break; |
| 3086 | case 1: op = rv_op_fsgnjn_s; break; |
| 3087 | case 2: op = rv_op_fsgnjx_s; break; |
| 3088 | } |
| 3089 | break; |
| 3090 | case 17: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3091 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3092 | case 0: op = rv_op_fsgnj_d; break; |
| 3093 | case 1: op = rv_op_fsgnjn_d; break; |
| 3094 | case 2: op = rv_op_fsgnjx_d; break; |
| 3095 | } |
| 3096 | break; |
| 3097 | case 19: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3098 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3099 | case 0: op = rv_op_fsgnj_q; break; |
| 3100 | case 1: op = rv_op_fsgnjn_q; break; |
| 3101 | case 2: op = rv_op_fsgnjx_q; break; |
| 3102 | } |
| 3103 | break; |
| 3104 | case 20: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3105 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3106 | case 0: op = rv_op_fmin_s; break; |
| 3107 | case 1: op = rv_op_fmax_s; break; |
| 3108 | } |
| 3109 | break; |
| 3110 | case 21: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3111 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3112 | case 0: op = rv_op_fmin_d; break; |
| 3113 | case 1: op = rv_op_fmax_d; break; |
| 3114 | } |
| 3115 | break; |
| 3116 | case 23: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3117 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3118 | case 0: op = rv_op_fmin_q; break; |
| 3119 | case 1: op = rv_op_fmax_q; break; |
| 3120 | } |
| 3121 | break; |
| 3122 | case 32: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3123 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3124 | case 1: op = rv_op_fcvt_s_d; break; |
| 3125 | case 3: op = rv_op_fcvt_s_q; break; |
| 3126 | } |
| 3127 | break; |
| 3128 | case 33: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3129 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3130 | case 0: op = rv_op_fcvt_d_s; break; |
| 3131 | case 3: op = rv_op_fcvt_d_q; break; |
| 3132 | } |
| 3133 | break; |
| 3134 | case 35: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3135 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3136 | case 0: op = rv_op_fcvt_q_s; break; |
| 3137 | case 1: op = rv_op_fcvt_q_d; break; |
| 3138 | } |
| 3139 | break; |
| 3140 | case 44: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3141 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3142 | case 0: op = rv_op_fsqrt_s; break; |
| 3143 | } |
| 3144 | break; |
| 3145 | case 45: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3146 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3147 | case 0: op = rv_op_fsqrt_d; break; |
| 3148 | } |
| 3149 | break; |
| 3150 | case 47: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3151 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3152 | case 0: op = rv_op_fsqrt_q; break; |
| 3153 | } |
| 3154 | break; |
| 3155 | case 80: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3156 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3157 | case 0: op = rv_op_fle_s; break; |
| 3158 | case 1: op = rv_op_flt_s; break; |
| 3159 | case 2: op = rv_op_feq_s; break; |
| 3160 | } |
| 3161 | break; |
| 3162 | case 81: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3163 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3164 | case 0: op = rv_op_fle_d; break; |
| 3165 | case 1: op = rv_op_flt_d; break; |
| 3166 | case 2: op = rv_op_feq_d; break; |
| 3167 | } |
| 3168 | break; |
| 3169 | case 83: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3170 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3171 | case 0: op = rv_op_fle_q; break; |
| 3172 | case 1: op = rv_op_flt_q; break; |
| 3173 | case 2: op = rv_op_feq_q; break; |
| 3174 | } |
| 3175 | break; |
| 3176 | case 96: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3177 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3178 | case 0: op = rv_op_fcvt_w_s; break; |
| 3179 | case 1: op = rv_op_fcvt_wu_s; break; |
| 3180 | case 2: op = rv_op_fcvt_l_s; break; |
| 3181 | case 3: op = rv_op_fcvt_lu_s; break; |
| 3182 | } |
| 3183 | break; |
| 3184 | case 97: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3185 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3186 | case 0: op = rv_op_fcvt_w_d; break; |
| 3187 | case 1: op = rv_op_fcvt_wu_d; break; |
| 3188 | case 2: op = rv_op_fcvt_l_d; break; |
| 3189 | case 3: op = rv_op_fcvt_lu_d; break; |
| 3190 | } |
| 3191 | break; |
| 3192 | case 99: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3193 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3194 | case 0: op = rv_op_fcvt_w_q; break; |
| 3195 | case 1: op = rv_op_fcvt_wu_q; break; |
| 3196 | case 2: op = rv_op_fcvt_l_q; break; |
| 3197 | case 3: op = rv_op_fcvt_lu_q; break; |
| 3198 | } |
| 3199 | break; |
| 3200 | case 104: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3201 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3202 | case 0: op = rv_op_fcvt_s_w; break; |
| 3203 | case 1: op = rv_op_fcvt_s_wu; break; |
| 3204 | case 2: op = rv_op_fcvt_s_l; break; |
| 3205 | case 3: op = rv_op_fcvt_s_lu; break; |
| 3206 | } |
| 3207 | break; |
| 3208 | case 105: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3209 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3210 | case 0: op = rv_op_fcvt_d_w; break; |
| 3211 | case 1: op = rv_op_fcvt_d_wu; break; |
| 3212 | case 2: op = rv_op_fcvt_d_l; break; |
| 3213 | case 3: op = rv_op_fcvt_d_lu; break; |
| 3214 | } |
| 3215 | break; |
| 3216 | case 107: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3217 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3218 | case 0: op = rv_op_fcvt_q_w; break; |
| 3219 | case 1: op = rv_op_fcvt_q_wu; break; |
| 3220 | case 2: op = rv_op_fcvt_q_l; break; |
| 3221 | case 3: op = rv_op_fcvt_q_lu; break; |
| 3222 | } |
| 3223 | break; |
| 3224 | case 112: |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3225 | switch (((inst >> 17) & 0b11111000) | |
| 3226 | ((inst >> 12) & 0b00000111)) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3227 | case 0: op = rv_op_fmv_x_s; break; |
| 3228 | case 1: op = rv_op_fclass_s; break; |
| 3229 | } |
| 3230 | break; |
| 3231 | case 113: |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3232 | switch (((inst >> 17) & 0b11111000) | |
| 3233 | ((inst >> 12) & 0b00000111)) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3234 | case 0: op = rv_op_fmv_x_d; break; |
| 3235 | case 1: op = rv_op_fclass_d; break; |
| 3236 | } |
| 3237 | break; |
| 3238 | case 115: |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3239 | switch (((inst >> 17) & 0b11111000) | |
| 3240 | ((inst >> 12) & 0b00000111)) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3241 | case 0: op = rv_op_fmv_x_q; break; |
| 3242 | case 1: op = rv_op_fclass_q; break; |
| 3243 | } |
| 3244 | break; |
| 3245 | case 120: |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3246 | switch (((inst >> 17) & 0b11111000) | |
| 3247 | ((inst >> 12) & 0b00000111)) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3248 | case 0: op = rv_op_fmv_s_x; break; |
| 3249 | } |
| 3250 | break; |
| 3251 | case 121: |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3252 | switch (((inst >> 17) & 0b11111000) | |
| 3253 | ((inst >> 12) & 0b00000111)) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3254 | case 0: op = rv_op_fmv_d_x; break; |
| 3255 | } |
| 3256 | break; |
| 3257 | case 123: |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3258 | switch (((inst >> 17) & 0b11111000) | |
| 3259 | ((inst >> 12) & 0b00000111)) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3260 | case 0: op = rv_op_fmv_q_x; break; |
| 3261 | } |
| 3262 | break; |
| 3263 | } |
| 3264 | break; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3265 | case 21: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3266 | switch ((inst >> 12) & 0b111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3267 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3268 | switch ((inst >> 26) & 0b111111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3269 | case 0: op = rv_op_vadd_vv; break; |
| 3270 | case 2: op = rv_op_vsub_vv; break; |
| 3271 | case 4: op = rv_op_vminu_vv; break; |
| 3272 | case 5: op = rv_op_vmin_vv; break; |
| 3273 | case 6: op = rv_op_vmaxu_vv; break; |
| 3274 | case 7: op = rv_op_vmax_vv; break; |
| 3275 | case 9: op = rv_op_vand_vv; break; |
| 3276 | case 10: op = rv_op_vor_vv; break; |
| 3277 | case 11: op = rv_op_vxor_vv; break; |
| 3278 | case 12: op = rv_op_vrgather_vv; break; |
| 3279 | case 14: op = rv_op_vrgatherei16_vv; break; |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3280 | case 16: |
| 3281 | if (((inst >> 25) & 1) == 0) { |
| 3282 | op = rv_op_vadc_vvm; |
| 3283 | } |
| 3284 | break; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3285 | case 17: op = rv_op_vmadc_vvm; break; |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3286 | case 18: |
| 3287 | if (((inst >> 25) & 1) == 0) { |
| 3288 | op = rv_op_vsbc_vvm; |
| 3289 | } |
| 3290 | break; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3291 | case 19: op = rv_op_vmsbc_vvm; break; |
| 3292 | case 23: |
| 3293 | if (((inst >> 20) & 0b111111) == 32) |
| 3294 | op = rv_op_vmv_v_v; |
| 3295 | else if (((inst >> 25) & 1) == 0) |
| 3296 | op = rv_op_vmerge_vvm; |
| 3297 | break; |
| 3298 | case 24: op = rv_op_vmseq_vv; break; |
| 3299 | case 25: op = rv_op_vmsne_vv; break; |
| 3300 | case 26: op = rv_op_vmsltu_vv; break; |
| 3301 | case 27: op = rv_op_vmslt_vv; break; |
| 3302 | case 28: op = rv_op_vmsleu_vv; break; |
| 3303 | case 29: op = rv_op_vmsle_vv; break; |
| 3304 | case 32: op = rv_op_vsaddu_vv; break; |
| 3305 | case 33: op = rv_op_vsadd_vv; break; |
| 3306 | case 34: op = rv_op_vssubu_vv; break; |
| 3307 | case 35: op = rv_op_vssub_vv; break; |
| 3308 | case 37: op = rv_op_vsll_vv; break; |
| 3309 | case 39: op = rv_op_vsmul_vv; break; |
| 3310 | case 40: op = rv_op_vsrl_vv; break; |
| 3311 | case 41: op = rv_op_vsra_vv; break; |
| 3312 | case 42: op = rv_op_vssrl_vv; break; |
| 3313 | case 43: op = rv_op_vssra_vv; break; |
| 3314 | case 44: op = rv_op_vnsrl_wv; break; |
| 3315 | case 45: op = rv_op_vnsra_wv; break; |
| 3316 | case 46: op = rv_op_vnclipu_wv; break; |
| 3317 | case 47: op = rv_op_vnclip_wv; break; |
| 3318 | case 48: op = rv_op_vwredsumu_vs; break; |
| 3319 | case 49: op = rv_op_vwredsum_vs; break; |
| 3320 | } |
| 3321 | break; |
| 3322 | case 1: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3323 | switch ((inst >> 26) & 0b111111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3324 | case 0: op = rv_op_vfadd_vv; break; |
| 3325 | case 1: op = rv_op_vfredusum_vs; break; |
| 3326 | case 2: op = rv_op_vfsub_vv; break; |
| 3327 | case 3: op = rv_op_vfredosum_vs; break; |
| 3328 | case 4: op = rv_op_vfmin_vv; break; |
| 3329 | case 5: op = rv_op_vfredmin_vs; break; |
| 3330 | case 6: op = rv_op_vfmax_vv; break; |
| 3331 | case 7: op = rv_op_vfredmax_vs; break; |
| 3332 | case 8: op = rv_op_vfsgnj_vv; break; |
| 3333 | case 9: op = rv_op_vfsgnjn_vv; break; |
| 3334 | case 10: op = rv_op_vfsgnjx_vv; break; |
| 3335 | case 16: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3336 | switch ((inst >> 15) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3337 | case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break; |
| 3338 | } |
| 3339 | break; |
| 3340 | case 18: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3341 | switch ((inst >> 15) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3342 | case 0: op = rv_op_vfcvt_xu_f_v; break; |
| 3343 | case 1: op = rv_op_vfcvt_x_f_v; break; |
| 3344 | case 2: op = rv_op_vfcvt_f_xu_v; break; |
| 3345 | case 3: op = rv_op_vfcvt_f_x_v; break; |
| 3346 | case 6: op = rv_op_vfcvt_rtz_xu_f_v; break; |
| 3347 | case 7: op = rv_op_vfcvt_rtz_x_f_v; break; |
| 3348 | case 8: op = rv_op_vfwcvt_xu_f_v; break; |
| 3349 | case 9: op = rv_op_vfwcvt_x_f_v; break; |
| 3350 | case 10: op = rv_op_vfwcvt_f_xu_v; break; |
| 3351 | case 11: op = rv_op_vfwcvt_f_x_v; break; |
| 3352 | case 12: op = rv_op_vfwcvt_f_f_v; break; |
| 3353 | case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break; |
| 3354 | case 15: op = rv_op_vfwcvt_rtz_x_f_v; break; |
| 3355 | case 16: op = rv_op_vfncvt_xu_f_w; break; |
| 3356 | case 17: op = rv_op_vfncvt_x_f_w; break; |
| 3357 | case 18: op = rv_op_vfncvt_f_xu_w; break; |
| 3358 | case 19: op = rv_op_vfncvt_f_x_w; break; |
| 3359 | case 20: op = rv_op_vfncvt_f_f_w; break; |
| 3360 | case 21: op = rv_op_vfncvt_rod_f_f_w; break; |
| 3361 | case 22: op = rv_op_vfncvt_rtz_xu_f_w; break; |
| 3362 | case 23: op = rv_op_vfncvt_rtz_x_f_w; break; |
| 3363 | } |
| 3364 | break; |
| 3365 | case 19: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3366 | switch ((inst >> 15) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3367 | case 0: op = rv_op_vfsqrt_v; break; |
| 3368 | case 4: op = rv_op_vfrsqrt7_v; break; |
| 3369 | case 5: op = rv_op_vfrec7_v; break; |
| 3370 | case 16: op = rv_op_vfclass_v; break; |
| 3371 | } |
| 3372 | break; |
| 3373 | case 24: op = rv_op_vmfeq_vv; break; |
| 3374 | case 25: op = rv_op_vmfle_vv; break; |
| 3375 | case 27: op = rv_op_vmflt_vv; break; |
| 3376 | case 28: op = rv_op_vmfne_vv; break; |
| 3377 | case 32: op = rv_op_vfdiv_vv; break; |
| 3378 | case 36: op = rv_op_vfmul_vv; break; |
| 3379 | case 40: op = rv_op_vfmadd_vv; break; |
| 3380 | case 41: op = rv_op_vfnmadd_vv; break; |
| 3381 | case 42: op = rv_op_vfmsub_vv; break; |
| 3382 | case 43: op = rv_op_vfnmsub_vv; break; |
| 3383 | case 44: op = rv_op_vfmacc_vv; break; |
| 3384 | case 45: op = rv_op_vfnmacc_vv; break; |
| 3385 | case 46: op = rv_op_vfmsac_vv; break; |
| 3386 | case 47: op = rv_op_vfnmsac_vv; break; |
| 3387 | case 48: op = rv_op_vfwadd_vv; break; |
| 3388 | case 49: op = rv_op_vfwredusum_vs; break; |
| 3389 | case 50: op = rv_op_vfwsub_vv; break; |
| 3390 | case 51: op = rv_op_vfwredosum_vs; break; |
| 3391 | case 52: op = rv_op_vfwadd_wv; break; |
| 3392 | case 54: op = rv_op_vfwsub_wv; break; |
| 3393 | case 56: op = rv_op_vfwmul_vv; break; |
| 3394 | case 60: op = rv_op_vfwmacc_vv; break; |
| 3395 | case 61: op = rv_op_vfwnmacc_vv; break; |
| 3396 | case 62: op = rv_op_vfwmsac_vv; break; |
| 3397 | case 63: op = rv_op_vfwnmsac_vv; break; |
| 3398 | } |
| 3399 | break; |
| 3400 | case 2: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3401 | switch ((inst >> 26) & 0b111111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3402 | case 0: op = rv_op_vredsum_vs; break; |
| 3403 | case 1: op = rv_op_vredand_vs; break; |
| 3404 | case 2: op = rv_op_vredor_vs; break; |
| 3405 | case 3: op = rv_op_vredxor_vs; break; |
| 3406 | case 4: op = rv_op_vredminu_vs; break; |
| 3407 | case 5: op = rv_op_vredmin_vs; break; |
| 3408 | case 6: op = rv_op_vredmaxu_vs; break; |
| 3409 | case 7: op = rv_op_vredmax_vs; break; |
| 3410 | case 8: op = rv_op_vaaddu_vv; break; |
| 3411 | case 9: op = rv_op_vaadd_vv; break; |
| 3412 | case 10: op = rv_op_vasubu_vv; break; |
| 3413 | case 11: op = rv_op_vasub_vv; break; |
| 3414 | case 16: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3415 | switch ((inst >> 15) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3416 | case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break; |
| 3417 | case 16: op = rv_op_vcpop_m; break; |
| 3418 | case 17: op = rv_op_vfirst_m; break; |
| 3419 | } |
| 3420 | break; |
| 3421 | case 18: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3422 | switch ((inst >> 15) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3423 | case 2: op = rv_op_vzext_vf8; break; |
| 3424 | case 3: op = rv_op_vsext_vf8; break; |
| 3425 | case 4: op = rv_op_vzext_vf4; break; |
| 3426 | case 5: op = rv_op_vsext_vf4; break; |
| 3427 | case 6: op = rv_op_vzext_vf2; break; |
| 3428 | case 7: op = rv_op_vsext_vf2; break; |
| 3429 | } |
| 3430 | break; |
| 3431 | case 20: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3432 | switch ((inst >> 15) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3433 | case 1: op = rv_op_vmsbf_m; break; |
| 3434 | case 2: op = rv_op_vmsof_m; break; |
| 3435 | case 3: op = rv_op_vmsif_m; break; |
| 3436 | case 16: op = rv_op_viota_m; break; |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3437 | case 17: |
| 3438 | if (((inst >> 20) & 0b11111) == 0) { |
| 3439 | op = rv_op_vid_v; |
| 3440 | } |
| 3441 | break; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3442 | } |
| 3443 | break; |
| 3444 | case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break; |
| 3445 | case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break; |
| 3446 | case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break; |
| 3447 | case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break; |
| 3448 | case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break; |
| 3449 | case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break; |
| 3450 | case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break; |
| 3451 | case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break; |
| 3452 | case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break; |
| 3453 | case 32: op = rv_op_vdivu_vv; break; |
| 3454 | case 33: op = rv_op_vdiv_vv; break; |
| 3455 | case 34: op = rv_op_vremu_vv; break; |
| 3456 | case 35: op = rv_op_vrem_vv; break; |
| 3457 | case 36: op = rv_op_vmulhu_vv; break; |
| 3458 | case 37: op = rv_op_vmul_vv; break; |
| 3459 | case 38: op = rv_op_vmulhsu_vv; break; |
| 3460 | case 39: op = rv_op_vmulh_vv; break; |
| 3461 | case 41: op = rv_op_vmadd_vv; break; |
| 3462 | case 43: op = rv_op_vnmsub_vv; break; |
| 3463 | case 45: op = rv_op_vmacc_vv; break; |
| 3464 | case 47: op = rv_op_vnmsac_vv; break; |
| 3465 | case 48: op = rv_op_vwaddu_vv; break; |
| 3466 | case 49: op = rv_op_vwadd_vv; break; |
| 3467 | case 50: op = rv_op_vwsubu_vv; break; |
| 3468 | case 51: op = rv_op_vwsub_vv; break; |
| 3469 | case 52: op = rv_op_vwaddu_wv; break; |
| 3470 | case 53: op = rv_op_vwadd_wv; break; |
| 3471 | case 54: op = rv_op_vwsubu_wv; break; |
| 3472 | case 55: op = rv_op_vwsub_wv; break; |
| 3473 | case 56: op = rv_op_vwmulu_vv; break; |
| 3474 | case 58: op = rv_op_vwmulsu_vv; break; |
| 3475 | case 59: op = rv_op_vwmul_vv; break; |
| 3476 | case 60: op = rv_op_vwmaccu_vv; break; |
| 3477 | case 61: op = rv_op_vwmacc_vv; break; |
| 3478 | case 63: op = rv_op_vwmaccsu_vv; break; |
| 3479 | } |
| 3480 | break; |
| 3481 | case 3: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3482 | switch ((inst >> 26) & 0b111111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3483 | case 0: op = rv_op_vadd_vi; break; |
| 3484 | case 3: op = rv_op_vrsub_vi; break; |
| 3485 | case 9: op = rv_op_vand_vi; break; |
| 3486 | case 10: op = rv_op_vor_vi; break; |
| 3487 | case 11: op = rv_op_vxor_vi; break; |
| 3488 | case 12: op = rv_op_vrgather_vi; break; |
| 3489 | case 14: op = rv_op_vslideup_vi; break; |
| 3490 | case 15: op = rv_op_vslidedown_vi; break; |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3491 | case 16: |
| 3492 | if (((inst >> 25) & 1) == 0) { |
| 3493 | op = rv_op_vadc_vim; |
| 3494 | } |
| 3495 | break; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3496 | case 17: op = rv_op_vmadc_vim; break; |
| 3497 | case 23: |
| 3498 | if (((inst >> 20) & 0b111111) == 32) |
| 3499 | op = rv_op_vmv_v_i; |
| 3500 | else if (((inst >> 25) & 1) == 0) |
| 3501 | op = rv_op_vmerge_vim; |
| 3502 | break; |
| 3503 | case 24: op = rv_op_vmseq_vi; break; |
| 3504 | case 25: op = rv_op_vmsne_vi; break; |
| 3505 | case 28: op = rv_op_vmsleu_vi; break; |
| 3506 | case 29: op = rv_op_vmsle_vi; break; |
| 3507 | case 30: op = rv_op_vmsgtu_vi; break; |
| 3508 | case 31: op = rv_op_vmsgt_vi; break; |
| 3509 | case 32: op = rv_op_vsaddu_vi; break; |
| 3510 | case 33: op = rv_op_vsadd_vi; break; |
| 3511 | case 37: op = rv_op_vsll_vi; break; |
| 3512 | case 39: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3513 | switch ((inst >> 15) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3514 | case 0: op = rv_op_vmv1r_v; break; |
| 3515 | case 1: op = rv_op_vmv2r_v; break; |
| 3516 | case 3: op = rv_op_vmv4r_v; break; |
| 3517 | case 7: op = rv_op_vmv8r_v; break; |
| 3518 | } |
| 3519 | break; |
| 3520 | case 40: op = rv_op_vsrl_vi; break; |
| 3521 | case 41: op = rv_op_vsra_vi; break; |
| 3522 | case 42: op = rv_op_vssrl_vi; break; |
| 3523 | case 43: op = rv_op_vssra_vi; break; |
| 3524 | case 44: op = rv_op_vnsrl_wi; break; |
| 3525 | case 45: op = rv_op_vnsra_wi; break; |
| 3526 | case 46: op = rv_op_vnclipu_wi; break; |
| 3527 | case 47: op = rv_op_vnclip_wi; break; |
| 3528 | } |
| 3529 | break; |
| 3530 | case 4: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3531 | switch ((inst >> 26) & 0b111111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3532 | case 0: op = rv_op_vadd_vx; break; |
| 3533 | case 2: op = rv_op_vsub_vx; break; |
| 3534 | case 3: op = rv_op_vrsub_vx; break; |
| 3535 | case 4: op = rv_op_vminu_vx; break; |
| 3536 | case 5: op = rv_op_vmin_vx; break; |
| 3537 | case 6: op = rv_op_vmaxu_vx; break; |
| 3538 | case 7: op = rv_op_vmax_vx; break; |
| 3539 | case 9: op = rv_op_vand_vx; break; |
| 3540 | case 10: op = rv_op_vor_vx; break; |
| 3541 | case 11: op = rv_op_vxor_vx; break; |
| 3542 | case 12: op = rv_op_vrgather_vx; break; |
| 3543 | case 14: op = rv_op_vslideup_vx; break; |
| 3544 | case 15: op = rv_op_vslidedown_vx; break; |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3545 | case 16: |
| 3546 | if (((inst >> 25) & 1) == 0) { |
| 3547 | op = rv_op_vadc_vxm; |
| 3548 | } |
| 3549 | break; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3550 | case 17: op = rv_op_vmadc_vxm; break; |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3551 | case 18: |
| 3552 | if (((inst >> 25) & 1) == 0) { |
| 3553 | op = rv_op_vsbc_vxm; |
| 3554 | } |
| 3555 | break; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3556 | case 19: op = rv_op_vmsbc_vxm; break; |
| 3557 | case 23: |
| 3558 | if (((inst >> 20) & 0b111111) == 32) |
| 3559 | op = rv_op_vmv_v_x; |
| 3560 | else if (((inst >> 25) & 1) == 0) |
| 3561 | op = rv_op_vmerge_vxm; |
| 3562 | break; |
| 3563 | case 24: op = rv_op_vmseq_vx; break; |
| 3564 | case 25: op = rv_op_vmsne_vx; break; |
| 3565 | case 26: op = rv_op_vmsltu_vx; break; |
| 3566 | case 27: op = rv_op_vmslt_vx; break; |
| 3567 | case 28: op = rv_op_vmsleu_vx; break; |
| 3568 | case 29: op = rv_op_vmsle_vx; break; |
| 3569 | case 30: op = rv_op_vmsgtu_vx; break; |
| 3570 | case 31: op = rv_op_vmsgt_vx; break; |
| 3571 | case 32: op = rv_op_vsaddu_vx; break; |
| 3572 | case 33: op = rv_op_vsadd_vx; break; |
| 3573 | case 34: op = rv_op_vssubu_vx; break; |
| 3574 | case 35: op = rv_op_vssub_vx; break; |
| 3575 | case 37: op = rv_op_vsll_vx; break; |
| 3576 | case 39: op = rv_op_vsmul_vx; break; |
| 3577 | case 40: op = rv_op_vsrl_vx; break; |
| 3578 | case 41: op = rv_op_vsra_vx; break; |
| 3579 | case 42: op = rv_op_vssrl_vx; break; |
| 3580 | case 43: op = rv_op_vssra_vx; break; |
| 3581 | case 44: op = rv_op_vnsrl_wx; break; |
| 3582 | case 45: op = rv_op_vnsra_wx; break; |
| 3583 | case 46: op = rv_op_vnclipu_wx; break; |
| 3584 | case 47: op = rv_op_vnclip_wx; break; |
| 3585 | } |
| 3586 | break; |
| 3587 | case 5: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3588 | switch ((inst >> 26) & 0b111111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3589 | case 0: op = rv_op_vfadd_vf; break; |
| 3590 | case 2: op = rv_op_vfsub_vf; break; |
| 3591 | case 4: op = rv_op_vfmin_vf; break; |
| 3592 | case 6: op = rv_op_vfmax_vf; break; |
| 3593 | case 8: op = rv_op_vfsgnj_vf; break; |
| 3594 | case 9: op = rv_op_vfsgnjn_vf; break; |
| 3595 | case 10: op = rv_op_vfsgnjx_vf; break; |
| 3596 | case 14: op = rv_op_vfslide1up_vf; break; |
| 3597 | case 15: op = rv_op_vfslide1down_vf; break; |
| 3598 | case 16: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3599 | switch ((inst >> 20) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3600 | case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break; |
| 3601 | } |
| 3602 | break; |
| 3603 | case 23: |
| 3604 | if (((inst >> 25) & 1) == 0) |
| 3605 | op = rv_op_vfmerge_vfm; |
| 3606 | else if (((inst >> 20) & 0b111111) == 32) |
| 3607 | op = rv_op_vfmv_v_f; |
| 3608 | break; |
| 3609 | case 24: op = rv_op_vmfeq_vf; break; |
| 3610 | case 25: op = rv_op_vmfle_vf; break; |
| 3611 | case 27: op = rv_op_vmflt_vf; break; |
| 3612 | case 28: op = rv_op_vmfne_vf; break; |
| 3613 | case 29: op = rv_op_vmfgt_vf; break; |
| 3614 | case 31: op = rv_op_vmfge_vf; break; |
| 3615 | case 32: op = rv_op_vfdiv_vf; break; |
| 3616 | case 33: op = rv_op_vfrdiv_vf; break; |
| 3617 | case 36: op = rv_op_vfmul_vf; break; |
| 3618 | case 39: op = rv_op_vfrsub_vf; break; |
| 3619 | case 40: op = rv_op_vfmadd_vf; break; |
| 3620 | case 41: op = rv_op_vfnmadd_vf; break; |
| 3621 | case 42: op = rv_op_vfmsub_vf; break; |
| 3622 | case 43: op = rv_op_vfnmsub_vf; break; |
| 3623 | case 44: op = rv_op_vfmacc_vf; break; |
| 3624 | case 45: op = rv_op_vfnmacc_vf; break; |
| 3625 | case 46: op = rv_op_vfmsac_vf; break; |
| 3626 | case 47: op = rv_op_vfnmsac_vf; break; |
| 3627 | case 48: op = rv_op_vfwadd_vf; break; |
| 3628 | case 50: op = rv_op_vfwsub_vf; break; |
| 3629 | case 52: op = rv_op_vfwadd_wf; break; |
| 3630 | case 54: op = rv_op_vfwsub_wf; break; |
| 3631 | case 56: op = rv_op_vfwmul_vf; break; |
| 3632 | case 60: op = rv_op_vfwmacc_vf; break; |
| 3633 | case 61: op = rv_op_vfwnmacc_vf; break; |
| 3634 | case 62: op = rv_op_vfwmsac_vf; break; |
| 3635 | case 63: op = rv_op_vfwnmsac_vf; break; |
| 3636 | } |
| 3637 | break; |
| 3638 | case 6: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3639 | switch ((inst >> 26) & 0b111111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3640 | case 8: op = rv_op_vaaddu_vx; break; |
| 3641 | case 9: op = rv_op_vaadd_vx; break; |
| 3642 | case 10: op = rv_op_vasubu_vx; break; |
| 3643 | case 11: op = rv_op_vasub_vx; break; |
| 3644 | case 14: op = rv_op_vslide1up_vx; break; |
| 3645 | case 15: op = rv_op_vslide1down_vx; break; |
| 3646 | case 16: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3647 | switch ((inst >> 20) & 0b11111) { |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 3648 | case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break; |
| 3649 | } |
| 3650 | break; |
| 3651 | case 32: op = rv_op_vdivu_vx; break; |
| 3652 | case 33: op = rv_op_vdiv_vx; break; |
| 3653 | case 34: op = rv_op_vremu_vx; break; |
| 3654 | case 35: op = rv_op_vrem_vx; break; |
| 3655 | case 36: op = rv_op_vmulhu_vx; break; |
| 3656 | case 37: op = rv_op_vmul_vx; break; |
| 3657 | case 38: op = rv_op_vmulhsu_vx; break; |
| 3658 | case 39: op = rv_op_vmulh_vx; break; |
| 3659 | case 41: op = rv_op_vmadd_vx; break; |
| 3660 | case 43: op = rv_op_vnmsub_vx; break; |
| 3661 | case 45: op = rv_op_vmacc_vx; break; |
| 3662 | case 47: op = rv_op_vnmsac_vx; break; |
| 3663 | case 48: op = rv_op_vwaddu_vx; break; |
| 3664 | case 49: op = rv_op_vwadd_vx; break; |
| 3665 | case 50: op = rv_op_vwsubu_vx; break; |
| 3666 | case 51: op = rv_op_vwsub_vx; break; |
| 3667 | case 52: op = rv_op_vwaddu_wx; break; |
| 3668 | case 53: op = rv_op_vwadd_wx; break; |
| 3669 | case 54: op = rv_op_vwsubu_wx; break; |
| 3670 | case 55: op = rv_op_vwsub_wx; break; |
| 3671 | case 56: op = rv_op_vwmulu_vx; break; |
| 3672 | case 58: op = rv_op_vwmulsu_vx; break; |
| 3673 | case 59: op = rv_op_vwmul_vx; break; |
| 3674 | case 60: op = rv_op_vwmaccu_vx; break; |
| 3675 | case 61: op = rv_op_vwmacc_vx; break; |
| 3676 | case 62: op = rv_op_vwmaccus_vx; break; |
| 3677 | case 63: op = rv_op_vwmaccsu_vx; break; |
| 3678 | } |
| 3679 | break; |
| 3680 | case 7: |
| 3681 | if (((inst >> 31) & 1) == 0) { |
| 3682 | op = rv_op_vsetvli; |
| 3683 | } else if ((inst >> 30) & 1) { |
| 3684 | op = rv_op_vsetivli; |
| 3685 | } else if (((inst >> 25) & 0b11111) == 0) { |
| 3686 | op = rv_op_vsetvl; |
| 3687 | } |
| 3688 | break; |
| 3689 | } |
| 3690 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3691 | case 22: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3692 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3693 | case 0: op = rv_op_addid; break; |
| 3694 | case 1: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3695 | switch ((inst >> 26) & 0b111111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3696 | case 0: op = rv_op_sllid; break; |
| 3697 | } |
| 3698 | break; |
| 3699 | case 5: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3700 | switch ((inst >> 26) & 0b111111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3701 | case 0: op = rv_op_srlid; break; |
| 3702 | case 16: op = rv_op_sraid; break; |
| 3703 | } |
| 3704 | break; |
| 3705 | } |
| 3706 | break; |
| 3707 | case 24: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3708 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3709 | case 0: op = rv_op_beq; break; |
| 3710 | case 1: op = rv_op_bne; break; |
| 3711 | case 4: op = rv_op_blt; break; |
| 3712 | case 5: op = rv_op_bge; break; |
| 3713 | case 6: op = rv_op_bltu; break; |
| 3714 | case 7: op = rv_op_bgeu; break; |
| 3715 | } |
| 3716 | break; |
| 3717 | case 25: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3718 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3719 | case 0: op = rv_op_jalr; break; |
| 3720 | } |
| 3721 | break; |
| 3722 | case 27: op = rv_op_jal; break; |
| 3723 | case 28: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3724 | switch ((inst >> 12) & 0b111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3725 | case 0: |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3726 | switch (((inst >> 20) & 0b111111100000) | |
| 3727 | ((inst >> 7) & 0b000000011111)) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3728 | case 0: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3729 | switch ((inst >> 15) & 0b1111111111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3730 | case 0: op = rv_op_ecall; break; |
| 3731 | case 32: op = rv_op_ebreak; break; |
| 3732 | case 64: op = rv_op_uret; break; |
| 3733 | } |
| 3734 | break; |
| 3735 | case 256: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3736 | switch ((inst >> 20) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3737 | case 2: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3738 | switch ((inst >> 15) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3739 | case 0: op = rv_op_sret; break; |
| 3740 | } |
| 3741 | break; |
| 3742 | case 4: op = rv_op_sfence_vm; break; |
| 3743 | case 5: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3744 | switch ((inst >> 15) & 0b11111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3745 | case 0: op = rv_op_wfi; break; |
| 3746 | } |
| 3747 | break; |
| 3748 | } |
| 3749 | break; |
| 3750 | case 288: op = rv_op_sfence_vma; break; |
| 3751 | case 512: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3752 | switch ((inst >> 15) & 0b1111111111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3753 | case 64: op = rv_op_hret; break; |
| 3754 | } |
| 3755 | break; |
| 3756 | case 768: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3757 | switch ((inst >> 15) & 0b1111111111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3758 | case 64: op = rv_op_mret; break; |
| 3759 | } |
| 3760 | break; |
| 3761 | case 1952: |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 3762 | switch ((inst >> 15) & 0b1111111111) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3763 | case 576: op = rv_op_dret; break; |
| 3764 | } |
| 3765 | break; |
| 3766 | } |
| 3767 | break; |
| 3768 | case 1: op = rv_op_csrrw; break; |
| 3769 | case 2: op = rv_op_csrrs; break; |
| 3770 | case 3: op = rv_op_csrrc; break; |
| 3771 | case 5: op = rv_op_csrrwi; break; |
| 3772 | case 6: op = rv_op_csrrsi; break; |
| 3773 | case 7: op = rv_op_csrrci; break; |
| 3774 | } |
| 3775 | break; |
| 3776 | case 30: |
Weiwei Li | 98624d1 | 2023-05-23 17:35:38 +0800 | [diff] [blame] | 3777 | switch (((inst >> 22) & 0b1111111000) | |
| 3778 | ((inst >> 12) & 0b0000000111)) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3779 | case 0: op = rv_op_addd; break; |
| 3780 | case 1: op = rv_op_slld; break; |
| 3781 | case 5: op = rv_op_srld; break; |
| 3782 | case 8: op = rv_op_muld; break; |
| 3783 | case 12: op = rv_op_divd; break; |
| 3784 | case 13: op = rv_op_divud; break; |
| 3785 | case 14: op = rv_op_remd; break; |
| 3786 | case 15: op = rv_op_remud; break; |
| 3787 | case 256: op = rv_op_subd; break; |
| 3788 | case 261: op = rv_op_srad; break; |
| 3789 | } |
| 3790 | break; |
| 3791 | } |
| 3792 | break; |
| 3793 | } |
| 3794 | dec->op = op; |
| 3795 | } |
| 3796 | |
| 3797 | /* operand extractors */ |
| 3798 | |
| 3799 | static uint32_t operand_rd(rv_inst inst) |
| 3800 | { |
| 3801 | return (inst << 52) >> 59; |
| 3802 | } |
| 3803 | |
| 3804 | static uint32_t operand_rs1(rv_inst inst) |
| 3805 | { |
| 3806 | return (inst << 44) >> 59; |
| 3807 | } |
| 3808 | |
| 3809 | static uint32_t operand_rs2(rv_inst inst) |
| 3810 | { |
| 3811 | return (inst << 39) >> 59; |
| 3812 | } |
| 3813 | |
| 3814 | static uint32_t operand_rs3(rv_inst inst) |
| 3815 | { |
| 3816 | return (inst << 32) >> 59; |
| 3817 | } |
| 3818 | |
| 3819 | static uint32_t operand_aq(rv_inst inst) |
| 3820 | { |
| 3821 | return (inst << 37) >> 63; |
| 3822 | } |
| 3823 | |
| 3824 | static uint32_t operand_rl(rv_inst inst) |
| 3825 | { |
| 3826 | return (inst << 38) >> 63; |
| 3827 | } |
| 3828 | |
| 3829 | static uint32_t operand_pred(rv_inst inst) |
| 3830 | { |
| 3831 | return (inst << 36) >> 60; |
| 3832 | } |
| 3833 | |
| 3834 | static uint32_t operand_succ(rv_inst inst) |
| 3835 | { |
| 3836 | return (inst << 40) >> 60; |
| 3837 | } |
| 3838 | |
| 3839 | static uint32_t operand_rm(rv_inst inst) |
| 3840 | { |
| 3841 | return (inst << 49) >> 61; |
| 3842 | } |
| 3843 | |
| 3844 | static uint32_t operand_shamt5(rv_inst inst) |
| 3845 | { |
| 3846 | return (inst << 39) >> 59; |
| 3847 | } |
| 3848 | |
| 3849 | static uint32_t operand_shamt6(rv_inst inst) |
| 3850 | { |
| 3851 | return (inst << 38) >> 58; |
| 3852 | } |
| 3853 | |
| 3854 | static uint32_t operand_shamt7(rv_inst inst) |
| 3855 | { |
| 3856 | return (inst << 37) >> 57; |
| 3857 | } |
| 3858 | |
| 3859 | static uint32_t operand_crdq(rv_inst inst) |
| 3860 | { |
| 3861 | return (inst << 59) >> 61; |
| 3862 | } |
| 3863 | |
| 3864 | static uint32_t operand_crs1q(rv_inst inst) |
| 3865 | { |
| 3866 | return (inst << 54) >> 61; |
| 3867 | } |
| 3868 | |
| 3869 | static uint32_t operand_crs1rdq(rv_inst inst) |
| 3870 | { |
| 3871 | return (inst << 54) >> 61; |
| 3872 | } |
| 3873 | |
| 3874 | static uint32_t operand_crs2q(rv_inst inst) |
| 3875 | { |
| 3876 | return (inst << 59) >> 61; |
| 3877 | } |
| 3878 | |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 3879 | static uint32_t calculate_xreg(uint32_t sreg) |
| 3880 | { |
| 3881 | return sreg < 2 ? sreg + 8 : sreg + 16; |
| 3882 | } |
| 3883 | |
| 3884 | static uint32_t operand_sreg1(rv_inst inst) |
| 3885 | { |
| 3886 | return calculate_xreg((inst << 54) >> 61); |
| 3887 | } |
| 3888 | |
| 3889 | static uint32_t operand_sreg2(rv_inst inst) |
| 3890 | { |
| 3891 | return calculate_xreg((inst << 59) >> 61); |
| 3892 | } |
| 3893 | |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3894 | static uint32_t operand_crd(rv_inst inst) |
| 3895 | { |
| 3896 | return (inst << 52) >> 59; |
| 3897 | } |
| 3898 | |
| 3899 | static uint32_t operand_crs1(rv_inst inst) |
| 3900 | { |
| 3901 | return (inst << 52) >> 59; |
| 3902 | } |
| 3903 | |
| 3904 | static uint32_t operand_crs1rd(rv_inst inst) |
| 3905 | { |
| 3906 | return (inst << 52) >> 59; |
| 3907 | } |
| 3908 | |
| 3909 | static uint32_t operand_crs2(rv_inst inst) |
| 3910 | { |
| 3911 | return (inst << 57) >> 59; |
| 3912 | } |
| 3913 | |
| 3914 | static uint32_t operand_cimmsh5(rv_inst inst) |
| 3915 | { |
| 3916 | return (inst << 57) >> 59; |
| 3917 | } |
| 3918 | |
| 3919 | static uint32_t operand_csr12(rv_inst inst) |
| 3920 | { |
| 3921 | return (inst << 32) >> 52; |
| 3922 | } |
| 3923 | |
| 3924 | static int32_t operand_imm12(rv_inst inst) |
| 3925 | { |
| 3926 | return ((int64_t)inst << 32) >> 52; |
| 3927 | } |
| 3928 | |
| 3929 | static int32_t operand_imm20(rv_inst inst) |
| 3930 | { |
| 3931 | return (((int64_t)inst << 32) >> 44) << 12; |
| 3932 | } |
| 3933 | |
| 3934 | static int32_t operand_jimm20(rv_inst inst) |
| 3935 | { |
| 3936 | return (((int64_t)inst << 32) >> 63) << 20 | |
| 3937 | ((inst << 33) >> 54) << 1 | |
| 3938 | ((inst << 43) >> 63) << 11 | |
| 3939 | ((inst << 44) >> 56) << 12; |
| 3940 | } |
| 3941 | |
| 3942 | static int32_t operand_simm12(rv_inst inst) |
| 3943 | { |
| 3944 | return (((int64_t)inst << 32) >> 57) << 5 | |
| 3945 | (inst << 52) >> 59; |
| 3946 | } |
| 3947 | |
| 3948 | static int32_t operand_sbimm12(rv_inst inst) |
| 3949 | { |
| 3950 | return (((int64_t)inst << 32) >> 63) << 12 | |
| 3951 | ((inst << 33) >> 58) << 5 | |
| 3952 | ((inst << 52) >> 60) << 1 | |
| 3953 | ((inst << 56) >> 63) << 11; |
| 3954 | } |
| 3955 | |
Frédéric Pétrot | 3363277 | 2022-07-10 13:04:51 +0200 | [diff] [blame] | 3956 | static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa) |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3957 | { |
Frédéric Pétrot | 3363277 | 2022-07-10 13:04:51 +0200 | [diff] [blame] | 3958 | int imm = ((inst << 51) >> 63) << 5 | |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3959 | (inst << 57) >> 59; |
Frédéric Pétrot | 3363277 | 2022-07-10 13:04:51 +0200 | [diff] [blame] | 3960 | if (isa == rv128) { |
| 3961 | imm = imm ? imm : 64; |
| 3962 | } |
| 3963 | return imm; |
| 3964 | } |
| 3965 | |
| 3966 | static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa) |
| 3967 | { |
| 3968 | int imm = ((inst << 51) >> 63) << 5 | |
| 3969 | (inst << 57) >> 59; |
| 3970 | if (isa == rv128) { |
| 3971 | imm = imm | (imm & 32) << 1; |
| 3972 | imm = imm ? imm : 64; |
| 3973 | } |
| 3974 | return imm; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 3975 | } |
| 3976 | |
| 3977 | static int32_t operand_cimmi(rv_inst inst) |
| 3978 | { |
| 3979 | return (((int64_t)inst << 51) >> 63) << 5 | |
| 3980 | (inst << 57) >> 59; |
| 3981 | } |
| 3982 | |
| 3983 | static int32_t operand_cimmui(rv_inst inst) |
| 3984 | { |
| 3985 | return (((int64_t)inst << 51) >> 63) << 17 | |
| 3986 | ((inst << 57) >> 59) << 12; |
| 3987 | } |
| 3988 | |
| 3989 | static uint32_t operand_cimmlwsp(rv_inst inst) |
| 3990 | { |
| 3991 | return ((inst << 51) >> 63) << 5 | |
| 3992 | ((inst << 57) >> 61) << 2 | |
| 3993 | ((inst << 60) >> 62) << 6; |
| 3994 | } |
| 3995 | |
| 3996 | static uint32_t operand_cimmldsp(rv_inst inst) |
| 3997 | { |
| 3998 | return ((inst << 51) >> 63) << 5 | |
| 3999 | ((inst << 57) >> 62) << 3 | |
| 4000 | ((inst << 59) >> 61) << 6; |
| 4001 | } |
| 4002 | |
| 4003 | static uint32_t operand_cimmlqsp(rv_inst inst) |
| 4004 | { |
| 4005 | return ((inst << 51) >> 63) << 5 | |
| 4006 | ((inst << 57) >> 63) << 4 | |
| 4007 | ((inst << 58) >> 60) << 6; |
| 4008 | } |
| 4009 | |
| 4010 | static int32_t operand_cimm16sp(rv_inst inst) |
| 4011 | { |
| 4012 | return (((int64_t)inst << 51) >> 63) << 9 | |
| 4013 | ((inst << 57) >> 63) << 4 | |
| 4014 | ((inst << 58) >> 63) << 6 | |
| 4015 | ((inst << 59) >> 62) << 7 | |
| 4016 | ((inst << 61) >> 63) << 5; |
| 4017 | } |
| 4018 | |
| 4019 | static int32_t operand_cimmj(rv_inst inst) |
| 4020 | { |
| 4021 | return (((int64_t)inst << 51) >> 63) << 11 | |
| 4022 | ((inst << 52) >> 63) << 4 | |
| 4023 | ((inst << 53) >> 62) << 8 | |
| 4024 | ((inst << 55) >> 63) << 10 | |
| 4025 | ((inst << 56) >> 63) << 6 | |
| 4026 | ((inst << 57) >> 63) << 7 | |
| 4027 | ((inst << 58) >> 61) << 1 | |
| 4028 | ((inst << 61) >> 63) << 5; |
| 4029 | } |
| 4030 | |
| 4031 | static int32_t operand_cimmb(rv_inst inst) |
| 4032 | { |
| 4033 | return (((int64_t)inst << 51) >> 63) << 8 | |
| 4034 | ((inst << 52) >> 62) << 3 | |
| 4035 | ((inst << 57) >> 62) << 6 | |
| 4036 | ((inst << 59) >> 62) << 1 | |
| 4037 | ((inst << 61) >> 63) << 5; |
| 4038 | } |
| 4039 | |
| 4040 | static uint32_t operand_cimmswsp(rv_inst inst) |
| 4041 | { |
| 4042 | return ((inst << 51) >> 60) << 2 | |
| 4043 | ((inst << 55) >> 62) << 6; |
| 4044 | } |
| 4045 | |
| 4046 | static uint32_t operand_cimmsdsp(rv_inst inst) |
| 4047 | { |
| 4048 | return ((inst << 51) >> 61) << 3 | |
| 4049 | ((inst << 54) >> 61) << 6; |
| 4050 | } |
| 4051 | |
| 4052 | static uint32_t operand_cimmsqsp(rv_inst inst) |
| 4053 | { |
| 4054 | return ((inst << 51) >> 62) << 4 | |
| 4055 | ((inst << 53) >> 60) << 6; |
| 4056 | } |
| 4057 | |
| 4058 | static uint32_t operand_cimm4spn(rv_inst inst) |
| 4059 | { |
| 4060 | return ((inst << 51) >> 62) << 4 | |
| 4061 | ((inst << 53) >> 60) << 6 | |
| 4062 | ((inst << 57) >> 63) << 2 | |
| 4063 | ((inst << 58) >> 63) << 3; |
| 4064 | } |
| 4065 | |
| 4066 | static uint32_t operand_cimmw(rv_inst inst) |
| 4067 | { |
| 4068 | return ((inst << 51) >> 61) << 3 | |
| 4069 | ((inst << 57) >> 63) << 2 | |
| 4070 | ((inst << 58) >> 63) << 6; |
| 4071 | } |
| 4072 | |
| 4073 | static uint32_t operand_cimmd(rv_inst inst) |
| 4074 | { |
| 4075 | return ((inst << 51) >> 61) << 3 | |
| 4076 | ((inst << 57) >> 62) << 6; |
| 4077 | } |
| 4078 | |
| 4079 | static uint32_t operand_cimmq(rv_inst inst) |
| 4080 | { |
| 4081 | return ((inst << 51) >> 62) << 4 | |
| 4082 | ((inst << 53) >> 63) << 8 | |
| 4083 | ((inst << 57) >> 62) << 6; |
| 4084 | } |
| 4085 | |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 4086 | static uint32_t operand_vimm(rv_inst inst) |
| 4087 | { |
| 4088 | return (int64_t)(inst << 44) >> 59; |
| 4089 | } |
| 4090 | |
| 4091 | static uint32_t operand_vzimm11(rv_inst inst) |
| 4092 | { |
| 4093 | return (inst << 33) >> 53; |
| 4094 | } |
| 4095 | |
| 4096 | static uint32_t operand_vzimm10(rv_inst inst) |
| 4097 | { |
| 4098 | return (inst << 34) >> 54; |
| 4099 | } |
| 4100 | |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 4101 | static uint32_t operand_bs(rv_inst inst) |
| 4102 | { |
| 4103 | return (inst << 32) >> 62; |
| 4104 | } |
| 4105 | |
| 4106 | static uint32_t operand_rnum(rv_inst inst) |
| 4107 | { |
| 4108 | return (inst << 40) >> 60; |
| 4109 | } |
| 4110 | |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 4111 | static uint32_t operand_vm(rv_inst inst) |
| 4112 | { |
| 4113 | return (inst << 38) >> 63; |
| 4114 | } |
| 4115 | |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 4116 | static uint32_t operand_uimm_c_lb(rv_inst inst) |
| 4117 | { |
| 4118 | return (((inst << 58) >> 63) << 1) | |
| 4119 | ((inst << 57) >> 63); |
| 4120 | } |
| 4121 | |
| 4122 | static uint32_t operand_uimm_c_lh(rv_inst inst) |
| 4123 | { |
| 4124 | return (((inst << 58) >> 63) << 1); |
| 4125 | } |
| 4126 | |
| 4127 | static uint32_t operand_zcmp_spimm(rv_inst inst) |
| 4128 | { |
| 4129 | return ((inst << 60) >> 62) << 4; |
| 4130 | } |
| 4131 | |
| 4132 | static uint32_t operand_zcmp_rlist(rv_inst inst) |
| 4133 | { |
| 4134 | return ((inst << 56) >> 60); |
| 4135 | } |
| 4136 | |
| 4137 | static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm) |
| 4138 | { |
| 4139 | int xlen_bytes_log2 = isa == rv64 ? 3 : 2; |
| 4140 | int regs = rlist == 15 ? 13 : rlist - 3; |
| 4141 | uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16); |
| 4142 | return stack_adj_base + spimm; |
| 4143 | } |
| 4144 | |
| 4145 | static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa) |
| 4146 | { |
| 4147 | return calculate_stack_adj(isa, operand_zcmp_rlist(inst), |
| 4148 | operand_zcmp_spimm(inst)); |
| 4149 | } |
| 4150 | |
| 4151 | static uint32_t operand_tbl_index(rv_inst inst) |
| 4152 | { |
| 4153 | return ((inst << 54) >> 56); |
| 4154 | } |
| 4155 | |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4156 | /* decode operands */ |
| 4157 | |
Frédéric Pétrot | 3363277 | 2022-07-10 13:04:51 +0200 | [diff] [blame] | 4158 | static void decode_inst_operands(rv_decode *dec, rv_isa isa) |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4159 | { |
| 4160 | rv_inst inst = dec->inst; |
| 4161 | dec->codec = opcode_data[dec->op].codec; |
| 4162 | switch (dec->codec) { |
| 4163 | case rv_codec_none: |
| 4164 | dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; |
| 4165 | dec->imm = 0; |
| 4166 | break; |
| 4167 | case rv_codec_u: |
| 4168 | dec->rd = operand_rd(inst); |
| 4169 | dec->rs1 = dec->rs2 = rv_ireg_zero; |
| 4170 | dec->imm = operand_imm20(inst); |
| 4171 | break; |
| 4172 | case rv_codec_uj: |
| 4173 | dec->rd = operand_rd(inst); |
| 4174 | dec->rs1 = dec->rs2 = rv_ireg_zero; |
| 4175 | dec->imm = operand_jimm20(inst); |
| 4176 | break; |
| 4177 | case rv_codec_i: |
| 4178 | dec->rd = operand_rd(inst); |
| 4179 | dec->rs1 = operand_rs1(inst); |
| 4180 | dec->rs2 = rv_ireg_zero; |
| 4181 | dec->imm = operand_imm12(inst); |
| 4182 | break; |
| 4183 | case rv_codec_i_sh5: |
| 4184 | dec->rd = operand_rd(inst); |
| 4185 | dec->rs1 = operand_rs1(inst); |
| 4186 | dec->rs2 = rv_ireg_zero; |
| 4187 | dec->imm = operand_shamt5(inst); |
| 4188 | break; |
| 4189 | case rv_codec_i_sh6: |
| 4190 | dec->rd = operand_rd(inst); |
| 4191 | dec->rs1 = operand_rs1(inst); |
| 4192 | dec->rs2 = rv_ireg_zero; |
| 4193 | dec->imm = operand_shamt6(inst); |
| 4194 | break; |
| 4195 | case rv_codec_i_sh7: |
| 4196 | dec->rd = operand_rd(inst); |
| 4197 | dec->rs1 = operand_rs1(inst); |
| 4198 | dec->rs2 = rv_ireg_zero; |
| 4199 | dec->imm = operand_shamt7(inst); |
| 4200 | break; |
| 4201 | case rv_codec_i_csr: |
| 4202 | dec->rd = operand_rd(inst); |
| 4203 | dec->rs1 = operand_rs1(inst); |
| 4204 | dec->rs2 = rv_ireg_zero; |
| 4205 | dec->imm = operand_csr12(inst); |
| 4206 | break; |
| 4207 | case rv_codec_s: |
| 4208 | dec->rd = rv_ireg_zero; |
| 4209 | dec->rs1 = operand_rs1(inst); |
| 4210 | dec->rs2 = operand_rs2(inst); |
| 4211 | dec->imm = operand_simm12(inst); |
| 4212 | break; |
| 4213 | case rv_codec_sb: |
| 4214 | dec->rd = rv_ireg_zero; |
| 4215 | dec->rs1 = operand_rs1(inst); |
| 4216 | dec->rs2 = operand_rs2(inst); |
| 4217 | dec->imm = operand_sbimm12(inst); |
| 4218 | break; |
| 4219 | case rv_codec_r: |
| 4220 | dec->rd = operand_rd(inst); |
| 4221 | dec->rs1 = operand_rs1(inst); |
| 4222 | dec->rs2 = operand_rs2(inst); |
| 4223 | dec->imm = 0; |
| 4224 | break; |
| 4225 | case rv_codec_r_m: |
| 4226 | dec->rd = operand_rd(inst); |
| 4227 | dec->rs1 = operand_rs1(inst); |
| 4228 | dec->rs2 = operand_rs2(inst); |
| 4229 | dec->imm = 0; |
| 4230 | dec->rm = operand_rm(inst); |
| 4231 | break; |
| 4232 | case rv_codec_r4_m: |
| 4233 | dec->rd = operand_rd(inst); |
| 4234 | dec->rs1 = operand_rs1(inst); |
| 4235 | dec->rs2 = operand_rs2(inst); |
| 4236 | dec->rs3 = operand_rs3(inst); |
| 4237 | dec->imm = 0; |
| 4238 | dec->rm = operand_rm(inst); |
| 4239 | break; |
| 4240 | case rv_codec_r_a: |
| 4241 | dec->rd = operand_rd(inst); |
| 4242 | dec->rs1 = operand_rs1(inst); |
| 4243 | dec->rs2 = operand_rs2(inst); |
| 4244 | dec->imm = 0; |
| 4245 | dec->aq = operand_aq(inst); |
| 4246 | dec->rl = operand_rl(inst); |
| 4247 | break; |
| 4248 | case rv_codec_r_l: |
| 4249 | dec->rd = operand_rd(inst); |
| 4250 | dec->rs1 = operand_rs1(inst); |
| 4251 | dec->rs2 = rv_ireg_zero; |
| 4252 | dec->imm = 0; |
| 4253 | dec->aq = operand_aq(inst); |
| 4254 | dec->rl = operand_rl(inst); |
| 4255 | break; |
| 4256 | case rv_codec_r_f: |
| 4257 | dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; |
| 4258 | dec->pred = operand_pred(inst); |
| 4259 | dec->succ = operand_succ(inst); |
| 4260 | dec->imm = 0; |
| 4261 | break; |
| 4262 | case rv_codec_cb: |
| 4263 | dec->rd = rv_ireg_zero; |
| 4264 | dec->rs1 = operand_crs1q(inst) + 8; |
| 4265 | dec->rs2 = rv_ireg_zero; |
| 4266 | dec->imm = operand_cimmb(inst); |
| 4267 | break; |
| 4268 | case rv_codec_cb_imm: |
| 4269 | dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; |
| 4270 | dec->rs2 = rv_ireg_zero; |
| 4271 | dec->imm = operand_cimmi(inst); |
| 4272 | break; |
| 4273 | case rv_codec_cb_sh5: |
| 4274 | dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; |
| 4275 | dec->rs2 = rv_ireg_zero; |
| 4276 | dec->imm = operand_cimmsh5(inst); |
| 4277 | break; |
| 4278 | case rv_codec_cb_sh6: |
| 4279 | dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; |
| 4280 | dec->rs2 = rv_ireg_zero; |
Frédéric Pétrot | 3363277 | 2022-07-10 13:04:51 +0200 | [diff] [blame] | 4281 | dec->imm = operand_cimmshr6(inst, isa); |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4282 | break; |
| 4283 | case rv_codec_ci: |
| 4284 | dec->rd = dec->rs1 = operand_crs1rd(inst); |
| 4285 | dec->rs2 = rv_ireg_zero; |
| 4286 | dec->imm = operand_cimmi(inst); |
| 4287 | break; |
| 4288 | case rv_codec_ci_sh5: |
| 4289 | dec->rd = dec->rs1 = operand_crs1rd(inst); |
| 4290 | dec->rs2 = rv_ireg_zero; |
| 4291 | dec->imm = operand_cimmsh5(inst); |
| 4292 | break; |
| 4293 | case rv_codec_ci_sh6: |
| 4294 | dec->rd = dec->rs1 = operand_crs1rd(inst); |
| 4295 | dec->rs2 = rv_ireg_zero; |
Frédéric Pétrot | 3363277 | 2022-07-10 13:04:51 +0200 | [diff] [blame] | 4296 | dec->imm = operand_cimmshl6(inst, isa); |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4297 | break; |
| 4298 | case rv_codec_ci_16sp: |
| 4299 | dec->rd = rv_ireg_sp; |
| 4300 | dec->rs1 = rv_ireg_sp; |
| 4301 | dec->rs2 = rv_ireg_zero; |
| 4302 | dec->imm = operand_cimm16sp(inst); |
| 4303 | break; |
| 4304 | case rv_codec_ci_lwsp: |
| 4305 | dec->rd = operand_crd(inst); |
| 4306 | dec->rs1 = rv_ireg_sp; |
| 4307 | dec->rs2 = rv_ireg_zero; |
| 4308 | dec->imm = operand_cimmlwsp(inst); |
| 4309 | break; |
| 4310 | case rv_codec_ci_ldsp: |
| 4311 | dec->rd = operand_crd(inst); |
| 4312 | dec->rs1 = rv_ireg_sp; |
| 4313 | dec->rs2 = rv_ireg_zero; |
| 4314 | dec->imm = operand_cimmldsp(inst); |
| 4315 | break; |
| 4316 | case rv_codec_ci_lqsp: |
| 4317 | dec->rd = operand_crd(inst); |
| 4318 | dec->rs1 = rv_ireg_sp; |
| 4319 | dec->rs2 = rv_ireg_zero; |
| 4320 | dec->imm = operand_cimmlqsp(inst); |
| 4321 | break; |
| 4322 | case rv_codec_ci_li: |
| 4323 | dec->rd = operand_crd(inst); |
| 4324 | dec->rs1 = rv_ireg_zero; |
| 4325 | dec->rs2 = rv_ireg_zero; |
| 4326 | dec->imm = operand_cimmi(inst); |
| 4327 | break; |
| 4328 | case rv_codec_ci_lui: |
| 4329 | dec->rd = operand_crd(inst); |
| 4330 | dec->rs1 = rv_ireg_zero; |
| 4331 | dec->rs2 = rv_ireg_zero; |
| 4332 | dec->imm = operand_cimmui(inst); |
| 4333 | break; |
| 4334 | case rv_codec_ci_none: |
| 4335 | dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; |
| 4336 | dec->imm = 0; |
| 4337 | break; |
| 4338 | case rv_codec_ciw_4spn: |
| 4339 | dec->rd = operand_crdq(inst) + 8; |
| 4340 | dec->rs1 = rv_ireg_sp; |
| 4341 | dec->rs2 = rv_ireg_zero; |
| 4342 | dec->imm = operand_cimm4spn(inst); |
| 4343 | break; |
| 4344 | case rv_codec_cj: |
| 4345 | dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; |
| 4346 | dec->imm = operand_cimmj(inst); |
| 4347 | break; |
| 4348 | case rv_codec_cj_jal: |
| 4349 | dec->rd = rv_ireg_ra; |
| 4350 | dec->rs1 = dec->rs2 = rv_ireg_zero; |
| 4351 | dec->imm = operand_cimmj(inst); |
| 4352 | break; |
| 4353 | case rv_codec_cl_lw: |
| 4354 | dec->rd = operand_crdq(inst) + 8; |
| 4355 | dec->rs1 = operand_crs1q(inst) + 8; |
| 4356 | dec->rs2 = rv_ireg_zero; |
| 4357 | dec->imm = operand_cimmw(inst); |
| 4358 | break; |
| 4359 | case rv_codec_cl_ld: |
| 4360 | dec->rd = operand_crdq(inst) + 8; |
| 4361 | dec->rs1 = operand_crs1q(inst) + 8; |
| 4362 | dec->rs2 = rv_ireg_zero; |
| 4363 | dec->imm = operand_cimmd(inst); |
| 4364 | break; |
| 4365 | case rv_codec_cl_lq: |
| 4366 | dec->rd = operand_crdq(inst) + 8; |
| 4367 | dec->rs1 = operand_crs1q(inst) + 8; |
| 4368 | dec->rs2 = rv_ireg_zero; |
| 4369 | dec->imm = operand_cimmq(inst); |
| 4370 | break; |
| 4371 | case rv_codec_cr: |
| 4372 | dec->rd = dec->rs1 = operand_crs1rd(inst); |
| 4373 | dec->rs2 = operand_crs2(inst); |
| 4374 | dec->imm = 0; |
| 4375 | break; |
| 4376 | case rv_codec_cr_mv: |
| 4377 | dec->rd = operand_crd(inst); |
| 4378 | dec->rs1 = operand_crs2(inst); |
| 4379 | dec->rs2 = rv_ireg_zero; |
| 4380 | dec->imm = 0; |
| 4381 | break; |
| 4382 | case rv_codec_cr_jalr: |
| 4383 | dec->rd = rv_ireg_ra; |
| 4384 | dec->rs1 = operand_crs1(inst); |
| 4385 | dec->rs2 = rv_ireg_zero; |
| 4386 | dec->imm = 0; |
| 4387 | break; |
| 4388 | case rv_codec_cr_jr: |
| 4389 | dec->rd = rv_ireg_zero; |
| 4390 | dec->rs1 = operand_crs1(inst); |
| 4391 | dec->rs2 = rv_ireg_zero; |
| 4392 | dec->imm = 0; |
| 4393 | break; |
| 4394 | case rv_codec_cs: |
| 4395 | dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; |
| 4396 | dec->rs2 = operand_crs2q(inst) + 8; |
| 4397 | dec->imm = 0; |
| 4398 | break; |
| 4399 | case rv_codec_cs_sw: |
| 4400 | dec->rd = rv_ireg_zero; |
| 4401 | dec->rs1 = operand_crs1q(inst) + 8; |
| 4402 | dec->rs2 = operand_crs2q(inst) + 8; |
| 4403 | dec->imm = operand_cimmw(inst); |
| 4404 | break; |
| 4405 | case rv_codec_cs_sd: |
| 4406 | dec->rd = rv_ireg_zero; |
| 4407 | dec->rs1 = operand_crs1q(inst) + 8; |
| 4408 | dec->rs2 = operand_crs2q(inst) + 8; |
| 4409 | dec->imm = operand_cimmd(inst); |
| 4410 | break; |
| 4411 | case rv_codec_cs_sq: |
| 4412 | dec->rd = rv_ireg_zero; |
| 4413 | dec->rs1 = operand_crs1q(inst) + 8; |
| 4414 | dec->rs2 = operand_crs2q(inst) + 8; |
| 4415 | dec->imm = operand_cimmq(inst); |
| 4416 | break; |
| 4417 | case rv_codec_css_swsp: |
| 4418 | dec->rd = rv_ireg_zero; |
| 4419 | dec->rs1 = rv_ireg_sp; |
| 4420 | dec->rs2 = operand_crs2(inst); |
| 4421 | dec->imm = operand_cimmswsp(inst); |
| 4422 | break; |
| 4423 | case rv_codec_css_sdsp: |
| 4424 | dec->rd = rv_ireg_zero; |
| 4425 | dec->rs1 = rv_ireg_sp; |
| 4426 | dec->rs2 = operand_crs2(inst); |
| 4427 | dec->imm = operand_cimmsdsp(inst); |
| 4428 | break; |
| 4429 | case rv_codec_css_sqsp: |
| 4430 | dec->rd = rv_ireg_zero; |
| 4431 | dec->rs1 = rv_ireg_sp; |
| 4432 | dec->rs2 = operand_crs2(inst); |
| 4433 | dec->imm = operand_cimmsqsp(inst); |
| 4434 | break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 4435 | case rv_codec_k_bs: |
| 4436 | dec->rs1 = operand_rs1(inst); |
| 4437 | dec->rs2 = operand_rs2(inst); |
| 4438 | dec->bs = operand_bs(inst); |
| 4439 | break; |
| 4440 | case rv_codec_k_rnum: |
| 4441 | dec->rd = operand_rd(inst); |
| 4442 | dec->rs1 = operand_rs1(inst); |
| 4443 | dec->rnum = operand_rnum(inst); |
| 4444 | break; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 4445 | case rv_codec_v_r: |
| 4446 | dec->rd = operand_rd(inst); |
| 4447 | dec->rs1 = operand_rs1(inst); |
| 4448 | dec->rs2 = operand_rs2(inst); |
| 4449 | dec->vm = operand_vm(inst); |
| 4450 | break; |
| 4451 | case rv_codec_v_ldst: |
| 4452 | dec->rd = operand_rd(inst); |
| 4453 | dec->rs1 = operand_rs1(inst); |
| 4454 | dec->vm = operand_vm(inst); |
| 4455 | break; |
| 4456 | case rv_codec_v_i: |
| 4457 | dec->rd = operand_rd(inst); |
| 4458 | dec->rs2 = operand_rs2(inst); |
| 4459 | dec->imm = operand_vimm(inst); |
| 4460 | dec->vm = operand_vm(inst); |
| 4461 | break; |
| 4462 | case rv_codec_vsetvli: |
| 4463 | dec->rd = operand_rd(inst); |
| 4464 | dec->rs1 = operand_rs1(inst); |
| 4465 | dec->vzimm = operand_vzimm11(inst); |
| 4466 | break; |
| 4467 | case rv_codec_vsetivli: |
| 4468 | dec->rd = operand_rd(inst); |
| 4469 | dec->imm = operand_vimm(inst); |
| 4470 | dec->vzimm = operand_vzimm10(inst); |
| 4471 | break; |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 4472 | case rv_codec_zcb_lb: |
| 4473 | dec->rs1 = operand_crs1q(inst) + 8; |
| 4474 | dec->rs2 = operand_crs2q(inst) + 8; |
| 4475 | dec->imm = operand_uimm_c_lb(inst); |
| 4476 | break; |
| 4477 | case rv_codec_zcb_lh: |
| 4478 | dec->rs1 = operand_crs1q(inst) + 8; |
| 4479 | dec->rs2 = operand_crs2q(inst) + 8; |
| 4480 | dec->imm = operand_uimm_c_lh(inst); |
| 4481 | break; |
| 4482 | case rv_codec_zcb_ext: |
| 4483 | dec->rd = operand_crs1q(inst) + 8; |
| 4484 | break; |
| 4485 | case rv_codec_zcb_mul: |
| 4486 | dec->rd = operand_crs1rdq(inst) + 8; |
| 4487 | dec->rs2 = operand_crs2q(inst) + 8; |
| 4488 | break; |
| 4489 | case rv_codec_zcmp_cm_pushpop: |
| 4490 | dec->imm = operand_zcmp_stack_adj(inst, isa); |
| 4491 | dec->rlist = operand_zcmp_rlist(inst); |
| 4492 | break; |
| 4493 | case rv_codec_zcmp_cm_mv: |
| 4494 | dec->rd = operand_sreg1(inst); |
| 4495 | dec->rs2 = operand_sreg2(inst); |
| 4496 | break; |
| 4497 | case rv_codec_zcmt_jt: |
| 4498 | dec->imm = operand_tbl_index(inst); |
| 4499 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4500 | }; |
| 4501 | } |
| 4502 | |
| 4503 | /* check constraint */ |
| 4504 | |
| 4505 | static bool check_constraints(rv_decode *dec, const rvc_constraint *c) |
| 4506 | { |
| 4507 | int32_t imm = dec->imm; |
| 4508 | uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2; |
| 4509 | while (*c != rvc_end) { |
| 4510 | switch (*c) { |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4511 | case rvc_rd_eq_ra: |
| 4512 | if (!(rd == 1)) { |
| 4513 | return false; |
| 4514 | } |
| 4515 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4516 | case rvc_rd_eq_x0: |
| 4517 | if (!(rd == 0)) { |
| 4518 | return false; |
| 4519 | } |
| 4520 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4521 | case rvc_rs1_eq_x0: |
| 4522 | if (!(rs1 == 0)) { |
| 4523 | return false; |
| 4524 | } |
| 4525 | break; |
| 4526 | case rvc_rs2_eq_x0: |
| 4527 | if (!(rs2 == 0)) { |
| 4528 | return false; |
| 4529 | } |
| 4530 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4531 | case rvc_rs2_eq_rs1: |
| 4532 | if (!(rs2 == rs1)) { |
| 4533 | return false; |
| 4534 | } |
| 4535 | break; |
| 4536 | case rvc_rs1_eq_ra: |
| 4537 | if (!(rs1 == 1)) { |
| 4538 | return false; |
| 4539 | } |
| 4540 | break; |
| 4541 | case rvc_imm_eq_zero: |
| 4542 | if (!(imm == 0)) { |
| 4543 | return false; |
| 4544 | } |
| 4545 | break; |
| 4546 | case rvc_imm_eq_n1: |
| 4547 | if (!(imm == -1)) { |
| 4548 | return false; |
| 4549 | } |
| 4550 | break; |
| 4551 | case rvc_imm_eq_p1: |
| 4552 | if (!(imm == 1)) { |
| 4553 | return false; |
| 4554 | } |
| 4555 | break; |
| 4556 | case rvc_csr_eq_0x001: |
| 4557 | if (!(imm == 0x001)) { |
| 4558 | return false; |
| 4559 | } |
| 4560 | break; |
| 4561 | case rvc_csr_eq_0x002: |
| 4562 | if (!(imm == 0x002)) { |
| 4563 | return false; |
| 4564 | } |
| 4565 | break; |
| 4566 | case rvc_csr_eq_0x003: |
| 4567 | if (!(imm == 0x003)) { |
| 4568 | return false; |
| 4569 | } |
| 4570 | break; |
| 4571 | case rvc_csr_eq_0xc00: |
| 4572 | if (!(imm == 0xc00)) { |
| 4573 | return false; |
| 4574 | } |
| 4575 | break; |
| 4576 | case rvc_csr_eq_0xc01: |
| 4577 | if (!(imm == 0xc01)) { |
| 4578 | return false; |
| 4579 | } |
| 4580 | break; |
| 4581 | case rvc_csr_eq_0xc02: |
| 4582 | if (!(imm == 0xc02)) { |
| 4583 | return false; |
| 4584 | } |
| 4585 | break; |
| 4586 | case rvc_csr_eq_0xc80: |
| 4587 | if (!(imm == 0xc80)) { |
| 4588 | return false; |
| 4589 | } |
| 4590 | break; |
| 4591 | case rvc_csr_eq_0xc81: |
| 4592 | if (!(imm == 0xc81)) { |
| 4593 | return false; |
| 4594 | } |
| 4595 | break; |
| 4596 | case rvc_csr_eq_0xc82: |
| 4597 | if (!(imm == 0xc82)) { |
| 4598 | return false; |
| 4599 | } |
| 4600 | break; |
| 4601 | default: break; |
| 4602 | } |
| 4603 | c++; |
| 4604 | } |
| 4605 | return true; |
| 4606 | } |
| 4607 | |
| 4608 | /* instruction length */ |
| 4609 | |
| 4610 | static size_t inst_length(rv_inst inst) |
| 4611 | { |
| 4612 | /* NOTE: supports maximum instruction size of 64-bits */ |
| 4613 | |
Weiwei Li | 3bd8717 | 2023-05-23 17:35:39 +0800 | [diff] [blame] | 4614 | /* |
| 4615 | * instruction length coding |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4616 | * |
| 4617 | * aa - 16 bit aa != 11 |
| 4618 | * bbb11 - 32 bit bbb != 111 |
| 4619 | * 011111 - 48 bit |
| 4620 | * 0111111 - 64 bit |
| 4621 | */ |
| 4622 | |
| 4623 | return (inst & 0b11) != 0b11 ? 2 |
| 4624 | : (inst & 0b11100) != 0b11100 ? 4 |
| 4625 | : (inst & 0b111111) == 0b011111 ? 6 |
| 4626 | : (inst & 0b1111111) == 0b0111111 ? 8 |
| 4627 | : 0; |
| 4628 | } |
| 4629 | |
| 4630 | /* format instruction */ |
| 4631 | |
| 4632 | static void append(char *s1, const char *s2, size_t n) |
| 4633 | { |
| 4634 | size_t l1 = strlen(s1); |
| 4635 | if (n - l1 - 1 > 0) { |
| 4636 | strncat(s1, s2, n - l1); |
| 4637 | } |
| 4638 | } |
| 4639 | |
| 4640 | static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) |
| 4641 | { |
| 4642 | char tmp[64]; |
| 4643 | const char *fmt; |
| 4644 | |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4645 | fmt = opcode_data[dec->op].format; |
| 4646 | while (*fmt) { |
| 4647 | switch (*fmt) { |
| 4648 | case 'O': |
| 4649 | append(buf, opcode_data[dec->op].name, buflen); |
| 4650 | break; |
| 4651 | case '(': |
| 4652 | append(buf, "(", buflen); |
| 4653 | break; |
| 4654 | case ',': |
| 4655 | append(buf, ",", buflen); |
| 4656 | break; |
| 4657 | case ')': |
| 4658 | append(buf, ")", buflen); |
| 4659 | break; |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 4660 | case '-': |
| 4661 | append(buf, "-", buflen); |
| 4662 | break; |
Weiwei Li | 5748c88 | 2022-04-23 10:35:09 +0800 | [diff] [blame] | 4663 | case 'b': |
| 4664 | snprintf(tmp, sizeof(tmp), "%d", dec->bs); |
| 4665 | append(buf, tmp, buflen); |
| 4666 | break; |
| 4667 | case 'n': |
| 4668 | snprintf(tmp, sizeof(tmp), "%d", dec->rnum); |
| 4669 | append(buf, tmp, buflen); |
| 4670 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4671 | case '0': |
| 4672 | append(buf, rv_ireg_name_sym[dec->rd], buflen); |
| 4673 | break; |
| 4674 | case '1': |
| 4675 | append(buf, rv_ireg_name_sym[dec->rs1], buflen); |
| 4676 | break; |
| 4677 | case '2': |
| 4678 | append(buf, rv_ireg_name_sym[dec->rs2], buflen); |
| 4679 | break; |
| 4680 | case '3': |
Weiwei Li | c54dab4 | 2023-05-23 17:35:36 +0800 | [diff] [blame] | 4681 | append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rd] : |
| 4682 | rv_freg_name_sym[dec->rd], |
| 4683 | buflen); |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4684 | break; |
| 4685 | case '4': |
Weiwei Li | c54dab4 | 2023-05-23 17:35:36 +0800 | [diff] [blame] | 4686 | append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs1] : |
| 4687 | rv_freg_name_sym[dec->rs1], |
| 4688 | buflen); |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4689 | break; |
| 4690 | case '5': |
Weiwei Li | c54dab4 | 2023-05-23 17:35:36 +0800 | [diff] [blame] | 4691 | append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs2] : |
| 4692 | rv_freg_name_sym[dec->rs2], |
| 4693 | buflen); |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4694 | break; |
| 4695 | case '6': |
Weiwei Li | c54dab4 | 2023-05-23 17:35:36 +0800 | [diff] [blame] | 4696 | append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs3] : |
| 4697 | rv_freg_name_sym[dec->rs3], |
| 4698 | buflen); |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4699 | break; |
| 4700 | case '7': |
| 4701 | snprintf(tmp, sizeof(tmp), "%d", dec->rs1); |
| 4702 | append(buf, tmp, buflen); |
| 4703 | break; |
| 4704 | case 'i': |
| 4705 | snprintf(tmp, sizeof(tmp), "%d", dec->imm); |
| 4706 | append(buf, tmp, buflen); |
| 4707 | break; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 4708 | case 'u': |
| 4709 | snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111)); |
| 4710 | append(buf, tmp, buflen); |
| 4711 | break; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4712 | case 'o': |
| 4713 | snprintf(tmp, sizeof(tmp), "%d", dec->imm); |
| 4714 | append(buf, tmp, buflen); |
| 4715 | while (strlen(buf) < tab * 2) { |
| 4716 | append(buf, " ", buflen); |
| 4717 | } |
| 4718 | snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64, |
| 4719 | dec->pc + dec->imm); |
| 4720 | append(buf, tmp, buflen); |
| 4721 | break; |
| 4722 | case 'c': { |
| 4723 | const char *name = csr_name(dec->imm & 0xfff); |
| 4724 | if (name) { |
| 4725 | append(buf, name, buflen); |
| 4726 | } else { |
| 4727 | snprintf(tmp, sizeof(tmp), "0x%03x", dec->imm & 0xfff); |
| 4728 | append(buf, tmp, buflen); |
| 4729 | } |
| 4730 | break; |
| 4731 | } |
| 4732 | case 'r': |
| 4733 | switch (dec->rm) { |
| 4734 | case rv_rm_rne: |
| 4735 | append(buf, "rne", buflen); |
| 4736 | break; |
| 4737 | case rv_rm_rtz: |
| 4738 | append(buf, "rtz", buflen); |
| 4739 | break; |
| 4740 | case rv_rm_rdn: |
| 4741 | append(buf, "rdn", buflen); |
| 4742 | break; |
| 4743 | case rv_rm_rup: |
| 4744 | append(buf, "rup", buflen); |
| 4745 | break; |
| 4746 | case rv_rm_rmm: |
| 4747 | append(buf, "rmm", buflen); |
| 4748 | break; |
| 4749 | case rv_rm_dyn: |
| 4750 | append(buf, "dyn", buflen); |
| 4751 | break; |
| 4752 | default: |
| 4753 | append(buf, "inv", buflen); |
| 4754 | break; |
| 4755 | } |
| 4756 | break; |
| 4757 | case 'p': |
| 4758 | if (dec->pred & rv_fence_i) { |
| 4759 | append(buf, "i", buflen); |
| 4760 | } |
| 4761 | if (dec->pred & rv_fence_o) { |
| 4762 | append(buf, "o", buflen); |
| 4763 | } |
| 4764 | if (dec->pred & rv_fence_r) { |
| 4765 | append(buf, "r", buflen); |
| 4766 | } |
| 4767 | if (dec->pred & rv_fence_w) { |
| 4768 | append(buf, "w", buflen); |
| 4769 | } |
| 4770 | break; |
| 4771 | case 's': |
| 4772 | if (dec->succ & rv_fence_i) { |
| 4773 | append(buf, "i", buflen); |
| 4774 | } |
| 4775 | if (dec->succ & rv_fence_o) { |
| 4776 | append(buf, "o", buflen); |
| 4777 | } |
| 4778 | if (dec->succ & rv_fence_r) { |
| 4779 | append(buf, "r", buflen); |
| 4780 | } |
| 4781 | if (dec->succ & rv_fence_w) { |
| 4782 | append(buf, "w", buflen); |
| 4783 | } |
| 4784 | break; |
| 4785 | case '\t': |
| 4786 | while (strlen(buf) < tab) { |
| 4787 | append(buf, " ", buflen); |
| 4788 | } |
| 4789 | break; |
| 4790 | case 'A': |
| 4791 | if (dec->aq) { |
| 4792 | append(buf, ".aq", buflen); |
| 4793 | } |
| 4794 | break; |
| 4795 | case 'R': |
| 4796 | if (dec->rl) { |
| 4797 | append(buf, ".rl", buflen); |
| 4798 | } |
| 4799 | break; |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 4800 | case 'l': |
| 4801 | append(buf, ",v0", buflen); |
| 4802 | break; |
| 4803 | case 'm': |
| 4804 | if (dec->vm == 0) { |
| 4805 | append(buf, ",v0.t", buflen); |
| 4806 | } |
| 4807 | break; |
| 4808 | case 'D': |
| 4809 | append(buf, rv_vreg_name_sym[dec->rd], buflen); |
| 4810 | break; |
| 4811 | case 'E': |
| 4812 | append(buf, rv_vreg_name_sym[dec->rs1], buflen); |
| 4813 | break; |
| 4814 | case 'F': |
| 4815 | append(buf, rv_vreg_name_sym[dec->rs2], buflen); |
| 4816 | break; |
| 4817 | case 'G': |
| 4818 | append(buf, rv_vreg_name_sym[dec->rs3], buflen); |
| 4819 | break; |
| 4820 | case 'v': { |
| 4821 | char nbuf[32] = {0}; |
| 4822 | const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3); |
| 4823 | sprintf(nbuf, "%d", sew); |
| 4824 | const int lmul = dec->vzimm & 0b11; |
| 4825 | const int flmul = (dec->vzimm >> 2) & 1; |
| 4826 | const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu"; |
| 4827 | const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu"; |
| 4828 | append(buf, "e", buflen); |
| 4829 | append(buf, nbuf, buflen); |
| 4830 | append(buf, ",m", buflen); |
| 4831 | if (flmul) { |
| 4832 | switch (lmul) { |
| 4833 | case 3: |
| 4834 | sprintf(nbuf, "f2"); |
| 4835 | break; |
| 4836 | case 2: |
| 4837 | sprintf(nbuf, "f4"); |
| 4838 | break; |
| 4839 | case 1: |
| 4840 | sprintf(nbuf, "f8"); |
| 4841 | break; |
| 4842 | } |
| 4843 | append(buf, nbuf, buflen); |
| 4844 | } else { |
| 4845 | sprintf(nbuf, "%d", 1 << lmul); |
| 4846 | append(buf, nbuf, buflen); |
| 4847 | } |
| 4848 | append(buf, ",", buflen); |
| 4849 | append(buf, vta, buflen); |
| 4850 | append(buf, ",", buflen); |
| 4851 | append(buf, vma, buflen); |
| 4852 | break; |
| 4853 | } |
Weiwei Li | 2c71d02 | 2023-03-07 16:14:02 +0800 | [diff] [blame] | 4854 | case 'x': { |
| 4855 | switch (dec->rlist) { |
| 4856 | case 4: |
| 4857 | snprintf(tmp, sizeof(tmp), "{ra}"); |
| 4858 | break; |
| 4859 | case 5: |
| 4860 | snprintf(tmp, sizeof(tmp), "{ra, s0}"); |
| 4861 | break; |
| 4862 | case 15: |
| 4863 | snprintf(tmp, sizeof(tmp), "{ra, s0-s11}"); |
| 4864 | break; |
| 4865 | default: |
| 4866 | snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5); |
| 4867 | break; |
| 4868 | } |
| 4869 | append(buf, tmp, buflen); |
| 4870 | break; |
| 4871 | } |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4872 | default: |
| 4873 | break; |
| 4874 | } |
| 4875 | fmt++; |
| 4876 | } |
| 4877 | } |
| 4878 | |
| 4879 | /* lift instruction to pseudo-instruction */ |
| 4880 | |
| 4881 | static void decode_inst_lift_pseudo(rv_decode *dec) |
| 4882 | { |
| 4883 | const rv_comp_data *comp_data = opcode_data[dec->op].pseudo; |
| 4884 | if (!comp_data) { |
| 4885 | return; |
| 4886 | } |
| 4887 | while (comp_data->constraints) { |
| 4888 | if (check_constraints(dec, comp_data->constraints)) { |
| 4889 | dec->op = comp_data->op; |
| 4890 | dec->codec = opcode_data[dec->op].codec; |
| 4891 | return; |
| 4892 | } |
| 4893 | comp_data++; |
| 4894 | } |
| 4895 | } |
| 4896 | |
| 4897 | /* decompress instruction */ |
| 4898 | |
| 4899 | static void decode_inst_decompress_rv32(rv_decode *dec) |
| 4900 | { |
| 4901 | int decomp_op = opcode_data[dec->op].decomp_rv32; |
| 4902 | if (decomp_op != rv_op_illegal) { |
Michael Clark | f88222d | 2019-06-24 16:42:33 -0700 | [diff] [blame] | 4903 | if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) |
| 4904 | && dec->imm == 0) { |
| 4905 | dec->op = rv_op_illegal; |
| 4906 | } else { |
| 4907 | dec->op = decomp_op; |
| 4908 | dec->codec = opcode_data[decomp_op].codec; |
| 4909 | } |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4910 | } |
| 4911 | } |
| 4912 | |
| 4913 | static void decode_inst_decompress_rv64(rv_decode *dec) |
| 4914 | { |
| 4915 | int decomp_op = opcode_data[dec->op].decomp_rv64; |
| 4916 | if (decomp_op != rv_op_illegal) { |
Michael Clark | f88222d | 2019-06-24 16:42:33 -0700 | [diff] [blame] | 4917 | if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) |
| 4918 | && dec->imm == 0) { |
| 4919 | dec->op = rv_op_illegal; |
| 4920 | } else { |
| 4921 | dec->op = decomp_op; |
| 4922 | dec->codec = opcode_data[decomp_op].codec; |
| 4923 | } |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4924 | } |
| 4925 | } |
| 4926 | |
| 4927 | static void decode_inst_decompress_rv128(rv_decode *dec) |
| 4928 | { |
| 4929 | int decomp_op = opcode_data[dec->op].decomp_rv128; |
| 4930 | if (decomp_op != rv_op_illegal) { |
Michael Clark | f88222d | 2019-06-24 16:42:33 -0700 | [diff] [blame] | 4931 | if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) |
| 4932 | && dec->imm == 0) { |
| 4933 | dec->op = rv_op_illegal; |
| 4934 | } else { |
| 4935 | dec->op = decomp_op; |
| 4936 | dec->codec = opcode_data[decomp_op].codec; |
| 4937 | } |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4938 | } |
| 4939 | } |
| 4940 | |
| 4941 | static void decode_inst_decompress(rv_decode *dec, rv_isa isa) |
| 4942 | { |
| 4943 | switch (isa) { |
| 4944 | case rv32: |
| 4945 | decode_inst_decompress_rv32(dec); |
| 4946 | break; |
| 4947 | case rv64: |
| 4948 | decode_inst_decompress_rv64(dec); |
| 4949 | break; |
| 4950 | case rv128: |
| 4951 | decode_inst_decompress_rv128(dec); |
| 4952 | break; |
| 4953 | } |
| 4954 | } |
| 4955 | |
| 4956 | /* disassemble instruction */ |
| 4957 | |
| 4958 | static void |
Weiwei Li | 454c220 | 2023-05-23 17:35:34 +0800 | [diff] [blame] | 4959 | disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst, |
| 4960 | RISCVCPUConfig *cfg) |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4961 | { |
| 4962 | rv_decode dec = { 0 }; |
| 4963 | dec.pc = pc; |
| 4964 | dec.inst = inst; |
Weiwei Li | 454c220 | 2023-05-23 17:35:34 +0800 | [diff] [blame] | 4965 | dec.cfg = cfg; |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4966 | decode_inst_opcode(&dec, isa); |
Frédéric Pétrot | 3363277 | 2022-07-10 13:04:51 +0200 | [diff] [blame] | 4967 | decode_inst_operands(&dec, isa); |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4968 | decode_inst_decompress(&dec, isa); |
| 4969 | decode_inst_lift_pseudo(&dec); |
Yang Liu | 07f4964 | 2022-09-28 13:18:42 +0800 | [diff] [blame] | 4970 | format_inst(buf, buflen, 24, &dec); |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4971 | } |
| 4972 | |
Michael Clark | 6296a79 | 2018-03-04 13:50:12 +1300 | [diff] [blame] | 4973 | #define INST_FMT_2 "%04" PRIx64 " " |
| 4974 | #define INST_FMT_4 "%08" PRIx64 " " |
| 4975 | #define INST_FMT_6 "%012" PRIx64 " " |
| 4976 | #define INST_FMT_8 "%016" PRIx64 " " |
| 4977 | |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 4978 | static int |
| 4979 | print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) |
| 4980 | { |
| 4981 | char buf[128] = { 0 }; |
| 4982 | bfd_byte packet[2]; |
| 4983 | rv_inst inst = 0; |
| 4984 | size_t len = 2; |
| 4985 | bfd_vma n; |
| 4986 | int status; |
| 4987 | |
| 4988 | /* Instructions are made of 2-byte packets in little-endian order */ |
| 4989 | for (n = 0; n < len; n += 2) { |
| 4990 | status = (*info->read_memory_func)(memaddr + n, packet, 2, info); |
| 4991 | if (status != 0) { |
| 4992 | /* Don't fail just because we fell off the end. */ |
| 4993 | if (n > 0) { |
| 4994 | break; |
| 4995 | } |
| 4996 | (*info->memory_error_func)(status, memaddr, info); |
| 4997 | return status; |
| 4998 | } |
| 4999 | inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n); |
| 5000 | if (n == 0) { |
| 5001 | len = inst_length(inst); |
| 5002 | } |
| 5003 | } |
| 5004 | |
Michael Clark | 6296a79 | 2018-03-04 13:50:12 +1300 | [diff] [blame] | 5005 | switch (len) { |
| 5006 | case 2: |
| 5007 | (*info->fprintf_func)(info->stream, INST_FMT_2, inst); |
| 5008 | break; |
| 5009 | case 4: |
| 5010 | (*info->fprintf_func)(info->stream, INST_FMT_4, inst); |
| 5011 | break; |
| 5012 | case 6: |
| 5013 | (*info->fprintf_func)(info->stream, INST_FMT_6, inst); |
| 5014 | break; |
| 5015 | default: |
| 5016 | (*info->fprintf_func)(info->stream, INST_FMT_8, inst); |
| 5017 | break; |
| 5018 | } |
| 5019 | |
Weiwei Li | 454c220 | 2023-05-23 17:35:34 +0800 | [diff] [blame] | 5020 | disasm_inst(buf, sizeof(buf), isa, memaddr, inst, |
| 5021 | (RISCVCPUConfig *)info->target_info); |
Michael Clark | ea10325 | 2018-03-03 01:31:10 +1300 | [diff] [blame] | 5022 | (*info->fprintf_func)(info->stream, "%s", buf); |
| 5023 | |
| 5024 | return len; |
| 5025 | } |
| 5026 | |
| 5027 | int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info) |
| 5028 | { |
| 5029 | return print_insn_riscv(memaddr, info, rv32); |
| 5030 | } |
| 5031 | |
| 5032 | int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info) |
| 5033 | { |
| 5034 | return print_insn_riscv(memaddr, info, rv64); |
| 5035 | } |
Frédéric Pétrot | 332dab6 | 2022-01-06 22:00:57 +0100 | [diff] [blame] | 5036 | |
| 5037 | int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info) |
| 5038 | { |
| 5039 | return print_insn_riscv(memaddr, info, rv128); |
| 5040 | } |