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Alistair Francisfe0fe472020-04-23 11:30:50 -07001/*
2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3 *
4 * Copyright (c) 2020 Western Digital
5 *
6 * Provides a board compatible with the OpenTitan FPGA platform:
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include "qemu/osdep.h"
Bin Meng91b1fbd2021-10-20 09:41:08 +080022#include "qemu/cutils.h"
Alistair Francisfe0fe472020-04-23 11:30:50 -070023#include "hw/riscv/opentitan.h"
24#include "qapi/error.h"
25#include "hw/boards.h"
26#include "hw/misc/unimp.h"
27#include "hw/riscv/boot.h"
Alistair Francis888c9af2020-06-09 16:08:29 -070028#include "qemu/units.h"
Alistair Francisb9fc5132020-04-23 18:40:57 -070029#include "sysemu/sysemu.h"
Alistair Francisfe0fe472020-04-23 11:30:50 -070030
Bin Meng73261282021-02-20 22:48:04 +080031static const MemMapEntry ibex_memmap[] = {
Eduardo Habkost30c717c2020-08-25 15:20:03 -040032 [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
33 [IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
34 [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
Alistair Francisd31e9702020-12-14 17:56:54 -080035 [IBEX_DEV_UART] = { 0x40000000, 0x1000 },
36 [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
37 [IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
38 [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
39 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
Alistair Francis3ef64342021-06-18 17:28:01 +100040 [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
Alistair Francisd31e9702020-12-14 17:56:54 -080041 [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
42 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
Alistair Francised481d92021-09-16 14:37:38 +100043 [IBEX_DEV_USBDEV] = { 0x40150000, 0x1000 },
Alistair Francisd31e9702020-12-14 17:56:54 -080044 [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
45 [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
46 [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
47 [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
48 [IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 },
Alistair Francisd31e9702020-12-14 17:56:54 -080049 [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
Alistair Francisd31e9702020-12-14 17:56:54 -080050 [IBEX_DEV_AES] = { 0x41100000, 0x1000 },
51 [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
52 [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
Alistair Francisef631002021-10-18 12:38:39 +100053 [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 },
54 [IBEX_DEV_KEYMGR] = { 0x41140000, 0x1000 },
Alistair Francisd31e9702020-12-14 17:56:54 -080055 [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 },
56 [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
57 [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
58 [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
59 [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
60 [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
Alistair Francis5ee25762021-07-09 13:38:39 +100061 [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
Alistair Francisef631002021-10-18 12:38:39 +100062 [IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 },
Alistair Francisbb7e0cd2021-07-09 13:38:48 +100063 [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
Alistair Francisfe0fe472020-04-23 11:30:50 -070064};
65
Bin Meng89494462020-06-08 07:17:31 -070066static void opentitan_board_init(MachineState *machine)
Alistair Francisfe0fe472020-04-23 11:30:50 -070067{
Bin Meng91b1fbd2021-10-20 09:41:08 +080068 MachineClass *mc = MACHINE_GET_CLASS(machine);
Bin Meng73261282021-02-20 22:48:04 +080069 const MemMapEntry *memmap = ibex_memmap;
Alistair Francisfe0fe472020-04-23 11:30:50 -070070 OpenTitanState *s = g_new0(OpenTitanState, 1);
71 MemoryRegion *sys_mem = get_system_memory();
Bin Meng91b1fbd2021-10-20 09:41:08 +080072
73 if (machine->ram_size != mc->default_ram_size) {
74 char *sz = size_to_str(mc->default_ram_size);
75 error_report("Invalid RAM size, should be %s", sz);
76 g_free(sz);
77 exit(EXIT_FAILURE);
78 }
Alistair Francisfe0fe472020-04-23 11:30:50 -070079
80 /* Initialize SoC */
81 object_initialize_child(OBJECT(machine), "soc", &s->soc,
Markus Armbruster9fc7fc42020-06-10 07:32:25 +020082 TYPE_RISCV_IBEX_SOC);
Markus Armbrusterce189ab2020-06-10 07:32:45 +020083 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
Alistair Francisfe0fe472020-04-23 11:30:50 -070084
Alistair Francisfe0fe472020-04-23 11:30:50 -070085 memory_region_add_subregion(sys_mem,
Bin Meng91b1fbd2021-10-20 09:41:08 +080086 memmap[IBEX_DEV_RAM].base, machine->ram);
Alistair Francisfe0fe472020-04-23 11:30:50 -070087
Alistair Francisfe0fe472020-04-23 11:30:50 -070088 if (machine->firmware) {
Eduardo Habkost30c717c2020-08-25 15:20:03 -040089 riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
Alistair Francisfe0fe472020-04-23 11:30:50 -070090 }
91
92 if (machine->kernel_filename) {
Alistair Francis38bc4e32020-10-13 17:17:33 -070093 riscv_load_kernel(machine->kernel_filename,
94 memmap[IBEX_DEV_RAM].base, NULL);
Alistair Francisfe0fe472020-04-23 11:30:50 -070095 }
96}
97
Bin Meng89494462020-06-08 07:17:31 -070098static void opentitan_machine_init(MachineClass *mc)
Alistair Francisfe0fe472020-04-23 11:30:50 -070099{
100 mc->desc = "RISC-V Board compatible with OpenTitan";
Bin Meng89494462020-06-08 07:17:31 -0700101 mc->init = opentitan_board_init;
Alistair Francisfe0fe472020-04-23 11:30:50 -0700102 mc->max_cpus = 1;
103 mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
Bin Meng91b1fbd2021-10-20 09:41:08 +0800104 mc->default_ram_id = "riscv.lowrisc.ibex.ram";
105 mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
Alistair Francisfe0fe472020-04-23 11:30:50 -0700106}
107
Bin Meng89494462020-06-08 07:17:31 -0700108DEFINE_MACHINE("opentitan", opentitan_machine_init)
Alistair Francisfe0fe472020-04-23 11:30:50 -0700109
Bin Meng89494462020-06-08 07:17:31 -0700110static void lowrisc_ibex_soc_init(Object *obj)
Alistair Francisfe0fe472020-04-23 11:30:50 -0700111{
112 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
113
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200114 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
Alistair Francisb9fc5132020-04-23 18:40:57 -0700115
Alistair Francisef631002021-10-18 12:38:39 +1000116 object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);
Alistair Franciscc411262020-04-23 14:08:45 -0700117
118 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
Alistair Francis3ef64342021-06-18 17:28:01 +1000119
120 object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700121}
122
Bin Meng89494462020-06-08 07:17:31 -0700123static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
Alistair Francisfe0fe472020-04-23 11:30:50 -0700124{
Bin Meng73261282021-02-20 22:48:04 +0800125 const MemMapEntry *memmap = ibex_memmap;
Alistair Francisfe0fe472020-04-23 11:30:50 -0700126 MachineState *ms = MACHINE(qdev_get_machine());
127 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
128 MemoryRegion *sys_mem = get_system_memory();
Alistair Francise5cc6aa2021-08-30 15:34:49 +1000129 int i;
Alistair Francisfe0fe472020-04-23 11:30:50 -0700130
Markus Armbruster5325cc32020-07-07 18:05:54 +0200131 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
Alistair Francisfe0fe472020-04-23 11:30:50 -0700132 &error_abort);
Markus Armbruster5325cc32020-07-07 18:05:54 +0200133 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
Alistair Francisfe0fe472020-04-23 11:30:50 -0700134 &error_abort);
Alexander Wagnerd11e3162021-04-20 10:00:08 +0200135 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200136 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700137
138 /* Boot ROM */
139 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400140 memmap[IBEX_DEV_ROM].size, &error_fatal);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700141 memory_region_add_subregion(sys_mem,
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400142 memmap[IBEX_DEV_ROM].base, &s->rom);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700143
144 /* Flash memory */
145 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400146 memmap[IBEX_DEV_FLASH].size, &error_fatal);
Alistair Francisbb7e0cd2021-07-09 13:38:48 +1000147 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
148 "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0,
149 memmap[IBEX_DEV_FLASH_VIRTUAL].size);
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400150 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
Alistair Francisfe0fe472020-04-23 11:30:50 -0700151 &s->flash_mem);
Alistair Francisbb7e0cd2021-07-09 13:38:48 +1000152 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,
153 &s->flash_alias);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700154
Alistair Francisb9fc5132020-04-23 18:40:57 -0700155 /* PLIC */
Alistair Francisef631002021-10-18 12:38:39 +1000156 qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
157 qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
158 qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
159 qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
160 qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
161 qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
162 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
163 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
Alistair Francis9b144ed2021-10-25 14:06:57 +1000164 qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
165 qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
Alistair Francisef631002021-10-18 12:38:39 +1000166 qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
167
Markus Armbruster668f62e2020-07-07 18:06:02 +0200168 if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
Alistair Francisb9fc5132020-04-23 18:40:57 -0700169 return;
170 }
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400171 sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
Alistair Francisb9fc5132020-04-23 18:40:57 -0700172
Alistair Francise5cc6aa2021-08-30 15:34:49 +1000173 for (i = 0; i < ms->smp.cpus; i++) {
174 CPUState *cpu = qemu_get_cpu(i);
175
Alistair Francisef631002021-10-18 12:38:39 +1000176 qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
Alistair Francise5cc6aa2021-08-30 15:34:49 +1000177 qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
178 }
179
Alistair Franciscc411262020-04-23 14:08:45 -0700180 /* UART */
181 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
Markus Armbruster668f62e2020-07-07 18:06:02 +0200182 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
Alistair Franciscc411262020-04-23 14:08:45 -0700183 return;
184 }
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400185 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
Alistair Franciscc411262020-04-23 14:08:45 -0700186 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
187 0, qdev_get_gpio_in(DEVICE(&s->plic),
Alistair Francisd4cad542021-03-31 11:00:11 -0400188 IBEX_UART0_TX_WATERMARK_IRQ));
Alistair Franciscc411262020-04-23 14:08:45 -0700189 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
190 1, qdev_get_gpio_in(DEVICE(&s->plic),
Alistair Francisd4cad542021-03-31 11:00:11 -0400191 IBEX_UART0_RX_WATERMARK_IRQ));
Alistair Franciscc411262020-04-23 14:08:45 -0700192 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
193 2, qdev_get_gpio_in(DEVICE(&s->plic),
Alistair Francisd4cad542021-03-31 11:00:11 -0400194 IBEX_UART0_TX_EMPTY_IRQ));
Alistair Franciscc411262020-04-23 14:08:45 -0700195 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
196 3, qdev_get_gpio_in(DEVICE(&s->plic),
Alistair Francisd4cad542021-03-31 11:00:11 -0400197 IBEX_UART0_RX_OVERFLOW_IRQ));
Alistair Franciscc411262020-04-23 14:08:45 -0700198
Alistair Francis3ef64342021-06-18 17:28:01 +1000199 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
200 return;
201 }
202 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
203 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
204 0, qdev_get_gpio_in(DEVICE(&s->plic),
205 IBEX_TIMER_TIMEREXPIRED0_0));
Alistair Francis57a3a622021-08-30 15:35:15 +1000206 qdev_connect_gpio_out(DEVICE(&s->timer), 0,
207 qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
208 IRQ_M_TIMER));
Alistair Francis3ef64342021-06-18 17:28:01 +1000209
Alistair Francisfe0fe472020-04-23 11:30:50 -0700210 create_unimplemented_device("riscv.lowrisc.ibex.gpio",
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400211 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700212 create_unimplemented_device("riscv.lowrisc.ibex.spi",
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400213 memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
Alistair Francisd31e9702020-12-14 17:56:54 -0800214 create_unimplemented_device("riscv.lowrisc.ibex.i2c",
215 memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
216 create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
217 memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
Alistair Francisd31e9702020-12-14 17:56:54 -0800218 create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
219 memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
220 create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
221 memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700222 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400223 memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700224 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400225 memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700226 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400227 memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
Alistair Francisd31e9702020-12-14 17:56:54 -0800228 create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
229 memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
230 create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
231 memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
232 create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
233 memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
234 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
235 memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700236 create_unimplemented_device("riscv.lowrisc.ibex.aes",
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400237 memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700238 create_unimplemented_device("riscv.lowrisc.ibex.hmac",
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400239 memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
Alistair Francisd31e9702020-12-14 17:56:54 -0800240 create_unimplemented_device("riscv.lowrisc.ibex.kmac",
241 memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
242 create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
243 memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
244 create_unimplemented_device("riscv.lowrisc.ibex.csrng",
245 memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
246 create_unimplemented_device("riscv.lowrisc.ibex.entropy",
247 memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
248 create_unimplemented_device("riscv.lowrisc.ibex.edn0",
249 memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
250 create_unimplemented_device("riscv.lowrisc.ibex.edn1",
251 memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700252 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400253 memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700254 create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
Eduardo Habkost30c717c2020-08-25 15:20:03 -0400255 memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
Alistair Francisd31e9702020-12-14 17:56:54 -0800256 create_unimplemented_device("riscv.lowrisc.ibex.otbn",
257 memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
Alistair Francis5ee25762021-07-09 13:38:39 +1000258 create_unimplemented_device("riscv.lowrisc.ibex.peri",
259 memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700260}
261
Bin Meng89494462020-06-08 07:17:31 -0700262static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
Alistair Francisfe0fe472020-04-23 11:30:50 -0700263{
264 DeviceClass *dc = DEVICE_CLASS(oc);
265
Bin Meng89494462020-06-08 07:17:31 -0700266 dc->realize = lowrisc_ibex_soc_realize;
Alistair Francisfe0fe472020-04-23 11:30:50 -0700267 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
268 dc->user_creatable = false;
269}
270
Bin Meng89494462020-06-08 07:17:31 -0700271static const TypeInfo lowrisc_ibex_soc_type_info = {
Alistair Francisfe0fe472020-04-23 11:30:50 -0700272 .name = TYPE_RISCV_IBEX_SOC,
273 .parent = TYPE_DEVICE,
274 .instance_size = sizeof(LowRISCIbexSoCState),
Bin Meng89494462020-06-08 07:17:31 -0700275 .instance_init = lowrisc_ibex_soc_init,
276 .class_init = lowrisc_ibex_soc_class_init,
Alistair Francisfe0fe472020-04-23 11:30:50 -0700277};
278
Bin Meng89494462020-06-08 07:17:31 -0700279static void lowrisc_ibex_soc_register_types(void)
Alistair Francisfe0fe472020-04-23 11:30:50 -0700280{
Bin Meng89494462020-06-08 07:17:31 -0700281 type_register_static(&lowrisc_ibex_soc_type_info);
Alistair Francisfe0fe472020-04-23 11:30:50 -0700282}
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Bin Meng89494462020-06-08 07:17:31 -0700284type_init(lowrisc_ibex_soc_register_types)