bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * common defines for all CPUs |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 18 | */ |
| 19 | #ifndef CPU_DEFS_H |
| 20 | #define CPU_DEFS_H |
| 21 | |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 22 | #ifndef NEED_CPU_H |
| 23 | #error cpu.h included from common code |
| 24 | #endif |
| 25 | |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 26 | #include "config.h" |
| 27 | #include <setjmp.h> |
bellard | ed1c0bc | 2004-02-16 22:17:43 +0000 | [diff] [blame] | 28 | #include <inttypes.h> |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 29 | #include "qemu/osdep.h" |
| 30 | #include "qemu/queue.h" |
Andreas Färber | ce927ed | 2013-05-28 14:02:38 +0200 | [diff] [blame] | 31 | #ifndef CONFIG_USER_ONLY |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 32 | #include "exec/hwaddr.h" |
Andreas Färber | ce927ed | 2013-05-28 14:02:38 +0200 | [diff] [blame] | 33 | #endif |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 34 | |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 35 | #ifndef TARGET_LONG_BITS |
| 36 | #error TARGET_LONG_BITS must be defined before including this header |
| 37 | #endif |
| 38 | |
| 39 | #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) |
| 40 | |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 41 | /* target_ulong is the type of a virtual address */ |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 42 | #if TARGET_LONG_SIZE == 4 |
Paolo Bonzini | 6cfd9b5 | 2013-04-17 16:26:41 +0200 | [diff] [blame] | 43 | typedef int32_t target_long; |
| 44 | typedef uint32_t target_ulong; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 45 | #define TARGET_FMT_lx "%08x" |
j_mayer | b62b461 | 2007-04-04 07:58:14 +0000 | [diff] [blame] | 46 | #define TARGET_FMT_ld "%d" |
j_mayer | 71c8b8f | 2007-09-19 05:46:03 +0000 | [diff] [blame] | 47 | #define TARGET_FMT_lu "%u" |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 48 | #elif TARGET_LONG_SIZE == 8 |
Paolo Bonzini | 6cfd9b5 | 2013-04-17 16:26:41 +0200 | [diff] [blame] | 49 | typedef int64_t target_long; |
| 50 | typedef uint64_t target_ulong; |
bellard | 26a7646 | 2006-06-25 18:15:32 +0000 | [diff] [blame] | 51 | #define TARGET_FMT_lx "%016" PRIx64 |
j_mayer | b62b461 | 2007-04-04 07:58:14 +0000 | [diff] [blame] | 52 | #define TARGET_FMT_ld "%" PRId64 |
j_mayer | 71c8b8f | 2007-09-19 05:46:03 +0000 | [diff] [blame] | 53 | #define TARGET_FMT_lu "%" PRIu64 |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 54 | #else |
| 55 | #error TARGET_LONG_SIZE undefined |
| 56 | #endif |
| 57 | |
bellard | 2be0071 | 2005-07-02 22:09:27 +0000 | [diff] [blame] | 58 | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
| 59 | #define EXCP_HLT 0x10001 /* hlt instruction reached */ |
| 60 | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ |
bellard | 5a1e3cf | 2005-11-23 21:02:53 +0000 | [diff] [blame] | 61 | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 62 | |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 63 | #define TB_JMP_CACHE_BITS 12 |
| 64 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) |
| 65 | |
pbrook | b362e5e | 2006-11-12 20:40:55 +0000 | [diff] [blame] | 66 | /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for |
| 67 | addresses on the same page. The top bits are the same. This allows |
| 68 | TLB invalidation to quickly clear a subset of the hash table. */ |
| 69 | #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) |
| 70 | #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) |
| 71 | #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) |
| 72 | #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) |
| 73 | |
Paul Brook | 20cb400 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 74 | #if !defined(CONFIG_USER_ONLY) |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 75 | #define CPU_TLB_BITS 8 |
| 76 | #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 77 | |
Paul Brook | 355b194 | 2010-04-05 00:28:53 +0100 | [diff] [blame] | 78 | #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 |
bellard | d656469 | 2008-01-31 09:22:27 +0000 | [diff] [blame] | 79 | #define CPU_TLB_ENTRY_BITS 4 |
| 80 | #else |
| 81 | #define CPU_TLB_ENTRY_BITS 5 |
| 82 | #endif |
| 83 | |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 84 | typedef struct CPUTLBEntry { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 85 | /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address |
| 86 | bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not |
| 87 | go directly to ram. |
bellard | db8d746 | 2003-10-27 21:12:17 +0000 | [diff] [blame] | 88 | bit 3 : indicates that the entry is invalid |
| 89 | bit 2..0 : zero |
| 90 | */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 91 | target_ulong addr_read; |
| 92 | target_ulong addr_write; |
| 93 | target_ulong addr_code; |
Paul Brook | 355b194 | 2010-04-05 00:28:53 +0100 | [diff] [blame] | 94 | /* Addend to virtual address to get host address. IO accesses |
pbrook | ee50add | 2008-11-29 13:33:23 +0000 | [diff] [blame] | 95 | use the corresponding iotlb value. */ |
Stefan Weil | 3b2992e | 2012-04-12 20:29:36 +0200 | [diff] [blame] | 96 | uintptr_t addend; |
bellard | d656469 | 2008-01-31 09:22:27 +0000 | [diff] [blame] | 97 | /* padding to get a power of two size */ |
Stefan Weil | 3b2992e | 2012-04-12 20:29:36 +0200 | [diff] [blame] | 98 | uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - |
| 99 | (sizeof(target_ulong) * 3 + |
| 100 | ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) + |
| 101 | sizeof(uintptr_t))]; |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 102 | } CPUTLBEntry; |
| 103 | |
Richard Henderson | e85ef53 | 2013-06-04 09:51:59 -0700 | [diff] [blame] | 104 | QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); |
Paul Brook | 355b194 | 2010-04-05 00:28:53 +0100 | [diff] [blame] | 105 | |
Paul Brook | 20cb400 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 106 | #define CPU_COMMON_TLB \ |
| 107 | /* The meaning of the MMU modes is defined in the target code. */ \ |
| 108 | CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 109 | hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 110 | target_ulong tlb_flush_addr; \ |
| 111 | target_ulong tlb_flush_mask; |
Paul Brook | 20cb400 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 112 | |
| 113 | #else |
| 114 | |
| 115 | #define CPU_COMMON_TLB |
| 116 | |
| 117 | #endif |
| 118 | |
| 119 | |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 120 | #ifdef HOST_WORDS_BIGENDIAN |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 121 | typedef struct icount_decr_u16 { |
| 122 | uint16_t high; |
| 123 | uint16_t low; |
| 124 | } icount_decr_u16; |
| 125 | #else |
| 126 | typedef struct icount_decr_u16 { |
| 127 | uint16_t low; |
| 128 | uint16_t high; |
| 129 | } icount_decr_u16; |
| 130 | #endif |
| 131 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 132 | typedef struct CPUBreakpoint { |
| 133 | target_ulong pc; |
| 134 | int flags; /* BP_* */ |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 135 | QTAILQ_ENTRY(CPUBreakpoint) entry; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 136 | } CPUBreakpoint; |
| 137 | |
| 138 | typedef struct CPUWatchpoint { |
| 139 | target_ulong vaddr; |
| 140 | target_ulong len_mask; |
| 141 | int flags; /* BP_* */ |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 142 | QTAILQ_ENTRY(CPUWatchpoint) entry; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 143 | } CPUWatchpoint; |
| 144 | |
blueswir1 | a20e31d | 2008-04-08 19:29:54 +0000 | [diff] [blame] | 145 | #define CPU_TEMP_BUF_NLONGS 128 |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 146 | #define CPU_COMMON \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 147 | /* soft mmu support */ \ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 148 | /* in order to avoid passing too many arguments to the MMIO \ |
| 149 | helpers, we store some rarely used information in the CPU \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 150 | context) */ \ |
Blue Swirl | 2050396 | 2012-04-09 14:20:20 +0000 | [diff] [blame] | 151 | uintptr_t mem_io_pc; /* host pc at which the memory was \ |
| 152 | accessed */ \ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 153 | target_ulong mem_io_vaddr; /* target virtual addr at which the \ |
| 154 | memory was accessed */ \ |
Paul Brook | 20cb400 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 155 | CPU_COMMON_TLB \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 156 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ |
blueswir1 | a20e31d | 2008-04-08 19:29:54 +0000 | [diff] [blame] | 157 | /* buffer for temporaries in the code generator */ \ |
| 158 | long temp_buf[CPU_TEMP_BUF_NLONGS]; \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 159 | \ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 160 | int64_t icount_extra; /* Instructions until next timer event. */ \ |
| 161 | /* Number of cycles left, with interrupt flag in high bit. \ |
| 162 | This allows a single read-compare-cbranch-write sequence to test \ |
| 163 | for both decrementer underflow and exceptions. */ \ |
| 164 | union { \ |
| 165 | uint32_t u32; \ |
| 166 | icount_decr_u16 u16; \ |
| 167 | } icount_decr; \ |
| 168 | uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ |
| 169 | \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 170 | /* from this point: preserved by CPU reset */ \ |
| 171 | /* ice debug support */ \ |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 172 | QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 173 | \ |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 174 | QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 175 | CPUWatchpoint *watchpoint_hit; \ |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 176 | \ |
bellard | 9133e39 | 2008-05-29 10:08:06 +0000 | [diff] [blame] | 177 | /* Core interrupt code */ \ |
Peter Maydell | 6ab7e54 | 2013-02-20 15:21:09 +0000 | [diff] [blame] | 178 | sigjmp_buf jmp_env; \ |
Anthony Liguori | acb6685 | 2009-12-18 08:16:30 -0600 | [diff] [blame] | 179 | int exception_index; \ |
bellard | 9133e39 | 2008-05-29 10:08:06 +0000 | [diff] [blame] | 180 | \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 181 | /* user data */ \ |
ths | 01ba981 | 2007-12-09 02:22:57 +0000 | [diff] [blame] | 182 | void *opaque; \ |
| 183 | \ |
Andreas Färber | f7575c96 | 2012-12-01 06:18:14 +0100 | [diff] [blame] | 184 | const char *cpu_model_str; |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 185 | |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 186 | #endif |