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bellardab93bbe2003-08-10 21:35:13 +00001/*
2 * common defines for all CPUs
ths5fafdf22007-09-16 21:08:06 +00003 *
bellardab93bbe2003-08-10 21:35:13 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellardab93bbe2003-08-10 21:35:13 +000018 */
19#ifndef CPU_DEFS_H
20#define CPU_DEFS_H
21
pbrook87ecb682007-11-17 17:14:51 +000022#ifndef NEED_CPU_H
23#error cpu.h included from common code
24#endif
25
bellardab93bbe2003-08-10 21:35:13 +000026#include "config.h"
27#include <setjmp.h>
bellarded1c0bc2004-02-16 22:17:43 +000028#include <inttypes.h>
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010029#include "qemu/osdep.h"
30#include "qemu/queue.h"
Andreas Färberce927ed2013-05-28 14:02:38 +020031#ifndef CONFIG_USER_ONLY
Paolo Bonzini022c62c2012-12-17 18:19:49 +010032#include "exec/hwaddr.h"
Andreas Färberce927ed2013-05-28 14:02:38 +020033#endif
bellardab93bbe2003-08-10 21:35:13 +000034
bellard35b66fc2004-01-24 15:26:06 +000035#ifndef TARGET_LONG_BITS
36#error TARGET_LONG_BITS must be defined before including this header
37#endif
38
39#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
40
bellardab6d9602004-04-25 21:25:15 +000041/* target_ulong is the type of a virtual address */
bellard35b66fc2004-01-24 15:26:06 +000042#if TARGET_LONG_SIZE == 4
Paolo Bonzini6cfd9b52013-04-17 16:26:41 +020043typedef int32_t target_long;
44typedef uint32_t target_ulong;
bellardc27004e2005-01-03 23:35:10 +000045#define TARGET_FMT_lx "%08x"
j_mayerb62b4612007-04-04 07:58:14 +000046#define TARGET_FMT_ld "%d"
j_mayer71c8b8f2007-09-19 05:46:03 +000047#define TARGET_FMT_lu "%u"
bellard35b66fc2004-01-24 15:26:06 +000048#elif TARGET_LONG_SIZE == 8
Paolo Bonzini6cfd9b52013-04-17 16:26:41 +020049typedef int64_t target_long;
50typedef uint64_t target_ulong;
bellard26a76462006-06-25 18:15:32 +000051#define TARGET_FMT_lx "%016" PRIx64
j_mayerb62b4612007-04-04 07:58:14 +000052#define TARGET_FMT_ld "%" PRId64
j_mayer71c8b8f2007-09-19 05:46:03 +000053#define TARGET_FMT_lu "%" PRIu64
bellard35b66fc2004-01-24 15:26:06 +000054#else
55#error TARGET_LONG_SIZE undefined
56#endif
57
bellard2be00712005-07-02 22:09:27 +000058#define EXCP_INTERRUPT 0x10000 /* async interruption */
59#define EXCP_HLT 0x10001 /* hlt instruction reached */
60#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
bellard5a1e3cf2005-11-23 21:02:53 +000061#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
bellardab93bbe2003-08-10 21:35:13 +000062
bellarda316d332005-11-20 10:32:34 +000063#define TB_JMP_CACHE_BITS 12
64#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
65
pbrookb362e5e2006-11-12 20:40:55 +000066/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
67 addresses on the same page. The top bits are the same. This allows
68 TLB invalidation to quickly clear a subset of the hash table. */
69#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
70#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
71#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
72#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
73
Paul Brook20cb4002010-03-12 16:54:58 +000074#if !defined(CONFIG_USER_ONLY)
bellard84b7b8e2005-11-28 21:19:04 +000075#define CPU_TLB_BITS 8
76#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
bellardab93bbe2003-08-10 21:35:13 +000077
Paul Brook355b1942010-04-05 00:28:53 +010078#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
bellardd6564692008-01-31 09:22:27 +000079#define CPU_TLB_ENTRY_BITS 4
80#else
81#define CPU_TLB_ENTRY_BITS 5
82#endif
83
bellardab93bbe2003-08-10 21:35:13 +000084typedef struct CPUTLBEntry {
pbrook0f459d12008-06-09 00:20:13 +000085 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
86 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
87 go directly to ram.
bellarddb8d7462003-10-27 21:12:17 +000088 bit 3 : indicates that the entry is invalid
89 bit 2..0 : zero
90 */
ths5fafdf22007-09-16 21:08:06 +000091 target_ulong addr_read;
92 target_ulong addr_write;
93 target_ulong addr_code;
Paul Brook355b1942010-04-05 00:28:53 +010094 /* Addend to virtual address to get host address. IO accesses
pbrookee50add2008-11-29 13:33:23 +000095 use the corresponding iotlb value. */
Stefan Weil3b2992e2012-04-12 20:29:36 +020096 uintptr_t addend;
bellardd6564692008-01-31 09:22:27 +000097 /* padding to get a power of two size */
Stefan Weil3b2992e2012-04-12 20:29:36 +020098 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
99 (sizeof(target_ulong) * 3 +
100 ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) +
101 sizeof(uintptr_t))];
bellardab93bbe2003-08-10 21:35:13 +0000102} CPUTLBEntry;
103
Richard Hendersone85ef532013-06-04 09:51:59 -0700104QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
Paul Brook355b1942010-04-05 00:28:53 +0100105
Paul Brook20cb4002010-03-12 16:54:58 +0000106#define CPU_COMMON_TLB \
107 /* The meaning of the MMU modes is defined in the target code. */ \
108 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
Avi Kivitya8170e52012-10-23 12:30:10 +0200109 hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
Paul Brookd4c430a2010-03-17 02:14:28 +0000110 target_ulong tlb_flush_addr; \
111 target_ulong tlb_flush_mask;
Paul Brook20cb4002010-03-12 16:54:58 +0000112
113#else
114
115#define CPU_COMMON_TLB
116
117#endif
118
119
Juan Quintelae2542fe2009-07-27 16:13:06 +0200120#ifdef HOST_WORDS_BIGENDIAN
pbrook2e70f6e2008-06-29 01:03:05 +0000121typedef struct icount_decr_u16 {
122 uint16_t high;
123 uint16_t low;
124} icount_decr_u16;
125#else
126typedef struct icount_decr_u16 {
127 uint16_t low;
128 uint16_t high;
129} icount_decr_u16;
130#endif
131
aliguoria1d1bb32008-11-18 20:07:32 +0000132typedef struct CPUBreakpoint {
133 target_ulong pc;
134 int flags; /* BP_* */
Blue Swirl72cf2d42009-09-12 07:36:22 +0000135 QTAILQ_ENTRY(CPUBreakpoint) entry;
aliguoria1d1bb32008-11-18 20:07:32 +0000136} CPUBreakpoint;
137
138typedef struct CPUWatchpoint {
139 target_ulong vaddr;
140 target_ulong len_mask;
141 int flags; /* BP_* */
Blue Swirl72cf2d42009-09-12 07:36:22 +0000142 QTAILQ_ENTRY(CPUWatchpoint) entry;
aliguoria1d1bb32008-11-18 20:07:32 +0000143} CPUWatchpoint;
144
blueswir1a20e31d2008-04-08 19:29:54 +0000145#define CPU_TEMP_BUF_NLONGS 128
bellarda316d332005-11-20 10:32:34 +0000146#define CPU_COMMON \
bellarda316d332005-11-20 10:32:34 +0000147 /* soft mmu support */ \
pbrook2e70f6e2008-06-29 01:03:05 +0000148 /* in order to avoid passing too many arguments to the MMIO \
149 helpers, we store some rarely used information in the CPU \
bellarda316d332005-11-20 10:32:34 +0000150 context) */ \
Blue Swirl20503962012-04-09 14:20:20 +0000151 uintptr_t mem_io_pc; /* host pc at which the memory was \
152 accessed */ \
pbrook2e70f6e2008-06-29 01:03:05 +0000153 target_ulong mem_io_vaddr; /* target virtual addr at which the \
154 memory was accessed */ \
Paul Brook20cb4002010-03-12 16:54:58 +0000155 CPU_COMMON_TLB \
bellarda316d332005-11-20 10:32:34 +0000156 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
blueswir1a20e31d2008-04-08 19:29:54 +0000157 /* buffer for temporaries in the code generator */ \
158 long temp_buf[CPU_TEMP_BUF_NLONGS]; \
bellarda316d332005-11-20 10:32:34 +0000159 \
pbrook2e70f6e2008-06-29 01:03:05 +0000160 int64_t icount_extra; /* Instructions until next timer event. */ \
161 /* Number of cycles left, with interrupt flag in high bit. \
162 This allows a single read-compare-cbranch-write sequence to test \
163 for both decrementer underflow and exceptions. */ \
164 union { \
165 uint32_t u32; \
166 icount_decr_u16 u16; \
167 } icount_decr; \
168 uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
169 \
bellarda316d332005-11-20 10:32:34 +0000170 /* from this point: preserved by CPU reset */ \
171 /* ice debug support */ \
Blue Swirl72cf2d42009-09-12 07:36:22 +0000172 QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
bellarda316d332005-11-20 10:32:34 +0000173 \
Blue Swirl72cf2d42009-09-12 07:36:22 +0000174 QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
aliguoria1d1bb32008-11-18 20:07:32 +0000175 CPUWatchpoint *watchpoint_hit; \
pbrook6658ffb2007-03-16 23:58:11 +0000176 \
bellard9133e392008-05-29 10:08:06 +0000177 /* Core interrupt code */ \
Peter Maydell6ab7e542013-02-20 15:21:09 +0000178 sigjmp_buf jmp_env; \
Anthony Liguoriacb66852009-12-18 08:16:30 -0600179 int exception_index; \
bellard9133e392008-05-29 10:08:06 +0000180 \
bellarda316d332005-11-20 10:32:34 +0000181 /* user data */ \
ths01ba9812007-12-09 02:22:57 +0000182 void *opaque; \
183 \
Andreas Färberf7575c962012-12-01 06:18:14 +0100184 const char *cpu_model_str;
bellarda316d332005-11-20 10:32:34 +0000185
bellardab93bbe2003-08-10 21:35:13 +0000186#endif