Jia Liu | dd29c7f | 2012-07-20 15:50:46 +0800 | [diff] [blame] | 1 | /* |
| 2 | * OpenRISC Programmable Interrupt Controller support. |
| 3 | * |
| 4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> |
| 5 | * Feng Gao <gf91597@gmail.com> |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
Peter Maydell | ed2decc | 2016-01-26 18:17:22 +0000 | [diff] [blame] | 21 | #include "qemu/osdep.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 22 | #include "hw/hw.h" |
Jia Liu | dd29c7f | 2012-07-20 15:50:46 +0800 | [diff] [blame] | 23 | #include "cpu.h" |
| 24 | |
| 25 | /* OpenRISC pic handler */ |
| 26 | static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) |
| 27 | { |
| 28 | OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; |
Andreas Färber | d8ed887 | 2013-01-17 22:30:20 +0100 | [diff] [blame] | 29 | CPUState *cs = CPU(cpu); |
Jia Liu | 7717f24 | 2013-08-21 09:31:36 +0800 | [diff] [blame] | 30 | uint32_t irq_bit; |
Jia Liu | dd29c7f | 2012-07-20 15:50:46 +0800 | [diff] [blame] | 31 | |
| 32 | if (irq > 31 || irq < 0) { |
| 33 | return; |
| 34 | } |
| 35 | |
Jia Liu | 7717f24 | 2013-08-21 09:31:36 +0800 | [diff] [blame] | 36 | irq_bit = 1U << irq; |
| 37 | |
Jia Liu | dd29c7f | 2012-07-20 15:50:46 +0800 | [diff] [blame] | 38 | if (level) { |
| 39 | cpu->env.picsr |= irq_bit; |
| 40 | } else { |
| 41 | cpu->env.picsr &= ~irq_bit; |
| 42 | } |
| 43 | |
Jia Liu | ed396e2 | 2013-08-21 09:23:10 +0800 | [diff] [blame] | 44 | if (cpu->env.picsr & cpu->env.picmr) { |
| 45 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
| 46 | } else { |
| 47 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
| 48 | cpu->env.picsr = 0; |
Jia Liu | dd29c7f | 2012-07-20 15:50:46 +0800 | [diff] [blame] | 49 | } |
| 50 | } |
| 51 | |
| 52 | void cpu_openrisc_pic_init(OpenRISCCPU *cpu) |
| 53 | { |
| 54 | int i; |
| 55 | qemu_irq *qi; |
| 56 | qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, cpu, NR_IRQS); |
| 57 | |
| 58 | for (i = 0; i < NR_IRQS; i++) { |
| 59 | cpu->env.irq[i] = qi[i]; |
| 60 | } |
| 61 | } |