blob: cf02f57a711773581298c2d8c436ecb28dc16122 [file] [log] [blame]
ths5fafdf22007-09-16 21:08:06 +00001/*
pbrook20dcee92007-06-03 11:13:39 +00002 * ColdFire Interrupt Controller emulation.
3 *
4 * Copyright (c) 2007 CodeSourcery.
5 *
Matthew Fernandez8e31bf32011-06-26 12:21:35 +10006 * This code is licensed under the GPL
pbrook20dcee92007-06-03 11:13:39 +00007 */
Markus Armbruster0b8fa322019-05-23 16:35:07 +02008
Peter Maydelld8416662016-01-26 18:17:23 +00009#include "qemu/osdep.h"
Markus Armbruster3e80f692020-06-10 07:31:58 +020010#include "qapi/error.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020011#include "qemu/module.h"
Philippe Mathieu-Daudéb8096672020-05-26 11:40:52 +020012#include "qemu/log.h"
Paolo Bonzini4771d752016-01-19 21:51:44 +010013#include "cpu.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010014#include "hw/hw.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020015#include "hw/irq.h"
Thomas Huth88b86982017-02-12 15:41:35 +010016#include "hw/sysbus.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010017#include "hw/m68k/mcf.h"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040018#include "qom/object.h"
pbrook20dcee92007-06-03 11:13:39 +000019
Thomas Huth88b86982017-02-12 15:41:35 +010020#define TYPE_MCF_INTC "mcf-intc"
Eduardo Habkost80633962020-09-16 14:25:19 -040021OBJECT_DECLARE_SIMPLE_TYPE(mcf_intc_state, MCF_INTC)
Thomas Huth88b86982017-02-12 15:41:35 +010022
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040023struct mcf_intc_state {
Thomas Huth88b86982017-02-12 15:41:35 +010024 SysBusDevice parent_obj;
25
Benoît Canet663d9442011-11-24 14:31:15 +010026 MemoryRegion iomem;
pbrook20dcee92007-06-03 11:13:39 +000027 uint64_t ipr;
28 uint64_t imr;
29 uint64_t ifr;
30 uint64_t enabled;
31 uint8_t icr[64];
Andreas Färber9a6ee9f2013-01-18 14:15:09 +010032 M68kCPU *cpu;
pbrook20dcee92007-06-03 11:13:39 +000033 int active_vector;
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040034};
pbrook20dcee92007-06-03 11:13:39 +000035
36static void mcf_intc_update(mcf_intc_state *s)
37{
38 uint64_t active;
39 int i;
40 int best;
41 int best_level;
42
43 active = (s->ipr | s->ifr) & s->enabled & ~s->imr;
44 best_level = 0;
45 best = 64;
46 if (active) {
47 for (i = 0; i < 64; i++) {
48 if ((active & 1) != 0 && s->icr[i] >= best_level) {
49 best_level = s->icr[i];
50 best = i;
51 }
52 active >>= 1;
53 }
54 }
55 s->active_vector = ((best == 64) ? 24 : (best + 64));
Andreas Färbercb3fb382013-01-18 14:20:52 +010056 m68k_set_irq_level(s->cpu, best_level, s->active_vector);
pbrook20dcee92007-06-03 11:13:39 +000057}
58
Avi Kivitya8170e52012-10-23 12:30:10 +020059static uint64_t mcf_intc_read(void *opaque, hwaddr addr,
Benoît Canet663d9442011-11-24 14:31:15 +010060 unsigned size)
pbrook20dcee92007-06-03 11:13:39 +000061{
62 int offset;
63 mcf_intc_state *s = (mcf_intc_state *)opaque;
64 offset = addr & 0xff;
65 if (offset >= 0x40 && offset < 0x80) {
66 return s->icr[offset - 0x40];
67 }
68 switch (offset) {
69 case 0x00:
70 return (uint32_t)(s->ipr >> 32);
71 case 0x04:
72 return (uint32_t)s->ipr;
73 case 0x08:
74 return (uint32_t)(s->imr >> 32);
75 case 0x0c:
76 return (uint32_t)s->imr;
77 case 0x10:
78 return (uint32_t)(s->ifr >> 32);
79 case 0x14:
80 return (uint32_t)s->ifr;
81 case 0xe0: /* SWIACK. */
82 return s->active_vector;
83 case 0xe1: case 0xe2: case 0xe3: case 0xe4:
84 case 0xe5: case 0xe6: case 0xe7:
85 /* LnIACK */
Philippe Mathieu-Daudéb8096672020-05-26 11:40:52 +020086 qemu_log_mask(LOG_UNIMP, "%s: LnIACK not implemented (offset 0x%02x)\n",
87 __func__, offset);
88 /* fallthru */
pbrook20dcee92007-06-03 11:13:39 +000089 default:
90 return 0;
91 }
92}
93
Avi Kivitya8170e52012-10-23 12:30:10 +020094static void mcf_intc_write(void *opaque, hwaddr addr,
Benoît Canet663d9442011-11-24 14:31:15 +010095 uint64_t val, unsigned size)
pbrook20dcee92007-06-03 11:13:39 +000096{
97 int offset;
98 mcf_intc_state *s = (mcf_intc_state *)opaque;
99 offset = addr & 0xff;
100 if (offset >= 0x40 && offset < 0x80) {
101 int n = offset - 0x40;
102 s->icr[n] = val;
103 if (val == 0)
104 s->enabled &= ~(1ull << n);
105 else
106 s->enabled |= (1ull << n);
107 mcf_intc_update(s);
108 return;
109 }
110 switch (offset) {
111 case 0x00: case 0x04:
112 /* Ignore IPR writes. */
113 return;
114 case 0x08:
115 s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32);
116 break;
117 case 0x0c:
118 s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
119 break;
Greg Ungerer8c52f0c2015-06-19 23:43:24 +1000120 case 0x1c:
121 if (val & 0x40) {
122 s->imr = ~0ull;
123 } else {
124 s->imr |= (0x1ull << (val & 0x3f));
125 }
126 break;
127 case 0x1d:
128 if (val & 0x40) {
129 s->imr = 0ull;
130 } else {
131 s->imr &= ~(0x1ull << (val & 0x3f));
132 }
133 break;
pbrook20dcee92007-06-03 11:13:39 +0000134 default:
Philippe Mathieu-Daudéb8096672020-05-26 11:40:52 +0200135 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n",
136 __func__, offset);
137 return;
pbrook20dcee92007-06-03 11:13:39 +0000138 }
139 mcf_intc_update(s);
140}
141
142static void mcf_intc_set_irq(void *opaque, int irq, int level)
143{
144 mcf_intc_state *s = (mcf_intc_state *)opaque;
145 if (irq >= 64)
146 return;
147 if (level)
148 s->ipr |= 1ull << irq;
149 else
150 s->ipr &= ~(1ull << irq);
151 mcf_intc_update(s);
152}
153
Thomas Huth88b86982017-02-12 15:41:35 +0100154static void mcf_intc_reset(DeviceState *dev)
pbrook20dcee92007-06-03 11:13:39 +0000155{
Thomas Huth88b86982017-02-12 15:41:35 +0100156 mcf_intc_state *s = MCF_INTC(dev);
157
pbrook20dcee92007-06-03 11:13:39 +0000158 s->imr = ~0ull;
159 s->ipr = 0;
160 s->ifr = 0;
161 s->enabled = 0;
162 memset(s->icr, 0, 64);
163 s->active_vector = 24;
164}
165
Benoît Canet663d9442011-11-24 14:31:15 +0100166static const MemoryRegionOps mcf_intc_ops = {
167 .read = mcf_intc_read,
168 .write = mcf_intc_write,
169 .endianness = DEVICE_NATIVE_ENDIAN,
pbrook20dcee92007-06-03 11:13:39 +0000170};
171
Thomas Huth88b86982017-02-12 15:41:35 +0100172static void mcf_intc_instance_init(Object *obj)
173{
174 mcf_intc_state *s = MCF_INTC(obj);
175
176 memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf", 0x100);
177}
178
179static void mcf_intc_class_init(ObjectClass *oc, void *data)
180{
181 DeviceClass *dc = DEVICE_CLASS(oc);
182
183 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
184 dc->reset = mcf_intc_reset;
185}
186
187static const TypeInfo mcf_intc_gate_info = {
188 .name = TYPE_MCF_INTC,
189 .parent = TYPE_SYS_BUS_DEVICE,
190 .instance_size = sizeof(mcf_intc_state),
191 .instance_init = mcf_intc_instance_init,
192 .class_init = mcf_intc_class_init,
193};
194
195static void mcf_intc_register_types(void)
196{
197 type_register_static(&mcf_intc_gate_info);
198}
199
200type_init(mcf_intc_register_types)
201
Benoît Canet663d9442011-11-24 14:31:15 +0100202qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
Avi Kivitya8170e52012-10-23 12:30:10 +0200203 hwaddr base,
Andreas Färber9a6ee9f2013-01-18 14:15:09 +0100204 M68kCPU *cpu)
pbrook20dcee92007-06-03 11:13:39 +0000205{
Thomas Huth88b86982017-02-12 15:41:35 +0100206 DeviceState *dev;
pbrook20dcee92007-06-03 11:13:39 +0000207 mcf_intc_state *s;
pbrook20dcee92007-06-03 11:13:39 +0000208
Markus Armbruster3e80f692020-06-10 07:31:58 +0200209 dev = qdev_new(TYPE_MCF_INTC);
Markus Armbruster3c6ef472020-06-10 07:32:34 +0200210 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
pbrook20dcee92007-06-03 11:13:39 +0000211
Thomas Huth88b86982017-02-12 15:41:35 +0100212 s = MCF_INTC(dev);
213 s->cpu = cpu;
214
Benoît Canet663d9442011-11-24 14:31:15 +0100215 memory_region_add_subregion(sysmem, base, &s->iomem);
pbrook20dcee92007-06-03 11:13:39 +0000216
217 return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
218}