ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1 | /* |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 2 | * ColdFire Interrupt Controller emulation. |
| 3 | * |
| 4 | * Copyright (c) 2007 CodeSourcery. |
| 5 | * |
Matthew Fernandez | 8e31bf3 | 2011-06-26 12:21:35 +1000 | [diff] [blame] | 6 | * This code is licensed under the GPL |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 7 | */ |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 8 | |
Peter Maydell | d841666 | 2016-01-26 18:17:23 +0000 | [diff] [blame] | 9 | #include "qemu/osdep.h" |
Markus Armbruster | 3e80f69 | 2020-06-10 07:31:58 +0200 | [diff] [blame] | 10 | #include "qapi/error.h" |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 11 | #include "qemu/module.h" |
Philippe Mathieu-Daudé | b809667 | 2020-05-26 11:40:52 +0200 | [diff] [blame] | 12 | #include "qemu/log.h" |
Paolo Bonzini | 4771d75 | 2016-01-19 21:51:44 +0100 | [diff] [blame] | 13 | #include "cpu.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 14 | #include "hw/hw.h" |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 15 | #include "hw/irq.h" |
Thomas Huth | 88b8698 | 2017-02-12 15:41:35 +0100 | [diff] [blame] | 16 | #include "hw/sysbus.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 17 | #include "hw/m68k/mcf.h" |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 18 | #include "qom/object.h" |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 19 | |
Thomas Huth | 88b8698 | 2017-02-12 15:41:35 +0100 | [diff] [blame] | 20 | #define TYPE_MCF_INTC "mcf-intc" |
Eduardo Habkost | 8063396 | 2020-09-16 14:25:19 -0400 | [diff] [blame] | 21 | OBJECT_DECLARE_SIMPLE_TYPE(mcf_intc_state, MCF_INTC) |
Thomas Huth | 88b8698 | 2017-02-12 15:41:35 +0100 | [diff] [blame] | 22 | |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 23 | struct mcf_intc_state { |
Thomas Huth | 88b8698 | 2017-02-12 15:41:35 +0100 | [diff] [blame] | 24 | SysBusDevice parent_obj; |
| 25 | |
Benoît Canet | 663d944 | 2011-11-24 14:31:15 +0100 | [diff] [blame] | 26 | MemoryRegion iomem; |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 27 | uint64_t ipr; |
| 28 | uint64_t imr; |
| 29 | uint64_t ifr; |
| 30 | uint64_t enabled; |
| 31 | uint8_t icr[64]; |
Andreas Färber | 9a6ee9f | 2013-01-18 14:15:09 +0100 | [diff] [blame] | 32 | M68kCPU *cpu; |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 33 | int active_vector; |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 34 | }; |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 35 | |
| 36 | static void mcf_intc_update(mcf_intc_state *s) |
| 37 | { |
| 38 | uint64_t active; |
| 39 | int i; |
| 40 | int best; |
| 41 | int best_level; |
| 42 | |
| 43 | active = (s->ipr | s->ifr) & s->enabled & ~s->imr; |
| 44 | best_level = 0; |
| 45 | best = 64; |
| 46 | if (active) { |
| 47 | for (i = 0; i < 64; i++) { |
| 48 | if ((active & 1) != 0 && s->icr[i] >= best_level) { |
| 49 | best_level = s->icr[i]; |
| 50 | best = i; |
| 51 | } |
| 52 | active >>= 1; |
| 53 | } |
| 54 | } |
| 55 | s->active_vector = ((best == 64) ? 24 : (best + 64)); |
Andreas Färber | cb3fb38 | 2013-01-18 14:20:52 +0100 | [diff] [blame] | 56 | m68k_set_irq_level(s->cpu, best_level, s->active_vector); |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 57 | } |
| 58 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 59 | static uint64_t mcf_intc_read(void *opaque, hwaddr addr, |
Benoît Canet | 663d944 | 2011-11-24 14:31:15 +0100 | [diff] [blame] | 60 | unsigned size) |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 61 | { |
| 62 | int offset; |
| 63 | mcf_intc_state *s = (mcf_intc_state *)opaque; |
| 64 | offset = addr & 0xff; |
| 65 | if (offset >= 0x40 && offset < 0x80) { |
| 66 | return s->icr[offset - 0x40]; |
| 67 | } |
| 68 | switch (offset) { |
| 69 | case 0x00: |
| 70 | return (uint32_t)(s->ipr >> 32); |
| 71 | case 0x04: |
| 72 | return (uint32_t)s->ipr; |
| 73 | case 0x08: |
| 74 | return (uint32_t)(s->imr >> 32); |
| 75 | case 0x0c: |
| 76 | return (uint32_t)s->imr; |
| 77 | case 0x10: |
| 78 | return (uint32_t)(s->ifr >> 32); |
| 79 | case 0x14: |
| 80 | return (uint32_t)s->ifr; |
| 81 | case 0xe0: /* SWIACK. */ |
| 82 | return s->active_vector; |
| 83 | case 0xe1: case 0xe2: case 0xe3: case 0xe4: |
| 84 | case 0xe5: case 0xe6: case 0xe7: |
| 85 | /* LnIACK */ |
Philippe Mathieu-Daudé | b809667 | 2020-05-26 11:40:52 +0200 | [diff] [blame] | 86 | qemu_log_mask(LOG_UNIMP, "%s: LnIACK not implemented (offset 0x%02x)\n", |
| 87 | __func__, offset); |
| 88 | /* fallthru */ |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 89 | default: |
| 90 | return 0; |
| 91 | } |
| 92 | } |
| 93 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 94 | static void mcf_intc_write(void *opaque, hwaddr addr, |
Benoît Canet | 663d944 | 2011-11-24 14:31:15 +0100 | [diff] [blame] | 95 | uint64_t val, unsigned size) |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 96 | { |
| 97 | int offset; |
| 98 | mcf_intc_state *s = (mcf_intc_state *)opaque; |
| 99 | offset = addr & 0xff; |
| 100 | if (offset >= 0x40 && offset < 0x80) { |
| 101 | int n = offset - 0x40; |
| 102 | s->icr[n] = val; |
| 103 | if (val == 0) |
| 104 | s->enabled &= ~(1ull << n); |
| 105 | else |
| 106 | s->enabled |= (1ull << n); |
| 107 | mcf_intc_update(s); |
| 108 | return; |
| 109 | } |
| 110 | switch (offset) { |
| 111 | case 0x00: case 0x04: |
| 112 | /* Ignore IPR writes. */ |
| 113 | return; |
| 114 | case 0x08: |
| 115 | s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32); |
| 116 | break; |
| 117 | case 0x0c: |
| 118 | s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val; |
| 119 | break; |
Greg Ungerer | 8c52f0c | 2015-06-19 23:43:24 +1000 | [diff] [blame] | 120 | case 0x1c: |
| 121 | if (val & 0x40) { |
| 122 | s->imr = ~0ull; |
| 123 | } else { |
| 124 | s->imr |= (0x1ull << (val & 0x3f)); |
| 125 | } |
| 126 | break; |
| 127 | case 0x1d: |
| 128 | if (val & 0x40) { |
| 129 | s->imr = 0ull; |
| 130 | } else { |
| 131 | s->imr &= ~(0x1ull << (val & 0x3f)); |
| 132 | } |
| 133 | break; |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 134 | default: |
Philippe Mathieu-Daudé | b809667 | 2020-05-26 11:40:52 +0200 | [diff] [blame] | 135 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", |
| 136 | __func__, offset); |
| 137 | return; |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 138 | } |
| 139 | mcf_intc_update(s); |
| 140 | } |
| 141 | |
| 142 | static void mcf_intc_set_irq(void *opaque, int irq, int level) |
| 143 | { |
| 144 | mcf_intc_state *s = (mcf_intc_state *)opaque; |
| 145 | if (irq >= 64) |
| 146 | return; |
| 147 | if (level) |
| 148 | s->ipr |= 1ull << irq; |
| 149 | else |
| 150 | s->ipr &= ~(1ull << irq); |
| 151 | mcf_intc_update(s); |
| 152 | } |
| 153 | |
Thomas Huth | 88b8698 | 2017-02-12 15:41:35 +0100 | [diff] [blame] | 154 | static void mcf_intc_reset(DeviceState *dev) |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 155 | { |
Thomas Huth | 88b8698 | 2017-02-12 15:41:35 +0100 | [diff] [blame] | 156 | mcf_intc_state *s = MCF_INTC(dev); |
| 157 | |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 158 | s->imr = ~0ull; |
| 159 | s->ipr = 0; |
| 160 | s->ifr = 0; |
| 161 | s->enabled = 0; |
| 162 | memset(s->icr, 0, 64); |
| 163 | s->active_vector = 24; |
| 164 | } |
| 165 | |
Benoît Canet | 663d944 | 2011-11-24 14:31:15 +0100 | [diff] [blame] | 166 | static const MemoryRegionOps mcf_intc_ops = { |
| 167 | .read = mcf_intc_read, |
| 168 | .write = mcf_intc_write, |
| 169 | .endianness = DEVICE_NATIVE_ENDIAN, |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 170 | }; |
| 171 | |
Thomas Huth | 88b8698 | 2017-02-12 15:41:35 +0100 | [diff] [blame] | 172 | static void mcf_intc_instance_init(Object *obj) |
| 173 | { |
| 174 | mcf_intc_state *s = MCF_INTC(obj); |
| 175 | |
| 176 | memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf", 0x100); |
| 177 | } |
| 178 | |
| 179 | static void mcf_intc_class_init(ObjectClass *oc, void *data) |
| 180 | { |
| 181 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 182 | |
| 183 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
| 184 | dc->reset = mcf_intc_reset; |
| 185 | } |
| 186 | |
| 187 | static const TypeInfo mcf_intc_gate_info = { |
| 188 | .name = TYPE_MCF_INTC, |
| 189 | .parent = TYPE_SYS_BUS_DEVICE, |
| 190 | .instance_size = sizeof(mcf_intc_state), |
| 191 | .instance_init = mcf_intc_instance_init, |
| 192 | .class_init = mcf_intc_class_init, |
| 193 | }; |
| 194 | |
| 195 | static void mcf_intc_register_types(void) |
| 196 | { |
| 197 | type_register_static(&mcf_intc_gate_info); |
| 198 | } |
| 199 | |
| 200 | type_init(mcf_intc_register_types) |
| 201 | |
Benoît Canet | 663d944 | 2011-11-24 14:31:15 +0100 | [diff] [blame] | 202 | qemu_irq *mcf_intc_init(MemoryRegion *sysmem, |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 203 | hwaddr base, |
Andreas Färber | 9a6ee9f | 2013-01-18 14:15:09 +0100 | [diff] [blame] | 204 | M68kCPU *cpu) |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 205 | { |
Thomas Huth | 88b8698 | 2017-02-12 15:41:35 +0100 | [diff] [blame] | 206 | DeviceState *dev; |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 207 | mcf_intc_state *s; |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 208 | |
Markus Armbruster | 3e80f69 | 2020-06-10 07:31:58 +0200 | [diff] [blame] | 209 | dev = qdev_new(TYPE_MCF_INTC); |
Markus Armbruster | 3c6ef47 | 2020-06-10 07:32:34 +0200 | [diff] [blame] | 210 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 211 | |
Thomas Huth | 88b8698 | 2017-02-12 15:41:35 +0100 | [diff] [blame] | 212 | s = MCF_INTC(dev); |
| 213 | s->cpu = cpu; |
| 214 | |
Benoît Canet | 663d944 | 2011-11-24 14:31:15 +0100 | [diff] [blame] | 215 | memory_region_add_subregion(sysmem, base, &s->iomem); |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 216 | |
| 217 | return qemu_allocate_irqs(mcf_intc_set_irq, s, 64); |
| 218 | } |