blob: 5cf64505fe83eba06453666e5e2f4293e791d7a1 [file] [log] [blame]
Hervé Poussineau1ae41f42012-04-14 22:48:35 +02001/*
2 * QEMU National Semiconductor PC87312 (Super I/O)
3 *
4 * Copyright (c) 2010-2012 Herve Poussineau
5 * Copyright (c) 2011-2012 Andreas Färber
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
Peter Maydell0d755902016-01-26 18:16:58 +000026#include "qemu/osdep.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010027#include "hw/isa/pc87312.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +010028#include "qapi/error.h"
Paolo Bonzinib4a42f82013-02-04 11:37:52 +010029#include "qemu/error-report.h"
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020030#include "trace.h"
31
32
33#define REG_FER 0
34#define REG_FAR 1
35#define REG_PTR 2
36
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020037#define FER_PARALLEL_EN 0x01
38#define FER_UART1_EN 0x02
39#define FER_UART2_EN 0x04
40#define FER_FDC_EN 0x08
41#define FER_FDC_4 0x10
42#define FER_FDC_ADDR 0x20
43#define FER_IDE_EN 0x40
44#define FER_IDE_ADDR 0x80
45
46#define FAR_PARALLEL_ADDR 0x03
47#define FAR_UART1_ADDR 0x0C
48#define FAR_UART2_ADDR 0x30
49#define FAR_UART_3_4 0xC0
50
51#define PTR_POWER_DOWN 0x01
52#define PTR_CLOCK_DOWN 0x02
53#define PTR_PWDN 0x04
54#define PTR_IRQ_5_7 0x08
55#define PTR_UART1_TEST 0x10
56#define PTR_UART2_TEST 0x20
57#define PTR_LOCK_CONF 0x40
58#define PTR_EPP_MODE 0x80
59
60
61/* Parallel port */
62
Philippe Mathieu-Daudé4c3119a2018-03-08 23:39:31 +010063static bool is_parallel_enabled(ISASuperIODevice *sio, uint8_t index)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020064{
Philippe Mathieu-Daudé4c3119a2018-03-08 23:39:31 +010065 PC87312State *s = PC87312(sio);
66 return index ? false : s->regs[REG_FER] & FER_PARALLEL_EN;
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020067}
68
Philippe Mathieu-Daudé4e001052018-03-08 23:39:27 +010069static const uint16_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 };
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020070
Philippe Mathieu-Daudé4c3119a2018-03-08 23:39:31 +010071static uint16_t get_parallel_iobase(ISASuperIODevice *sio, uint8_t index)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020072{
Philippe Mathieu-Daudé4c3119a2018-03-08 23:39:31 +010073 PC87312State *s = PC87312(sio);
Blue Swirl08bb4a72013-01-13 08:12:45 +000074 return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR];
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020075}
76
Philippe Mathieu-Daudé818c9d92018-03-08 23:39:28 +010077static const unsigned int parallel_irq[] = { 5, 7, 5, 0 };
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020078
Philippe Mathieu-Daudé4c3119a2018-03-08 23:39:31 +010079static unsigned int get_parallel_irq(ISASuperIODevice *sio, uint8_t index)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020080{
Philippe Mathieu-Daudé4c3119a2018-03-08 23:39:31 +010081 PC87312State *s = PC87312(sio);
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020082 int idx;
Blue Swirl08bb4a72013-01-13 08:12:45 +000083 idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR);
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020084 if (idx == 0) {
Blue Swirl08bb4a72013-01-13 08:12:45 +000085 return (s->regs[REG_PTR] & PTR_IRQ_5_7) ? 7 : 5;
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020086 } else {
87 return parallel_irq[idx];
88 }
89}
90
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020091
92/* UARTs */
93
Philippe Mathieu-Daudé4e001052018-03-08 23:39:27 +010094static const uint16_t uart_base[2][4] = {
Hervé Poussineau1ae41f42012-04-14 22:48:35 +020095 { 0x3e8, 0x338, 0x2e8, 0x220 },
96 { 0x2e8, 0x238, 0x2e0, 0x228 }
97};
98
Philippe Mathieu-Daudécd9526a2018-03-08 23:39:32 +010099static uint16_t get_uart_iobase(ISASuperIODevice *sio, uint8_t i)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200100{
Philippe Mathieu-Daudécd9526a2018-03-08 23:39:32 +0100101 PC87312State *s = PC87312(sio);
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200102 int idx;
Blue Swirl08bb4a72013-01-13 08:12:45 +0000103 idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200104 if (idx == 0) {
105 return 0x3f8;
106 } else if (idx == 1) {
107 return 0x2f8;
108 } else {
Blue Swirl08bb4a72013-01-13 08:12:45 +0000109 return uart_base[idx & 1][(s->regs[REG_FAR] & FAR_UART_3_4) >> 6];
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200110 }
111}
112
Philippe Mathieu-Daudécd9526a2018-03-08 23:39:32 +0100113static unsigned int get_uart_irq(ISASuperIODevice *sio, uint8_t i)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200114{
Philippe Mathieu-Daudécd9526a2018-03-08 23:39:32 +0100115 PC87312State *s = PC87312(sio);
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200116 int idx;
Blue Swirl08bb4a72013-01-13 08:12:45 +0000117 idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200118 return (idx & 1) ? 3 : 4;
119}
120
Philippe Mathieu-Daudécd9526a2018-03-08 23:39:32 +0100121static bool is_uart_enabled(ISASuperIODevice *sio, uint8_t i)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200122{
Philippe Mathieu-Daudécd9526a2018-03-08 23:39:32 +0100123 PC87312State *s = PC87312(sio);
Blue Swirl08bb4a72013-01-13 08:12:45 +0000124 return s->regs[REG_FER] & (FER_UART1_EN << i);
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200125}
126
127
128/* Floppy controller */
129
Philippe Mathieu-Daudé6f6695b2018-03-08 23:39:33 +0100130static bool is_fdc_enabled(ISASuperIODevice *sio, uint8_t index)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200131{
Philippe Mathieu-Daudé6f6695b2018-03-08 23:39:33 +0100132 PC87312State *s = PC87312(sio);
133 assert(!index);
Blue Swirl08bb4a72013-01-13 08:12:45 +0000134 return s->regs[REG_FER] & FER_FDC_EN;
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200135}
136
Philippe Mathieu-Daudé6f6695b2018-03-08 23:39:33 +0100137static uint16_t get_fdc_iobase(ISASuperIODevice *sio, uint8_t index)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200138{
Philippe Mathieu-Daudé6f6695b2018-03-08 23:39:33 +0100139 PC87312State *s = PC87312(sio);
140 assert(!index);
Blue Swirl08bb4a72013-01-13 08:12:45 +0000141 return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0;
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200142}
143
Philippe Mathieu-Daudé6f6695b2018-03-08 23:39:33 +0100144static unsigned int get_fdc_irq(ISASuperIODevice *sio, uint8_t index)
145{
146 assert(!index);
147 return 6;
148}
149
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200150
151/* IDE controller */
152
Philippe Mathieu-Daudéc16a4e12018-03-08 23:39:35 +0100153static bool is_ide_enabled(ISASuperIODevice *sio, uint8_t index)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200154{
Philippe Mathieu-Daudéc16a4e12018-03-08 23:39:35 +0100155 PC87312State *s = PC87312(sio);
156
Blue Swirl08bb4a72013-01-13 08:12:45 +0000157 return s->regs[REG_FER] & FER_IDE_EN;
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200158}
159
Philippe Mathieu-Daudéc16a4e12018-03-08 23:39:35 +0100160static uint16_t get_ide_iobase(ISASuperIODevice *sio, uint8_t index)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200161{
Philippe Mathieu-Daudéc16a4e12018-03-08 23:39:35 +0100162 PC87312State *s = PC87312(sio);
163
164 if (index == 1) {
165 return get_ide_iobase(sio, 0) + 0x206;
166 }
Blue Swirl08bb4a72013-01-13 08:12:45 +0000167 return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0;
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200168}
169
Philippe Mathieu-Daudéc16a4e12018-03-08 23:39:35 +0100170static unsigned int get_ide_irq(ISASuperIODevice *sio, uint8_t index)
171{
172 assert(index == 0);
173 return 14;
174}
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200175
176static void reconfigure_devices(PC87312State *s)
177{
178 error_report("pc87312: unsupported device reconfiguration (%02x %02x %02x)",
Blue Swirl08bb4a72013-01-13 08:12:45 +0000179 s->regs[REG_FER], s->regs[REG_FAR], s->regs[REG_PTR]);
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200180}
181
182static void pc87312_soft_reset(PC87312State *s)
183{
184 static const uint8_t fer_init[] = {
185 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b,
186 0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f,
187 0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07,
188 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00,
189 };
190 static const uint8_t far_init[] = {
191 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01,
192 0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24,
193 0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24,
194 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10,
195 };
196 static const uint8_t ptr_init[] = {
197 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
199 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
200 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
201 };
202
203 s->read_id_step = 0;
204 s->selected_index = REG_FER;
205
Blue Swirl08bb4a72013-01-13 08:12:45 +0000206 s->regs[REG_FER] = fer_init[s->config & 0x1f];
207 s->regs[REG_FAR] = far_init[s->config & 0x1f];
208 s->regs[REG_PTR] = ptr_init[s->config & 0x1f];
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200209}
210
211static void pc87312_hard_reset(PC87312State *s)
212{
213 pc87312_soft_reset(s);
214}
215
Andreas Färber328c24a2013-01-11 21:11:20 +0100216static void pc87312_io_write(void *opaque, hwaddr addr, uint64_t val,
217 unsigned int size)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200218{
219 PC87312State *s = opaque;
220
221 trace_pc87312_io_write(addr, val);
222
223 if ((addr & 1) == 0) {
224 /* Index register */
225 s->read_id_step = 2;
226 s->selected_index = val;
227 } else {
228 /* Data register */
229 if (s->selected_index < 3) {
230 s->regs[s->selected_index] = val;
231 reconfigure_devices(s);
232 }
233 }
234}
235
Andreas Färber328c24a2013-01-11 21:11:20 +0100236static uint64_t pc87312_io_read(void *opaque, hwaddr addr, unsigned int size)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200237{
238 PC87312State *s = opaque;
239 uint32_t val;
240
241 if ((addr & 1) == 0) {
242 /* Index register */
243 if (s->read_id_step++ == 0) {
244 val = 0x88;
245 } else if (s->read_id_step++ == 1) {
246 val = 0;
247 } else {
248 val = s->selected_index;
249 }
250 } else {
251 /* Data register */
252 if (s->selected_index < 3) {
253 val = s->regs[s->selected_index];
254 } else {
255 /* Invalid selected index */
256 val = 0;
257 }
258 }
259
260 trace_pc87312_io_read(addr, val);
261 return val;
262}
263
Andreas Färber328c24a2013-01-11 21:11:20 +0100264static const MemoryRegionOps pc87312_io_ops = {
265 .read = pc87312_io_read,
266 .write = pc87312_io_write,
267 .endianness = DEVICE_LITTLE_ENDIAN,
268 .valid = {
269 .min_access_size = 1,
270 .max_access_size = 1,
271 },
272};
273
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200274static int pc87312_post_load(void *opaque, int version_id)
275{
276 PC87312State *s = opaque;
277
278 reconfigure_devices(s);
279 return 0;
280}
281
282static void pc87312_reset(DeviceState *d)
283{
284 PC87312State *s = PC87312(d);
285
286 pc87312_soft_reset(s);
287}
288
Andreas Färberdb895a12012-11-25 02:37:14 +0100289static void pc87312_realize(DeviceState *dev, Error **errp)
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200290{
291 PC87312State *s;
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200292 ISADevice *isa;
Philippe Mathieu-Daudé63f01a72018-03-08 23:39:30 +0100293 Error *local_err = NULL;
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200294
295 s = PC87312(dev);
Andreas Färberdb895a12012-11-25 02:37:14 +0100296 isa = ISA_DEVICE(dev);
Andreas Färberdb895a12012-11-25 02:37:14 +0100297 isa_register_ioport(isa, &s->io, s->iobase);
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200298 pc87312_hard_reset(s);
299
Philippe Mathieu-Daudé63f01a72018-03-08 23:39:30 +0100300 ISA_SUPERIO_GET_CLASS(dev)->parent_realize(dev, &local_err);
301 if (local_err) {
302 error_propagate(errp, local_err);
303 return;
304 }
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200305}
306
Andreas Färber328c24a2013-01-11 21:11:20 +0100307static void pc87312_initfn(Object *obj)
308{
309 PC87312State *s = PC87312(obj);
310
Paolo Bonzini1437c942013-06-06 21:25:08 -0400311 memory_region_init_io(&s->io, obj, &pc87312_io_ops, s, "pc87312", 2);
Andreas Färber328c24a2013-01-11 21:11:20 +0100312}
313
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200314static const VMStateDescription vmstate_pc87312 = {
315 .name = "pc87312",
316 .version_id = 1,
317 .minimum_version_id = 1,
318 .post_load = pc87312_post_load,
319 .fields = (VMStateField[]) {
320 VMSTATE_UINT8(read_id_step, PC87312State),
321 VMSTATE_UINT8(selected_index, PC87312State),
322 VMSTATE_UINT8_ARRAY(regs, PC87312State, 3),
323 VMSTATE_END_OF_LIST()
324 }
325};
326
327static Property pc87312_properties[] = {
Philippe Mathieu-Daudé4e001052018-03-08 23:39:27 +0100328 DEFINE_PROP_UINT16("iobase", PC87312State, iobase, 0x398),
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200329 DEFINE_PROP_UINT8("config", PC87312State, config, 1),
330 DEFINE_PROP_END_OF_LIST()
331};
332
333static void pc87312_class_init(ObjectClass *klass, void *data)
334{
335 DeviceClass *dc = DEVICE_CLASS(klass);
Philippe Mathieu-Daudé63f01a72018-03-08 23:39:30 +0100336 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200337
Philippe Mathieu-Daudé63f01a72018-03-08 23:39:30 +0100338 sc->parent_realize = dc->realize;
Andreas Färberdb895a12012-11-25 02:37:14 +0100339 dc->realize = pc87312_realize;
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200340 dc->reset = pc87312_reset;
341 dc->vmsd = &vmstate_pc87312;
342 dc->props = pc87312_properties;
Philippe Mathieu-Daudé4c3119a2018-03-08 23:39:31 +0100343
344 sc->parallel = (ISASuperIOFuncs){
345 .count = 1,
346 .is_enabled = is_parallel_enabled,
347 .get_iobase = get_parallel_iobase,
348 .get_irq = get_parallel_irq,
349 };
Philippe Mathieu-Daudécd9526a2018-03-08 23:39:32 +0100350 sc->serial = (ISASuperIOFuncs){
351 .count = 2,
352 .is_enabled = is_uart_enabled,
353 .get_iobase = get_uart_iobase,
354 .get_irq = get_uart_irq,
355 };
Philippe Mathieu-Daudé6f6695b2018-03-08 23:39:33 +0100356 sc->floppy = (ISASuperIOFuncs){
357 .count = 1,
358 .is_enabled = is_fdc_enabled,
359 .get_iobase = get_fdc_iobase,
360 .get_irq = get_fdc_irq,
361 };
Philippe Mathieu-Daudéc16a4e12018-03-08 23:39:35 +0100362 sc->ide = (ISASuperIOFuncs){
363 .count = 1,
364 .is_enabled = is_ide_enabled,
365 .get_iobase = get_ide_iobase,
366 .get_irq = get_ide_irq,
367 };
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200368}
369
370static const TypeInfo pc87312_type_info = {
Philippe Mathieu-Daudé010d2dc2018-03-08 23:39:26 +0100371 .name = TYPE_PC87312_SUPERIO,
Philippe Mathieu-Daudé63f01a72018-03-08 23:39:30 +0100372 .parent = TYPE_ISA_SUPERIO,
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200373 .instance_size = sizeof(PC87312State),
Andreas Färber328c24a2013-01-11 21:11:20 +0100374 .instance_init = pc87312_initfn,
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200375 .class_init = pc87312_class_init,
Philippe Mathieu-Daudé6f6695b2018-03-08 23:39:33 +0100376 /* FIXME use a qdev drive property instead of drive_get() */
Hervé Poussineau1ae41f42012-04-14 22:48:35 +0200377};
378
379static void pc87312_register_types(void)
380{
381 type_register_static(&pc87312_type_info);
382}
383
384type_init(pc87312_register_types)