blob: 5969eb86b31b6aad20e629338148d507a56ed3fb [file] [log] [blame]
bellardbb36d472005-11-05 14:22:28 +00001/*
2 * USB UHCI controller emulation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellardbb36d472005-11-05 14:22:28 +00004 * Copyright (c) 2005 Fabrice Bellard
ths5fafdf22007-09-16 21:08:06 +00005 *
aliguori54f254f2008-08-21 19:30:31 +00006 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
9 *
bellardbb36d472005-11-05 14:22:28 +000010 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * THE SOFTWARE.
27 */
Markus Armbruster0b8fa322019-05-23 16:35:07 +020028
Peter Maydelle532b2e2016-01-26 18:17:12 +000029#include "qemu/osdep.h"
Gerd Hoffmannf1ae32a2012-03-07 14:55:18 +010030#include "hw/usb.h"
Gerd Hoffmann9a1d1112014-05-08 10:58:44 +020031#include "hw/usb/uhci-regs.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020032#include "migration/vmstate.h"
Michael S. Tsirkina2cb15b2012-12-12 14:24:50 +020033#include "hw/pci/pci.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020034#include "hw/qdev-properties.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +010035#include "qapi/error.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010036#include "qemu/timer.h"
37#include "qemu/iov.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010038#include "sysemu/dma.h"
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +010039#include "trace.h"
Alex Bligh6a1751b2013-08-21 16:02:47 +010040#include "qemu/main-loop.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020041#include "qemu/module.h"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040042#include "qom/object.h"
bellardbb36d472005-11-05 14:22:28 +000043
bellardbb36d472005-11-05 14:22:28 +000044#define FRAME_TIMER_FREQ 1000
45
Gerd Hoffmann3200d102012-01-26 13:57:40 +010046#define FRAME_MAX_LOOPS 256
bellardbb36d472005-11-05 14:22:28 +000047
Hans de Goede475443c2012-12-14 14:35:35 +010048/* Must be large enough to handle 10 frame delay for initial isoc requests */
49#define QH_VALID 32
50
Hans de Goedef8f48b62012-12-14 14:35:36 +010051#define MAX_FRAMES_PER_TICK (QH_VALID / 2)
52
bellardbb36d472005-11-05 14:22:28 +000053#define NB_PORTS 2
54
Gerd Hoffmann60e1b2a2012-03-09 11:09:49 +010055enum {
Gerd Hoffmann0cd178c2012-03-09 11:11:46 +010056 TD_RESULT_STOP_FRAME = 10,
57 TD_RESULT_COMPLETE,
58 TD_RESULT_NEXT_QH,
Gerd Hoffmann4efe4ef2012-03-09 11:15:41 +010059 TD_RESULT_ASYNC_START,
60 TD_RESULT_ASYNC_CONT,
Gerd Hoffmann60e1b2a2012-03-09 11:09:49 +010061};
62
Gerd Hoffmann7b5a44c2010-12-15 10:26:15 +010063typedef struct UHCIState UHCIState;
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +010064typedef struct UHCIAsync UHCIAsync;
65typedef struct UHCIQueue UHCIQueue;
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +020066typedef struct UHCIInfo UHCIInfo;
Gerd Hoffmann8f3f90b2012-10-26 14:56:19 +020067typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass;
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +020068
69struct UHCIInfo {
70 const char *name;
71 uint16_t vendor_id;
72 uint16_t device_id;
73 uint8_t revision;
Gerd Hoffmann8f3f90b2012-10-26 14:56:19 +020074 uint8_t irq_pin;
Markus Armbruster63216dc2015-02-17 14:28:05 +010075 void (*realize)(PCIDevice *dev, Error **errp);
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +020076 bool unplug;
77};
Gerd Hoffmann7b5a44c2010-12-15 10:26:15 +010078
Gerd Hoffmann8f3f90b2012-10-26 14:56:19 +020079struct UHCIPCIDeviceClass {
80 PCIDeviceClass parent_class;
81 UHCIInfo info;
82};
83
aliguori54f254f2008-08-21 19:30:31 +000084/*
85 * Pending async transaction.
86 * 'packet' must be the first field because completion
87 * handler does "(UHCIAsync *) pkt" cast.
88 */
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +010089
90struct UHCIAsync {
aliguori54f254f2008-08-21 19:30:31 +000091 USBPacket packet;
Hans de Goede98222612013-05-06 10:48:57 +020092 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */
93 uint8_t *buf;
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +010094 UHCIQueue *queue;
Gerd Hoffmannddf65832010-12-14 18:19:47 +010095 QTAILQ_ENTRY(UHCIAsync) next;
Hans de Goede1f250cc2012-10-24 18:31:10 +020096 uint32_t td_addr;
aliguori54f254f2008-08-21 19:30:31 +000097 uint8_t done;
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +010098};
99
100struct UHCIQueue {
Hans de Goede66a08cb2012-10-24 18:31:15 +0200101 uint32_t qh_addr;
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100102 uint32_t token;
103 UHCIState *uhci;
Hans de Goede11d15e42012-10-24 18:31:13 +0200104 USBEndpoint *ep;
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100105 QTAILQ_ENTRY(UHCIQueue) next;
Paolo Bonzinieae3eb32018-12-06 13:10:34 +0100106 QTAILQ_HEAD(, UHCIAsync) asyncs;
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100107 int8_t valid;
108};
aliguori54f254f2008-08-21 19:30:31 +0000109
bellardbb36d472005-11-05 14:22:28 +0000110typedef struct UHCIPort {
111 USBPort port;
112 uint16_t ctrl;
bellardbb36d472005-11-05 14:22:28 +0000113} UHCIPort;
114
Gerd Hoffmann7b5a44c2010-12-15 10:26:15 +0100115struct UHCIState {
bellardbb36d472005-11-05 14:22:28 +0000116 PCIDevice dev;
Avi Kivitya03f66e2011-08-08 16:09:24 +0300117 MemoryRegion io_bar;
Hans de Goede35e49772011-06-24 17:44:53 +0200118 USBBus bus; /* Note unused when we're a companion controller */
bellardbb36d472005-11-05 14:22:28 +0000119 uint16_t cmd; /* cmd register */
120 uint16_t status;
121 uint16_t intr; /* interrupt enable register */
122 uint16_t frnum; /* frame number */
123 uint32_t fl_base_addr; /* frame list base address */
124 uint8_t sof_timing;
125 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
David S. Ahern8e65b7c2010-02-03 08:49:39 -0700126 int64_t expire_time;
bellardbb36d472005-11-05 14:22:28 +0000127 QEMUTimer *frame_timer;
Gerd Hoffmann9a16c592012-05-11 09:33:07 +0200128 QEMUBH *bh;
Gerd Hoffmann4aed20e2012-05-11 09:18:05 +0200129 uint32_t frame_bytes;
Gerd Hoffmann40141d12012-05-11 10:02:53 +0200130 uint32_t frame_bandwidth;
Hans de Goede88793812012-11-17 12:11:49 +0100131 bool completions_only;
bellardbb36d472005-11-05 14:22:28 +0000132 UHCIPort ports[NB_PORTS];
pbrook4d611c92006-08-12 01:04:27 +0000133
134 /* Interrupts that should be raised at the end of the current frame. */
135 uint32_t pending_int_mask;
aliguori54f254f2008-08-21 19:30:31 +0000136
137 /* Active packets */
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100138 QTAILQ_HEAD(, UHCIQueue) queues;
Juan Quintela64e58fe2009-10-14 12:21:50 +0200139 uint8_t num_ports_vmstate;
Hans de Goede35e49772011-06-24 17:44:53 +0200140
141 /* Properties */
142 char *masterbus;
143 uint32_t firstport;
Hans de Goede9fdf7022012-12-14 14:35:37 +0100144 uint32_t maxframes;
Gerd Hoffmann7b5a44c2010-12-15 10:26:15 +0100145};
bellardbb36d472005-11-05 14:22:28 +0000146
147typedef struct UHCI_TD {
148 uint32_t link;
149 uint32_t ctrl; /* see TD_CTRL_xxx */
150 uint32_t token;
151 uint32_t buffer;
152} UHCI_TD;
153
154typedef struct UHCI_QH {
155 uint32_t link;
156 uint32_t el_link;
157} UHCI_QH;
158
Hans de Goede40507372012-10-24 18:31:09 +0200159static void uhci_async_cancel(UHCIAsync *async);
Hans de Goede11d15e42012-10-24 18:31:13 +0200160static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td);
Gerd Hoffmann9f0f1a02013-06-26 17:05:06 +0200161static void uhci_resume(void *opaque);
Hans de Goede40507372012-10-24 18:31:09 +0200162
Gonglei49184b62015-05-06 20:55:23 +0800163#define TYPE_UHCI "pci-uhci-usb"
Eduardo Habkost8110fa12020-08-31 17:07:33 -0400164DECLARE_INSTANCE_CHECKER(UHCIState, UHCI,
165 TYPE_UHCI)
Gonglei49184b62015-05-06 20:55:23 +0800166
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100167static inline int32_t uhci_queue_token(UHCI_TD *td)
168{
Hans de Goede6fe30912012-10-24 18:31:20 +0200169 if ((td->token & (0xf << 15)) == 0) {
170 /* ctrl ep, cover ep and dev, not pid! */
171 return td->token & 0x7ff00;
172 } else {
173 /* covers ep, dev, pid -> identifies the endpoint */
174 return td->token & 0x7ffff;
175 }
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100176}
177
Hans de Goede66a08cb2012-10-24 18:31:15 +0200178static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td,
179 USBEndpoint *ep)
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100180{
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100181 UHCIQueue *queue;
182
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100183 queue = g_new0(UHCIQueue, 1);
184 queue->uhci = s;
Hans de Goede66a08cb2012-10-24 18:31:15 +0200185 queue->qh_addr = qh_addr;
186 queue->token = uhci_queue_token(td);
Hans de Goede11d15e42012-10-24 18:31:13 +0200187 queue->ep = ep;
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100188 QTAILQ_INIT(&queue->asyncs);
189 QTAILQ_INSERT_HEAD(&s->queues, queue, next);
Hans de Goede475443c2012-12-14 14:35:35 +0100190 queue->valid = QH_VALID;
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +0100191 trace_usb_uhci_queue_add(queue->token);
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100192 return queue;
193}
194
Hans de Goede66a08cb2012-10-24 18:31:15 +0200195static void uhci_queue_free(UHCIQueue *queue, const char *reason)
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100196{
197 UHCIState *s = queue->uhci;
Hans de Goede40507372012-10-24 18:31:09 +0200198 UHCIAsync *async;
199
200 while (!QTAILQ_EMPTY(&queue->asyncs)) {
201 async = QTAILQ_FIRST(&queue->asyncs);
202 uhci_async_cancel(async);
203 }
Hans de Goedef79738b2012-12-14 14:35:40 +0100204 usb_device_ep_stopped(queue->ep->dev, queue->ep);
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100205
Hans de Goede66a08cb2012-10-24 18:31:15 +0200206 trace_usb_uhci_queue_del(queue->token, reason);
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100207 QTAILQ_REMOVE(&s->queues, queue, next);
208 g_free(queue);
209}
210
Hans de Goede66a08cb2012-10-24 18:31:15 +0200211static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td)
212{
213 uint32_t token = uhci_queue_token(td);
214 UHCIQueue *queue;
215
216 QTAILQ_FOREACH(queue, &s->queues, next) {
217 if (queue->token == token) {
218 return queue;
219 }
220 }
221 return NULL;
222}
223
224static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td,
225 uint32_t td_addr, bool queuing)
226{
227 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs);
Gerd Hoffmannc348e482014-02-05 14:54:14 +0100228 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f;
Hans de Goede66a08cb2012-10-24 18:31:15 +0200229
230 return queue->qh_addr == qh_addr &&
231 queue->token == uhci_queue_token(td) &&
Gerd Hoffmannc348e482014-02-05 14:54:14 +0100232 queue_token_addr == queue->ep->dev->addr &&
Hans de Goede66a08cb2012-10-24 18:31:15 +0200233 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL ||
234 first->td_addr == td_addr);
235}
236
Hans de Goede1f250cc2012-10-24 18:31:10 +0200237static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr)
aliguori54f254f2008-08-21 19:30:31 +0000238{
Gerd Hoffmann326700e2012-01-27 14:17:59 +0100239 UHCIAsync *async = g_new0(UHCIAsync, 1);
aliguori487414f2009-02-05 22:06:05 +0000240
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100241 async->queue = queue;
Hans de Goede1f250cc2012-10-24 18:31:10 +0200242 async->td_addr = td_addr;
Gerd Hoffmann4f4321c2011-07-12 15:22:25 +0200243 usb_packet_init(&async->packet);
Hans de Goede1f250cc2012-10-24 18:31:10 +0200244 trace_usb_uhci_packet_add(async->queue->token, async->td_addr);
aliguori54f254f2008-08-21 19:30:31 +0000245
246 return async;
247}
248
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100249static void uhci_async_free(UHCIAsync *async)
aliguori54f254f2008-08-21 19:30:31 +0000250{
Hans de Goede1f250cc2012-10-24 18:31:10 +0200251 trace_usb_uhci_packet_del(async->queue->token, async->td_addr);
Gerd Hoffmann4f4321c2011-07-12 15:22:25 +0200252 usb_packet_cleanup(&async->packet);
Hans de Goede98222612013-05-06 10:48:57 +0200253 if (async->buf != async->static_buf) {
254 g_free(async->buf);
255 }
Anthony Liguori7267c092011-08-20 22:09:37 -0500256 g_free(async);
aliguori54f254f2008-08-21 19:30:31 +0000257}
258
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100259static void uhci_async_link(UHCIAsync *async)
aliguori54f254f2008-08-21 19:30:31 +0000260{
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100261 UHCIQueue *queue = async->queue;
262 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
Hans de Goede1f250cc2012-10-24 18:31:10 +0200263 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr);
aliguori54f254f2008-08-21 19:30:31 +0000264}
265
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100266static void uhci_async_unlink(UHCIAsync *async)
aliguori54f254f2008-08-21 19:30:31 +0000267{
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100268 UHCIQueue *queue = async->queue;
269 QTAILQ_REMOVE(&queue->asyncs, async, next);
Hans de Goede1f250cc2012-10-24 18:31:10 +0200270 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr);
aliguori54f254f2008-08-21 19:30:31 +0000271}
272
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100273static void uhci_async_cancel(UHCIAsync *async)
aliguori54f254f2008-08-21 19:30:31 +0000274{
Hans de Goede2f2ee262012-10-24 18:31:06 +0200275 uhci_async_unlink(async);
Hans de Goede1f250cc2012-10-24 18:31:10 +0200276 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr,
277 async->done);
aliguori54f254f2008-08-21 19:30:31 +0000278 if (!async->done)
279 usb_cancel_packet(&async->packet);
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100280 uhci_async_free(async);
aliguori54f254f2008-08-21 19:30:31 +0000281}
282
283/*
284 * Mark all outstanding async packets as invalid.
285 * This is used for canceling them when TDs are removed by the HCD.
286 */
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100287static void uhci_async_validate_begin(UHCIState *s)
aliguori54f254f2008-08-21 19:30:31 +0000288{
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100289 UHCIQueue *queue;
aliguori54f254f2008-08-21 19:30:31 +0000290
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100291 QTAILQ_FOREACH(queue, &s->queues, next) {
292 queue->valid--;
aliguori54f254f2008-08-21 19:30:31 +0000293 }
aliguori54f254f2008-08-21 19:30:31 +0000294}
295
296/*
297 * Cancel async packets that are no longer valid
298 */
299static void uhci_async_validate_end(UHCIState *s)
300{
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100301 UHCIQueue *queue, *n;
aliguori54f254f2008-08-21 19:30:31 +0000302
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100303 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
Hans de Goede40507372012-10-24 18:31:09 +0200304 if (!queue->valid) {
Hans de Goede66a08cb2012-10-24 18:31:15 +0200305 uhci_queue_free(queue, "validate-end");
aliguori54f254f2008-08-21 19:30:31 +0000306 }
aliguori54f254f2008-08-21 19:30:31 +0000307 }
308}
309
Gerd Hoffmann07771f62011-05-23 17:37:12 +0200310static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
311{
Hans de Goede5ad23e82012-10-24 18:31:14 +0200312 UHCIQueue *queue, *n;
Gerd Hoffmann07771f62011-05-23 17:37:12 +0200313
Hans de Goede5ad23e82012-10-24 18:31:14 +0200314 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
315 if (queue->ep->dev == dev) {
316 uhci_queue_free(queue, "cancel-device");
Gerd Hoffmann07771f62011-05-23 17:37:12 +0200317 }
Gerd Hoffmann07771f62011-05-23 17:37:12 +0200318 }
319}
320
aliguori54f254f2008-08-21 19:30:31 +0000321static void uhci_async_cancel_all(UHCIState *s)
322{
Gerd Hoffmann77fa9ae2012-06-15 09:39:50 +0200323 UHCIQueue *queue, *nq;
aliguori54f254f2008-08-21 19:30:31 +0000324
Gerd Hoffmann77fa9ae2012-06-15 09:39:50 +0200325 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) {
Hans de Goede66a08cb2012-10-24 18:31:15 +0200326 uhci_queue_free(queue, "cancel-all");
aliguori54f254f2008-08-21 19:30:31 +0000327 }
aliguori54f254f2008-08-21 19:30:31 +0000328}
329
Hans de Goede8c75a892012-10-24 18:31:16 +0200330static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr)
aliguori54f254f2008-08-21 19:30:31 +0000331{
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100332 UHCIQueue *queue;
Gerd Hoffmannddf65832010-12-14 18:19:47 +0100333 UHCIAsync *async;
aurel32e8ee3c72008-08-22 09:23:06 +0000334
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100335 QTAILQ_FOREACH(queue, &s->queues, next) {
Hans de Goede8c75a892012-10-24 18:31:16 +0200336 QTAILQ_FOREACH(async, &queue->asyncs, next) {
337 if (async->td_addr == td_addr) {
338 return async;
339 }
aliguori54f254f2008-08-21 19:30:31 +0000340 }
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100341 }
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100342 return NULL;
aliguori54f254f2008-08-21 19:30:31 +0000343}
344
bellardbb36d472005-11-05 14:22:28 +0000345static void uhci_update_irq(UHCIState *s)
346{
347 int level;
348 if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
349 ((s->status2 & 2) && (s->intr & (1 << 3))) ||
350 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
351 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
352 (s->status & UHCI_STS_HSERR) ||
353 (s->status & UHCI_STS_HCPERR)) {
354 level = 1;
355 } else {
356 level = 0;
357 }
Marcel Apfelbaum9e64f8a2013-10-07 10:36:39 +0300358 pci_set_irq(&s->dev, level);
bellardbb36d472005-11-05 14:22:28 +0000359}
360
Gonglei537e5722015-03-18 17:33:46 +0800361static void uhci_reset(DeviceState *dev)
bellardbb36d472005-11-05 14:22:28 +0000362{
Gonglei537e5722015-03-18 17:33:46 +0800363 PCIDevice *d = PCI_DEVICE(dev);
Gonglei49184b62015-05-06 20:55:23 +0800364 UHCIState *s = UHCI(d);
bellardbb36d472005-11-05 14:22:28 +0000365 uint8_t *pci_conf;
366 int i;
367 UHCIPort *port;
368
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +0100369 trace_usb_uhci_reset();
aliguori6f382b52008-08-21 19:33:09 +0000370
bellardbb36d472005-11-05 14:22:28 +0000371 pci_conf = s->dev.config;
372
373 pci_conf[0x6a] = 0x01; /* usb clock */
374 pci_conf[0x6b] = 0x00;
375 s->cmd = 0;
Gerd Hoffmannca5a21c2015-05-07 09:24:00 +0200376 s->status = UHCI_STS_HCHALTED;
bellardbb36d472005-11-05 14:22:28 +0000377 s->status2 = 0;
378 s->intr = 0;
379 s->fl_base_addr = 0;
380 s->sof_timing = 64;
aliguori54f254f2008-08-21 19:30:31 +0000381
bellardbb36d472005-11-05 14:22:28 +0000382 for(i = 0; i < NB_PORTS; i++) {
383 port = &s->ports[i];
384 port->ctrl = 0x0080;
Gerd Hoffmann891fb2c2011-09-01 13:56:37 +0200385 if (port->port.dev && port->port.dev->attached) {
Gerd Hoffmannd28f4e22012-01-06 15:23:10 +0100386 usb_port_reset(&port->port);
Gerd Hoffmann618c1692010-12-01 11:27:05 +0100387 }
bellardbb36d472005-11-05 14:22:28 +0000388 }
aliguori54f254f2008-08-21 19:30:31 +0000389
390 uhci_async_cancel_all(s);
Gerd Hoffmann9a16c592012-05-11 09:33:07 +0200391 qemu_bh_cancel(s->bh);
Gerd Hoffmannaba1f242012-04-20 15:13:24 +0200392 uhci_update_irq(s);
bellardbb36d472005-11-05 14:22:28 +0000393}
394
Juan Quintela817afc62009-10-14 12:49:30 +0200395static const VMStateDescription vmstate_uhci_port = {
396 .name = "uhci port",
397 .version_id = 1,
398 .minimum_version_id = 1,
Juan Quintela6e3d6522014-04-16 13:31:26 +0200399 .fields = (VMStateField[]) {
Juan Quintela817afc62009-10-14 12:49:30 +0200400 VMSTATE_UINT16(ctrl, UHCIPort),
401 VMSTATE_END_OF_LIST()
402 }
403};
balrogb9dc0332007-10-04 22:47:34 +0000404
Gerd Hoffmann75f151c2012-07-10 12:51:07 +0200405static int uhci_post_load(void *opaque, int version_id)
406{
407 UHCIState *s = opaque;
408
409 if (version_id < 2) {
Alex Blighbc72ad62013-08-21 16:03:08 +0100410 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
Rutuja Shah73bcb242016-03-21 21:32:30 +0530411 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ);
Gerd Hoffmann75f151c2012-07-10 12:51:07 +0200412 }
413 return 0;
414}
415
Juan Quintela817afc62009-10-14 12:49:30 +0200416static const VMStateDescription vmstate_uhci = {
417 .name = "uhci",
Hans de Goedeecfdc152012-12-14 14:35:34 +0100418 .version_id = 3,
Juan Quintela817afc62009-10-14 12:49:30 +0200419 .minimum_version_id = 1,
Gerd Hoffmann75f151c2012-07-10 12:51:07 +0200420 .post_load = uhci_post_load,
Juan Quintela6e3d6522014-04-16 13:31:26 +0200421 .fields = (VMStateField[]) {
Juan Quintela817afc62009-10-14 12:49:30 +0200422 VMSTATE_PCI_DEVICE(dev, UHCIState),
Halil Pasicd2164ad2017-06-23 16:48:23 +0200423 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState, NULL),
Juan Quintela817afc62009-10-14 12:49:30 +0200424 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
425 vmstate_uhci_port, UHCIPort),
426 VMSTATE_UINT16(cmd, UHCIState),
427 VMSTATE_UINT16(status, UHCIState),
428 VMSTATE_UINT16(intr, UHCIState),
429 VMSTATE_UINT16(frnum, UHCIState),
430 VMSTATE_UINT32(fl_base_addr, UHCIState),
431 VMSTATE_UINT8(sof_timing, UHCIState),
432 VMSTATE_UINT8(status2, UHCIState),
Paolo Bonzinie7206772015-01-08 10:18:59 +0100433 VMSTATE_TIMER_PTR(frame_timer, UHCIState),
TeLeMan6881dd52010-06-01 12:26:20 +0800434 VMSTATE_INT64_V(expire_time, UHCIState, 2),
Hans de Goedeecfdc152012-12-14 14:35:34 +0100435 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3),
Juan Quintela817afc62009-10-14 12:49:30 +0200436 VMSTATE_END_OF_LIST()
437 }
438};
balrogb9dc0332007-10-04 22:47:34 +0000439
Gerd Hoffmann89eb1472013-01-03 12:29:41 +0100440static void uhci_port_write(void *opaque, hwaddr addr,
441 uint64_t val, unsigned size)
bellardbb36d472005-11-05 14:22:28 +0000442{
443 UHCIState *s = opaque;
ths3b46e622007-09-17 08:09:54 +0000444
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +0100445 trace_usb_uhci_mmio_writew(addr, val);
aliguori54f254f2008-08-21 19:30:31 +0000446
bellardbb36d472005-11-05 14:22:28 +0000447 switch(addr) {
448 case 0x00:
449 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
450 /* start frame processing */
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +0100451 trace_usb_uhci_schedule_start();
Alex Blighbc72ad62013-08-21 16:03:08 +0100452 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
Rutuja Shah73bcb242016-03-21 21:32:30 +0530453 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ);
Alex Blighbc72ad62013-08-21 16:03:08 +0100454 timer_mod(s->frame_timer, s->expire_time);
bellard52328142006-04-24 21:38:50 +0000455 s->status &= ~UHCI_STS_HCHALTED;
bellard467d4092006-04-25 21:01:19 +0000456 } else if (!(val & UHCI_CMD_RS)) {
bellard52328142006-04-24 21:38:50 +0000457 s->status |= UHCI_STS_HCHALTED;
bellardbb36d472005-11-05 14:22:28 +0000458 }
459 if (val & UHCI_CMD_GRESET) {
460 UHCIPort *port;
bellardbb36d472005-11-05 14:22:28 +0000461 int i;
462
463 /* send reset on the USB bus */
464 for(i = 0; i < NB_PORTS; i++) {
465 port = &s->ports[i];
Gerd Hoffmannd28f4e22012-01-06 15:23:10 +0100466 usb_device_reset(port->port.dev);
bellardbb36d472005-11-05 14:22:28 +0000467 }
Gonglei537e5722015-03-18 17:33:46 +0800468 uhci_reset(DEVICE(s));
bellardbb36d472005-11-05 14:22:28 +0000469 return;
470 }
bellard5e9ab4c2005-11-19 17:43:37 +0000471 if (val & UHCI_CMD_HCRESET) {
Gonglei537e5722015-03-18 17:33:46 +0800472 uhci_reset(DEVICE(s));
bellardbb36d472005-11-05 14:22:28 +0000473 return;
474 }
475 s->cmd = val;
Gerd Hoffmann9f0f1a02013-06-26 17:05:06 +0200476 if (val & UHCI_CMD_EGSM) {
477 if ((s->ports[0].ctrl & UHCI_PORT_RD) ||
478 (s->ports[1].ctrl & UHCI_PORT_RD)) {
479 uhci_resume(s);
480 }
481 }
bellardbb36d472005-11-05 14:22:28 +0000482 break;
483 case 0x02:
484 s->status &= ~val;
485 /* XXX: the chip spec is not coherent, so we add a hidden
486 register to distinguish between IOC and SPD */
487 if (val & UHCI_STS_USBINT)
488 s->status2 = 0;
489 uhci_update_irq(s);
490 break;
491 case 0x04:
492 s->intr = val;
493 uhci_update_irq(s);
494 break;
495 case 0x06:
496 if (s->status & UHCI_STS_HCHALTED)
497 s->frnum = val & 0x7ff;
498 break;
Gerd Hoffmann89eb1472013-01-03 12:29:41 +0100499 case 0x08:
500 s->fl_base_addr &= 0xffff0000;
501 s->fl_base_addr |= val & ~0xfff;
502 break;
503 case 0x0a:
504 s->fl_base_addr &= 0x0000ffff;
505 s->fl_base_addr |= (val << 16);
506 break;
507 case 0x0c:
508 s->sof_timing = val & 0xff;
509 break;
bellardbb36d472005-11-05 14:22:28 +0000510 case 0x10 ... 0x1f:
511 {
512 UHCIPort *port;
513 USBDevice *dev;
514 int n;
515
516 n = (addr >> 1) & 7;
517 if (n >= NB_PORTS)
518 return;
519 port = &s->ports[n];
bellarda594cfb2005-11-06 16:13:29 +0000520 dev = port->port.dev;
Gerd Hoffmann891fb2c2011-09-01 13:56:37 +0200521 if (dev && dev->attached) {
bellardbb36d472005-11-05 14:22:28 +0000522 /* port reset */
ths5fafdf22007-09-16 21:08:06 +0000523 if ( (val & UHCI_PORT_RESET) &&
bellardbb36d472005-11-05 14:22:28 +0000524 !(port->ctrl & UHCI_PORT_RESET) ) {
Gerd Hoffmannd28f4e22012-01-06 15:23:10 +0100525 usb_device_reset(dev);
bellardbb36d472005-11-05 14:22:28 +0000526 }
527 }
Gerd Hoffmann9159f672010-12-01 11:47:40 +0100528 port->ctrl &= UHCI_PORT_READ_ONLY;
Hans de Goede1cbdde92012-11-17 12:11:50 +0100529 /* enabled may only be set if a device is connected */
530 if (!(port->ctrl & UHCI_PORT_CCS)) {
531 val &= ~UHCI_PORT_EN;
532 }
Gerd Hoffmann9159f672010-12-01 11:47:40 +0100533 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
bellardbb36d472005-11-05 14:22:28 +0000534 /* some bits are reset when a '1' is written to them */
Gerd Hoffmann9159f672010-12-01 11:47:40 +0100535 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
bellardbb36d472005-11-05 14:22:28 +0000536 }
537 break;
538 }
539}
540
Gerd Hoffmann89eb1472013-01-03 12:29:41 +0100541static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size)
bellardbb36d472005-11-05 14:22:28 +0000542{
543 UHCIState *s = opaque;
544 uint32_t val;
545
bellardbb36d472005-11-05 14:22:28 +0000546 switch(addr) {
547 case 0x00:
548 val = s->cmd;
549 break;
550 case 0x02:
551 val = s->status;
552 break;
553 case 0x04:
554 val = s->intr;
555 break;
556 case 0x06:
557 val = s->frnum;
558 break;
Gerd Hoffmann89eb1472013-01-03 12:29:41 +0100559 case 0x08:
560 val = s->fl_base_addr & 0xffff;
561 break;
562 case 0x0a:
563 val = (s->fl_base_addr >> 16) & 0xffff;
564 break;
565 case 0x0c:
566 val = s->sof_timing;
567 break;
bellardbb36d472005-11-05 14:22:28 +0000568 case 0x10 ... 0x1f:
569 {
570 UHCIPort *port;
571 int n;
572 n = (addr >> 1) & 7;
ths5fafdf22007-09-16 21:08:06 +0000573 if (n >= NB_PORTS)
bellardbb36d472005-11-05 14:22:28 +0000574 goto read_default;
575 port = &s->ports[n];
576 val = port->ctrl;
577 }
578 break;
579 default:
580 read_default:
581 val = 0xff7f; /* disabled port */
582 break;
583 }
aliguori54f254f2008-08-21 19:30:31 +0000584
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +0100585 trace_usb_uhci_mmio_readw(addr, val);
aliguori54f254f2008-08-21 19:30:31 +0000586
bellardbb36d472005-11-05 14:22:28 +0000587 return val;
588}
589
ths96217e32007-02-22 20:21:33 +0000590/* signal resume if controller suspended */
591static void uhci_resume (void *opaque)
592{
593 UHCIState *s = (UHCIState *)opaque;
594
595 if (!s)
596 return;
597
598 if (s->cmd & UHCI_CMD_EGSM) {
599 s->cmd |= UHCI_CMD_FGR;
600 s->status |= UHCI_STS_RD;
601 uhci_update_irq(s);
602 }
603}
604
Gerd Hoffmann618c1692010-12-01 11:27:05 +0100605static void uhci_attach(USBPort *port1)
bellardbb36d472005-11-05 14:22:28 +0000606{
607 UHCIState *s = port1->opaque;
608 UHCIPort *port = &s->ports[port1->index];
609
Gerd Hoffmann618c1692010-12-01 11:27:05 +0100610 /* set connect status */
611 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
pbrook61064872006-05-22 17:17:06 +0000612
Gerd Hoffmann618c1692010-12-01 11:27:05 +0100613 /* update speed */
614 if (port->port.dev->speed == USB_SPEED_LOW) {
615 port->ctrl |= UHCI_PORT_LSDA;
bellardbb36d472005-11-05 14:22:28 +0000616 } else {
Gerd Hoffmann618c1692010-12-01 11:27:05 +0100617 port->ctrl &= ~UHCI_PORT_LSDA;
bellardbb36d472005-11-05 14:22:28 +0000618 }
Gerd Hoffmann618c1692010-12-01 11:27:05 +0100619
620 uhci_resume(s);
621}
622
623static void uhci_detach(USBPort *port1)
624{
625 UHCIState *s = port1->opaque;
626 UHCIPort *port = &s->ports[port1->index];
627
Hans de Goede4706ab62011-06-24 12:31:11 +0200628 uhci_async_cancel_device(s, port1->dev);
629
Gerd Hoffmann618c1692010-12-01 11:27:05 +0100630 /* set connect status */
631 if (port->ctrl & UHCI_PORT_CCS) {
632 port->ctrl &= ~UHCI_PORT_CCS;
633 port->ctrl |= UHCI_PORT_CSC;
634 }
635 /* disable port */
636 if (port->ctrl & UHCI_PORT_EN) {
637 port->ctrl &= ~UHCI_PORT_EN;
638 port->ctrl |= UHCI_PORT_ENC;
639 }
640
641 uhci_resume(s);
bellardbb36d472005-11-05 14:22:28 +0000642}
643
Hans de Goede4706ab62011-06-24 12:31:11 +0200644static void uhci_child_detach(USBPort *port1, USBDevice *child)
645{
646 UHCIState *s = port1->opaque;
647
648 uhci_async_cancel_device(s, child);
649}
650
Hans de Goeded47e59b2011-06-21 11:52:28 +0200651static void uhci_wakeup(USBPort *port1)
Gerd Hoffmann9159f672010-12-01 11:47:40 +0100652{
Hans de Goeded47e59b2011-06-21 11:52:28 +0200653 UHCIState *s = port1->opaque;
654 UHCIPort *port = &s->ports[port1->index];
Gerd Hoffmann9159f672010-12-01 11:47:40 +0100655
656 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
657 port->ctrl |= UHCI_PORT_RD;
658 uhci_resume(s);
659 }
660}
661
Gerd Hoffmann461700c2012-01-10 17:34:24 +0100662static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
bellardbb36d472005-11-05 14:22:28 +0000663{
Gerd Hoffmann461700c2012-01-10 17:34:24 +0100664 USBDevice *dev;
665 int i;
bellardbb36d472005-11-05 14:22:28 +0000666
Gerd Hoffmann461700c2012-01-10 17:34:24 +0100667 for (i = 0; i < NB_PORTS; i++) {
aliguori54f254f2008-08-21 19:30:31 +0000668 UHCIPort *port = &s->ports[i];
Gerd Hoffmann461700c2012-01-10 17:34:24 +0100669 if (!(port->ctrl & UHCI_PORT_EN)) {
670 continue;
671 }
672 dev = usb_find_device(&port->port, addr);
673 if (dev != NULL) {
674 return dev;
Gerd Hoffmann891fb2c2011-09-01 13:56:37 +0200675 }
bellardbb36d472005-11-05 14:22:28 +0000676 }
Gerd Hoffmann461700c2012-01-10 17:34:24 +0100677 return NULL;
bellardbb36d472005-11-05 14:22:28 +0000678}
679
Hans de Goede963a68b2012-10-24 18:31:11 +0200680static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link)
681{
682 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td));
683 le32_to_cpus(&td->link);
684 le32_to_cpus(&td->ctrl);
685 le32_to_cpus(&td->token);
686 le32_to_cpus(&td->buffer);
687}
688
Hans de Goedefaccca02012-10-31 12:54:36 +0100689static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr,
690 int status, uint32_t *int_mask)
691{
692 uint32_t queue_token = uhci_queue_token(td);
693 int ret;
694
695 switch (status) {
696 case USB_RET_NAK:
697 td->ctrl |= TD_CTRL_NAK;
698 return TD_RESULT_NEXT_QH;
699
700 case USB_RET_STALL:
701 td->ctrl |= TD_CTRL_STALL;
702 trace_usb_uhci_packet_complete_stall(queue_token, td_addr);
703 ret = TD_RESULT_NEXT_QH;
704 break;
705
706 case USB_RET_BABBLE:
707 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
708 /* frame interrupted */
709 trace_usb_uhci_packet_complete_babble(queue_token, td_addr);
710 ret = TD_RESULT_STOP_FRAME;
711 break;
712
713 case USB_RET_IOERROR:
714 case USB_RET_NODEV:
715 default:
716 td->ctrl |= TD_CTRL_TIMEOUT;
717 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT);
718 trace_usb_uhci_packet_complete_error(queue_token, td_addr);
719 ret = TD_RESULT_NEXT_QH;
720 break;
721 }
722
723 td->ctrl &= ~TD_CTRL_ACTIVE;
724 s->status |= UHCI_STS_USBERR;
725 if (td->ctrl & TD_CTRL_IOC) {
726 *int_mask |= 0x01;
727 }
728 uhci_update_irq(s);
729 return ret;
730}
731
aliguori54f254f2008-08-21 19:30:31 +0000732static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
bellardbb36d472005-11-05 14:22:28 +0000733{
Hans de Goede9a77a0f2012-11-01 17:15:01 +0100734 int len = 0, max_len;
bellardbb36d472005-11-05 14:22:28 +0000735 uint8_t pid;
bellardbb36d472005-11-05 14:22:28 +0000736
bellardbb36d472005-11-05 14:22:28 +0000737 max_len = ((td->token >> 21) + 1) & 0x7ff;
738 pid = td->token & 0xff;
balrogb9dc0332007-10-04 22:47:34 +0000739
bellardbb36d472005-11-05 14:22:28 +0000740 if (td->ctrl & TD_CTRL_IOS)
741 td->ctrl &= ~TD_CTRL_ACTIVE;
aliguori54f254f2008-08-21 19:30:31 +0000742
Hans de Goede9a77a0f2012-11-01 17:15:01 +0100743 if (async->packet.status != USB_RET_SUCCESS) {
744 return uhci_handle_td_error(s, td, async->td_addr,
745 async->packet.status, int_mask);
Hans de Goedefaccca02012-10-31 12:54:36 +0100746 }
aliguori54f254f2008-08-21 19:30:31 +0000747
Hans de Goede9a77a0f2012-11-01 17:15:01 +0100748 len = async->packet.actual_length;
aliguori54f254f2008-08-21 19:30:31 +0000749 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
750
751 /* The NAK bit may have been set by a previous frame, so clear it
752 here. The docs are somewhat unclear, but win2k relies on this
753 behavior. */
754 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
Paul Brook5bd2c0d2010-04-04 21:48:31 +0100755 if (td->ctrl & TD_CTRL_IOC)
756 *int_mask |= 0x01;
aliguori54f254f2008-08-21 19:30:31 +0000757
758 if (pid == USB_TOKEN_IN) {
Hans de Goede98222612013-05-06 10:48:57 +0200759 pci_dma_write(&s->dev, td->buffer, async->buf, len);
aliguori54f254f2008-08-21 19:30:31 +0000760 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
bellardbb36d472005-11-05 14:22:28 +0000761 *int_mask |= 0x02;
762 /* short packet: do not update QH */
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +0100763 trace_usb_uhci_packet_complete_shortxfer(async->queue->token,
Hans de Goede1f250cc2012-10-24 18:31:10 +0200764 async->td_addr);
Gerd Hoffmann60e1b2a2012-03-09 11:09:49 +0100765 return TD_RESULT_NEXT_QH;
bellardbb36d472005-11-05 14:22:28 +0000766 }
767 }
aliguori54f254f2008-08-21 19:30:31 +0000768
769 /* success */
Hans de Goede1f250cc2012-10-24 18:31:10 +0200770 trace_usb_uhci_packet_complete_success(async->queue->token,
771 async->td_addr);
Gerd Hoffmann60e1b2a2012-03-09 11:09:49 +0100772 return TD_RESULT_COMPLETE;
bellardbb36d472005-11-05 14:22:28 +0000773}
774
Hans de Goede66a08cb2012-10-24 18:31:15 +0200775static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
Hans de Goedea4f30cd2012-10-24 18:31:12 +0200776 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask)
aliguori54f254f2008-08-21 19:30:31 +0000777{
Hans de Goede9a77a0f2012-11-01 17:15:01 +0100778 int ret, max_len;
Hans de Goede6ba43f12012-10-24 18:14:09 +0200779 bool spd;
Hans de Goedea4f30cd2012-10-24 18:31:12 +0200780 bool queuing = (q != NULL);
Hans de Goede11d15e42012-10-24 18:31:13 +0200781 uint8_t pid = td->token & 0xff;
Gonglei5f77e062016-02-19 15:33:58 +0800782 UHCIAsync *async;
Hans de Goede8c75a892012-10-24 18:31:16 +0200783
Gonglei5f77e062016-02-19 15:33:58 +0800784 async = uhci_async_find_td(s, td_addr);
Hans de Goede8c75a892012-10-24 18:31:16 +0200785 if (async) {
786 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) {
787 assert(q == NULL || q == async->queue);
788 q = async->queue;
789 } else {
790 uhci_queue_free(async->queue, "guest re-used pending td");
791 async = NULL;
792 }
793 }
aliguori54f254f2008-08-21 19:30:31 +0000794
Hans de Goede66a08cb2012-10-24 18:31:15 +0200795 if (q == NULL) {
796 q = uhci_queue_find(s, td);
797 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) {
798 uhci_queue_free(q, "guest re-used qh");
799 q = NULL;
800 }
801 }
802
Hans de Goede39050972012-10-24 18:31:18 +0200803 if (q) {
Hans de Goede475443c2012-12-14 14:35:35 +0100804 q->valid = QH_VALID;
Hans de Goede39050972012-10-24 18:31:18 +0200805 }
806
aliguori54f254f2008-08-21 19:30:31 +0000807 /* Is active ? */
Hans de Goede883bca72012-10-10 15:50:36 +0200808 if (!(td->ctrl & TD_CTRL_ACTIVE)) {
Hans de Goede420ca982012-10-24 18:31:17 +0200809 if (async) {
810 /* Guest marked a pending td non-active, cancel the queue */
811 uhci_queue_free(async->queue, "pending td non-active");
812 }
Hans de Goede883bca72012-10-10 15:50:36 +0200813 /*
814 * ehci11d spec page 22: "Even if the Active bit in the TD is already
815 * cleared when the TD is fetched ... an IOC interrupt is generated"
816 */
817 if (td->ctrl & TD_CTRL_IOC) {
818 *int_mask |= 0x01;
819 }
Gerd Hoffmann60e1b2a2012-03-09 11:09:49 +0100820 return TD_RESULT_NEXT_QH;
Hans de Goede883bca72012-10-10 15:50:36 +0200821 }
aliguori54f254f2008-08-21 19:30:31 +0000822
Gerd Hoffmannf419a622016-04-22 12:44:53 +0200823 switch (pid) {
824 case USB_TOKEN_OUT:
825 case USB_TOKEN_SETUP:
826 case USB_TOKEN_IN:
827 break;
828 default:
829 /* invalid pid : frame interrupted */
830 s->status |= UHCI_STS_HCPERR;
831 s->cmd &= ~UHCI_CMD_RS;
832 uhci_update_irq(s);
833 return TD_RESULT_STOP_FRAME;
834 }
835
aliguori54f254f2008-08-21 19:30:31 +0000836 if (async) {
Gerd Hoffmannee008ba2012-03-29 16:02:20 +0200837 if (queuing) {
838 /* we are busy filling the queue, we are not prepared
839 to consume completed packages then, just leave them
840 in async state */
841 return TD_RESULT_ASYNC_CONT;
842 }
Hans de Goede8928c9c2012-10-24 18:31:19 +0200843 if (!async->done) {
844 UHCI_TD last_td;
Paolo Bonzinieae3eb32018-12-06 13:10:34 +0100845 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs);
Hans de Goede8928c9c2012-10-24 18:31:19 +0200846 /*
847 * While we are waiting for the current td to complete, the guest
848 * may have added more tds to the queue. Note we re-read the td
849 * rather then caching it, as we want to see guest made changes!
850 */
851 uhci_read_td(s, &last_td, last->td_addr);
852 uhci_queue_fill(async->queue, &last_td);
aliguori54f254f2008-08-21 19:30:31 +0000853
Hans de Goede8928c9c2012-10-24 18:31:19 +0200854 return TD_RESULT_ASYNC_CONT;
855 }
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100856 uhci_async_unlink(async);
aliguori54f254f2008-08-21 19:30:31 +0000857 goto done;
858 }
859
Hans de Goede88793812012-11-17 12:11:49 +0100860 if (s->completions_only) {
861 return TD_RESULT_ASYNC_CONT;
862 }
863
aliguori54f254f2008-08-21 19:30:31 +0000864 /* Allocate new packet */
Hans de Goedea4f30cd2012-10-24 18:31:12 +0200865 if (q == NULL) {
Liam Merwickff668532019-02-06 13:36:53 +0000866 USBDevice *dev;
867 USBEndpoint *ep;
Hans de Goede7f102eb2012-10-31 12:54:37 +0100868
Liam Merwickff668532019-02-06 13:36:53 +0000869 dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
870 if (dev == NULL) {
Hans de Goede7f102eb2012-10-31 12:54:37 +0100871 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV,
872 int_mask);
873 }
Liam Merwickff668532019-02-06 13:36:53 +0000874 ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
Hans de Goede66a08cb2012-10-24 18:31:15 +0200875 q = uhci_queue_new(s, qh_addr, td, ep);
Hans de Goedea4f30cd2012-10-24 18:31:12 +0200876 }
877 async = uhci_async_alloc(q, td_addr);
aliguori54f254f2008-08-21 19:30:31 +0000878
aliguori54f254f2008-08-21 19:30:31 +0000879 max_len = ((td->token >> 21) + 1) & 0x7ff;
Hans de Goede6ba43f12012-10-24 18:14:09 +0200880 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0);
Gerd Hoffmann8550a022013-01-29 12:44:35 +0100881 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd,
Hans de Goedea6fb2dd2012-10-24 18:14:10 +0200882 (td->ctrl & TD_CTRL_IOC) != 0);
Hans de Goede98222612013-05-06 10:48:57 +0200883 if (max_len <= sizeof(async->static_buf)) {
884 async->buf = async->static_buf;
885 } else {
886 async->buf = g_malloc(max_len);
887 }
888 usb_packet_addbuf(&async->packet, async->buf, max_len);
aliguori54f254f2008-08-21 19:30:31 +0000889
890 switch(pid) {
891 case USB_TOKEN_OUT:
892 case USB_TOKEN_SETUP:
Hans de Goede98222612013-05-06 10:48:57 +0200893 pci_dma_read(&s->dev, td->buffer, async->buf, max_len);
Hans de Goede9a77a0f2012-11-01 17:15:01 +0100894 usb_handle_packet(q->ep->dev, &async->packet);
895 if (async->packet.status == USB_RET_SUCCESS) {
896 async->packet.actual_length = max_len;
897 }
aliguori54f254f2008-08-21 19:30:31 +0000898 break;
899
900 case USB_TOKEN_IN:
Hans de Goede9a77a0f2012-11-01 17:15:01 +0100901 usb_handle_packet(q->ep->dev, &async->packet);
aliguori54f254f2008-08-21 19:30:31 +0000902 break;
903
904 default:
Gonglei5f77e062016-02-19 15:33:58 +0800905 abort(); /* Never to execute */
aliguori54f254f2008-08-21 19:30:31 +0000906 }
Hans de Goede9a77a0f2012-11-01 17:15:01 +0100907
908 if (async->packet.status == USB_RET_ASYNC) {
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100909 uhci_async_link(async);
Hans de Goedea4f30cd2012-10-24 18:31:12 +0200910 if (!queuing) {
Hans de Goede11d15e42012-10-24 18:31:13 +0200911 uhci_queue_fill(q, td);
Hans de Goedea4f30cd2012-10-24 18:31:12 +0200912 }
Gerd Hoffmann4efe4ef2012-03-09 11:15:41 +0100913 return TD_RESULT_ASYNC_START;
aliguori54f254f2008-08-21 19:30:31 +0000914 }
915
aliguori54f254f2008-08-21 19:30:31 +0000916done:
Hans de Goede9a77a0f2012-11-01 17:15:01 +0100917 ret = uhci_complete_td(s, td, async, int_mask);
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100918 uhci_async_free(async);
Hans de Goede9a77a0f2012-11-01 17:15:01 +0100919 return ret;
aliguori54f254f2008-08-21 19:30:31 +0000920}
921
Hans de Goeded47e59b2011-06-21 11:52:28 +0200922static void uhci_async_complete(USBPort *port, USBPacket *packet)
pbrook4d611c92006-08-12 01:04:27 +0000923{
Gerd Hoffmann7b5a44c2010-12-15 10:26:15 +0100924 UHCIAsync *async = container_of(packet, UHCIAsync, packet);
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +0100925 UHCIState *s = async->queue->uhci;
aliguori54f254f2008-08-21 19:30:31 +0000926
Hans de Goede9a77a0f2012-11-01 17:15:01 +0100927 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
Hans de Goede0cae7b12012-10-24 18:14:08 +0200928 uhci_async_cancel(async);
929 return;
930 }
931
Hans de Goede5b352ed2012-10-24 18:31:05 +0200932 async->done = 1;
Hans de Goede88793812012-11-17 12:11:49 +0100933 /* Force processing of this packet *now*, needed for migration */
934 s->completions_only = true;
935 qemu_bh_schedule(s->bh);
aliguori54f254f2008-08-21 19:30:31 +0000936}
937
938static int is_valid(uint32_t link)
939{
940 return (link & 1) == 0;
941}
942
943static int is_qh(uint32_t link)
944{
945 return (link & 2) != 0;
946}
947
948static int depth_first(uint32_t link)
949{
950 return (link & 4) != 0;
951}
952
953/* QH DB used for detecting QH loops */
954#define UHCI_MAX_QUEUES 128
955typedef struct {
956 uint32_t addr[UHCI_MAX_QUEUES];
957 int count;
958} QhDb;
959
960static void qhdb_reset(QhDb *db)
961{
962 db->count = 0;
963}
964
965/* Add QH to DB. Returns 1 if already present or DB is full. */
966static int qhdb_insert(QhDb *db, uint32_t addr)
967{
968 int i;
969 for (i = 0; i < db->count; i++)
970 if (db->addr[i] == addr)
971 return 1;
972
973 if (db->count >= UHCI_MAX_QUEUES)
974 return 1;
975
976 db->addr[db->count++] = addr;
977 return 0;
978}
979
Hans de Goede11d15e42012-10-24 18:31:13 +0200980static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td)
Gerd Hoffmann5a248282012-01-27 17:27:31 +0100981{
982 uint32_t int_mask = 0;
983 uint32_t plink = td->link;
Gerd Hoffmann5a248282012-01-27 17:27:31 +0100984 UHCI_TD ptd;
985 int ret;
986
Hans de Goede6ba43f12012-10-24 18:14:09 +0200987 while (is_valid(plink)) {
Hans de Goedea4f30cd2012-10-24 18:31:12 +0200988 uhci_read_td(q->uhci, &ptd, plink);
Gerd Hoffmann5a248282012-01-27 17:27:31 +0100989 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
990 break;
991 }
Hans de Goedea4f30cd2012-10-24 18:31:12 +0200992 if (uhci_queue_token(&ptd) != q->token) {
Gerd Hoffmann5a248282012-01-27 17:27:31 +0100993 break;
994 }
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +0100995 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
Hans de Goede66a08cb2012-10-24 18:31:15 +0200996 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask);
Gerd Hoffmann52b0fec2012-03-21 18:25:25 +0100997 if (ret == TD_RESULT_ASYNC_CONT) {
998 break;
999 }
Gerd Hoffmann4efe4ef2012-03-09 11:15:41 +01001000 assert(ret == TD_RESULT_ASYNC_START);
Gerd Hoffmann5a248282012-01-27 17:27:31 +01001001 assert(int_mask == 0);
1002 plink = ptd.link;
1003 }
Hans de Goede11d15e42012-10-24 18:31:13 +02001004 usb_device_flush_ep_queue(q->ep->dev, q->ep);
Gerd Hoffmann5a248282012-01-27 17:27:31 +01001005}
1006
aliguori54f254f2008-08-21 19:30:31 +00001007static void uhci_process_frame(UHCIState *s)
1008{
1009 uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
Gerd Hoffmann4aed20e2012-05-11 09:18:05 +02001010 uint32_t curr_qh, td_count = 0;
aliguori54f254f2008-08-21 19:30:31 +00001011 int cnt, ret;
pbrook4d611c92006-08-12 01:04:27 +00001012 UHCI_TD td;
aliguori54f254f2008-08-21 19:30:31 +00001013 UHCI_QH qh;
1014 QhDb qhdb;
pbrook4d611c92006-08-12 01:04:27 +00001015
aliguori54f254f2008-08-21 19:30:31 +00001016 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
balrogb9dc0332007-10-04 22:47:34 +00001017
David Gibson9fe2fd62011-11-04 12:03:38 +11001018 pci_dma_read(&s->dev, frame_addr, &link, 4);
aliguori54f254f2008-08-21 19:30:31 +00001019 le32_to_cpus(&link);
balrogb9dc0332007-10-04 22:47:34 +00001020
aliguori54f254f2008-08-21 19:30:31 +00001021 int_mask = 0;
1022 curr_qh = 0;
balrogb9dc0332007-10-04 22:47:34 +00001023
aliguori54f254f2008-08-21 19:30:31 +00001024 qhdb_reset(&qhdb);
1025
1026 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
Hans de Goede88793812012-11-17 12:11:49 +01001027 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) {
Gerd Hoffmann4aed20e2012-05-11 09:18:05 +02001028 /* We've reached the usb 1.1 bandwidth, which is
1029 1280 bytes/frame, stop processing */
1030 trace_usb_uhci_frame_stop_bandwidth();
1031 break;
1032 }
aliguori54f254f2008-08-21 19:30:31 +00001033 if (is_qh(link)) {
1034 /* QH */
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +01001035 trace_usb_uhci_qh_load(link & ~0xf);
aliguori54f254f2008-08-21 19:30:31 +00001036
1037 if (qhdb_insert(&qhdb, link)) {
1038 /*
1039 * We're going in circles. Which is not a bug because
Gerd Hoffmann3200d102012-01-26 13:57:40 +01001040 * HCD is allowed to do that as part of the BW management.
1041 *
Gerd Hoffmann4aed20e2012-05-11 09:18:05 +02001042 * Stop processing here if no transaction has been done
1043 * since we've been here last time.
aliguori54f254f2008-08-21 19:30:31 +00001044 */
Gerd Hoffmann3200d102012-01-26 13:57:40 +01001045 if (td_count == 0) {
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +01001046 trace_usb_uhci_frame_loop_stop_idle();
Gerd Hoffmann3200d102012-01-26 13:57:40 +01001047 break;
Gerd Hoffmann3200d102012-01-26 13:57:40 +01001048 } else {
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +01001049 trace_usb_uhci_frame_loop_continue();
Gerd Hoffmann3200d102012-01-26 13:57:40 +01001050 td_count = 0;
1051 qhdb_reset(&qhdb);
1052 qhdb_insert(&qhdb, link);
1053 }
aliguori54f254f2008-08-21 19:30:31 +00001054 }
1055
David Gibson9fe2fd62011-11-04 12:03:38 +11001056 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
aliguori54f254f2008-08-21 19:30:31 +00001057 le32_to_cpus(&qh.link);
1058 le32_to_cpus(&qh.el_link);
1059
aliguori54f254f2008-08-21 19:30:31 +00001060 if (!is_valid(qh.el_link)) {
1061 /* QH w/o elements */
1062 curr_qh = 0;
1063 link = qh.link;
1064 } else {
1065 /* QH with elements */
Paolo Bonzini72e21db2018-12-13 23:37:36 +01001066 curr_qh = link;
1067 link = qh.el_link;
aliguori54f254f2008-08-21 19:30:31 +00001068 }
1069 continue;
pbrook4d611c92006-08-12 01:04:27 +00001070 }
aliguori54f254f2008-08-21 19:30:31 +00001071
1072 /* TD */
Hans de Goede963a68b2012-10-24 18:31:11 +02001073 uhci_read_td(s, &td, link);
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +01001074 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token);
aliguori54f254f2008-08-21 19:30:31 +00001075
1076 old_td_ctrl = td.ctrl;
Hans de Goede66a08cb2012-10-24 18:31:15 +02001077 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask);
aliguori54f254f2008-08-21 19:30:31 +00001078 if (old_td_ctrl != td.ctrl) {
1079 /* update the status bits of the TD */
1080 val = cpu_to_le32(td.ctrl);
David Gibson9fe2fd62011-11-04 12:03:38 +11001081 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
aliguori54f254f2008-08-21 19:30:31 +00001082 }
1083
Gerd Hoffmann971a5a42012-01-27 16:38:42 +01001084 switch (ret) {
Gerd Hoffmann60e1b2a2012-03-09 11:09:49 +01001085 case TD_RESULT_STOP_FRAME: /* interrupted frame */
Gerd Hoffmann971a5a42012-01-27 16:38:42 +01001086 goto out;
aliguori54f254f2008-08-21 19:30:31 +00001087
Gerd Hoffmann60e1b2a2012-03-09 11:09:49 +01001088 case TD_RESULT_NEXT_QH:
Gerd Hoffmann4efe4ef2012-03-09 11:15:41 +01001089 case TD_RESULT_ASYNC_CONT:
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +01001090 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf);
aliguori54f254f2008-08-21 19:30:31 +00001091 link = curr_qh ? qh.link : td.link;
1092 continue;
aliguori54f254f2008-08-21 19:30:31 +00001093
Gerd Hoffmann4efe4ef2012-03-09 11:15:41 +01001094 case TD_RESULT_ASYNC_START:
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +01001095 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf);
Gerd Hoffmann971a5a42012-01-27 16:38:42 +01001096 link = curr_qh ? qh.link : td.link;
1097 continue;
aliguori54f254f2008-08-21 19:30:31 +00001098
Gerd Hoffmann60e1b2a2012-03-09 11:09:49 +01001099 case TD_RESULT_COMPLETE:
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +01001100 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf);
Gerd Hoffmann971a5a42012-01-27 16:38:42 +01001101 link = td.link;
1102 td_count++;
Gerd Hoffmann4aed20e2012-05-11 09:18:05 +02001103 s->frame_bytes += (td.ctrl & 0x7ff) + 1;
aliguori54f254f2008-08-21 19:30:31 +00001104
Gerd Hoffmann971a5a42012-01-27 16:38:42 +01001105 if (curr_qh) {
1106 /* update QH element link */
1107 qh.el_link = link;
1108 val = cpu_to_le32(qh.el_link);
1109 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
aliguori54f254f2008-08-21 19:30:31 +00001110
Gerd Hoffmann971a5a42012-01-27 16:38:42 +01001111 if (!depth_first(link)) {
1112 /* done with this QH */
Gerd Hoffmann971a5a42012-01-27 16:38:42 +01001113 curr_qh = 0;
1114 link = qh.link;
1115 }
aliguori54f254f2008-08-21 19:30:31 +00001116 }
Gerd Hoffmann971a5a42012-01-27 16:38:42 +01001117 break;
1118
1119 default:
1120 assert(!"unknown return code");
aliguori54f254f2008-08-21 19:30:31 +00001121 }
1122
1123 /* go to the next entry */
pbrook4d611c92006-08-12 01:04:27 +00001124 }
aliguori54f254f2008-08-21 19:30:31 +00001125
Gerd Hoffmann971a5a42012-01-27 16:38:42 +01001126out:
David S. Ahern8e65b7c2010-02-03 08:49:39 -07001127 s->pending_int_mask |= int_mask;
pbrook4d611c92006-08-12 01:04:27 +00001128}
1129
Gerd Hoffmann9a16c592012-05-11 09:33:07 +02001130static void uhci_bh(void *opaque)
1131{
1132 UHCIState *s = opaque;
1133 uhci_process_frame(s);
1134}
1135
bellardbb36d472005-11-05 14:22:28 +00001136static void uhci_frame_timer(void *opaque)
1137{
1138 UHCIState *s = opaque;
Hans de Goedef8f48b62012-12-14 14:35:36 +01001139 uint64_t t_now, t_last_run;
1140 int i, frames;
Rutuja Shah73bcb242016-03-21 21:32:30 +05301141 const uint64_t frame_t = NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ;
David S. Ahern8e65b7c2010-02-03 08:49:39 -07001142
Hans de Goede88793812012-11-17 12:11:49 +01001143 s->completions_only = false;
Gerd Hoffmann9a16c592012-05-11 09:33:07 +02001144 qemu_bh_cancel(s->bh);
bellardbb36d472005-11-05 14:22:28 +00001145
1146 if (!(s->cmd & UHCI_CMD_RS)) {
aliguori54f254f2008-08-21 19:30:31 +00001147 /* Full stop */
Gerd Hoffmann50dcc0f2012-03-08 13:12:38 +01001148 trace_usb_uhci_schedule_stop();
Alex Blighbc72ad62013-08-21 16:03:08 +01001149 timer_del(s->frame_timer);
Gerd Hoffmannd9a528d2012-03-08 13:37:52 +01001150 uhci_async_cancel_all(s);
bellard52328142006-04-24 21:38:50 +00001151 /* set hchalted bit in status - UHCI11D 2.1.2 */
1152 s->status |= UHCI_STS_HCHALTED;
bellardbb36d472005-11-05 14:22:28 +00001153 return;
1154 }
aliguori54f254f2008-08-21 19:30:31 +00001155
Hans de Goedef8f48b62012-12-14 14:35:36 +01001156 /* We still store expire_time in our state, for migration */
1157 t_last_run = s->expire_time - frame_t;
Alex Blighbc72ad62013-08-21 16:03:08 +01001158 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
balrogb9dc0332007-10-04 22:47:34 +00001159
Hans de Goedef8f48b62012-12-14 14:35:36 +01001160 /* Process up to MAX_FRAMES_PER_TICK frames */
1161 frames = (t_now - t_last_run) / frame_t;
Hans de Goede9fdf7022012-12-14 14:35:37 +01001162 if (frames > s->maxframes) {
1163 int skipped = frames - s->maxframes;
1164 s->expire_time += skipped * frame_t;
1165 s->frnum = (s->frnum + skipped) & 0x7ff;
1166 frames -= skipped;
1167 }
Hans de Goedef8f48b62012-12-14 14:35:36 +01001168 if (frames > MAX_FRAMES_PER_TICK) {
1169 frames = MAX_FRAMES_PER_TICK;
1170 }
aliguori54f254f2008-08-21 19:30:31 +00001171
Hans de Goedef8f48b62012-12-14 14:35:36 +01001172 for (i = 0; i < frames; i++) {
1173 s->frame_bytes = 0;
1174 trace_usb_uhci_frame_start(s->frnum);
1175 uhci_async_validate_begin(s);
1176 uhci_process_frame(s);
1177 uhci_async_validate_end(s);
1178 /* The spec says frnum is the frame currently being processed, and
1179 * the guest must look at frnum - 1 on interrupt, so inc frnum now */
1180 s->frnum = (s->frnum + 1) & 0x7ff;
1181 s->expire_time += frame_t;
1182 }
aliguori54f254f2008-08-21 19:30:31 +00001183
Hans de Goedef8f48b62012-12-14 14:35:36 +01001184 /* Complete the previous frame(s) */
Hans de Goede719c1302012-12-14 14:35:33 +01001185 if (s->pending_int_mask) {
1186 s->status2 |= s->pending_int_mask;
1187 s->status |= UHCI_STS_USBINT;
1188 uhci_update_irq(s);
1189 }
1190 s->pending_int_mask = 0;
1191
Alex Blighbc72ad62013-08-21 16:03:08 +01001192 timer_mod(s->frame_timer, t_now + frame_t);
bellardbb36d472005-11-05 14:22:28 +00001193}
1194
Avi Kivitya03f66e2011-08-08 16:09:24 +03001195static const MemoryRegionOps uhci_ioport_ops = {
Gerd Hoffmann89eb1472013-01-03 12:29:41 +01001196 .read = uhci_port_read,
1197 .write = uhci_port_write,
1198 .valid.min_access_size = 1,
1199 .valid.max_access_size = 4,
1200 .impl.min_access_size = 2,
1201 .impl.max_access_size = 2,
1202 .endianness = DEVICE_LITTLE_ENDIAN,
Avi Kivitya03f66e2011-08-08 16:09:24 +03001203};
bellardbb36d472005-11-05 14:22:28 +00001204
Gerd Hoffmann0d86d2b2010-12-01 11:08:44 +01001205static USBPortOps uhci_port_ops = {
1206 .attach = uhci_attach,
Gerd Hoffmann618c1692010-12-01 11:27:05 +01001207 .detach = uhci_detach,
Hans de Goede4706ab62011-06-24 12:31:11 +02001208 .child_detach = uhci_child_detach,
Gerd Hoffmann9159f672010-12-01 11:47:40 +01001209 .wakeup = uhci_wakeup,
Gerd Hoffmann13a9a0d2010-12-16 17:03:44 +01001210 .complete = uhci_async_complete,
Gerd Hoffmann0d86d2b2010-12-01 11:08:44 +01001211};
1212
Gerd Hoffmann07771f62011-05-23 17:37:12 +02001213static USBBusOps uhci_bus_ops = {
Gerd Hoffmann07771f62011-05-23 17:37:12 +02001214};
1215
Markus Armbruster63216dc2015-02-17 14:28:05 +01001216static void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
bellardbb36d472005-11-05 14:22:28 +00001217{
Markus Armbrusterf4bbaaf2015-02-17 14:28:02 +01001218 Error *err = NULL;
Gerd Hoffmann973002c2012-05-25 12:53:47 +02001219 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
Gerd Hoffmann8f3f90b2012-10-26 14:56:19 +02001220 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class);
Gonglei49184b62015-05-06 20:55:23 +08001221 UHCIState *s = UHCI(dev);
Gerd Hoffmann6cf9b6f2009-08-31 14:24:02 +02001222 uint8_t *pci_conf = s->dev.config;
bellardbb36d472005-11-05 14:22:28 +00001223 int i;
1224
Michael S. Tsirkindb579e92009-12-10 19:25:03 +02001225 pci_conf[PCI_CLASS_PROG] = 0x00;
Michael S. Tsirkindb579e92009-12-10 19:25:03 +02001226 /* TODO: reset value should be 0. */
Brad Hardse59d33a2011-06-02 11:18:47 +10001227 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
ths3b46e622007-09-17 08:09:54 +00001228
Marcel Apfelbaum9e64f8a2013-10-07 10:36:39 +03001229 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1);
Gerd Hoffmann973002c2012-05-25 12:53:47 +02001230
Hans de Goede35e49772011-06-24 17:44:53 +02001231 if (s->masterbus) {
1232 USBPort *ports[NB_PORTS];
1233 for(i = 0; i < NB_PORTS; i++) {
1234 ports[i] = &s->ports[i].port;
1235 }
Markus Armbrusterf4bbaaf2015-02-17 14:28:02 +01001236 usb_register_companion(s->masterbus, ports, NB_PORTS,
1237 s->firstport, s, &uhci_port_ops,
1238 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL,
1239 &err);
1240 if (err) {
Markus Armbruster63216dc2015-02-17 14:28:05 +01001241 error_propagate(errp, err);
1242 return;
Hans de Goede35e49772011-06-24 17:44:53 +02001243 }
1244 } else {
Andreas Färberc889b3a2013-08-23 20:32:04 +02001245 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev));
Hans de Goede35e49772011-06-24 17:44:53 +02001246 for (i = 0; i < NB_PORTS; i++) {
1247 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1248 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1249 }
bellardbb36d472005-11-05 14:22:28 +00001250 }
Gerd Hoffmann9a16c592012-05-11 09:33:07 +02001251 s->bh = qemu_bh_new(uhci_bh, s);
Alex Blighbc72ad62013-08-21 16:03:08 +01001252 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s);
Juan Quintela64e58fe2009-10-14 12:21:50 +02001253 s->num_ports_vmstate = NB_PORTS;
Gerd Hoffmannf8af1e82012-01-27 14:17:06 +01001254 QTAILQ_INIT(&s->queues);
bellardbb36d472005-11-05 14:22:28 +00001255
Paolo Bonzini22fc8602013-06-06 21:25:08 -04001256 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s,
1257 "uhci", 0x20);
1258
pbrook38ca0f62006-03-11 18:03:38 +00001259 /* Use region 4 for consistency with real hardware. BSD guests seem
1260 to rely on this. */
Avi Kivitye824b2c2011-08-08 16:09:31 +03001261 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
Gerd Hoffmann6cf9b6f2009-08-31 14:24:02 +02001262}
1263
Markus Armbruster63216dc2015-02-17 14:28:05 +01001264static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp)
Huacai Chen30235a52010-06-29 10:50:09 +08001265{
Gonglei49184b62015-05-06 20:55:23 +08001266 UHCIState *s = UHCI(dev);
Huacai Chen30235a52010-06-29 10:50:09 +08001267 uint8_t *pci_conf = s->dev.config;
1268
Huacai Chen30235a52010-06-29 10:50:09 +08001269 /* USB misc control 1/2 */
1270 pci_set_long(pci_conf + 0x40,0x00001000);
1271 /* PM capability */
1272 pci_set_long(pci_conf + 0x80,0x00020001);
1273 /* USB legacy support */
1274 pci_set_long(pci_conf + 0xc0,0x00002000);
1275
Markus Armbruster63216dc2015-02-17 14:28:05 +01001276 usb_uhci_common_realize(dev, errp);
Huacai Chen30235a52010-06-29 10:50:09 +08001277}
1278
Gonglei3a3464b2014-06-04 16:31:49 +08001279static void usb_uhci_exit(PCIDevice *dev)
1280{
Gonglei49184b62015-05-06 20:55:23 +08001281 UHCIState *s = UHCI(dev);
Gonglei3a3464b2014-06-04 16:31:49 +08001282
Gongleid733f742014-06-04 16:31:55 +08001283 trace_usb_uhci_exit();
1284
Gonglei3a3464b2014-06-04 16:31:49 +08001285 if (s->frame_timer) {
Gonglei3a3464b2014-06-04 16:31:49 +08001286 timer_free(s->frame_timer);
1287 s->frame_timer = NULL;
1288 }
1289
1290 if (s->bh) {
1291 qemu_bh_delete(s->bh);
1292 }
1293
1294 uhci_async_cancel_all(s);
1295
1296 if (!s->masterbus) {
1297 usb_bus_release(&s->bus);
1298 }
1299}
1300
Gerd Hoffmann638ca932014-08-29 14:13:11 +02001301static Property uhci_properties_companion[] = {
Gerd Hoffmann1b5a7572011-07-01 09:48:49 +02001302 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1303 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
Gerd Hoffmann40141d12012-05-11 10:02:53 +02001304 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
Hans de Goede9fdf7022012-12-14 14:35:37 +01001305 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128),
Gerd Hoffmann1b5a7572011-07-01 09:48:49 +02001306 DEFINE_PROP_END_OF_LIST(),
1307};
Gerd Hoffmann638ca932014-08-29 14:13:11 +02001308static Property uhci_properties_standalone[] = {
1309 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1310 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128),
1311 DEFINE_PROP_END_OF_LIST(),
1312};
Gerd Hoffmann1b5a7572011-07-01 09:48:49 +02001313
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001314static void uhci_class_init(ObjectClass *klass, void *data)
Anthony Liguori40021f02011-12-04 12:22:06 -06001315{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001316 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -06001317 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
Gonglei49184b62015-05-06 20:55:23 +08001318
1319 k->class_id = PCI_CLASS_SERIAL_USB;
1320 dc->vmsd = &vmstate_uhci;
1321 dc->reset = uhci_reset;
1322 set_bit(DEVICE_CATEGORY_USB, dc->categories);
1323}
1324
1325static const TypeInfo uhci_pci_type_info = {
1326 .name = TYPE_UHCI,
1327 .parent = TYPE_PCI_DEVICE,
1328 .instance_size = sizeof(UHCIState),
1329 .class_size = sizeof(UHCIPCIDeviceClass),
1330 .abstract = true,
1331 .class_init = uhci_class_init,
Eduardo Habkostfd3b02c2017-09-27 16:56:34 -03001332 .interfaces = (InterfaceInfo[]) {
1333 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1334 { },
1335 },
Gonglei49184b62015-05-06 20:55:23 +08001336};
1337
1338static void uhci_data_class_init(ObjectClass *klass, void *data)
1339{
1340 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1341 DeviceClass *dc = DEVICE_CLASS(klass);
Gerd Hoffmann8f3f90b2012-10-26 14:56:19 +02001342 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class);
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001343 UHCIInfo *info = data;
Anthony Liguori40021f02011-12-04 12:22:06 -06001344
Markus Armbruster63216dc2015-02-17 14:28:05 +01001345 k->realize = info->realize ? info->realize : usb_uhci_common_realize;
Gonglei3a3464b2014-06-04 16:31:49 +08001346 k->exit = info->unplug ? usb_uhci_exit : NULL;
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001347 k->vendor_id = info->vendor_id;
1348 k->device_id = info->device_id;
1349 k->revision = info->revision;
Gerd Hoffmann638ca932014-08-29 14:13:11 +02001350 if (!info->unplug) {
1351 /* uhci controllers in companion setups can't be hotplugged */
1352 dc->hotpluggable = false;
Marc-André Lureau4f67d302020-01-10 19:30:32 +04001353 device_class_set_props(dc, uhci_properties_companion);
Gerd Hoffmann638ca932014-08-29 14:13:11 +02001354 } else {
Marc-André Lureau4f67d302020-01-10 19:30:32 +04001355 device_class_set_props(dc, uhci_properties_standalone);
Gerd Hoffmann638ca932014-08-29 14:13:11 +02001356 }
Gerd Hoffmann8f3f90b2012-10-26 14:56:19 +02001357 u->info = *info;
Anthony Liguori40021f02011-12-04 12:22:06 -06001358}
1359
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001360static UHCIInfo uhci_info[] = {
1361 {
1362 .name = "piix3-usb-uhci",
1363 .vendor_id = PCI_VENDOR_ID_INTEL,
1364 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2,
1365 .revision = 0x01,
Gerd Hoffmann8f3f90b2012-10-26 14:56:19 +02001366 .irq_pin = 3,
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001367 .unplug = true,
1368 },{
1369 .name = "piix4-usb-uhci",
1370 .vendor_id = PCI_VENDOR_ID_INTEL,
1371 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2,
1372 .revision = 0x01,
Gerd Hoffmann8f3f90b2012-10-26 14:56:19 +02001373 .irq_pin = 3,
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001374 .unplug = true,
1375 },{
1376 .name = "vt82c686b-usb-uhci",
1377 .vendor_id = PCI_VENDOR_ID_VIA,
1378 .device_id = PCI_DEVICE_ID_VIA_UHCI,
1379 .revision = 0x01,
Gerd Hoffmann8f3f90b2012-10-26 14:56:19 +02001380 .irq_pin = 3,
Markus Armbruster63216dc2015-02-17 14:28:05 +01001381 .realize = usb_uhci_vt82c686b_realize,
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001382 .unplug = true,
1383 },{
Gerd Hoffmann74625ea2012-10-30 09:57:28 +01001384 .name = "ich9-usb-uhci1", /* 00:1d.0 */
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001385 .vendor_id = PCI_VENDOR_ID_INTEL,
1386 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1,
1387 .revision = 0x03,
Gerd Hoffmann8f3f90b2012-10-26 14:56:19 +02001388 .irq_pin = 0,
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001389 .unplug = false,
1390 },{
Gerd Hoffmann74625ea2012-10-30 09:57:28 +01001391 .name = "ich9-usb-uhci2", /* 00:1d.1 */
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001392 .vendor_id = PCI_VENDOR_ID_INTEL,
1393 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2,
1394 .revision = 0x03,
Gerd Hoffmann8f3f90b2012-10-26 14:56:19 +02001395 .irq_pin = 1,
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001396 .unplug = false,
1397 },{
Gerd Hoffmann74625ea2012-10-30 09:57:28 +01001398 .name = "ich9-usb-uhci3", /* 00:1d.2 */
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001399 .vendor_id = PCI_VENDOR_ID_INTEL,
1400 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3,
1401 .revision = 0x03,
Gerd Hoffmann8f3f90b2012-10-26 14:56:19 +02001402 .irq_pin = 2,
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001403 .unplug = false,
Gerd Hoffmann74625ea2012-10-30 09:57:28 +01001404 },{
1405 .name = "ich9-usb-uhci4", /* 00:1a.0 */
1406 .vendor_id = PCI_VENDOR_ID_INTEL,
1407 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4,
1408 .revision = 0x03,
1409 .irq_pin = 0,
1410 .unplug = false,
1411 },{
1412 .name = "ich9-usb-uhci5", /* 00:1a.1 */
1413 .vendor_id = PCI_VENDOR_ID_INTEL,
1414 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5,
1415 .revision = 0x03,
1416 .irq_pin = 1,
1417 .unplug = false,
1418 },{
1419 .name = "ich9-usb-uhci6", /* 00:1a.2 */
1420 .vendor_id = PCI_VENDOR_ID_INTEL,
1421 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6,
1422 .revision = 0x03,
1423 .irq_pin = 2,
1424 .unplug = false,
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001425 }
Gerd Hoffmann6cf9b6f2009-08-31 14:24:02 +02001426};
1427
Andreas Färber83f7d432012-02-09 15:20:55 +01001428static void uhci_register_types(void)
Gerd Hoffmann6cf9b6f2009-08-31 14:24:02 +02001429{
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001430 TypeInfo uhci_type_info = {
Gonglei49184b62015-05-06 20:55:23 +08001431 .parent = TYPE_UHCI,
1432 .class_init = uhci_data_class_init,
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001433 };
1434 int i;
1435
Gonglei49184b62015-05-06 20:55:23 +08001436 type_register_static(&uhci_pci_type_info);
1437
Gerd Hoffmann2c2e8522012-10-25 16:22:57 +02001438 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) {
1439 uhci_type_info.name = uhci_info[i].name;
1440 uhci_type_info.class_data = uhci_info + i;
1441 type_register(&uhci_type_info);
1442 }
Gerd Hoffmann6cf9b6f2009-08-31 14:24:02 +02001443}
Andreas Färber83f7d432012-02-09 15:20:55 +01001444
1445type_init(uhci_register_types)