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ths81fdc5f2007-10-08 13:04:02 +00001/*
2 * CRIS virtual CPU header
3 *
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
ths81fdc5f2007-10-08 13:04:02 +000019 */
20#ifndef CPU_CRIS_H
21#define CPU_CRIS_H
22
23#define TARGET_LONG_BITS 32
24
pbrookc2764712009-03-07 15:24:59 +000025#define CPUState struct CPUCRISState
26
ths81fdc5f2007-10-08 13:04:02 +000027#include "cpu-defs.h"
28
ths81fdc5f2007-10-08 13:04:02 +000029#define TARGET_HAS_ICE 1
30
31#define ELF_MACHINE EM_CRIS
32
edgar_igl1b1a38b2008-06-09 23:18:06 +000033#define EXCP_NMI 1
34#define EXCP_GURU 2
35#define EXCP_BUSFAULT 3
36#define EXCP_IRQ 4
37#define EXCP_BREAK 5
ths81fdc5f2007-10-08 13:04:02 +000038
edgar_iglb41f7df2008-05-02 22:16:17 +000039/* Register aliases. R0 - R15 */
40#define R_FP 8
41#define R_SP 14
42#define R_ACR 15
43
44/* Support regs, P0 - P15 */
45#define PR_BZ 0
46#define PR_VR 1
47#define PR_PID 2
48#define PR_SRS 3
49#define PR_WZ 4
50#define PR_EXS 5
51#define PR_EDA 6
52#define PR_MOF 7
53#define PR_DZ 8
54#define PR_EBP 9
55#define PR_ERP 10
56#define PR_SRP 11
edgar_igl1b1a38b2008-06-09 23:18:06 +000057#define PR_NRP 12
edgar_iglb41f7df2008-05-02 22:16:17 +000058#define PR_CCS 13
59#define PR_USP 14
60#define PR_SPC 15
61
ths81fdc5f2007-10-08 13:04:02 +000062/* CPU flags. */
edgar_igl1b1a38b2008-06-09 23:18:06 +000063#define Q_FLAG 0x80000000
64#define M_FLAG 0x40000000
ths81fdc5f2007-10-08 13:04:02 +000065#define S_FLAG 0x200
66#define R_FLAG 0x100
67#define P_FLAG 0x80
68#define U_FLAG 0x40
ths81fdc5f2007-10-08 13:04:02 +000069#define I_FLAG 0x20
70#define X_FLAG 0x10
71#define N_FLAG 0x08
72#define Z_FLAG 0x04
73#define V_FLAG 0x02
74#define C_FLAG 0x01
75#define ALU_FLAGS 0x1F
76
77/* Condition codes. */
78#define CC_CC 0
79#define CC_CS 1
80#define CC_NE 2
81#define CC_EQ 3
82#define CC_VC 4
83#define CC_VS 5
84#define CC_PL 6
85#define CC_MI 7
86#define CC_LS 8
87#define CC_HI 9
88#define CC_GE 10
89#define CC_LT 11
90#define CC_GT 12
91#define CC_LE 13
92#define CC_A 14
93#define CC_P 15
94
j_mayer6ebbf392007-10-14 07:07:08 +000095#define NB_MMU_MODES 2
96
ths81fdc5f2007-10-08 13:04:02 +000097typedef struct CPUCRISState {
ths81fdc5f2007-10-08 13:04:02 +000098 uint32_t regs[16];
edgar_iglb41f7df2008-05-02 22:16:17 +000099 /* P0 - P15 are referred to as special registers in the docs. */
ths81fdc5f2007-10-08 13:04:02 +0000100 uint32_t pregs[16];
edgar_iglb41f7df2008-05-02 22:16:17 +0000101
102 /* Pseudo register for the PC. Not directly accessable on CRIS. */
ths81fdc5f2007-10-08 13:04:02 +0000103 uint32_t pc;
ths81fdc5f2007-10-08 13:04:02 +0000104
edgar_iglb41f7df2008-05-02 22:16:17 +0000105 /* Pseudo register for the kernel stack. */
106 uint32_t ksp;
107
edgar_iglcf1d97f2008-05-13 10:59:14 +0000108 /* Branch. */
109 int dslot;
ths81fdc5f2007-10-08 13:04:02 +0000110 int btaken;
edgar_iglcf1d97f2008-05-13 10:59:14 +0000111 uint32_t btarget;
ths81fdc5f2007-10-08 13:04:02 +0000112
ths81fdc5f2007-10-08 13:04:02 +0000113 /* Condition flag tracking. */
114 uint32_t cc_op;
115 uint32_t cc_mask;
116 uint32_t cc_dest;
117 uint32_t cc_src;
118 uint32_t cc_result;
ths81fdc5f2007-10-08 13:04:02 +0000119 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
120 int cc_size;
edgar_igl30abcfc2008-05-27 21:10:56 +0000121 /* X flag at the time of cc snapshot. */
ths81fdc5f2007-10-08 13:04:02 +0000122 int cc_x;
123
edgar_igl786c02f2008-03-14 01:08:09 +0000124 int interrupt_vector;
125 int fault_vector;
126 int trap_vector;
127
edgar_iglb41f7df2008-05-02 22:16:17 +0000128 /* FIXME: add a check in the translator to avoid writing to support
129 register sets beyond the 4th. The ISA allows up to 256! but in
130 practice there is no core that implements more than 4.
131
132 Support function registers are used to control units close to the
133 core. Accesses do not pass down the normal hierarchy.
134 */
135 uint32_t sregs[4][16];
136
edgar_igl44cd42e2008-05-11 14:28:14 +0000137 /* Linear feedback shift reg in the mmu. Used to provide pseudo
138 randomness for the 'hint' the mmu gives to sw for chosing valid
139 sets on TLB refills. */
140 uint32_t mmu_rand_lfsr;
141
edgar_iglb41f7df2008-05-02 22:16:17 +0000142 /*
143 * We just store the stores to the tlbset here for later evaluation
144 * when the hw needs access to them.
145 *
146 * One for I and another for D.
147 */
148 struct
149 {
150 uint32_t hi;
151 uint32_t lo;
152 } tlbsets[2][4][16];
153
ths81fdc5f2007-10-08 13:04:02 +0000154 CPU_COMMON
155} CPUCRISState;
156
bellardaaed9092007-11-10 15:15:54 +0000157CPUCRISState *cpu_cris_init(const char *cpu_model);
ths81fdc5f2007-10-08 13:04:02 +0000158int cpu_cris_exec(CPUCRISState *s);
159void cpu_cris_close(CPUCRISState *s);
160void do_interrupt(CPUCRISState *env);
161/* you can call this signal handler from your SIGBUS and SIGSEGV
162 signal handlers to inform the virtual CPU of exceptions. non zero
163 is returned if the signal was handled by the virtual CPU. */
164int cpu_cris_signal_handler(int host_signum, void *pinfo,
165 void *puc);
ths81fdc5f2007-10-08 13:04:02 +0000166
167enum {
168 CC_OP_DYNAMIC, /* Use env->cc_op */
169 CC_OP_FLAGS,
ths81fdc5f2007-10-08 13:04:02 +0000170 CC_OP_CMP,
171 CC_OP_MOVE,
ths81fdc5f2007-10-08 13:04:02 +0000172 CC_OP_ADD,
173 CC_OP_ADDC,
174 CC_OP_MCP,
175 CC_OP_ADDU,
176 CC_OP_SUB,
177 CC_OP_SUBU,
178 CC_OP_NEG,
179 CC_OP_BTST,
180 CC_OP_MULS,
181 CC_OP_MULU,
182 CC_OP_DSTEP,
183 CC_OP_BOUND,
184
185 CC_OP_OR,
186 CC_OP_AND,
187 CC_OP_XOR,
188 CC_OP_LSL,
189 CC_OP_LSR,
190 CC_OP_ASR,
191 CC_OP_LZ
192};
193
ths81fdc5f2007-10-08 13:04:02 +0000194/* CRIS uses 8k pages. */
195#define TARGET_PAGE_BITS 13
pbrookbb7ec042008-03-25 22:28:25 +0000196#define MMAP_SHIFT TARGET_PAGE_BITS
ths81fdc5f2007-10-08 13:04:02 +0000197
ths81fdc5f2007-10-08 13:04:02 +0000198#define cpu_init cpu_cris_init
199#define cpu_exec cpu_cris_exec
200#define cpu_gen_code cpu_cris_gen_code
201#define cpu_signal_handler cpu_cris_signal_handler
202
pbrookb3c77242008-06-30 16:31:04 +0000203#define CPU_SAVE_VERSION 1
204
j_mayer6ebbf392007-10-14 07:07:08 +0000205/* MMU modes definitions */
206#define MMU_MODE0_SUFFIX _kernel
207#define MMU_MODE1_SUFFIX _user
208#define MMU_USER_IDX 1
j_mayer6ebbf392007-10-14 07:07:08 +0000209static inline int cpu_mmu_index (CPUState *env)
210{
edgar_iglb41f7df2008-05-02 22:16:17 +0000211 return !!(env->pregs[PR_CCS] & U_FLAG);
j_mayer6ebbf392007-10-14 07:07:08 +0000212}
213
edgar_iglcc53adb2009-02-22 11:59:59 +0000214int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
215 int mmu_idx, int is_softmmu);
Nathan Froyd0b5c1ce2009-08-10 13:37:36 -0700216#define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
edgar_iglcc53adb2009-02-22 11:59:59 +0000217
pbrook6e68e072008-05-30 17:22:15 +0000218#if defined(CONFIG_USER_ONLY)
219static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
220{
pbrookf8ed7072008-05-30 17:54:15 +0000221 if (newsp)
pbrook6e68e072008-05-30 17:22:15 +0000222 env->regs[14] = newsp;
223 env->regs[10] = 0;
224}
225#endif
226
edgar_iglef967792009-01-07 14:19:38 +0000227static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
228{
229 env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
230}
231
edgar_igl90046272008-02-28 08:28:32 +0000232/* Support function regs. */
ths81fdc5f2007-10-08 13:04:02 +0000233#define SFR_RW_GC_CFG 0][0
edgar_iglb41f7df2008-05-02 22:16:17 +0000234#define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
235#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
236#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
237#define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
238#define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
239#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
240#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
ths81fdc5f2007-10-08 13:04:02 +0000241
edgar_iglb41f7df2008-05-02 22:16:17 +0000242#include "cpu-all.h"
aliguori622ed362008-11-18 19:36:03 +0000243#include "exec-all.h"
244
245static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
246{
247 env->pc = tb->pc;
248}
249
aliguori6b917542008-11-18 19:46:41 +0000250static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
251 target_ulong *cs_base, int *flags)
252{
253 *pc = env->pc;
254 *cs_base = 0;
255 *flags = env->dslot |
256 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG | X_FLAG));
257}
258
ths81fdc5f2007-10-08 13:04:02 +0000259#endif