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bellardab93bbe2003-08-10 21:35:13 +00001/*
2 * common defines for all CPUs
ths5fafdf22007-09-16 21:08:06 +00003 *
bellardab93bbe2003-08-10 21:35:13 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef CPU_DEFS_H
21#define CPU_DEFS_H
22
pbrook87ecb682007-11-17 17:14:51 +000023#ifndef NEED_CPU_H
24#error cpu.h included from common code
25#endif
26
bellardab93bbe2003-08-10 21:35:13 +000027#include "config.h"
28#include <setjmp.h>
bellarded1c0bc2004-02-16 22:17:43 +000029#include <inttypes.h>
30#include "osdep.h"
bellardab93bbe2003-08-10 21:35:13 +000031
bellard35b66fc2004-01-24 15:26:06 +000032#ifndef TARGET_LONG_BITS
33#error TARGET_LONG_BITS must be defined before including this header
34#endif
35
ths5fafdf22007-09-16 21:08:06 +000036#ifndef TARGET_PHYS_ADDR_BITS
bellard4f2ac232004-04-26 19:44:02 +000037#if TARGET_LONG_BITS >= HOST_LONG_BITS
bellardab6d9602004-04-25 21:25:15 +000038#define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
bellard4f2ac232004-04-26 19:44:02 +000039#else
40#define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
41#endif
bellardab6d9602004-04-25 21:25:15 +000042#endif
43
bellard35b66fc2004-01-24 15:26:06 +000044#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
45
bellardab6d9602004-04-25 21:25:15 +000046/* target_ulong is the type of a virtual address */
bellard35b66fc2004-01-24 15:26:06 +000047#if TARGET_LONG_SIZE == 4
48typedef int32_t target_long;
49typedef uint32_t target_ulong;
bellardc27004e2005-01-03 23:35:10 +000050#define TARGET_FMT_lx "%08x"
j_mayerb62b4612007-04-04 07:58:14 +000051#define TARGET_FMT_ld "%d"
j_mayer71c8b8f2007-09-19 05:46:03 +000052#define TARGET_FMT_lu "%u"
bellard35b66fc2004-01-24 15:26:06 +000053#elif TARGET_LONG_SIZE == 8
54typedef int64_t target_long;
55typedef uint64_t target_ulong;
bellard26a76462006-06-25 18:15:32 +000056#define TARGET_FMT_lx "%016" PRIx64
j_mayerb62b4612007-04-04 07:58:14 +000057#define TARGET_FMT_ld "%" PRId64
j_mayer71c8b8f2007-09-19 05:46:03 +000058#define TARGET_FMT_lu "%" PRIu64
bellard35b66fc2004-01-24 15:26:06 +000059#else
60#error TARGET_LONG_SIZE undefined
61#endif
62
bellardab6d9602004-04-25 21:25:15 +000063/* target_phys_addr_t is the type of a physical address (its size can
bellard4f2ac232004-04-26 19:44:02 +000064 be different from 'target_ulong'). We have sizeof(target_phys_addr)
65 = max(sizeof(unsigned long),
66 sizeof(size_of_target_physical_address)) because we must pass a
67 host pointer to memory operations in some cases */
68
bellardab6d9602004-04-25 21:25:15 +000069#if TARGET_PHYS_ADDR_BITS == 32
70typedef uint32_t target_phys_addr_t;
j_mayerba13c432007-04-14 12:15:36 +000071#define TARGET_FMT_plx "%08x"
bellardab6d9602004-04-25 21:25:15 +000072#elif TARGET_PHYS_ADDR_BITS == 64
73typedef uint64_t target_phys_addr_t;
j_mayerba13c432007-04-14 12:15:36 +000074#define TARGET_FMT_plx "%016" PRIx64
bellardab6d9602004-04-25 21:25:15 +000075#else
76#error TARGET_PHYS_ADDR_BITS undefined
77#endif
78
bellardf193c792004-03-21 17:06:25 +000079#define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
80
bellard2be00712005-07-02 22:09:27 +000081#define EXCP_INTERRUPT 0x10000 /* async interruption */
82#define EXCP_HLT 0x10001 /* hlt instruction reached */
83#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
bellard5a1e3cf2005-11-23 21:02:53 +000084#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
bellardab93bbe2003-08-10 21:35:13 +000085#define MAX_BREAKPOINTS 32
pbrook6658ffb2007-03-16 23:58:11 +000086#define MAX_WATCHPOINTS 32
bellardab93bbe2003-08-10 21:35:13 +000087
bellarda316d332005-11-20 10:32:34 +000088#define TB_JMP_CACHE_BITS 12
89#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
90
pbrookb362e5e2006-11-12 20:40:55 +000091/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
92 addresses on the same page. The top bits are the same. This allows
93 TLB invalidation to quickly clear a subset of the hash table. */
94#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
95#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
96#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
97#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
98
bellard84b7b8e2005-11-28 21:19:04 +000099#define CPU_TLB_BITS 8
100#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
bellardab93bbe2003-08-10 21:35:13 +0000101
bellardd6564692008-01-31 09:22:27 +0000102#if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
103#define CPU_TLB_ENTRY_BITS 4
104#else
105#define CPU_TLB_ENTRY_BITS 5
106#endif
107
bellardab93bbe2003-08-10 21:35:13 +0000108typedef struct CPUTLBEntry {
pbrook0f459d12008-06-09 00:20:13 +0000109 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
110 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
111 go directly to ram.
bellarddb8d7462003-10-27 21:12:17 +0000112 bit 3 : indicates that the entry is invalid
113 bit 2..0 : zero
114 */
ths5fafdf22007-09-16 21:08:06 +0000115 target_ulong addr_read;
116 target_ulong addr_write;
117 target_ulong addr_code;
pbrook0f459d12008-06-09 00:20:13 +0000118 /* Addend to virtual address to get physical address. IO accesses
119 use the correcponding iotlb value. */
bellardd6564692008-01-31 09:22:27 +0000120#if TARGET_PHYS_ADDR_BITS == 64
121 /* on i386 Linux make sure it is aligned */
122 target_phys_addr_t addend __attribute__((aligned(8)));
123#else
ths5fafdf22007-09-16 21:08:06 +0000124 target_phys_addr_t addend;
bellardd6564692008-01-31 09:22:27 +0000125#endif
126 /* padding to get a power of two size */
127 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
128 (sizeof(target_ulong) * 3 +
129 ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
130 sizeof(target_phys_addr_t))];
bellardab93bbe2003-08-10 21:35:13 +0000131} CPUTLBEntry;
132
pbrook2e70f6e2008-06-29 01:03:05 +0000133#ifdef WORDS_BIGENDIAN
134typedef struct icount_decr_u16 {
135 uint16_t high;
136 uint16_t low;
137} icount_decr_u16;
138#else
139typedef struct icount_decr_u16 {
140 uint16_t low;
141 uint16_t high;
142} icount_decr_u16;
143#endif
144
blueswir1a20e31d2008-04-08 19:29:54 +0000145#define CPU_TEMP_BUF_NLONGS 128
bellarda316d332005-11-20 10:32:34 +0000146#define CPU_COMMON \
147 struct TranslationBlock *current_tb; /* currently executing TB */ \
148 /* soft mmu support */ \
pbrook2e70f6e2008-06-29 01:03:05 +0000149 /* in order to avoid passing too many arguments to the MMIO \
150 helpers, we store some rarely used information in the CPU \
bellarda316d332005-11-20 10:32:34 +0000151 context) */ \
pbrook2e70f6e2008-06-29 01:03:05 +0000152 unsigned long mem_io_pc; /* host pc at which the memory was \
153 accessed */ \
154 target_ulong mem_io_vaddr; /* target virtual addr at which the \
155 memory was accessed */ \
pbrook9656f322008-07-01 20:01:19 +0000156 uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
157 uint32_t interrupt_request; \
ths623a9302007-10-28 19:45:05 +0000158 /* The meaning of the MMU modes is defined in the target code. */ \
j_mayer6fa4cea2007-04-05 06:43:27 +0000159 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
pbrook0f459d12008-06-09 00:20:13 +0000160 target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
bellarda316d332005-11-20 10:32:34 +0000161 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
blueswir1a20e31d2008-04-08 19:29:54 +0000162 /* buffer for temporaries in the code generator */ \
163 long temp_buf[CPU_TEMP_BUF_NLONGS]; \
bellarda316d332005-11-20 10:32:34 +0000164 \
pbrook2e70f6e2008-06-29 01:03:05 +0000165 int64_t icount_extra; /* Instructions until next timer event. */ \
166 /* Number of cycles left, with interrupt flag in high bit. \
167 This allows a single read-compare-cbranch-write sequence to test \
168 for both decrementer underflow and exceptions. */ \
169 union { \
170 uint32_t u32; \
171 icount_decr_u16 u16; \
172 } icount_decr; \
173 uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
174 \
bellarda316d332005-11-20 10:32:34 +0000175 /* from this point: preserved by CPU reset */ \
176 /* ice debug support */ \
177 target_ulong breakpoints[MAX_BREAKPOINTS]; \
178 int nb_breakpoints; \
179 int singlestep_enabled; \
180 \
pbrook6658ffb2007-03-16 23:58:11 +0000181 struct { \
182 target_ulong vaddr; \
pbrook0f459d12008-06-09 00:20:13 +0000183 int type; /* PAGE_READ/PAGE_WRITE */ \
pbrook6658ffb2007-03-16 23:58:11 +0000184 } watchpoint[MAX_WATCHPOINTS]; \
185 int nb_watchpoints; \
186 int watchpoint_hit; \
187 \
bellard9133e392008-05-29 10:08:06 +0000188 /* Core interrupt code */ \
189 jmp_buf jmp_env; \
190 int exception_index; \
191 \
pbrook9656f322008-07-01 20:01:19 +0000192 int user_mode_only; \
193 \
bellard6a00d602005-11-21 23:25:50 +0000194 void *next_cpu; /* next CPU sharing TB cache */ \
195 int cpu_index; /* CPU index (informative) */ \
pbrookd5975362008-06-07 20:50:51 +0000196 int running; /* Nonzero if cpu is currently running(usermode). */ \
bellarda316d332005-11-20 10:32:34 +0000197 /* user data */ \
ths01ba9812007-12-09 02:22:57 +0000198 void *opaque; \
199 \
200 const char *cpu_model_str;
bellarda316d332005-11-20 10:32:34 +0000201
bellardab93bbe2003-08-10 21:35:13 +0000202#endif