Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 1 | /* |
| 2 | * xio3130_upstream.c |
| 3 | * TI X3130 pci express upstream port switch |
| 4 | * |
| 5 | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> |
| 6 | * VA Linux Systems Japan K.K. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License along |
| 19 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 20 | */ |
| 21 | |
| 22 | #include "pci_ids.h" |
| 23 | #include "msi.h" |
| 24 | #include "pcie.h" |
| 25 | #include "xio3130_upstream.h" |
| 26 | |
| 27 | #define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */ |
| 28 | #define XIO3130_REVISION 0x2 |
| 29 | #define XIO3130_MSI_OFFSET 0x70 |
| 30 | #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT |
| 31 | #define XIO3130_MSI_NR_VECTOR 1 |
| 32 | #define XIO3130_SSVID_OFFSET 0x80 |
| 33 | #define XIO3130_SSVID_SVID 0 |
| 34 | #define XIO3130_SSVID_SSID 0 |
| 35 | #define XIO3130_EXP_OFFSET 0x90 |
| 36 | #define XIO3130_AER_OFFSET 0x100 |
| 37 | |
| 38 | static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address, |
| 39 | uint32_t val, int len) |
| 40 | { |
| 41 | pci_bridge_write_config(d, address, val, len); |
| 42 | pcie_cap_flr_write_config(d, address, val, len); |
| 43 | msi_write_config(d, address, val, len); |
Isaku Yamahata | a158f92 | 2010-11-16 17:26:11 +0900 | [diff] [blame] | 44 | pcie_aer_write_config(d, address, val, len); |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 45 | } |
| 46 | |
| 47 | static void xio3130_upstream_reset(DeviceState *qdev) |
| 48 | { |
Anthony Liguori | 40021f0 | 2011-12-04 12:22:06 -0600 | [diff] [blame] | 49 | PCIDevice *d = PCI_DEVICE(qdev); |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 50 | msi_reset(d); |
| 51 | pci_bridge_reset(qdev); |
| 52 | pcie_cap_deverr_reset(d); |
| 53 | } |
| 54 | |
| 55 | static int xio3130_upstream_initfn(PCIDevice *d) |
| 56 | { |
| 57 | PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); |
| 58 | PCIEPort *p = DO_UPCAST(PCIEPort, br, br); |
| 59 | int rc; |
Isaku Yamahata | a158f92 | 2010-11-16 17:26:11 +0900 | [diff] [blame] | 60 | int tmp; |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 61 | |
| 62 | rc = pci_bridge_initfn(d); |
| 63 | if (rc < 0) { |
| 64 | return rc; |
| 65 | } |
| 66 | |
| 67 | pcie_port_init_reg(d); |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 68 | |
| 69 | rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, |
| 70 | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, |
| 71 | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); |
| 72 | if (rc < 0) { |
Isaku Yamahata | a158f92 | 2010-11-16 17:26:11 +0900 | [diff] [blame] | 73 | goto err_bridge; |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 74 | } |
| 75 | rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, |
| 76 | XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); |
| 77 | if (rc < 0) { |
Isaku Yamahata | a158f92 | 2010-11-16 17:26:11 +0900 | [diff] [blame] | 78 | goto err_bridge; |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 79 | } |
| 80 | rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, |
| 81 | p->port); |
| 82 | if (rc < 0) { |
Isaku Yamahata | a158f92 | 2010-11-16 17:26:11 +0900 | [diff] [blame] | 83 | goto err_msi; |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 84 | } |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 85 | pcie_cap_flr_init(d); |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 86 | pcie_cap_deverr_init(d); |
Isaku Yamahata | a158f92 | 2010-11-16 17:26:11 +0900 | [diff] [blame] | 87 | rc = pcie_aer_init(d, XIO3130_AER_OFFSET); |
| 88 | if (rc < 0) { |
| 89 | goto err; |
| 90 | } |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 91 | |
| 92 | return 0; |
Isaku Yamahata | a158f92 | 2010-11-16 17:26:11 +0900 | [diff] [blame] | 93 | |
| 94 | err: |
| 95 | pcie_cap_exit(d); |
| 96 | err_msi: |
| 97 | msi_uninit(d); |
| 98 | err_bridge: |
| 99 | tmp = pci_bridge_exitfn(d); |
| 100 | assert(!tmp); |
| 101 | return rc; |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | static int xio3130_upstream_exitfn(PCIDevice *d) |
| 105 | { |
Isaku Yamahata | a158f92 | 2010-11-16 17:26:11 +0900 | [diff] [blame] | 106 | pcie_aer_exit(d); |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 107 | pcie_cap_exit(d); |
Isaku Yamahata | a158f92 | 2010-11-16 17:26:11 +0900 | [diff] [blame] | 108 | msi_uninit(d); |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 109 | return pci_bridge_exitfn(d); |
| 110 | } |
| 111 | |
| 112 | PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction, |
| 113 | const char *bus_name, pci_map_irq_fn map_irq, |
| 114 | uint8_t port) |
| 115 | { |
| 116 | PCIDevice *d; |
| 117 | PCIBridge *br; |
| 118 | DeviceState *qdev; |
| 119 | |
| 120 | d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream"); |
| 121 | if (!d) { |
| 122 | return NULL; |
| 123 | } |
| 124 | br = DO_UPCAST(PCIBridge, dev, d); |
| 125 | |
| 126 | qdev = &br->dev.qdev; |
| 127 | pci_bridge_map_irq(br, bus_name, map_irq); |
| 128 | qdev_prop_set_uint8(qdev, "port", port); |
| 129 | qdev_init_nofail(qdev); |
| 130 | |
| 131 | return DO_UPCAST(PCIEPort, br, br); |
| 132 | } |
| 133 | |
| 134 | static const VMStateDescription vmstate_xio3130_upstream = { |
| 135 | .name = "xio3130-express-upstream-port", |
| 136 | .version_id = 1, |
| 137 | .minimum_version_id = 1, |
| 138 | .minimum_version_id_old = 1, |
| 139 | .fields = (VMStateField[]) { |
| 140 | VMSTATE_PCIE_DEVICE(br.dev, PCIEPort), |
Isaku Yamahata | a158f92 | 2010-11-16 17:26:11 +0900 | [diff] [blame] | 141 | VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log, |
| 142 | PCIEAERLog), |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 143 | VMSTATE_END_OF_LIST() |
| 144 | } |
| 145 | }; |
| 146 | |
Anthony Liguori | 40021f0 | 2011-12-04 12:22:06 -0600 | [diff] [blame] | 147 | static Property xio3130_upstream_properties[] = { |
| 148 | DEFINE_PROP_UINT8("port", PCIEPort, port, 0), |
| 149 | DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_max, |
| 150 | PCIE_AER_LOG_MAX_DEFAULT), |
| 151 | DEFINE_PROP_END_OF_LIST(), |
| 152 | }; |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 153 | |
Anthony Liguori | 40021f0 | 2011-12-04 12:22:06 -0600 | [diff] [blame] | 154 | static void xio3130_upstream_class_init(ObjectClass *klass, void *data) |
| 155 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 156 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 40021f0 | 2011-12-04 12:22:06 -0600 | [diff] [blame] | 157 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 158 | |
Anthony Liguori | 40021f0 | 2011-12-04 12:22:06 -0600 | [diff] [blame] | 159 | k->is_express = 1; |
| 160 | k->is_bridge = 1; |
| 161 | k->config_write = xio3130_upstream_write_config; |
| 162 | k->init = xio3130_upstream_initfn; |
| 163 | k->exit = xio3130_upstream_exitfn; |
| 164 | k->vendor_id = PCI_VENDOR_ID_TI; |
| 165 | k->device_id = PCI_DEVICE_ID_TI_XIO3130U; |
| 166 | k->revision = XIO3130_REVISION; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 167 | dc->desc = "TI X3130 Upstream Port of PCI Express Switch"; |
| 168 | dc->reset = xio3130_upstream_reset; |
| 169 | dc->vmsd = &vmstate_xio3130_upstream; |
| 170 | dc->props = xio3130_upstream_properties; |
Anthony Liguori | 40021f0 | 2011-12-04 12:22:06 -0600 | [diff] [blame] | 171 | } |
| 172 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 173 | static TypeInfo xio3130_upstream_info = { |
| 174 | .name = "x3130-upstream", |
| 175 | .parent = TYPE_PCI_DEVICE, |
| 176 | .instance_size = sizeof(PCIEPort), |
| 177 | .class_init = xio3130_upstream_class_init, |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 178 | }; |
| 179 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 180 | static void xio3130_upstream_register_types(void) |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 181 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 182 | type_register_static(&xio3130_upstream_info); |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 183 | } |
| 184 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 185 | type_init(xio3130_upstream_register_types) |
Isaku Yamahata | faf1e70 | 2010-10-20 17:18:54 +0900 | [diff] [blame] | 186 | |
| 187 | |
| 188 | /* |
| 189 | * Local variables: |
| 190 | * c-indent-level: 4 |
| 191 | * c-basic-offset: 4 |
| 192 | * tab-width: 8 |
| 193 | * indent-tab-mode: nil |
| 194 | * End: |
| 195 | */ |