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bellardeaa728e2008-05-28 12:51:20 +00001/*
Blue Swirl10774992012-04-29 16:39:13 +00002 * x86 segmentation related helpers:
3 * TSS, interrupts, system calls, jumps and call/task gates, descriptors
bellardeaa728e2008-05-28 12:51:20 +00004 *
5 * Copyright (c) 2003 Fabrice Bellard
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellardeaa728e2008-05-28 12:51:20 +000019 */
Paolo Bonzini83dae092010-06-29 09:58:49 +020020
Peter Maydellb6a0aa02016-01-26 18:17:03 +000021#include "qemu/osdep.h"
Blue Swirl3e457172011-07-13 12:44:15 +000022#include "cpu.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010023#include "qemu/log.h"
Richard Henderson2ef61752014-04-07 22:31:41 -070024#include "exec/helper-proto.h"
Paolo Bonzini63c91552016-03-15 13:18:37 +010025#include "exec/exec-all.h"
Paolo Bonzinif08b6172014-03-28 19:42:10 +010026#include "exec/cpu_ldst.h"
Paolo Bonzini508127e2016-01-07 16:55:28 +030027#include "exec/log.h"
Blue Swirl3e457172011-07-13 12:44:15 +000028
bellardeaa728e2008-05-28 12:51:20 +000029//#define DEBUG_PCALL
30
aliguorid12d51d2009-01-15 21:48:06 +000031#ifdef DEBUG_PCALL
Blue Swirl20054ef2012-04-28 15:33:48 +000032# define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__)
Andreas Färber8995b7a2013-07-03 01:07:10 +020033# define LOG_PCALL_STATE(cpu) \
34 log_cpu_state_mask(CPU_LOG_PCALL, (cpu), CPU_DUMP_CCOP)
aliguorid12d51d2009-01-15 21:48:06 +000035#else
Blue Swirl20054ef2012-04-28 15:33:48 +000036# define LOG_PCALL(...) do { } while (0)
Andreas Färber8995b7a2013-07-03 01:07:10 +020037# define LOG_PCALL_STATE(cpu) do { } while (0)
aliguorid12d51d2009-01-15 21:48:06 +000038#endif
39
Peter Maydell9220fe52015-01-20 15:19:34 +000040#ifdef CONFIG_USER_ONLY
41#define MEMSUFFIX _kernel
42#define DATA_SIZE 1
43#include "exec/cpu_ldst_useronly_template.h"
44
45#define DATA_SIZE 2
46#include "exec/cpu_ldst_useronly_template.h"
47
48#define DATA_SIZE 4
49#include "exec/cpu_ldst_useronly_template.h"
50
51#define DATA_SIZE 8
52#include "exec/cpu_ldst_useronly_template.h"
53#undef MEMSUFFIX
54#else
Paolo Bonzini8a201bd2014-03-28 11:43:45 +010055#define CPU_MMU_INDEX (cpu_mmu_index_kernel(env))
56#define MEMSUFFIX _kernel
57#define DATA_SIZE 1
58#include "exec/cpu_ldst_template.h"
59
60#define DATA_SIZE 2
61#include "exec/cpu_ldst_template.h"
62
63#define DATA_SIZE 4
64#include "exec/cpu_ldst_template.h"
65
66#define DATA_SIZE 8
67#include "exec/cpu_ldst_template.h"
68#undef CPU_MMU_INDEX
69#undef MEMSUFFIX
70#endif
71
bellardeaa728e2008-05-28 12:51:20 +000072/* return non zero if error */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +030073static inline int load_segment_ra(CPUX86State *env, uint32_t *e1_ptr,
74 uint32_t *e2_ptr, int selector,
75 uintptr_t retaddr)
bellardeaa728e2008-05-28 12:51:20 +000076{
77 SegmentCache *dt;
78 int index;
79 target_ulong ptr;
80
Blue Swirl20054ef2012-04-28 15:33:48 +000081 if (selector & 0x4) {
bellardeaa728e2008-05-28 12:51:20 +000082 dt = &env->ldt;
Blue Swirl20054ef2012-04-28 15:33:48 +000083 } else {
bellardeaa728e2008-05-28 12:51:20 +000084 dt = &env->gdt;
Blue Swirl20054ef2012-04-28 15:33:48 +000085 }
bellardeaa728e2008-05-28 12:51:20 +000086 index = selector & ~7;
Blue Swirl20054ef2012-04-28 15:33:48 +000087 if ((index + 7) > dt->limit) {
bellardeaa728e2008-05-28 12:51:20 +000088 return -1;
Blue Swirl20054ef2012-04-28 15:33:48 +000089 }
bellardeaa728e2008-05-28 12:51:20 +000090 ptr = dt->base + index;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +030091 *e1_ptr = cpu_ldl_kernel_ra(env, ptr, retaddr);
92 *e2_ptr = cpu_ldl_kernel_ra(env, ptr + 4, retaddr);
bellardeaa728e2008-05-28 12:51:20 +000093 return 0;
94}
95
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +030096static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr,
97 uint32_t *e2_ptr, int selector)
98{
99 return load_segment_ra(env, e1_ptr, e2_ptr, selector, 0);
100}
101
bellardeaa728e2008-05-28 12:51:20 +0000102static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
103{
104 unsigned int limit;
Blue Swirl20054ef2012-04-28 15:33:48 +0000105
bellardeaa728e2008-05-28 12:51:20 +0000106 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
Blue Swirl20054ef2012-04-28 15:33:48 +0000107 if (e2 & DESC_G_MASK) {
bellardeaa728e2008-05-28 12:51:20 +0000108 limit = (limit << 12) | 0xfff;
Blue Swirl20054ef2012-04-28 15:33:48 +0000109 }
bellardeaa728e2008-05-28 12:51:20 +0000110 return limit;
111}
112
113static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
114{
Blue Swirl20054ef2012-04-28 15:33:48 +0000115 return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000);
bellardeaa728e2008-05-28 12:51:20 +0000116}
117
Blue Swirl20054ef2012-04-28 15:33:48 +0000118static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1,
119 uint32_t e2)
bellardeaa728e2008-05-28 12:51:20 +0000120{
121 sc->base = get_seg_base(e1, e2);
122 sc->limit = get_seg_limit(e1, e2);
123 sc->flags = e2;
124}
125
126/* init the segment cache in vm86 mode. */
Blue Swirl2999a0b2012-04-29 19:47:06 +0000127static inline void load_seg_vm(CPUX86State *env, int seg, int selector)
bellardeaa728e2008-05-28 12:51:20 +0000128{
129 selector &= 0xffff;
Paolo Bonzinib98dbc92014-05-15 16:07:04 +0200130
131 cpu_x86_load_seg_cache(env, seg, selector, (selector << 4), 0xffff,
132 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
133 DESC_A_MASK | (3 << DESC_DPL_SHIFT));
bellardeaa728e2008-05-28 12:51:20 +0000134}
135
Blue Swirl2999a0b2012-04-29 19:47:06 +0000136static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300137 uint32_t *esp_ptr, int dpl,
138 uintptr_t retaddr)
bellardeaa728e2008-05-28 12:51:20 +0000139{
Andreas Färbera47dddd2013-09-03 17:38:47 +0200140 X86CPU *cpu = x86_env_get_cpu(env);
bellardeaa728e2008-05-28 12:51:20 +0000141 int type, index, shift;
142
143#if 0
144 {
145 int i;
146 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
Blue Swirl20054ef2012-04-28 15:33:48 +0000147 for (i = 0; i < env->tr.limit; i++) {
bellardeaa728e2008-05-28 12:51:20 +0000148 printf("%02x ", env->tr.base[i]);
Blue Swirl20054ef2012-04-28 15:33:48 +0000149 if ((i & 7) == 7) {
150 printf("\n");
151 }
bellardeaa728e2008-05-28 12:51:20 +0000152 }
153 printf("\n");
154 }
155#endif
156
Blue Swirl20054ef2012-04-28 15:33:48 +0000157 if (!(env->tr.flags & DESC_P_MASK)) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200158 cpu_abort(CPU(cpu), "invalid tss");
Blue Swirl20054ef2012-04-28 15:33:48 +0000159 }
bellardeaa728e2008-05-28 12:51:20 +0000160 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +0000161 if ((type & 7) != 1) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200162 cpu_abort(CPU(cpu), "invalid tss type");
Blue Swirl20054ef2012-04-28 15:33:48 +0000163 }
bellardeaa728e2008-05-28 12:51:20 +0000164 shift = type >> 3;
165 index = (dpl * 4 + 2) << shift;
Blue Swirl20054ef2012-04-28 15:33:48 +0000166 if (index + (4 << shift) - 1 > env->tr.limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300167 raise_exception_err_ra(env, EXCP0A_TSS, env->tr.selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000168 }
bellardeaa728e2008-05-28 12:51:20 +0000169 if (shift == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300170 *esp_ptr = cpu_lduw_kernel_ra(env, env->tr.base + index, retaddr);
171 *ss_ptr = cpu_lduw_kernel_ra(env, env->tr.base + index + 2, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000172 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300173 *esp_ptr = cpu_ldl_kernel_ra(env, env->tr.base + index, retaddr);
174 *ss_ptr = cpu_lduw_kernel_ra(env, env->tr.base + index + 4, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000175 }
176}
177
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300178static void tss_load_seg(CPUX86State *env, int seg_reg, int selector, int cpl,
179 uintptr_t retaddr)
bellardeaa728e2008-05-28 12:51:20 +0000180{
181 uint32_t e1, e2;
Paolo Bonzinid3b54912014-05-15 18:19:17 +0200182 int rpl, dpl;
bellardeaa728e2008-05-28 12:51:20 +0000183
184 if ((selector & 0xfffc) != 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300185 if (load_segment_ra(env, &e1, &e2, selector, retaddr) != 0) {
186 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000187 }
188 if (!(e2 & DESC_S_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300189 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000190 }
bellardeaa728e2008-05-28 12:51:20 +0000191 rpl = selector & 3;
192 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
bellardeaa728e2008-05-28 12:51:20 +0000193 if (seg_reg == R_CS) {
Blue Swirl20054ef2012-04-28 15:33:48 +0000194 if (!(e2 & DESC_CS_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300195 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000196 }
Blue Swirl20054ef2012-04-28 15:33:48 +0000197 if (dpl != rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300198 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000199 }
bellardeaa728e2008-05-28 12:51:20 +0000200 } else if (seg_reg == R_SS) {
201 /* SS must be writable data */
Blue Swirl20054ef2012-04-28 15:33:48 +0000202 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300203 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000204 }
205 if (dpl != cpl || dpl != rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300206 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000207 }
bellardeaa728e2008-05-28 12:51:20 +0000208 } else {
209 /* not readable code */
Blue Swirl20054ef2012-04-28 15:33:48 +0000210 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300211 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000212 }
bellardeaa728e2008-05-28 12:51:20 +0000213 /* if data or non conforming code, checks the rights */
214 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
Blue Swirl20054ef2012-04-28 15:33:48 +0000215 if (dpl < cpl || dpl < rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300216 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000217 }
bellardeaa728e2008-05-28 12:51:20 +0000218 }
219 }
Blue Swirl20054ef2012-04-28 15:33:48 +0000220 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300221 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000222 }
bellardeaa728e2008-05-28 12:51:20 +0000223 cpu_x86_load_seg_cache(env, seg_reg, selector,
Blue Swirl20054ef2012-04-28 15:33:48 +0000224 get_seg_base(e1, e2),
225 get_seg_limit(e1, e2),
226 e2);
bellardeaa728e2008-05-28 12:51:20 +0000227 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +0000228 if (seg_reg == R_SS || seg_reg == R_CS) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300229 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000230 }
bellardeaa728e2008-05-28 12:51:20 +0000231 }
232}
233
234#define SWITCH_TSS_JMP 0
235#define SWITCH_TSS_IRET 1
236#define SWITCH_TSS_CALL 2
237
238/* XXX: restore CPU state in registers (PowerPC case) */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300239static void switch_tss_ra(CPUX86State *env, int tss_selector,
240 uint32_t e1, uint32_t e2, int source,
241 uint32_t next_eip, uintptr_t retaddr)
bellardeaa728e2008-05-28 12:51:20 +0000242{
243 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
244 target_ulong tss_base;
245 uint32_t new_regs[8], new_segs[6];
246 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
247 uint32_t old_eflags, eflags_mask;
248 SegmentCache *dt;
249 int index;
250 target_ulong ptr;
251
252 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +0000253 LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type,
254 source);
bellardeaa728e2008-05-28 12:51:20 +0000255
256 /* if task gate, we read the TSS segment and we load it */
257 if (type == 5) {
Blue Swirl20054ef2012-04-28 15:33:48 +0000258 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300259 raise_exception_err_ra(env, EXCP0B_NOSEG, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000260 }
bellardeaa728e2008-05-28 12:51:20 +0000261 tss_selector = e1 >> 16;
Blue Swirl20054ef2012-04-28 15:33:48 +0000262 if (tss_selector & 4) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300263 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000264 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300265 if (load_segment_ra(env, &e1, &e2, tss_selector, retaddr) != 0) {
266 raise_exception_err_ra(env, EXCP0D_GPF, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000267 }
268 if (e2 & DESC_S_MASK) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300269 raise_exception_err_ra(env, EXCP0D_GPF, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000270 }
bellardeaa728e2008-05-28 12:51:20 +0000271 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +0000272 if ((type & 7) != 1) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300273 raise_exception_err_ra(env, EXCP0D_GPF, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000274 }
bellardeaa728e2008-05-28 12:51:20 +0000275 }
276
Blue Swirl20054ef2012-04-28 15:33:48 +0000277 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300278 raise_exception_err_ra(env, EXCP0B_NOSEG, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000279 }
bellardeaa728e2008-05-28 12:51:20 +0000280
Blue Swirl20054ef2012-04-28 15:33:48 +0000281 if (type & 8) {
bellardeaa728e2008-05-28 12:51:20 +0000282 tss_limit_max = 103;
Blue Swirl20054ef2012-04-28 15:33:48 +0000283 } else {
bellardeaa728e2008-05-28 12:51:20 +0000284 tss_limit_max = 43;
Blue Swirl20054ef2012-04-28 15:33:48 +0000285 }
bellardeaa728e2008-05-28 12:51:20 +0000286 tss_limit = get_seg_limit(e1, e2);
287 tss_base = get_seg_base(e1, e2);
288 if ((tss_selector & 4) != 0 ||
Blue Swirl20054ef2012-04-28 15:33:48 +0000289 tss_limit < tss_limit_max) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300290 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000291 }
bellardeaa728e2008-05-28 12:51:20 +0000292 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +0000293 if (old_type & 8) {
bellardeaa728e2008-05-28 12:51:20 +0000294 old_tss_limit_max = 103;
Blue Swirl20054ef2012-04-28 15:33:48 +0000295 } else {
bellardeaa728e2008-05-28 12:51:20 +0000296 old_tss_limit_max = 43;
Blue Swirl20054ef2012-04-28 15:33:48 +0000297 }
bellardeaa728e2008-05-28 12:51:20 +0000298
299 /* read all the registers from the new TSS */
300 if (type & 8) {
301 /* 32 bit */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300302 new_cr3 = cpu_ldl_kernel_ra(env, tss_base + 0x1c, retaddr);
303 new_eip = cpu_ldl_kernel_ra(env, tss_base + 0x20, retaddr);
304 new_eflags = cpu_ldl_kernel_ra(env, tss_base + 0x24, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000305 for (i = 0; i < 8; i++) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300306 new_regs[i] = cpu_ldl_kernel_ra(env, tss_base + (0x28 + i * 4),
307 retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000308 }
309 for (i = 0; i < 6; i++) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300310 new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x48 + i * 4),
311 retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000312 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300313 new_ldt = cpu_lduw_kernel_ra(env, tss_base + 0x60, retaddr);
314 new_trap = cpu_ldl_kernel_ra(env, tss_base + 0x64, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000315 } else {
316 /* 16 bit */
317 new_cr3 = 0;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300318 new_eip = cpu_lduw_kernel_ra(env, tss_base + 0x0e, retaddr);
319 new_eflags = cpu_lduw_kernel_ra(env, tss_base + 0x10, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000320 for (i = 0; i < 8; i++) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300321 new_regs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x12 + i * 2),
322 retaddr) | 0xffff0000;
Blue Swirl20054ef2012-04-28 15:33:48 +0000323 }
324 for (i = 0; i < 4; i++) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300325 new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x22 + i * 4),
326 retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000327 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300328 new_ldt = cpu_lduw_kernel_ra(env, tss_base + 0x2a, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000329 new_segs[R_FS] = 0;
330 new_segs[R_GS] = 0;
331 new_trap = 0;
332 }
Blue Swirl4581cbc2010-10-13 18:38:08 +0000333 /* XXX: avoid a compiler warning, see
334 http://support.amd.com/us/Processor_TechDocs/24593.pdf
335 chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
336 (void)new_trap;
bellardeaa728e2008-05-28 12:51:20 +0000337
338 /* NOTE: we must avoid memory exceptions during the task switch,
339 so we make dummy accesses before */
340 /* XXX: it can still fail in some cases, so a bigger hack is
341 necessary to valid the TLB after having done the accesses */
342
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300343 v1 = cpu_ldub_kernel_ra(env, env->tr.base, retaddr);
344 v2 = cpu_ldub_kernel_ra(env, env->tr.base + old_tss_limit_max, retaddr);
345 cpu_stb_kernel_ra(env, env->tr.base, v1, retaddr);
346 cpu_stb_kernel_ra(env, env->tr.base + old_tss_limit_max, v2, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000347
348 /* clear busy bit (it is restartable) */
349 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
350 target_ulong ptr;
351 uint32_t e2;
Blue Swirl20054ef2012-04-28 15:33:48 +0000352
bellardeaa728e2008-05-28 12:51:20 +0000353 ptr = env->gdt.base + (env->tr.selector & ~7);
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300354 e2 = cpu_ldl_kernel_ra(env, ptr + 4, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000355 e2 &= ~DESC_TSS_BUSY_MASK;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300356 cpu_stl_kernel_ra(env, ptr + 4, e2, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000357 }
Blue Swirl997ff0d2012-04-29 15:01:21 +0000358 old_eflags = cpu_compute_eflags(env);
Blue Swirl20054ef2012-04-28 15:33:48 +0000359 if (source == SWITCH_TSS_IRET) {
bellardeaa728e2008-05-28 12:51:20 +0000360 old_eflags &= ~NT_MASK;
Blue Swirl20054ef2012-04-28 15:33:48 +0000361 }
bellardeaa728e2008-05-28 12:51:20 +0000362
363 /* save the current state in the old TSS */
364 if (type & 8) {
365 /* 32 bit */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300366 cpu_stl_kernel_ra(env, env->tr.base + 0x20, next_eip, retaddr);
367 cpu_stl_kernel_ra(env, env->tr.base + 0x24, old_eflags, retaddr);
368 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX], retaddr);
369 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX], retaddr);
370 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX], retaddr);
371 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX], retaddr);
372 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP], retaddr);
373 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP], retaddr);
374 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 6 * 4), env->regs[R_ESI], retaddr);
375 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 7 * 4), env->regs[R_EDI], retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000376 for (i = 0; i < 6; i++) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300377 cpu_stw_kernel_ra(env, env->tr.base + (0x48 + i * 4),
378 env->segs[i].selector, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000379 }
bellardeaa728e2008-05-28 12:51:20 +0000380 } else {
381 /* 16 bit */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300382 cpu_stw_kernel_ra(env, env->tr.base + 0x0e, next_eip, retaddr);
383 cpu_stw_kernel_ra(env, env->tr.base + 0x10, old_eflags, retaddr);
384 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX], retaddr);
385 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX], retaddr);
386 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX], retaddr);
387 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX], retaddr);
388 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP], retaddr);
389 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP], retaddr);
390 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI], retaddr);
391 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI], retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000392 for (i = 0; i < 4; i++) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300393 cpu_stw_kernel_ra(env, env->tr.base + (0x22 + i * 4),
394 env->segs[i].selector, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000395 }
bellardeaa728e2008-05-28 12:51:20 +0000396 }
397
398 /* now if an exception occurs, it will occurs in the next task
399 context */
400
401 if (source == SWITCH_TSS_CALL) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300402 cpu_stw_kernel_ra(env, tss_base, env->tr.selector, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000403 new_eflags |= NT_MASK;
404 }
405
406 /* set busy bit */
407 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
408 target_ulong ptr;
409 uint32_t e2;
Blue Swirl20054ef2012-04-28 15:33:48 +0000410
bellardeaa728e2008-05-28 12:51:20 +0000411 ptr = env->gdt.base + (tss_selector & ~7);
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300412 e2 = cpu_ldl_kernel_ra(env, ptr + 4, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000413 e2 |= DESC_TSS_BUSY_MASK;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300414 cpu_stl_kernel_ra(env, ptr + 4, e2, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000415 }
416
417 /* set the new CPU state */
418 /* from this point, any exception which occurs can give problems */
419 env->cr[0] |= CR0_TS_MASK;
420 env->hflags |= HF_TS_MASK;
421 env->tr.selector = tss_selector;
422 env->tr.base = tss_base;
423 env->tr.limit = tss_limit;
424 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
425
426 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
427 cpu_x86_update_cr3(env, new_cr3);
428 }
429
430 /* load all registers without an exception, then reload them with
431 possible exception */
432 env->eip = new_eip;
433 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
434 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
Blue Swirl20054ef2012-04-28 15:33:48 +0000435 if (!(type & 8)) {
bellardeaa728e2008-05-28 12:51:20 +0000436 eflags_mask &= 0xffff;
Blue Swirl20054ef2012-04-28 15:33:48 +0000437 }
Blue Swirl997ff0d2012-04-29 15:01:21 +0000438 cpu_load_eflags(env, new_eflags, eflags_mask);
Blue Swirl20054ef2012-04-28 15:33:48 +0000439 /* XXX: what to do in 16 bit case? */
liguang4b34e3a2013-05-28 16:20:59 +0800440 env->regs[R_EAX] = new_regs[0];
liguanga4165612013-05-28 16:21:01 +0800441 env->regs[R_ECX] = new_regs[1];
liguang00f5e6f2013-05-28 16:21:02 +0800442 env->regs[R_EDX] = new_regs[2];
liguang70b51362013-05-28 16:21:00 +0800443 env->regs[R_EBX] = new_regs[3];
liguang08b3ded2013-05-28 16:21:04 +0800444 env->regs[R_ESP] = new_regs[4];
liguangc12dddd2013-05-28 16:21:03 +0800445 env->regs[R_EBP] = new_regs[5];
liguang78c3c6d2013-05-28 16:21:05 +0800446 env->regs[R_ESI] = new_regs[6];
liguangcf75c592013-05-28 16:21:06 +0800447 env->regs[R_EDI] = new_regs[7];
bellardeaa728e2008-05-28 12:51:20 +0000448 if (new_eflags & VM_MASK) {
Blue Swirl20054ef2012-04-28 15:33:48 +0000449 for (i = 0; i < 6; i++) {
Blue Swirl2999a0b2012-04-29 19:47:06 +0000450 load_seg_vm(env, i, new_segs[i]);
Blue Swirl20054ef2012-04-28 15:33:48 +0000451 }
bellardeaa728e2008-05-28 12:51:20 +0000452 } else {
bellardeaa728e2008-05-28 12:51:20 +0000453 /* first just selectors as the rest may trigger exceptions */
Blue Swirl20054ef2012-04-28 15:33:48 +0000454 for (i = 0; i < 6; i++) {
bellardeaa728e2008-05-28 12:51:20 +0000455 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
Blue Swirl20054ef2012-04-28 15:33:48 +0000456 }
bellardeaa728e2008-05-28 12:51:20 +0000457 }
458
459 env->ldt.selector = new_ldt & ~4;
460 env->ldt.base = 0;
461 env->ldt.limit = 0;
462 env->ldt.flags = 0;
463
464 /* load the LDT */
Blue Swirl20054ef2012-04-28 15:33:48 +0000465 if (new_ldt & 4) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300466 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000467 }
bellardeaa728e2008-05-28 12:51:20 +0000468
469 if ((new_ldt & 0xfffc) != 0) {
470 dt = &env->gdt;
471 index = new_ldt & ~7;
Blue Swirl20054ef2012-04-28 15:33:48 +0000472 if ((index + 7) > dt->limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300473 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000474 }
bellardeaa728e2008-05-28 12:51:20 +0000475 ptr = dt->base + index;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300476 e1 = cpu_ldl_kernel_ra(env, ptr, retaddr);
477 e2 = cpu_ldl_kernel_ra(env, ptr + 4, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000478 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300479 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000480 }
481 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300482 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000483 }
bellardeaa728e2008-05-28 12:51:20 +0000484 load_seg_cache_raw_dt(&env->ldt, e1, e2);
485 }
486
487 /* load the segments */
488 if (!(new_eflags & VM_MASK)) {
Paolo Bonzinid3b54912014-05-15 18:19:17 +0200489 int cpl = new_segs[R_CS] & 3;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300490 tss_load_seg(env, R_CS, new_segs[R_CS], cpl, retaddr);
491 tss_load_seg(env, R_SS, new_segs[R_SS], cpl, retaddr);
492 tss_load_seg(env, R_ES, new_segs[R_ES], cpl, retaddr);
493 tss_load_seg(env, R_DS, new_segs[R_DS], cpl, retaddr);
494 tss_load_seg(env, R_FS, new_segs[R_FS], cpl, retaddr);
495 tss_load_seg(env, R_GS, new_segs[R_GS], cpl, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000496 }
497
liguanga78d0ea2013-05-28 16:21:07 +0800498 /* check that env->eip is in the CS segment limits */
bellardeaa728e2008-05-28 12:51:20 +0000499 if (new_eip > env->segs[R_CS].limit) {
Blue Swirl20054ef2012-04-28 15:33:48 +0000500 /* XXX: different exception if CALL? */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300501 raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000502 }
aliguori01df0402008-11-18 21:08:15 +0000503
504#ifndef CONFIG_USER_ONLY
505 /* reset local breakpoints */
liguang428065c2013-01-15 13:39:55 +0800506 if (env->dr[7] & DR7_LOCAL_BP_MASK) {
Richard Henderson93d00d02015-09-15 11:45:08 -0700507 cpu_x86_update_dr7(env, env->dr[7] & ~DR7_LOCAL_BP_MASK);
aliguori01df0402008-11-18 21:08:15 +0000508 }
509#endif
bellardeaa728e2008-05-28 12:51:20 +0000510}
511
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300512static void switch_tss(CPUX86State *env, int tss_selector,
513 uint32_t e1, uint32_t e2, int source,
514 uint32_t next_eip)
515{
516 switch_tss_ra(env, tss_selector, e1, e2, source, next_eip, 0);
517}
518
bellardeaa728e2008-05-28 12:51:20 +0000519static inline unsigned int get_sp_mask(unsigned int e2)
520{
Blue Swirl20054ef2012-04-28 15:33:48 +0000521 if (e2 & DESC_B_MASK) {
bellardeaa728e2008-05-28 12:51:20 +0000522 return 0xffffffff;
Blue Swirl20054ef2012-04-28 15:33:48 +0000523 } else {
bellardeaa728e2008-05-28 12:51:20 +0000524 return 0xffff;
Blue Swirl20054ef2012-04-28 15:33:48 +0000525 }
bellardeaa728e2008-05-28 12:51:20 +0000526}
527
Blue Swirl20054ef2012-04-28 15:33:48 +0000528static int exception_has_error_code(int intno)
aliguori2ed51f52009-04-22 20:20:07 +0000529{
Blue Swirl20054ef2012-04-28 15:33:48 +0000530 switch (intno) {
531 case 8:
532 case 10:
533 case 11:
534 case 12:
535 case 13:
536 case 14:
537 case 17:
538 return 1;
539 }
540 return 0;
aliguori2ed51f52009-04-22 20:20:07 +0000541}
542
bellardeaa728e2008-05-28 12:51:20 +0000543#ifdef TARGET_X86_64
liguang08b3ded2013-05-28 16:21:04 +0800544#define SET_ESP(val, sp_mask) \
545 do { \
546 if ((sp_mask) == 0xffff) { \
547 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \
548 ((val) & 0xffff); \
549 } else if ((sp_mask) == 0xffffffffLL) { \
550 env->regs[R_ESP] = (uint32_t)(val); \
551 } else { \
552 env->regs[R_ESP] = (val); \
553 } \
Blue Swirl20054ef2012-04-28 15:33:48 +0000554 } while (0)
bellardeaa728e2008-05-28 12:51:20 +0000555#else
liguang08b3ded2013-05-28 16:21:04 +0800556#define SET_ESP(val, sp_mask) \
557 do { \
558 env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \
559 ((val) & (sp_mask)); \
Blue Swirl20054ef2012-04-28 15:33:48 +0000560 } while (0)
bellardeaa728e2008-05-28 12:51:20 +0000561#endif
562
aliguoric0a04f02008-09-09 14:49:02 +0000563/* in 64-bit machines, this can overflow. So this segment addition macro
564 * can be used to trim the value to 32-bit whenever needed */
565#define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
566
bellardeaa728e2008-05-28 12:51:20 +0000567/* XXX: add a is_user flag to have proper security support */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300568#define PUSHW_RA(ssp, sp, sp_mask, val, ra) \
Blue Swirl329e6072012-04-29 19:11:01 +0000569 { \
570 sp -= 2; \
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300571 cpu_stw_kernel_ra(env, (ssp) + (sp & (sp_mask)), (val), ra); \
Blue Swirl20054ef2012-04-28 15:33:48 +0000572 }
bellardeaa728e2008-05-28 12:51:20 +0000573
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300574#define PUSHL_RA(ssp, sp, sp_mask, val, ra) \
Blue Swirl20054ef2012-04-28 15:33:48 +0000575 { \
576 sp -= 4; \
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300577 cpu_stl_kernel_ra(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val), ra); \
Blue Swirl20054ef2012-04-28 15:33:48 +0000578 }
bellardeaa728e2008-05-28 12:51:20 +0000579
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300580#define POPW_RA(ssp, sp, sp_mask, val, ra) \
Blue Swirl329e6072012-04-29 19:11:01 +0000581 { \
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300582 val = cpu_lduw_kernel_ra(env, (ssp) + (sp & (sp_mask)), ra); \
Blue Swirl329e6072012-04-29 19:11:01 +0000583 sp += 2; \
Blue Swirl20054ef2012-04-28 15:33:48 +0000584 }
bellardeaa728e2008-05-28 12:51:20 +0000585
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300586#define POPL_RA(ssp, sp, sp_mask, val, ra) \
Blue Swirl329e6072012-04-29 19:11:01 +0000587 { \
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300588 val = (uint32_t)cpu_ldl_kernel_ra(env, SEG_ADDL(ssp, sp, sp_mask), ra); \
Blue Swirl329e6072012-04-29 19:11:01 +0000589 sp += 4; \
Blue Swirl20054ef2012-04-28 15:33:48 +0000590 }
bellardeaa728e2008-05-28 12:51:20 +0000591
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300592#define PUSHW(ssp, sp, sp_mask, val) PUSHW_RA(ssp, sp, sp_mask, val, 0)
593#define PUSHL(ssp, sp, sp_mask, val) PUSHL_RA(ssp, sp, sp_mask, val, 0)
594#define POPW(ssp, sp, sp_mask, val) POPW_RA(ssp, sp, sp_mask, val, 0)
595#define POPL(ssp, sp, sp_mask, val) POPL_RA(ssp, sp, sp_mask, val, 0)
596
bellardeaa728e2008-05-28 12:51:20 +0000597/* protected mode interrupt */
Blue Swirl2999a0b2012-04-29 19:47:06 +0000598static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
599 int error_code, unsigned int next_eip,
600 int is_hw)
bellardeaa728e2008-05-28 12:51:20 +0000601{
602 SegmentCache *dt;
603 target_ulong ptr, ssp;
604 int type, dpl, selector, ss_dpl, cpl;
605 int has_error_code, new_stack, shift;
blueswir11c918eb2009-01-14 19:27:02 +0000606 uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0;
bellardeaa728e2008-05-28 12:51:20 +0000607 uint32_t old_eip, sp_mask;
Kevin O'Connor87446322014-05-20 17:10:24 -0400608 int vm86 = env->eflags & VM_MASK;
bellardeaa728e2008-05-28 12:51:20 +0000609
bellardeaa728e2008-05-28 12:51:20 +0000610 has_error_code = 0;
Blue Swirl20054ef2012-04-28 15:33:48 +0000611 if (!is_int && !is_hw) {
612 has_error_code = exception_has_error_code(intno);
613 }
614 if (is_int) {
bellardeaa728e2008-05-28 12:51:20 +0000615 old_eip = next_eip;
Blue Swirl20054ef2012-04-28 15:33:48 +0000616 } else {
bellardeaa728e2008-05-28 12:51:20 +0000617 old_eip = env->eip;
Blue Swirl20054ef2012-04-28 15:33:48 +0000618 }
bellardeaa728e2008-05-28 12:51:20 +0000619
620 dt = &env->idt;
Blue Swirl20054ef2012-04-28 15:33:48 +0000621 if (intno * 8 + 7 > dt->limit) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000622 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000623 }
bellardeaa728e2008-05-28 12:51:20 +0000624 ptr = dt->base + intno * 8;
Blue Swirl329e6072012-04-29 19:11:01 +0000625 e1 = cpu_ldl_kernel(env, ptr);
626 e2 = cpu_ldl_kernel(env, ptr + 4);
bellardeaa728e2008-05-28 12:51:20 +0000627 /* check gate type */
628 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
Blue Swirl20054ef2012-04-28 15:33:48 +0000629 switch (type) {
bellardeaa728e2008-05-28 12:51:20 +0000630 case 5: /* task gate */
631 /* must do that check here to return the correct error code */
Blue Swirl20054ef2012-04-28 15:33:48 +0000632 if (!(e2 & DESC_P_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000633 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000634 }
Blue Swirl2999a0b2012-04-29 19:47:06 +0000635 switch_tss(env, intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
bellardeaa728e2008-05-28 12:51:20 +0000636 if (has_error_code) {
637 int type;
638 uint32_t mask;
Blue Swirl20054ef2012-04-28 15:33:48 +0000639
bellardeaa728e2008-05-28 12:51:20 +0000640 /* push the error code */
641 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
642 shift = type >> 3;
Blue Swirl20054ef2012-04-28 15:33:48 +0000643 if (env->segs[R_SS].flags & DESC_B_MASK) {
bellardeaa728e2008-05-28 12:51:20 +0000644 mask = 0xffffffff;
Blue Swirl20054ef2012-04-28 15:33:48 +0000645 } else {
bellardeaa728e2008-05-28 12:51:20 +0000646 mask = 0xffff;
Blue Swirl20054ef2012-04-28 15:33:48 +0000647 }
liguang08b3ded2013-05-28 16:21:04 +0800648 esp = (env->regs[R_ESP] - (2 << shift)) & mask;
bellardeaa728e2008-05-28 12:51:20 +0000649 ssp = env->segs[R_SS].base + esp;
Blue Swirl20054ef2012-04-28 15:33:48 +0000650 if (shift) {
Blue Swirl329e6072012-04-29 19:11:01 +0000651 cpu_stl_kernel(env, ssp, error_code);
Blue Swirl20054ef2012-04-28 15:33:48 +0000652 } else {
Blue Swirl329e6072012-04-29 19:11:01 +0000653 cpu_stw_kernel(env, ssp, error_code);
Blue Swirl20054ef2012-04-28 15:33:48 +0000654 }
bellardeaa728e2008-05-28 12:51:20 +0000655 SET_ESP(esp, mask);
656 }
657 return;
658 case 6: /* 286 interrupt gate */
659 case 7: /* 286 trap gate */
660 case 14: /* 386 interrupt gate */
661 case 15: /* 386 trap gate */
662 break;
663 default:
Blue Swirl77b2bc22012-04-28 19:35:10 +0000664 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
bellardeaa728e2008-05-28 12:51:20 +0000665 break;
666 }
667 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
668 cpl = env->hflags & HF_CPL_MASK;
ths1235fc02008-06-03 19:51:57 +0000669 /* check privilege if software int */
Blue Swirl20054ef2012-04-28 15:33:48 +0000670 if (is_int && dpl < cpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000671 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000672 }
bellardeaa728e2008-05-28 12:51:20 +0000673 /* check valid bit */
Blue Swirl20054ef2012-04-28 15:33:48 +0000674 if (!(e2 & DESC_P_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000675 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000676 }
bellardeaa728e2008-05-28 12:51:20 +0000677 selector = e1 >> 16;
678 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
Blue Swirl20054ef2012-04-28 15:33:48 +0000679 if ((selector & 0xfffc) == 0) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000680 raise_exception_err(env, EXCP0D_GPF, 0);
Blue Swirl20054ef2012-04-28 15:33:48 +0000681 }
Blue Swirl2999a0b2012-04-29 19:47:06 +0000682 if (load_segment(env, &e1, &e2, selector) != 0) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000683 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000684 }
685 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000686 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000687 }
bellardeaa728e2008-05-28 12:51:20 +0000688 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +0000689 if (dpl > cpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000690 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000691 }
692 if (!(e2 & DESC_P_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000693 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000694 }
bellardeaa728e2008-05-28 12:51:20 +0000695 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
696 /* to inner privilege */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300697 get_ss_esp_from_tss(env, &ss, &esp, dpl, 0);
Blue Swirl20054ef2012-04-28 15:33:48 +0000698 if ((ss & 0xfffc) == 0) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000699 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000700 }
701 if ((ss & 3) != dpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000702 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000703 }
Blue Swirl2999a0b2012-04-29 19:47:06 +0000704 if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000705 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000706 }
bellardeaa728e2008-05-28 12:51:20 +0000707 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +0000708 if (ss_dpl != dpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000709 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000710 }
bellardeaa728e2008-05-28 12:51:20 +0000711 if (!(ss_e2 & DESC_S_MASK) ||
712 (ss_e2 & DESC_CS_MASK) ||
Blue Swirl20054ef2012-04-28 15:33:48 +0000713 !(ss_e2 & DESC_W_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000714 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000715 }
716 if (!(ss_e2 & DESC_P_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000717 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000718 }
bellardeaa728e2008-05-28 12:51:20 +0000719 new_stack = 1;
720 sp_mask = get_sp_mask(ss_e2);
721 ssp = get_seg_base(ss_e1, ss_e2);
722 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
723 /* to same privilege */
Kevin O'Connor87446322014-05-20 17:10:24 -0400724 if (vm86) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000725 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000726 }
bellardeaa728e2008-05-28 12:51:20 +0000727 new_stack = 0;
728 sp_mask = get_sp_mask(env->segs[R_SS].flags);
729 ssp = env->segs[R_SS].base;
liguang08b3ded2013-05-28 16:21:04 +0800730 esp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +0000731 dpl = cpl;
732 } else {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000733 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
bellardeaa728e2008-05-28 12:51:20 +0000734 new_stack = 0; /* avoid warning */
735 sp_mask = 0; /* avoid warning */
736 ssp = 0; /* avoid warning */
737 esp = 0; /* avoid warning */
738 }
739
740 shift = type >> 3;
741
742#if 0
743 /* XXX: check that enough room is available */
744 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
Kevin O'Connor87446322014-05-20 17:10:24 -0400745 if (vm86) {
bellardeaa728e2008-05-28 12:51:20 +0000746 push_size += 8;
Blue Swirl20054ef2012-04-28 15:33:48 +0000747 }
bellardeaa728e2008-05-28 12:51:20 +0000748 push_size <<= shift;
749#endif
750 if (shift == 1) {
751 if (new_stack) {
Kevin O'Connor87446322014-05-20 17:10:24 -0400752 if (vm86) {
bellardeaa728e2008-05-28 12:51:20 +0000753 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
754 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
755 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
756 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
757 }
758 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
liguang08b3ded2013-05-28 16:21:04 +0800759 PUSHL(ssp, esp, sp_mask, env->regs[R_ESP]);
bellardeaa728e2008-05-28 12:51:20 +0000760 }
Blue Swirl997ff0d2012-04-29 15:01:21 +0000761 PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));
bellardeaa728e2008-05-28 12:51:20 +0000762 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
763 PUSHL(ssp, esp, sp_mask, old_eip);
764 if (has_error_code) {
765 PUSHL(ssp, esp, sp_mask, error_code);
766 }
767 } else {
768 if (new_stack) {
Kevin O'Connor87446322014-05-20 17:10:24 -0400769 if (vm86) {
bellardeaa728e2008-05-28 12:51:20 +0000770 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
771 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
772 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
773 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
774 }
775 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
liguang08b3ded2013-05-28 16:21:04 +0800776 PUSHW(ssp, esp, sp_mask, env->regs[R_ESP]);
bellardeaa728e2008-05-28 12:51:20 +0000777 }
Blue Swirl997ff0d2012-04-29 15:01:21 +0000778 PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));
bellardeaa728e2008-05-28 12:51:20 +0000779 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
780 PUSHW(ssp, esp, sp_mask, old_eip);
781 if (has_error_code) {
782 PUSHW(ssp, esp, sp_mask, error_code);
783 }
784 }
785
Kevin O'Connorfd460602014-04-29 16:38:31 -0400786 /* interrupt gate clear IF mask */
787 if ((type & 1) == 0) {
788 env->eflags &= ~IF_MASK;
789 }
790 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
791
bellardeaa728e2008-05-28 12:51:20 +0000792 if (new_stack) {
Kevin O'Connor87446322014-05-20 17:10:24 -0400793 if (vm86) {
bellardeaa728e2008-05-28 12:51:20 +0000794 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
795 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
796 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
797 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
798 }
799 ss = (ss & ~3) | dpl;
800 cpu_x86_load_seg_cache(env, R_SS, ss,
801 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
802 }
803 SET_ESP(esp, sp_mask);
804
805 selector = (selector & ~3) | dpl;
806 cpu_x86_load_seg_cache(env, R_CS, selector,
807 get_seg_base(e1, e2),
808 get_seg_limit(e1, e2),
809 e2);
bellardeaa728e2008-05-28 12:51:20 +0000810 env->eip = offset;
bellardeaa728e2008-05-28 12:51:20 +0000811}
812
813#ifdef TARGET_X86_64
814
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300815#define PUSHQ_RA(sp, val, ra) \
Blue Swirl20054ef2012-04-28 15:33:48 +0000816 { \
817 sp -= 8; \
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300818 cpu_stq_kernel_ra(env, sp, (val), ra); \
Blue Swirl20054ef2012-04-28 15:33:48 +0000819 }
bellardeaa728e2008-05-28 12:51:20 +0000820
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300821#define POPQ_RA(sp, val, ra) \
Blue Swirl20054ef2012-04-28 15:33:48 +0000822 { \
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300823 val = cpu_ldq_kernel_ra(env, sp, ra); \
Blue Swirl20054ef2012-04-28 15:33:48 +0000824 sp += 8; \
825 }
bellardeaa728e2008-05-28 12:51:20 +0000826
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300827#define PUSHQ(sp, val) PUSHQ_RA(sp, val, 0)
828#define POPQ(sp, val) POPQ_RA(sp, val, 0)
829
Blue Swirl2999a0b2012-04-29 19:47:06 +0000830static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
bellardeaa728e2008-05-28 12:51:20 +0000831{
Andreas Färbera47dddd2013-09-03 17:38:47 +0200832 X86CPU *cpu = x86_env_get_cpu(env);
bellardeaa728e2008-05-28 12:51:20 +0000833 int index;
834
835#if 0
836 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
837 env->tr.base, env->tr.limit);
838#endif
839
Blue Swirl20054ef2012-04-28 15:33:48 +0000840 if (!(env->tr.flags & DESC_P_MASK)) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200841 cpu_abort(CPU(cpu), "invalid tss");
Blue Swirl20054ef2012-04-28 15:33:48 +0000842 }
bellardeaa728e2008-05-28 12:51:20 +0000843 index = 8 * level + 4;
Blue Swirl20054ef2012-04-28 15:33:48 +0000844 if ((index + 7) > env->tr.limit) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000845 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000846 }
Blue Swirl329e6072012-04-29 19:11:01 +0000847 return cpu_ldq_kernel(env, env->tr.base + index);
bellardeaa728e2008-05-28 12:51:20 +0000848}
849
850/* 64 bit interrupt */
Blue Swirl2999a0b2012-04-29 19:47:06 +0000851static void do_interrupt64(CPUX86State *env, int intno, int is_int,
852 int error_code, target_ulong next_eip, int is_hw)
bellardeaa728e2008-05-28 12:51:20 +0000853{
854 SegmentCache *dt;
855 target_ulong ptr;
856 int type, dpl, selector, cpl, ist;
857 int has_error_code, new_stack;
858 uint32_t e1, e2, e3, ss;
859 target_ulong old_eip, esp, offset;
bellardeaa728e2008-05-28 12:51:20 +0000860
bellardeaa728e2008-05-28 12:51:20 +0000861 has_error_code = 0;
Blue Swirl20054ef2012-04-28 15:33:48 +0000862 if (!is_int && !is_hw) {
863 has_error_code = exception_has_error_code(intno);
864 }
865 if (is_int) {
bellardeaa728e2008-05-28 12:51:20 +0000866 old_eip = next_eip;
Blue Swirl20054ef2012-04-28 15:33:48 +0000867 } else {
bellardeaa728e2008-05-28 12:51:20 +0000868 old_eip = env->eip;
Blue Swirl20054ef2012-04-28 15:33:48 +0000869 }
bellardeaa728e2008-05-28 12:51:20 +0000870
871 dt = &env->idt;
Blue Swirl20054ef2012-04-28 15:33:48 +0000872 if (intno * 16 + 15 > dt->limit) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000873 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000874 }
bellardeaa728e2008-05-28 12:51:20 +0000875 ptr = dt->base + intno * 16;
Blue Swirl329e6072012-04-29 19:11:01 +0000876 e1 = cpu_ldl_kernel(env, ptr);
877 e2 = cpu_ldl_kernel(env, ptr + 4);
878 e3 = cpu_ldl_kernel(env, ptr + 8);
bellardeaa728e2008-05-28 12:51:20 +0000879 /* check gate type */
880 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
Blue Swirl20054ef2012-04-28 15:33:48 +0000881 switch (type) {
bellardeaa728e2008-05-28 12:51:20 +0000882 case 14: /* 386 interrupt gate */
883 case 15: /* 386 trap gate */
884 break;
885 default:
Blue Swirl77b2bc22012-04-28 19:35:10 +0000886 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
bellardeaa728e2008-05-28 12:51:20 +0000887 break;
888 }
889 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
890 cpl = env->hflags & HF_CPL_MASK;
ths1235fc02008-06-03 19:51:57 +0000891 /* check privilege if software int */
Blue Swirl20054ef2012-04-28 15:33:48 +0000892 if (is_int && dpl < cpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000893 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000894 }
bellardeaa728e2008-05-28 12:51:20 +0000895 /* check valid bit */
Blue Swirl20054ef2012-04-28 15:33:48 +0000896 if (!(e2 & DESC_P_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000897 raise_exception_err(env, EXCP0B_NOSEG, intno * 16 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000898 }
bellardeaa728e2008-05-28 12:51:20 +0000899 selector = e1 >> 16;
900 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
901 ist = e2 & 7;
Blue Swirl20054ef2012-04-28 15:33:48 +0000902 if ((selector & 0xfffc) == 0) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000903 raise_exception_err(env, EXCP0D_GPF, 0);
Blue Swirl20054ef2012-04-28 15:33:48 +0000904 }
bellardeaa728e2008-05-28 12:51:20 +0000905
Blue Swirl2999a0b2012-04-29 19:47:06 +0000906 if (load_segment(env, &e1, &e2, selector) != 0) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000907 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000908 }
909 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000910 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000911 }
bellardeaa728e2008-05-28 12:51:20 +0000912 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +0000913 if (dpl > cpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000914 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000915 }
916 if (!(e2 & DESC_P_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000917 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000918 }
919 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000920 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000921 }
bellardeaa728e2008-05-28 12:51:20 +0000922 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
923 /* to inner privilege */
bellardeaa728e2008-05-28 12:51:20 +0000924 new_stack = 1;
Paolo Bonziniae67dc72014-11-12 12:04:56 +0100925 esp = get_rsp_from_tss(env, ist != 0 ? ist + 3 : dpl);
926 ss = 0;
bellardeaa728e2008-05-28 12:51:20 +0000927 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
928 /* to same privilege */
Blue Swirl20054ef2012-04-28 15:33:48 +0000929 if (env->eflags & VM_MASK) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000930 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000931 }
bellardeaa728e2008-05-28 12:51:20 +0000932 new_stack = 0;
Paolo Bonziniae67dc72014-11-12 12:04:56 +0100933 esp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +0000934 dpl = cpl;
935 } else {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000936 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
bellardeaa728e2008-05-28 12:51:20 +0000937 new_stack = 0; /* avoid warning */
938 esp = 0; /* avoid warning */
939 }
Paolo Bonziniae67dc72014-11-12 12:04:56 +0100940 esp &= ~0xfLL; /* align stack */
bellardeaa728e2008-05-28 12:51:20 +0000941
942 PUSHQ(esp, env->segs[R_SS].selector);
liguang08b3ded2013-05-28 16:21:04 +0800943 PUSHQ(esp, env->regs[R_ESP]);
Blue Swirl997ff0d2012-04-29 15:01:21 +0000944 PUSHQ(esp, cpu_compute_eflags(env));
bellardeaa728e2008-05-28 12:51:20 +0000945 PUSHQ(esp, env->segs[R_CS].selector);
946 PUSHQ(esp, old_eip);
947 if (has_error_code) {
948 PUSHQ(esp, error_code);
949 }
950
Kevin O'Connorfd460602014-04-29 16:38:31 -0400951 /* interrupt gate clear IF mask */
952 if ((type & 1) == 0) {
953 env->eflags &= ~IF_MASK;
954 }
955 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
956
bellardeaa728e2008-05-28 12:51:20 +0000957 if (new_stack) {
958 ss = 0 | dpl;
959 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
960 }
liguang08b3ded2013-05-28 16:21:04 +0800961 env->regs[R_ESP] = esp;
bellardeaa728e2008-05-28 12:51:20 +0000962
963 selector = (selector & ~3) | dpl;
964 cpu_x86_load_seg_cache(env, R_CS, selector,
965 get_seg_base(e1, e2),
966 get_seg_limit(e1, e2),
967 e2);
bellardeaa728e2008-05-28 12:51:20 +0000968 env->eip = offset;
bellardeaa728e2008-05-28 12:51:20 +0000969}
970#endif
971
blueswir1d9957a82008-12-13 11:49:17 +0000972#ifdef TARGET_X86_64
bellardeaa728e2008-05-28 12:51:20 +0000973#if defined(CONFIG_USER_ONLY)
Blue Swirl2999a0b2012-04-29 19:47:06 +0000974void helper_syscall(CPUX86State *env, int next_eip_addend)
bellardeaa728e2008-05-28 12:51:20 +0000975{
Andreas Färber27103422013-08-26 08:31:06 +0200976 CPUState *cs = CPU(x86_env_get_cpu(env));
977
978 cs->exception_index = EXCP_SYSCALL;
bellardeaa728e2008-05-28 12:51:20 +0000979 env->exception_next_eip = env->eip + next_eip_addend;
Andreas Färber5638d182013-08-27 17:52:12 +0200980 cpu_loop_exit(cs);
bellardeaa728e2008-05-28 12:51:20 +0000981}
982#else
Blue Swirl2999a0b2012-04-29 19:47:06 +0000983void helper_syscall(CPUX86State *env, int next_eip_addend)
bellardeaa728e2008-05-28 12:51:20 +0000984{
985 int selector;
986
987 if (!(env->efer & MSR_EFER_SCE)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300988 raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
bellardeaa728e2008-05-28 12:51:20 +0000989 }
990 selector = (env->star >> 32) & 0xffff;
bellardeaa728e2008-05-28 12:51:20 +0000991 if (env->hflags & HF_LMA_MASK) {
992 int code64;
993
liguanga4165612013-05-28 16:21:01 +0800994 env->regs[R_ECX] = env->eip + next_eip_addend;
Blue Swirl997ff0d2012-04-29 15:01:21 +0000995 env->regs[11] = cpu_compute_eflags(env);
bellardeaa728e2008-05-28 12:51:20 +0000996
997 code64 = env->hflags & HF_CS64_MASK;
998
Kevin O'Connorfd460602014-04-29 16:38:31 -0400999 env->eflags &= ~env->fmask;
1000 cpu_load_eflags(env, env->eflags, 0);
bellardeaa728e2008-05-28 12:51:20 +00001001 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1002 0, 0xffffffff,
1003 DESC_G_MASK | DESC_P_MASK |
1004 DESC_S_MASK |
Blue Swirl20054ef2012-04-28 15:33:48 +00001005 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1006 DESC_L_MASK);
bellardeaa728e2008-05-28 12:51:20 +00001007 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1008 0, 0xffffffff,
1009 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1010 DESC_S_MASK |
1011 DESC_W_MASK | DESC_A_MASK);
Blue Swirl20054ef2012-04-28 15:33:48 +00001012 if (code64) {
bellardeaa728e2008-05-28 12:51:20 +00001013 env->eip = env->lstar;
Blue Swirl20054ef2012-04-28 15:33:48 +00001014 } else {
bellardeaa728e2008-05-28 12:51:20 +00001015 env->eip = env->cstar;
Blue Swirl20054ef2012-04-28 15:33:48 +00001016 }
blueswir1d9957a82008-12-13 11:49:17 +00001017 } else {
liguanga4165612013-05-28 16:21:01 +08001018 env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend);
bellardeaa728e2008-05-28 12:51:20 +00001019
Kevin O'Connorfd460602014-04-29 16:38:31 -04001020 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
bellardeaa728e2008-05-28 12:51:20 +00001021 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1022 0, 0xffffffff,
1023 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1024 DESC_S_MASK |
1025 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1026 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1027 0, 0xffffffff,
1028 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1029 DESC_S_MASK |
1030 DESC_W_MASK | DESC_A_MASK);
bellardeaa728e2008-05-28 12:51:20 +00001031 env->eip = (uint32_t)env->star;
1032 }
1033}
1034#endif
blueswir1d9957a82008-12-13 11:49:17 +00001035#endif
bellardeaa728e2008-05-28 12:51:20 +00001036
blueswir1d9957a82008-12-13 11:49:17 +00001037#ifdef TARGET_X86_64
Blue Swirl2999a0b2012-04-29 19:47:06 +00001038void helper_sysret(CPUX86State *env, int dflag)
bellardeaa728e2008-05-28 12:51:20 +00001039{
1040 int cpl, selector;
1041
1042 if (!(env->efer & MSR_EFER_SCE)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001043 raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001044 }
1045 cpl = env->hflags & HF_CPL_MASK;
1046 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001047 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001048 }
1049 selector = (env->star >> 48) & 0xffff;
bellardeaa728e2008-05-28 12:51:20 +00001050 if (env->hflags & HF_LMA_MASK) {
Kevin O'Connorfd460602014-04-29 16:38:31 -04001051 cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK
1052 | ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK |
1053 NT_MASK);
bellardeaa728e2008-05-28 12:51:20 +00001054 if (dflag == 2) {
1055 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1056 0, 0xffffffff,
1057 DESC_G_MASK | DESC_P_MASK |
1058 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1059 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1060 DESC_L_MASK);
liguanga4165612013-05-28 16:21:01 +08001061 env->eip = env->regs[R_ECX];
bellardeaa728e2008-05-28 12:51:20 +00001062 } else {
1063 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1064 0, 0xffffffff,
1065 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1066 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1067 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
liguanga4165612013-05-28 16:21:01 +08001068 env->eip = (uint32_t)env->regs[R_ECX];
bellardeaa728e2008-05-28 12:51:20 +00001069 }
Bill Paulac576222015-03-09 15:48:01 -07001070 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) | 3,
bellardeaa728e2008-05-28 12:51:20 +00001071 0, 0xffffffff,
1072 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1073 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1074 DESC_W_MASK | DESC_A_MASK);
blueswir1d9957a82008-12-13 11:49:17 +00001075 } else {
Kevin O'Connorfd460602014-04-29 16:38:31 -04001076 env->eflags |= IF_MASK;
bellardeaa728e2008-05-28 12:51:20 +00001077 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1078 0, 0xffffffff,
1079 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1080 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1081 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
liguanga4165612013-05-28 16:21:01 +08001082 env->eip = (uint32_t)env->regs[R_ECX];
Bill Paulac576222015-03-09 15:48:01 -07001083 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) | 3,
bellardeaa728e2008-05-28 12:51:20 +00001084 0, 0xffffffff,
1085 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1086 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1087 DESC_W_MASK | DESC_A_MASK);
bellardeaa728e2008-05-28 12:51:20 +00001088 }
bellardeaa728e2008-05-28 12:51:20 +00001089}
blueswir1d9957a82008-12-13 11:49:17 +00001090#endif
bellardeaa728e2008-05-28 12:51:20 +00001091
1092/* real mode interrupt */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001093static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
1094 int error_code, unsigned int next_eip)
bellardeaa728e2008-05-28 12:51:20 +00001095{
1096 SegmentCache *dt;
1097 target_ulong ptr, ssp;
1098 int selector;
1099 uint32_t offset, esp;
1100 uint32_t old_cs, old_eip;
bellardeaa728e2008-05-28 12:51:20 +00001101
Blue Swirl20054ef2012-04-28 15:33:48 +00001102 /* real mode (simpler!) */
bellardeaa728e2008-05-28 12:51:20 +00001103 dt = &env->idt;
Blue Swirl20054ef2012-04-28 15:33:48 +00001104 if (intno * 4 + 3 > dt->limit) {
Blue Swirl77b2bc22012-04-28 19:35:10 +00001105 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +00001106 }
bellardeaa728e2008-05-28 12:51:20 +00001107 ptr = dt->base + intno * 4;
Blue Swirl329e6072012-04-29 19:11:01 +00001108 offset = cpu_lduw_kernel(env, ptr);
1109 selector = cpu_lduw_kernel(env, ptr + 2);
liguang08b3ded2013-05-28 16:21:04 +08001110 esp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +00001111 ssp = env->segs[R_SS].base;
Blue Swirl20054ef2012-04-28 15:33:48 +00001112 if (is_int) {
bellardeaa728e2008-05-28 12:51:20 +00001113 old_eip = next_eip;
Blue Swirl20054ef2012-04-28 15:33:48 +00001114 } else {
bellardeaa728e2008-05-28 12:51:20 +00001115 old_eip = env->eip;
Blue Swirl20054ef2012-04-28 15:33:48 +00001116 }
bellardeaa728e2008-05-28 12:51:20 +00001117 old_cs = env->segs[R_CS].selector;
Blue Swirl20054ef2012-04-28 15:33:48 +00001118 /* XXX: use SS segment size? */
Blue Swirl997ff0d2012-04-29 15:01:21 +00001119 PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env));
bellardeaa728e2008-05-28 12:51:20 +00001120 PUSHW(ssp, esp, 0xffff, old_cs);
1121 PUSHW(ssp, esp, 0xffff, old_eip);
1122
1123 /* update processor state */
liguang08b3ded2013-05-28 16:21:04 +08001124 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | (esp & 0xffff);
bellardeaa728e2008-05-28 12:51:20 +00001125 env->eip = offset;
1126 env->segs[R_CS].selector = selector;
1127 env->segs[R_CS].base = (selector << 4);
1128 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1129}
1130
Blue Swirle694d4e2011-05-16 19:38:48 +00001131#if defined(CONFIG_USER_ONLY)
Peter Maydell33271822016-05-17 15:18:06 +01001132/* fake user mode interrupt. is_int is TRUE if coming from the int
1133 * instruction. next_eip is the env->eip value AFTER the interrupt
1134 * instruction. It is only relevant if is_int is TRUE or if intno
1135 * is EXCP_SYSCALL.
1136 */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001137static void do_interrupt_user(CPUX86State *env, int intno, int is_int,
1138 int error_code, target_ulong next_eip)
bellardeaa728e2008-05-28 12:51:20 +00001139{
Stanislav Shmarov885b7c42016-09-13 16:23:28 +03001140 if (is_int) {
1141 SegmentCache *dt;
1142 target_ulong ptr;
1143 int dpl, cpl, shift;
1144 uint32_t e2;
bellardeaa728e2008-05-28 12:51:20 +00001145
Stanislav Shmarov885b7c42016-09-13 16:23:28 +03001146 dt = &env->idt;
1147 if (env->hflags & HF_LMA_MASK) {
1148 shift = 4;
1149 } else {
1150 shift = 3;
1151 }
1152 ptr = dt->base + (intno << shift);
1153 e2 = cpu_ldl_kernel(env, ptr + 4);
bellardeaa728e2008-05-28 12:51:20 +00001154
Stanislav Shmarov885b7c42016-09-13 16:23:28 +03001155 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1156 cpl = env->hflags & HF_CPL_MASK;
1157 /* check privilege if software int */
1158 if (dpl < cpl) {
1159 raise_exception_err(env, EXCP0D_GPF, (intno << shift) + 2);
1160 }
Blue Swirl20054ef2012-04-28 15:33:48 +00001161 }
bellardeaa728e2008-05-28 12:51:20 +00001162
1163 /* Since we emulate only user space, we cannot do more than
1164 exiting the emulation with the suitable exception and error
Jincheng Miao47575992014-08-08 11:56:54 +08001165 code. So update EIP for INT 0x80 and EXCP_SYSCALL. */
1166 if (is_int || intno == EXCP_SYSCALL) {
liguanga78d0ea2013-05-28 16:21:07 +08001167 env->eip = next_eip;
Blue Swirl20054ef2012-04-28 15:33:48 +00001168 }
bellardeaa728e2008-05-28 12:51:20 +00001169}
1170
Blue Swirle694d4e2011-05-16 19:38:48 +00001171#else
1172
Blue Swirl2999a0b2012-04-29 19:47:06 +00001173static void handle_even_inj(CPUX86State *env, int intno, int is_int,
1174 int error_code, int is_hw, int rm)
aliguori2ed51f52009-04-22 20:20:07 +00001175{
Andreas Färber19d6ca12014-03-09 19:15:27 +01001176 CPUState *cs = CPU(x86_env_get_cpu(env));
Paolo Bonzinib216aa62015-04-08 13:39:37 +02001177 uint32_t event_inj = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb,
Blue Swirl20054ef2012-04-28 15:33:48 +00001178 control.event_inj));
1179
aliguori2ed51f52009-04-22 20:20:07 +00001180 if (!(event_inj & SVM_EVTINJ_VALID)) {
Blue Swirl20054ef2012-04-28 15:33:48 +00001181 int type;
1182
1183 if (is_int) {
1184 type = SVM_EVTINJ_TYPE_SOFT;
1185 } else {
1186 type = SVM_EVTINJ_TYPE_EXEPT;
1187 }
1188 event_inj = intno | type | SVM_EVTINJ_VALID;
1189 if (!rm && exception_has_error_code(intno)) {
1190 event_inj |= SVM_EVTINJ_VALID_ERR;
Paolo Bonzinib216aa62015-04-08 13:39:37 +02001191 x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb,
Blue Swirl20054ef2012-04-28 15:33:48 +00001192 control.event_inj_err),
1193 error_code);
1194 }
Paolo Bonzinib216aa62015-04-08 13:39:37 +02001195 x86_stl_phys(cs,
Edgar E. Iglesiasab1da852013-12-17 15:07:29 +10001196 env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
Blue Swirl20054ef2012-04-28 15:33:48 +00001197 event_inj);
aliguori2ed51f52009-04-22 20:20:07 +00001198 }
1199}
aliguori00ea18d2009-04-23 13:16:56 +00001200#endif
aliguori2ed51f52009-04-22 20:20:07 +00001201
bellardeaa728e2008-05-28 12:51:20 +00001202/*
1203 * Begin execution of an interruption. is_int is TRUE if coming from
liguanga78d0ea2013-05-28 16:21:07 +08001204 * the int instruction. next_eip is the env->eip value AFTER the interrupt
bellardeaa728e2008-05-28 12:51:20 +00001205 * instruction. It is only relevant if is_int is TRUE.
1206 */
Andreas Färberca4c8102013-07-03 02:00:09 +02001207static void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
Blue Swirl2999a0b2012-04-29 19:47:06 +00001208 int error_code, target_ulong next_eip, int is_hw)
bellardeaa728e2008-05-28 12:51:20 +00001209{
Andreas Färberca4c8102013-07-03 02:00:09 +02001210 CPUX86State *env = &cpu->env;
1211
aliguori8fec2b82009-01-15 22:36:53 +00001212 if (qemu_loglevel_mask(CPU_LOG_INT)) {
bellardeaa728e2008-05-28 12:51:20 +00001213 if ((env->cr[0] & CR0_PE_MASK)) {
1214 static int count;
Blue Swirl20054ef2012-04-28 15:33:48 +00001215
1216 qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
1217 " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1218 count, intno, error_code, is_int,
1219 env->hflags & HF_CPL_MASK,
liguanga78d0ea2013-05-28 16:21:07 +08001220 env->segs[R_CS].selector, env->eip,
1221 (int)env->segs[R_CS].base + env->eip,
liguang08b3ded2013-05-28 16:21:04 +08001222 env->segs[R_SS].selector, env->regs[R_ESP]);
bellardeaa728e2008-05-28 12:51:20 +00001223 if (intno == 0x0e) {
aliguori93fcfe32009-01-15 22:34:14 +00001224 qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
bellardeaa728e2008-05-28 12:51:20 +00001225 } else {
liguang4b34e3a2013-05-28 16:20:59 +08001226 qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]);
bellardeaa728e2008-05-28 12:51:20 +00001227 }
aliguori93fcfe32009-01-15 22:34:14 +00001228 qemu_log("\n");
Andreas Färbera0762852013-06-16 07:28:50 +02001229 log_cpu_state(CPU(cpu), CPU_DUMP_CCOP);
bellardeaa728e2008-05-28 12:51:20 +00001230#if 0
1231 {
1232 int i;
Adam Lackorzynski9bd54942010-04-01 23:46:20 +02001233 target_ulong ptr;
Blue Swirl20054ef2012-04-28 15:33:48 +00001234
aliguori93fcfe32009-01-15 22:34:14 +00001235 qemu_log(" code=");
bellardeaa728e2008-05-28 12:51:20 +00001236 ptr = env->segs[R_CS].base + env->eip;
Blue Swirl20054ef2012-04-28 15:33:48 +00001237 for (i = 0; i < 16; i++) {
aliguori93fcfe32009-01-15 22:34:14 +00001238 qemu_log(" %02x", ldub(ptr + i));
bellardeaa728e2008-05-28 12:51:20 +00001239 }
aliguori93fcfe32009-01-15 22:34:14 +00001240 qemu_log("\n");
bellardeaa728e2008-05-28 12:51:20 +00001241 }
1242#endif
1243 count++;
1244 }
1245 }
1246 if (env->cr[0] & CR0_PE_MASK) {
aliguori00ea18d2009-04-23 13:16:56 +00001247#if !defined(CONFIG_USER_ONLY)
Blue Swirl20054ef2012-04-28 15:33:48 +00001248 if (env->hflags & HF_SVMI_MASK) {
Blue Swirl2999a0b2012-04-29 19:47:06 +00001249 handle_even_inj(env, intno, is_int, error_code, is_hw, 0);
Blue Swirl20054ef2012-04-28 15:33:48 +00001250 }
aliguori00ea18d2009-04-23 13:16:56 +00001251#endif
blueswir1eb38c522008-09-06 17:47:39 +00001252#ifdef TARGET_X86_64
bellardeaa728e2008-05-28 12:51:20 +00001253 if (env->hflags & HF_LMA_MASK) {
Blue Swirl2999a0b2012-04-29 19:47:06 +00001254 do_interrupt64(env, intno, is_int, error_code, next_eip, is_hw);
bellardeaa728e2008-05-28 12:51:20 +00001255 } else
1256#endif
1257 {
Blue Swirl2999a0b2012-04-29 19:47:06 +00001258 do_interrupt_protected(env, intno, is_int, error_code, next_eip,
1259 is_hw);
bellardeaa728e2008-05-28 12:51:20 +00001260 }
1261 } else {
aliguori00ea18d2009-04-23 13:16:56 +00001262#if !defined(CONFIG_USER_ONLY)
Blue Swirl20054ef2012-04-28 15:33:48 +00001263 if (env->hflags & HF_SVMI_MASK) {
Blue Swirl2999a0b2012-04-29 19:47:06 +00001264 handle_even_inj(env, intno, is_int, error_code, is_hw, 1);
Blue Swirl20054ef2012-04-28 15:33:48 +00001265 }
aliguori00ea18d2009-04-23 13:16:56 +00001266#endif
Blue Swirl2999a0b2012-04-29 19:47:06 +00001267 do_interrupt_real(env, intno, is_int, error_code, next_eip);
bellardeaa728e2008-05-28 12:51:20 +00001268 }
aliguori2ed51f52009-04-22 20:20:07 +00001269
aliguori00ea18d2009-04-23 13:16:56 +00001270#if !defined(CONFIG_USER_ONLY)
aliguori2ed51f52009-04-22 20:20:07 +00001271 if (env->hflags & HF_SVMI_MASK) {
Edgar E. Iglesiasfdfba1a2013-11-15 14:46:38 +01001272 CPUState *cs = CPU(cpu);
Paolo Bonzinib216aa62015-04-08 13:39:37 +02001273 uint32_t event_inj = x86_ldl_phys(cs, env->vm_vmcb +
Blue Swirl20054ef2012-04-28 15:33:48 +00001274 offsetof(struct vmcb,
1275 control.event_inj));
1276
Paolo Bonzinib216aa62015-04-08 13:39:37 +02001277 x86_stl_phys(cs,
Edgar E. Iglesiasab1da852013-12-17 15:07:29 +10001278 env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
Blue Swirl20054ef2012-04-28 15:33:48 +00001279 event_inj & ~SVM_EVTINJ_VALID);
aliguori2ed51f52009-04-22 20:20:07 +00001280 }
aliguori00ea18d2009-04-23 13:16:56 +00001281#endif
bellardeaa728e2008-05-28 12:51:20 +00001282}
1283
Andreas Färber97a8ea52013-02-02 10:57:51 +01001284void x86_cpu_do_interrupt(CPUState *cs)
Blue Swirle694d4e2011-05-16 19:38:48 +00001285{
Andreas Färber97a8ea52013-02-02 10:57:51 +01001286 X86CPU *cpu = X86_CPU(cs);
1287 CPUX86State *env = &cpu->env;
1288
Blue Swirle694d4e2011-05-16 19:38:48 +00001289#if defined(CONFIG_USER_ONLY)
1290 /* if user mode only, we simulate a fake exception
1291 which will be handled outside the cpu execution
1292 loop */
Andreas Färber27103422013-08-26 08:31:06 +02001293 do_interrupt_user(env, cs->exception_index,
Blue Swirle694d4e2011-05-16 19:38:48 +00001294 env->exception_is_int,
1295 env->error_code,
1296 env->exception_next_eip);
1297 /* successfully delivered */
1298 env->old_exception = -1;
1299#else
1300 /* simulate a real cpu exception. On i386, it can
1301 trigger new exceptions, but we do not handle
1302 double or triple faults yet. */
Andreas Färber27103422013-08-26 08:31:06 +02001303 do_interrupt_all(cpu, cs->exception_index,
Blue Swirle694d4e2011-05-16 19:38:48 +00001304 env->exception_is_int,
1305 env->error_code,
1306 env->exception_next_eip, 0);
1307 /* successfully delivered */
1308 env->old_exception = -1;
1309#endif
Blue Swirle694d4e2011-05-16 19:38:48 +00001310}
1311
Blue Swirl2999a0b2012-04-29 19:47:06 +00001312void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
Blue Swirle694d4e2011-05-16 19:38:48 +00001313{
Andreas Färberca4c8102013-07-03 02:00:09 +02001314 do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw);
Blue Swirle694d4e2011-05-16 19:38:48 +00001315}
1316
Richard Henderson42f53fe2014-09-13 09:45:33 -07001317bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
1318{
1319 X86CPU *cpu = X86_CPU(cs);
1320 CPUX86State *env = &cpu->env;
1321 bool ret = false;
1322
1323#if !defined(CONFIG_USER_ONLY)
1324 if (interrupt_request & CPU_INTERRUPT_POLL) {
1325 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
1326 apic_poll_irq(cpu->apic_state);
Pavel Dovgalyuka4fc3212015-09-17 19:24:11 +03001327 /* Don't process multiple interrupt requests in a single call.
1328 This is required to make icount-driven execution deterministic. */
1329 return true;
Richard Henderson42f53fe2014-09-13 09:45:33 -07001330 }
1331#endif
1332 if (interrupt_request & CPU_INTERRUPT_SIPI) {
1333 do_cpu_sipi(cpu);
1334 } else if (env->hflags2 & HF2_GIF_MASK) {
1335 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
1336 !(env->hflags & HF_SMM_MASK)) {
1337 cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0);
1338 cs->interrupt_request &= ~CPU_INTERRUPT_SMI;
1339 do_smm_enter(cpu);
1340 ret = true;
1341 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
1342 !(env->hflags2 & HF2_NMI_MASK)) {
1343 cs->interrupt_request &= ~CPU_INTERRUPT_NMI;
1344 env->hflags2 |= HF2_NMI_MASK;
1345 do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
1346 ret = true;
1347 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
1348 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
1349 do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
1350 ret = true;
1351 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
1352 (((env->hflags2 & HF2_VINTR_MASK) &&
1353 (env->hflags2 & HF2_HIF_MASK)) ||
1354 (!(env->hflags2 & HF2_VINTR_MASK) &&
1355 (env->eflags & IF_MASK &&
1356 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
1357 int intno;
1358 cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0);
1359 cs->interrupt_request &= ~(CPU_INTERRUPT_HARD |
1360 CPU_INTERRUPT_VIRQ);
1361 intno = cpu_get_pic_interrupt(env);
1362 qemu_log_mask(CPU_LOG_TB_IN_ASM,
1363 "Servicing hardware INT=0x%02x\n", intno);
1364 do_interrupt_x86_hardirq(env, intno, 1);
1365 /* ensure that no TB jump will be modified as
1366 the program flow was changed */
1367 ret = true;
1368#if !defined(CONFIG_USER_ONLY)
1369 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
1370 (env->eflags & IF_MASK) &&
1371 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
1372 int intno;
1373 /* FIXME: this should respect TPR */
1374 cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0);
Paolo Bonzinib216aa62015-04-08 13:39:37 +02001375 intno = x86_ldl_phys(cs, env->vm_vmcb
Richard Henderson42f53fe2014-09-13 09:45:33 -07001376 + offsetof(struct vmcb, control.int_vector));
1377 qemu_log_mask(CPU_LOG_TB_IN_ASM,
1378 "Servicing virtual hardware INT=0x%02x\n", intno);
1379 do_interrupt_x86_hardirq(env, intno, 1);
1380 cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
1381 ret = true;
1382#endif
1383 }
1384 }
1385
1386 return ret;
1387}
1388
Blue Swirl2999a0b2012-04-29 19:47:06 +00001389void helper_lldt(CPUX86State *env, int selector)
bellardeaa728e2008-05-28 12:51:20 +00001390{
1391 SegmentCache *dt;
1392 uint32_t e1, e2;
1393 int index, entry_limit;
1394 target_ulong ptr;
1395
1396 selector &= 0xffff;
1397 if ((selector & 0xfffc) == 0) {
1398 /* XXX: NULL selector case: invalid LDT */
1399 env->ldt.base = 0;
1400 env->ldt.limit = 0;
1401 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00001402 if (selector & 0x4) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001403 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001404 }
bellardeaa728e2008-05-28 12:51:20 +00001405 dt = &env->gdt;
1406 index = selector & ~7;
1407#ifdef TARGET_X86_64
Blue Swirl20054ef2012-04-28 15:33:48 +00001408 if (env->hflags & HF_LMA_MASK) {
bellardeaa728e2008-05-28 12:51:20 +00001409 entry_limit = 15;
Blue Swirl20054ef2012-04-28 15:33:48 +00001410 } else
bellardeaa728e2008-05-28 12:51:20 +00001411#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00001412 {
bellardeaa728e2008-05-28 12:51:20 +00001413 entry_limit = 7;
Blue Swirl20054ef2012-04-28 15:33:48 +00001414 }
1415 if ((index + entry_limit) > dt->limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001416 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001417 }
bellardeaa728e2008-05-28 12:51:20 +00001418 ptr = dt->base + index;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001419 e1 = cpu_ldl_kernel_ra(env, ptr, GETPC());
1420 e2 = cpu_ldl_kernel_ra(env, ptr + 4, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001421 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001422 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001423 }
1424 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001425 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001426 }
bellardeaa728e2008-05-28 12:51:20 +00001427#ifdef TARGET_X86_64
1428 if (env->hflags & HF_LMA_MASK) {
1429 uint32_t e3;
Blue Swirl20054ef2012-04-28 15:33:48 +00001430
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001431 e3 = cpu_ldl_kernel_ra(env, ptr + 8, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001432 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1433 env->ldt.base |= (target_ulong)e3 << 32;
1434 } else
1435#endif
1436 {
1437 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1438 }
1439 }
1440 env->ldt.selector = selector;
1441}
1442
Blue Swirl2999a0b2012-04-29 19:47:06 +00001443void helper_ltr(CPUX86State *env, int selector)
bellardeaa728e2008-05-28 12:51:20 +00001444{
1445 SegmentCache *dt;
1446 uint32_t e1, e2;
1447 int index, type, entry_limit;
1448 target_ulong ptr;
1449
1450 selector &= 0xffff;
1451 if ((selector & 0xfffc) == 0) {
1452 /* NULL selector case: invalid TR */
1453 env->tr.base = 0;
1454 env->tr.limit = 0;
1455 env->tr.flags = 0;
1456 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00001457 if (selector & 0x4) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001458 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001459 }
bellardeaa728e2008-05-28 12:51:20 +00001460 dt = &env->gdt;
1461 index = selector & ~7;
1462#ifdef TARGET_X86_64
Blue Swirl20054ef2012-04-28 15:33:48 +00001463 if (env->hflags & HF_LMA_MASK) {
bellardeaa728e2008-05-28 12:51:20 +00001464 entry_limit = 15;
Blue Swirl20054ef2012-04-28 15:33:48 +00001465 } else
bellardeaa728e2008-05-28 12:51:20 +00001466#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00001467 {
bellardeaa728e2008-05-28 12:51:20 +00001468 entry_limit = 7;
Blue Swirl20054ef2012-04-28 15:33:48 +00001469 }
1470 if ((index + entry_limit) > dt->limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001471 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001472 }
bellardeaa728e2008-05-28 12:51:20 +00001473 ptr = dt->base + index;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001474 e1 = cpu_ldl_kernel_ra(env, ptr, GETPC());
1475 e2 = cpu_ldl_kernel_ra(env, ptr + 4, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001476 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1477 if ((e2 & DESC_S_MASK) ||
Blue Swirl20054ef2012-04-28 15:33:48 +00001478 (type != 1 && type != 9)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001479 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001480 }
1481 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001482 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001483 }
bellardeaa728e2008-05-28 12:51:20 +00001484#ifdef TARGET_X86_64
1485 if (env->hflags & HF_LMA_MASK) {
1486 uint32_t e3, e4;
Blue Swirl20054ef2012-04-28 15:33:48 +00001487
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001488 e3 = cpu_ldl_kernel_ra(env, ptr + 8, GETPC());
1489 e4 = cpu_ldl_kernel_ra(env, ptr + 12, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001490 if ((e4 >> DESC_TYPE_SHIFT) & 0xf) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001491 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001492 }
bellardeaa728e2008-05-28 12:51:20 +00001493 load_seg_cache_raw_dt(&env->tr, e1, e2);
1494 env->tr.base |= (target_ulong)e3 << 32;
1495 } else
1496#endif
1497 {
1498 load_seg_cache_raw_dt(&env->tr, e1, e2);
1499 }
1500 e2 |= DESC_TSS_BUSY_MASK;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001501 cpu_stl_kernel_ra(env, ptr + 4, e2, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001502 }
1503 env->tr.selector = selector;
1504}
1505
1506/* only works if protected mode and not VM86. seg_reg must be != R_CS */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001507void helper_load_seg(CPUX86State *env, int seg_reg, int selector)
bellardeaa728e2008-05-28 12:51:20 +00001508{
1509 uint32_t e1, e2;
1510 int cpl, dpl, rpl;
1511 SegmentCache *dt;
1512 int index;
1513 target_ulong ptr;
1514
1515 selector &= 0xffff;
1516 cpl = env->hflags & HF_CPL_MASK;
1517 if ((selector & 0xfffc) == 0) {
1518 /* null selector case */
1519 if (seg_reg == R_SS
1520#ifdef TARGET_X86_64
1521 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
1522#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00001523 ) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001524 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001525 }
bellardeaa728e2008-05-28 12:51:20 +00001526 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1527 } else {
1528
Blue Swirl20054ef2012-04-28 15:33:48 +00001529 if (selector & 0x4) {
bellardeaa728e2008-05-28 12:51:20 +00001530 dt = &env->ldt;
Blue Swirl20054ef2012-04-28 15:33:48 +00001531 } else {
bellardeaa728e2008-05-28 12:51:20 +00001532 dt = &env->gdt;
Blue Swirl20054ef2012-04-28 15:33:48 +00001533 }
bellardeaa728e2008-05-28 12:51:20 +00001534 index = selector & ~7;
Blue Swirl20054ef2012-04-28 15:33:48 +00001535 if ((index + 7) > dt->limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001536 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001537 }
bellardeaa728e2008-05-28 12:51:20 +00001538 ptr = dt->base + index;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001539 e1 = cpu_ldl_kernel_ra(env, ptr, GETPC());
1540 e2 = cpu_ldl_kernel_ra(env, ptr + 4, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001541
Blue Swirl20054ef2012-04-28 15:33:48 +00001542 if (!(e2 & DESC_S_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001543 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001544 }
bellardeaa728e2008-05-28 12:51:20 +00001545 rpl = selector & 3;
1546 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1547 if (seg_reg == R_SS) {
1548 /* must be writable segment */
Blue Swirl20054ef2012-04-28 15:33:48 +00001549 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001550 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001551 }
1552 if (rpl != cpl || dpl != cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001553 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001554 }
bellardeaa728e2008-05-28 12:51:20 +00001555 } else {
1556 /* must be readable segment */
Blue Swirl20054ef2012-04-28 15:33:48 +00001557 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001558 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001559 }
bellardeaa728e2008-05-28 12:51:20 +00001560
1561 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1562 /* if not conforming code, test rights */
Blue Swirl20054ef2012-04-28 15:33:48 +00001563 if (dpl < cpl || dpl < rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001564 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001565 }
bellardeaa728e2008-05-28 12:51:20 +00001566 }
1567 }
1568
1569 if (!(e2 & DESC_P_MASK)) {
Blue Swirl20054ef2012-04-28 15:33:48 +00001570 if (seg_reg == R_SS) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001571 raise_exception_err_ra(env, EXCP0C_STACK, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001572 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001573 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001574 }
bellardeaa728e2008-05-28 12:51:20 +00001575 }
1576
1577 /* set the access bit if not already set */
1578 if (!(e2 & DESC_A_MASK)) {
1579 e2 |= DESC_A_MASK;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001580 cpu_stl_kernel_ra(env, ptr + 4, e2, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001581 }
1582
1583 cpu_x86_load_seg_cache(env, seg_reg, selector,
1584 get_seg_base(e1, e2),
1585 get_seg_limit(e1, e2),
1586 e2);
1587#if 0
aliguori93fcfe32009-01-15 22:34:14 +00001588 qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
bellardeaa728e2008-05-28 12:51:20 +00001589 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1590#endif
1591 }
1592}
1593
1594/* protected mode jump */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001595void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001596 target_ulong next_eip)
bellardeaa728e2008-05-28 12:51:20 +00001597{
1598 int gate_cs, type;
1599 uint32_t e1, e2, cpl, dpl, rpl, limit;
bellardeaa728e2008-05-28 12:51:20 +00001600
Blue Swirl20054ef2012-04-28 15:33:48 +00001601 if ((new_cs & 0xfffc) == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001602 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001603 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001604 if (load_segment_ra(env, &e1, &e2, new_cs, GETPC()) != 0) {
1605 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001606 }
bellardeaa728e2008-05-28 12:51:20 +00001607 cpl = env->hflags & HF_CPL_MASK;
1608 if (e2 & DESC_S_MASK) {
Blue Swirl20054ef2012-04-28 15:33:48 +00001609 if (!(e2 & DESC_CS_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001610 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001611 }
bellardeaa728e2008-05-28 12:51:20 +00001612 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1613 if (e2 & DESC_C_MASK) {
1614 /* conforming code segment */
Blue Swirl20054ef2012-04-28 15:33:48 +00001615 if (dpl > cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001616 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001617 }
bellardeaa728e2008-05-28 12:51:20 +00001618 } else {
1619 /* non conforming code segment */
1620 rpl = new_cs & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00001621 if (rpl > cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001622 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001623 }
1624 if (dpl != cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001625 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001626 }
bellardeaa728e2008-05-28 12:51:20 +00001627 }
Blue Swirl20054ef2012-04-28 15:33:48 +00001628 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001629 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001630 }
bellardeaa728e2008-05-28 12:51:20 +00001631 limit = get_seg_limit(e1, e2);
1632 if (new_eip > limit &&
Blue Swirl20054ef2012-04-28 15:33:48 +00001633 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001634 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001635 }
bellardeaa728e2008-05-28 12:51:20 +00001636 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1637 get_seg_base(e1, e2), limit, e2);
liguanga78d0ea2013-05-28 16:21:07 +08001638 env->eip = new_eip;
bellardeaa728e2008-05-28 12:51:20 +00001639 } else {
1640 /* jump to call or task gate */
1641 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1642 rpl = new_cs & 3;
1643 cpl = env->hflags & HF_CPL_MASK;
1644 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +00001645 switch (type) {
bellardeaa728e2008-05-28 12:51:20 +00001646 case 1: /* 286 TSS */
1647 case 9: /* 386 TSS */
1648 case 5: /* task gate */
Blue Swirl20054ef2012-04-28 15:33:48 +00001649 if (dpl < cpl || dpl < rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001650 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001651 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001652 switch_tss_ra(env, new_cs, e1, e2, SWITCH_TSS_JMP, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001653 break;
1654 case 4: /* 286 call gate */
1655 case 12: /* 386 call gate */
Blue Swirl20054ef2012-04-28 15:33:48 +00001656 if ((dpl < cpl) || (dpl < rpl)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001657 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001658 }
1659 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001660 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001661 }
bellardeaa728e2008-05-28 12:51:20 +00001662 gate_cs = e1 >> 16;
1663 new_eip = (e1 & 0xffff);
Blue Swirl20054ef2012-04-28 15:33:48 +00001664 if (type == 12) {
bellardeaa728e2008-05-28 12:51:20 +00001665 new_eip |= (e2 & 0xffff0000);
Blue Swirl20054ef2012-04-28 15:33:48 +00001666 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001667 if (load_segment_ra(env, &e1, &e2, gate_cs, GETPC()) != 0) {
1668 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001669 }
bellardeaa728e2008-05-28 12:51:20 +00001670 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1671 /* must be code segment */
1672 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
Blue Swirl20054ef2012-04-28 15:33:48 +00001673 (DESC_S_MASK | DESC_CS_MASK))) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001674 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001675 }
bellardeaa728e2008-05-28 12:51:20 +00001676 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
Blue Swirl20054ef2012-04-28 15:33:48 +00001677 (!(e2 & DESC_C_MASK) && (dpl != cpl))) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001678 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001679 }
1680 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001681 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001682 }
bellardeaa728e2008-05-28 12:51:20 +00001683 limit = get_seg_limit(e1, e2);
Blue Swirl20054ef2012-04-28 15:33:48 +00001684 if (new_eip > limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001685 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001686 }
bellardeaa728e2008-05-28 12:51:20 +00001687 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1688 get_seg_base(e1, e2), limit, e2);
liguanga78d0ea2013-05-28 16:21:07 +08001689 env->eip = new_eip;
bellardeaa728e2008-05-28 12:51:20 +00001690 break;
1691 default:
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001692 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001693 break;
1694 }
1695 }
1696}
1697
1698/* real mode call */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001699void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1,
bellardeaa728e2008-05-28 12:51:20 +00001700 int shift, int next_eip)
1701{
1702 int new_eip;
1703 uint32_t esp, esp_mask;
1704 target_ulong ssp;
1705
1706 new_eip = new_eip1;
liguang08b3ded2013-05-28 16:21:04 +08001707 esp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +00001708 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1709 ssp = env->segs[R_SS].base;
1710 if (shift) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001711 PUSHL_RA(ssp, esp, esp_mask, env->segs[R_CS].selector, GETPC());
1712 PUSHL_RA(ssp, esp, esp_mask, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001713 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001714 PUSHW_RA(ssp, esp, esp_mask, env->segs[R_CS].selector, GETPC());
1715 PUSHW_RA(ssp, esp, esp_mask, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001716 }
1717
1718 SET_ESP(esp, esp_mask);
1719 env->eip = new_eip;
1720 env->segs[R_CS].selector = new_cs;
1721 env->segs[R_CS].base = (new_cs << 4);
1722}
1723
1724/* protected mode call */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001725void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001726 int shift, target_ulong next_eip)
bellardeaa728e2008-05-28 12:51:20 +00001727{
1728 int new_stack, i;
1729 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
blueswir11c918eb2009-01-14 19:27:02 +00001730 uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask;
bellardeaa728e2008-05-28 12:51:20 +00001731 uint32_t val, limit, old_sp_mask;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001732 target_ulong ssp, old_ssp;
bellardeaa728e2008-05-28 12:51:20 +00001733
aliguorid12d51d2009-01-15 21:48:06 +00001734 LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
Andreas Färber8995b7a2013-07-03 01:07:10 +02001735 LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
Blue Swirl20054ef2012-04-28 15:33:48 +00001736 if ((new_cs & 0xfffc) == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001737 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001738 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001739 if (load_segment_ra(env, &e1, &e2, new_cs, GETPC()) != 0) {
1740 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001741 }
bellardeaa728e2008-05-28 12:51:20 +00001742 cpl = env->hflags & HF_CPL_MASK;
aliguorid12d51d2009-01-15 21:48:06 +00001743 LOG_PCALL("desc=%08x:%08x\n", e1, e2);
bellardeaa728e2008-05-28 12:51:20 +00001744 if (e2 & DESC_S_MASK) {
Blue Swirl20054ef2012-04-28 15:33:48 +00001745 if (!(e2 & DESC_CS_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001746 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001747 }
bellardeaa728e2008-05-28 12:51:20 +00001748 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1749 if (e2 & DESC_C_MASK) {
1750 /* conforming code segment */
Blue Swirl20054ef2012-04-28 15:33:48 +00001751 if (dpl > cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001752 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001753 }
bellardeaa728e2008-05-28 12:51:20 +00001754 } else {
1755 /* non conforming code segment */
1756 rpl = new_cs & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00001757 if (rpl > cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001758 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001759 }
1760 if (dpl != cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001761 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001762 }
bellardeaa728e2008-05-28 12:51:20 +00001763 }
Blue Swirl20054ef2012-04-28 15:33:48 +00001764 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001765 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001766 }
bellardeaa728e2008-05-28 12:51:20 +00001767
1768#ifdef TARGET_X86_64
1769 /* XXX: check 16/32 bit cases in long mode */
1770 if (shift == 2) {
1771 target_ulong rsp;
Blue Swirl20054ef2012-04-28 15:33:48 +00001772
bellardeaa728e2008-05-28 12:51:20 +00001773 /* 64 bit case */
liguang08b3ded2013-05-28 16:21:04 +08001774 rsp = env->regs[R_ESP];
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001775 PUSHQ_RA(rsp, env->segs[R_CS].selector, GETPC());
1776 PUSHQ_RA(rsp, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001777 /* from this point, not restartable */
liguang08b3ded2013-05-28 16:21:04 +08001778 env->regs[R_ESP] = rsp;
bellardeaa728e2008-05-28 12:51:20 +00001779 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1780 get_seg_base(e1, e2),
1781 get_seg_limit(e1, e2), e2);
liguanga78d0ea2013-05-28 16:21:07 +08001782 env->eip = new_eip;
bellardeaa728e2008-05-28 12:51:20 +00001783 } else
1784#endif
1785 {
liguang08b3ded2013-05-28 16:21:04 +08001786 sp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +00001787 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1788 ssp = env->segs[R_SS].base;
1789 if (shift) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001790 PUSHL_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
1791 PUSHL_RA(ssp, sp, sp_mask, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001792 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001793 PUSHW_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
1794 PUSHW_RA(ssp, sp, sp_mask, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001795 }
1796
1797 limit = get_seg_limit(e1, e2);
Blue Swirl20054ef2012-04-28 15:33:48 +00001798 if (new_eip > limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001799 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001800 }
bellardeaa728e2008-05-28 12:51:20 +00001801 /* from this point, not restartable */
1802 SET_ESP(sp, sp_mask);
1803 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1804 get_seg_base(e1, e2), limit, e2);
liguanga78d0ea2013-05-28 16:21:07 +08001805 env->eip = new_eip;
bellardeaa728e2008-05-28 12:51:20 +00001806 }
1807 } else {
1808 /* check gate type */
1809 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1810 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1811 rpl = new_cs & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00001812 switch (type) {
bellardeaa728e2008-05-28 12:51:20 +00001813 case 1: /* available 286 TSS */
1814 case 9: /* available 386 TSS */
1815 case 5: /* task gate */
Blue Swirl20054ef2012-04-28 15:33:48 +00001816 if (dpl < cpl || dpl < rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001817 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001818 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001819 switch_tss_ra(env, new_cs, e1, e2, SWITCH_TSS_CALL, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001820 return;
1821 case 4: /* 286 call gate */
1822 case 12: /* 386 call gate */
1823 break;
1824 default:
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001825 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001826 break;
1827 }
1828 shift = type >> 3;
1829
Blue Swirl20054ef2012-04-28 15:33:48 +00001830 if (dpl < cpl || dpl < rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001831 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001832 }
bellardeaa728e2008-05-28 12:51:20 +00001833 /* check valid bit */
Blue Swirl20054ef2012-04-28 15:33:48 +00001834 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001835 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001836 }
bellardeaa728e2008-05-28 12:51:20 +00001837 selector = e1 >> 16;
1838 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
1839 param_count = e2 & 0x1f;
Blue Swirl20054ef2012-04-28 15:33:48 +00001840 if ((selector & 0xfffc) == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001841 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001842 }
bellardeaa728e2008-05-28 12:51:20 +00001843
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001844 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
1845 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001846 }
1847 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001848 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001849 }
bellardeaa728e2008-05-28 12:51:20 +00001850 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00001851 if (dpl > cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001852 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001853 }
1854 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001855 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001856 }
bellardeaa728e2008-05-28 12:51:20 +00001857
1858 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
1859 /* to inner privilege */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001860 get_ss_esp_from_tss(env, &ss, &sp, dpl, GETPC());
liguang90a25412013-05-28 16:21:10 +08001861 LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
1862 TARGET_FMT_lx "\n", ss, sp, param_count,
1863 env->regs[R_ESP]);
Blue Swirl20054ef2012-04-28 15:33:48 +00001864 if ((ss & 0xfffc) == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001865 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001866 }
1867 if ((ss & 3) != dpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001868 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001869 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001870 if (load_segment_ra(env, &ss_e1, &ss_e2, ss, GETPC()) != 0) {
1871 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001872 }
bellardeaa728e2008-05-28 12:51:20 +00001873 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00001874 if (ss_dpl != dpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001875 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001876 }
bellardeaa728e2008-05-28 12:51:20 +00001877 if (!(ss_e2 & DESC_S_MASK) ||
1878 (ss_e2 & DESC_CS_MASK) ||
Blue Swirl20054ef2012-04-28 15:33:48 +00001879 !(ss_e2 & DESC_W_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001880 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001881 }
1882 if (!(ss_e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001883 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001884 }
bellardeaa728e2008-05-28 12:51:20 +00001885
Blue Swirl20054ef2012-04-28 15:33:48 +00001886 /* push_size = ((param_count * 2) + 8) << shift; */
bellardeaa728e2008-05-28 12:51:20 +00001887
1888 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
1889 old_ssp = env->segs[R_SS].base;
1890
1891 sp_mask = get_sp_mask(ss_e2);
1892 ssp = get_seg_base(ss_e1, ss_e2);
1893 if (shift) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001894 PUSHL_RA(ssp, sp, sp_mask, env->segs[R_SS].selector, GETPC());
1895 PUSHL_RA(ssp, sp, sp_mask, env->regs[R_ESP], GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001896 for (i = param_count - 1; i >= 0; i--) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001897 val = cpu_ldl_kernel_ra(env, old_ssp +
1898 ((env->regs[R_ESP] + i * 4) &
1899 old_sp_mask), GETPC());
1900 PUSHL_RA(ssp, sp, sp_mask, val, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001901 }
1902 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001903 PUSHW_RA(ssp, sp, sp_mask, env->segs[R_SS].selector, GETPC());
1904 PUSHW_RA(ssp, sp, sp_mask, env->regs[R_ESP], GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001905 for (i = param_count - 1; i >= 0; i--) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001906 val = cpu_lduw_kernel_ra(env, old_ssp +
1907 ((env->regs[R_ESP] + i * 2) &
1908 old_sp_mask), GETPC());
1909 PUSHW_RA(ssp, sp, sp_mask, val, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001910 }
1911 }
1912 new_stack = 1;
1913 } else {
1914 /* to same privilege */
liguang08b3ded2013-05-28 16:21:04 +08001915 sp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +00001916 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1917 ssp = env->segs[R_SS].base;
Blue Swirl20054ef2012-04-28 15:33:48 +00001918 /* push_size = (4 << shift); */
bellardeaa728e2008-05-28 12:51:20 +00001919 new_stack = 0;
1920 }
1921
1922 if (shift) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001923 PUSHL_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
1924 PUSHL_RA(ssp, sp, sp_mask, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001925 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001926 PUSHW_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
1927 PUSHW_RA(ssp, sp, sp_mask, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001928 }
1929
1930 /* from this point, not restartable */
1931
1932 if (new_stack) {
1933 ss = (ss & ~3) | dpl;
1934 cpu_x86_load_seg_cache(env, R_SS, ss,
1935 ssp,
1936 get_seg_limit(ss_e1, ss_e2),
1937 ss_e2);
1938 }
1939
1940 selector = (selector & ~3) | dpl;
1941 cpu_x86_load_seg_cache(env, R_CS, selector,
1942 get_seg_base(e1, e2),
1943 get_seg_limit(e1, e2),
1944 e2);
bellardeaa728e2008-05-28 12:51:20 +00001945 SET_ESP(sp, sp_mask);
liguanga78d0ea2013-05-28 16:21:07 +08001946 env->eip = offset;
bellardeaa728e2008-05-28 12:51:20 +00001947 }
bellardeaa728e2008-05-28 12:51:20 +00001948}
1949
1950/* real and vm86 mode iret */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001951void helper_iret_real(CPUX86State *env, int shift)
bellardeaa728e2008-05-28 12:51:20 +00001952{
1953 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
1954 target_ulong ssp;
1955 int eflags_mask;
1956
Blue Swirl20054ef2012-04-28 15:33:48 +00001957 sp_mask = 0xffff; /* XXXX: use SS segment size? */
liguang08b3ded2013-05-28 16:21:04 +08001958 sp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +00001959 ssp = env->segs[R_SS].base;
1960 if (shift == 1) {
1961 /* 32 bits */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001962 POPL_RA(ssp, sp, sp_mask, new_eip, GETPC());
1963 POPL_RA(ssp, sp, sp_mask, new_cs, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001964 new_cs &= 0xffff;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001965 POPL_RA(ssp, sp, sp_mask, new_eflags, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001966 } else {
1967 /* 16 bits */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001968 POPW_RA(ssp, sp, sp_mask, new_eip, GETPC());
1969 POPW_RA(ssp, sp, sp_mask, new_cs, GETPC());
1970 POPW_RA(ssp, sp, sp_mask, new_eflags, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001971 }
liguang08b3ded2013-05-28 16:21:04 +08001972 env->regs[R_ESP] = (env->regs[R_ESP] & ~sp_mask) | (sp & sp_mask);
malcbdadc0b2008-10-02 20:02:27 +00001973 env->segs[R_CS].selector = new_cs;
1974 env->segs[R_CS].base = (new_cs << 4);
bellardeaa728e2008-05-28 12:51:20 +00001975 env->eip = new_eip;
Blue Swirl20054ef2012-04-28 15:33:48 +00001976 if (env->eflags & VM_MASK) {
1977 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK |
1978 NT_MASK;
1979 } else {
1980 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK |
1981 RF_MASK | NT_MASK;
1982 }
1983 if (shift == 0) {
bellardeaa728e2008-05-28 12:51:20 +00001984 eflags_mask &= 0xffff;
Blue Swirl20054ef2012-04-28 15:33:48 +00001985 }
Blue Swirl997ff0d2012-04-29 15:01:21 +00001986 cpu_load_eflags(env, new_eflags, eflags_mask);
bellarddb620f42008-06-04 17:02:19 +00001987 env->hflags2 &= ~HF2_NMI_MASK;
bellardeaa728e2008-05-28 12:51:20 +00001988}
1989
Blue Swirl2999a0b2012-04-29 19:47:06 +00001990static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl)
bellardeaa728e2008-05-28 12:51:20 +00001991{
1992 int dpl;
1993 uint32_t e2;
1994
1995 /* XXX: on x86_64, we do not want to nullify FS and GS because
1996 they may still contain a valid base. I would be interested to
1997 know how a real x86_64 CPU behaves */
1998 if ((seg_reg == R_FS || seg_reg == R_GS) &&
Blue Swirl20054ef2012-04-28 15:33:48 +00001999 (env->segs[seg_reg].selector & 0xfffc) == 0) {
bellardeaa728e2008-05-28 12:51:20 +00002000 return;
Blue Swirl20054ef2012-04-28 15:33:48 +00002001 }
bellardeaa728e2008-05-28 12:51:20 +00002002
2003 e2 = env->segs[seg_reg].flags;
2004 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2005 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
2006 /* data or non conforming code segment */
2007 if (dpl < cpl) {
2008 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
2009 }
2010 }
2011}
2012
2013/* protected mode iret */
Blue Swirl2999a0b2012-04-29 19:47:06 +00002014static inline void helper_ret_protected(CPUX86State *env, int shift,
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002015 int is_iret, int addend,
2016 uintptr_t retaddr)
bellardeaa728e2008-05-28 12:51:20 +00002017{
2018 uint32_t new_cs, new_eflags, new_ss;
2019 uint32_t new_es, new_ds, new_fs, new_gs;
2020 uint32_t e1, e2, ss_e1, ss_e2;
2021 int cpl, dpl, rpl, eflags_mask, iopl;
2022 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
2023
2024#ifdef TARGET_X86_64
Blue Swirl20054ef2012-04-28 15:33:48 +00002025 if (shift == 2) {
bellardeaa728e2008-05-28 12:51:20 +00002026 sp_mask = -1;
Blue Swirl20054ef2012-04-28 15:33:48 +00002027 } else
bellardeaa728e2008-05-28 12:51:20 +00002028#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00002029 {
bellardeaa728e2008-05-28 12:51:20 +00002030 sp_mask = get_sp_mask(env->segs[R_SS].flags);
Blue Swirl20054ef2012-04-28 15:33:48 +00002031 }
liguang08b3ded2013-05-28 16:21:04 +08002032 sp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +00002033 ssp = env->segs[R_SS].base;
2034 new_eflags = 0; /* avoid warning */
2035#ifdef TARGET_X86_64
2036 if (shift == 2) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002037 POPQ_RA(sp, new_eip, retaddr);
2038 POPQ_RA(sp, new_cs, retaddr);
bellardeaa728e2008-05-28 12:51:20 +00002039 new_cs &= 0xffff;
2040 if (is_iret) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002041 POPQ_RA(sp, new_eflags, retaddr);
bellardeaa728e2008-05-28 12:51:20 +00002042 }
2043 } else
2044#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00002045 {
2046 if (shift == 1) {
2047 /* 32 bits */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002048 POPL_RA(ssp, sp, sp_mask, new_eip, retaddr);
2049 POPL_RA(ssp, sp, sp_mask, new_cs, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002050 new_cs &= 0xffff;
2051 if (is_iret) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002052 POPL_RA(ssp, sp, sp_mask, new_eflags, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002053 if (new_eflags & VM_MASK) {
2054 goto return_to_vm86;
2055 }
2056 }
2057 } else {
2058 /* 16 bits */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002059 POPW_RA(ssp, sp, sp_mask, new_eip, retaddr);
2060 POPW_RA(ssp, sp, sp_mask, new_cs, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002061 if (is_iret) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002062 POPW_RA(ssp, sp, sp_mask, new_eflags, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002063 }
bellardeaa728e2008-05-28 12:51:20 +00002064 }
bellardeaa728e2008-05-28 12:51:20 +00002065 }
aliguorid12d51d2009-01-15 21:48:06 +00002066 LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2067 new_cs, new_eip, shift, addend);
Andreas Färber8995b7a2013-07-03 01:07:10 +02002068 LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
Blue Swirl20054ef2012-04-28 15:33:48 +00002069 if ((new_cs & 0xfffc) == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002070 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002071 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002072 if (load_segment_ra(env, &e1, &e2, new_cs, retaddr) != 0) {
2073 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002074 }
bellardeaa728e2008-05-28 12:51:20 +00002075 if (!(e2 & DESC_S_MASK) ||
Blue Swirl20054ef2012-04-28 15:33:48 +00002076 !(e2 & DESC_CS_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002077 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002078 }
bellardeaa728e2008-05-28 12:51:20 +00002079 cpl = env->hflags & HF_CPL_MASK;
2080 rpl = new_cs & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00002081 if (rpl < cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002082 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002083 }
bellardeaa728e2008-05-28 12:51:20 +00002084 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2085 if (e2 & DESC_C_MASK) {
Blue Swirl20054ef2012-04-28 15:33:48 +00002086 if (dpl > rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002087 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002088 }
bellardeaa728e2008-05-28 12:51:20 +00002089 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00002090 if (dpl != rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002091 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002092 }
bellardeaa728e2008-05-28 12:51:20 +00002093 }
Blue Swirl20054ef2012-04-28 15:33:48 +00002094 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002095 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002096 }
bellardeaa728e2008-05-28 12:51:20 +00002097
2098 sp += addend;
2099 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2100 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
ths1235fc02008-06-03 19:51:57 +00002101 /* return to same privilege level */
bellardeaa728e2008-05-28 12:51:20 +00002102 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2103 get_seg_base(e1, e2),
2104 get_seg_limit(e1, e2),
2105 e2);
2106 } else {
2107 /* return to different privilege level */
2108#ifdef TARGET_X86_64
2109 if (shift == 2) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002110 POPQ_RA(sp, new_esp, retaddr);
2111 POPQ_RA(sp, new_ss, retaddr);
bellardeaa728e2008-05-28 12:51:20 +00002112 new_ss &= 0xffff;
2113 } else
2114#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00002115 {
2116 if (shift == 1) {
2117 /* 32 bits */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002118 POPL_RA(ssp, sp, sp_mask, new_esp, retaddr);
2119 POPL_RA(ssp, sp, sp_mask, new_ss, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002120 new_ss &= 0xffff;
2121 } else {
2122 /* 16 bits */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002123 POPW_RA(ssp, sp, sp_mask, new_esp, retaddr);
2124 POPW_RA(ssp, sp, sp_mask, new_ss, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002125 }
bellardeaa728e2008-05-28 12:51:20 +00002126 }
aliguorid12d51d2009-01-15 21:48:06 +00002127 LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n",
Blue Swirl20054ef2012-04-28 15:33:48 +00002128 new_ss, new_esp);
bellardeaa728e2008-05-28 12:51:20 +00002129 if ((new_ss & 0xfffc) == 0) {
2130#ifdef TARGET_X86_64
Blue Swirl20054ef2012-04-28 15:33:48 +00002131 /* NULL ss is allowed in long mode if cpl != 3 */
2132 /* XXX: test CS64? */
bellardeaa728e2008-05-28 12:51:20 +00002133 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2134 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2135 0, 0xffffffff,
2136 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2137 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2138 DESC_W_MASK | DESC_A_MASK);
Blue Swirl20054ef2012-04-28 15:33:48 +00002139 ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */
bellardeaa728e2008-05-28 12:51:20 +00002140 } else
2141#endif
2142 {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002143 raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr);
bellardeaa728e2008-05-28 12:51:20 +00002144 }
2145 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00002146 if ((new_ss & 3) != rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002147 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002148 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002149 if (load_segment_ra(env, &ss_e1, &ss_e2, new_ss, retaddr) != 0) {
2150 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002151 }
bellardeaa728e2008-05-28 12:51:20 +00002152 if (!(ss_e2 & DESC_S_MASK) ||
2153 (ss_e2 & DESC_CS_MASK) ||
Blue Swirl20054ef2012-04-28 15:33:48 +00002154 !(ss_e2 & DESC_W_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002155 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002156 }
bellardeaa728e2008-05-28 12:51:20 +00002157 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00002158 if (dpl != rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002159 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002160 }
2161 if (!(ss_e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002162 raise_exception_err_ra(env, EXCP0B_NOSEG, new_ss & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002163 }
bellardeaa728e2008-05-28 12:51:20 +00002164 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2165 get_seg_base(ss_e1, ss_e2),
2166 get_seg_limit(ss_e1, ss_e2),
2167 ss_e2);
2168 }
2169
2170 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2171 get_seg_base(e1, e2),
2172 get_seg_limit(e1, e2),
2173 e2);
bellardeaa728e2008-05-28 12:51:20 +00002174 sp = new_esp;
2175#ifdef TARGET_X86_64
Blue Swirl20054ef2012-04-28 15:33:48 +00002176 if (env->hflags & HF_CS64_MASK) {
bellardeaa728e2008-05-28 12:51:20 +00002177 sp_mask = -1;
Blue Swirl20054ef2012-04-28 15:33:48 +00002178 } else
bellardeaa728e2008-05-28 12:51:20 +00002179#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00002180 {
bellardeaa728e2008-05-28 12:51:20 +00002181 sp_mask = get_sp_mask(ss_e2);
Blue Swirl20054ef2012-04-28 15:33:48 +00002182 }
bellardeaa728e2008-05-28 12:51:20 +00002183
2184 /* validate data segments */
Blue Swirl2999a0b2012-04-29 19:47:06 +00002185 validate_seg(env, R_ES, rpl);
2186 validate_seg(env, R_DS, rpl);
2187 validate_seg(env, R_FS, rpl);
2188 validate_seg(env, R_GS, rpl);
bellardeaa728e2008-05-28 12:51:20 +00002189
2190 sp += addend;
2191 }
2192 SET_ESP(sp, sp_mask);
2193 env->eip = new_eip;
2194 if (is_iret) {
2195 /* NOTE: 'cpl' is the _old_ CPL */
2196 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
Blue Swirl20054ef2012-04-28 15:33:48 +00002197 if (cpl == 0) {
bellardeaa728e2008-05-28 12:51:20 +00002198 eflags_mask |= IOPL_MASK;
Blue Swirl20054ef2012-04-28 15:33:48 +00002199 }
bellardeaa728e2008-05-28 12:51:20 +00002200 iopl = (env->eflags >> IOPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00002201 if (cpl <= iopl) {
bellardeaa728e2008-05-28 12:51:20 +00002202 eflags_mask |= IF_MASK;
Blue Swirl20054ef2012-04-28 15:33:48 +00002203 }
2204 if (shift == 0) {
bellardeaa728e2008-05-28 12:51:20 +00002205 eflags_mask &= 0xffff;
Blue Swirl20054ef2012-04-28 15:33:48 +00002206 }
Blue Swirl997ff0d2012-04-29 15:01:21 +00002207 cpu_load_eflags(env, new_eflags, eflags_mask);
bellardeaa728e2008-05-28 12:51:20 +00002208 }
2209 return;
2210
2211 return_to_vm86:
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002212 POPL_RA(ssp, sp, sp_mask, new_esp, retaddr);
2213 POPL_RA(ssp, sp, sp_mask, new_ss, retaddr);
2214 POPL_RA(ssp, sp, sp_mask, new_es, retaddr);
2215 POPL_RA(ssp, sp, sp_mask, new_ds, retaddr);
2216 POPL_RA(ssp, sp, sp_mask, new_fs, retaddr);
2217 POPL_RA(ssp, sp, sp_mask, new_gs, retaddr);
bellardeaa728e2008-05-28 12:51:20 +00002218
2219 /* modify processor state */
Blue Swirl997ff0d2012-04-29 15:01:21 +00002220 cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK |
2221 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK |
2222 VIP_MASK);
Blue Swirl2999a0b2012-04-29 19:47:06 +00002223 load_seg_vm(env, R_CS, new_cs & 0xffff);
Blue Swirl2999a0b2012-04-29 19:47:06 +00002224 load_seg_vm(env, R_SS, new_ss & 0xffff);
2225 load_seg_vm(env, R_ES, new_es & 0xffff);
2226 load_seg_vm(env, R_DS, new_ds & 0xffff);
2227 load_seg_vm(env, R_FS, new_fs & 0xffff);
2228 load_seg_vm(env, R_GS, new_gs & 0xffff);
bellardeaa728e2008-05-28 12:51:20 +00002229
2230 env->eip = new_eip & 0xffff;
liguang08b3ded2013-05-28 16:21:04 +08002231 env->regs[R_ESP] = new_esp;
bellardeaa728e2008-05-28 12:51:20 +00002232}
2233
Blue Swirl2999a0b2012-04-29 19:47:06 +00002234void helper_iret_protected(CPUX86State *env, int shift, int next_eip)
bellardeaa728e2008-05-28 12:51:20 +00002235{
2236 int tss_selector, type;
2237 uint32_t e1, e2;
2238
2239 /* specific case for TSS */
2240 if (env->eflags & NT_MASK) {
2241#ifdef TARGET_X86_64
Blue Swirl20054ef2012-04-28 15:33:48 +00002242 if (env->hflags & HF_LMA_MASK) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002243 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00002244 }
bellardeaa728e2008-05-28 12:51:20 +00002245#endif
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002246 tss_selector = cpu_lduw_kernel_ra(env, env->tr.base + 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00002247 if (tss_selector & 4) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002248 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00002249 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002250 if (load_segment_ra(env, &e1, &e2, tss_selector, GETPC()) != 0) {
2251 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00002252 }
bellardeaa728e2008-05-28 12:51:20 +00002253 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2254 /* NOTE: we check both segment and busy TSS */
Blue Swirl20054ef2012-04-28 15:33:48 +00002255 if (type != 3) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002256 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00002257 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002258 switch_tss_ra(env, tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00002259 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002260 helper_ret_protected(env, shift, 1, 0, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00002261 }
bellarddb620f42008-06-04 17:02:19 +00002262 env->hflags2 &= ~HF2_NMI_MASK;
bellardeaa728e2008-05-28 12:51:20 +00002263}
2264
Blue Swirl2999a0b2012-04-29 19:47:06 +00002265void helper_lret_protected(CPUX86State *env, int shift, int addend)
bellardeaa728e2008-05-28 12:51:20 +00002266{
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002267 helper_ret_protected(env, shift, 0, addend, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00002268}
2269
Blue Swirl2999a0b2012-04-29 19:47:06 +00002270void helper_sysenter(CPUX86State *env)
bellardeaa728e2008-05-28 12:51:20 +00002271{
2272 if (env->sysenter_cs == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002273 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00002274 }
2275 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
balrog2436b612008-09-25 18:16:18 +00002276
2277#ifdef TARGET_X86_64
2278 if (env->hflags & HF_LMA_MASK) {
2279 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2280 0, 0xffffffff,
2281 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2282 DESC_S_MASK |
Blue Swirl20054ef2012-04-28 15:33:48 +00002283 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2284 DESC_L_MASK);
balrog2436b612008-09-25 18:16:18 +00002285 } else
2286#endif
2287 {
2288 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2289 0, 0xffffffff,
2290 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2291 DESC_S_MASK |
2292 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2293 }
bellardeaa728e2008-05-28 12:51:20 +00002294 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2295 0, 0xffffffff,
2296 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2297 DESC_S_MASK |
2298 DESC_W_MASK | DESC_A_MASK);
liguang08b3ded2013-05-28 16:21:04 +08002299 env->regs[R_ESP] = env->sysenter_esp;
liguanga78d0ea2013-05-28 16:21:07 +08002300 env->eip = env->sysenter_eip;
bellardeaa728e2008-05-28 12:51:20 +00002301}
2302
Blue Swirl2999a0b2012-04-29 19:47:06 +00002303void helper_sysexit(CPUX86State *env, int dflag)
bellardeaa728e2008-05-28 12:51:20 +00002304{
2305 int cpl;
2306
2307 cpl = env->hflags & HF_CPL_MASK;
2308 if (env->sysenter_cs == 0 || cpl != 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002309 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00002310 }
balrog2436b612008-09-25 18:16:18 +00002311#ifdef TARGET_X86_64
2312 if (dflag == 2) {
Blue Swirl20054ef2012-04-28 15:33:48 +00002313 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) |
2314 3, 0, 0xffffffff,
balrog2436b612008-09-25 18:16:18 +00002315 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2316 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
Blue Swirl20054ef2012-04-28 15:33:48 +00002317 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2318 DESC_L_MASK);
2319 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) |
2320 3, 0, 0xffffffff,
balrog2436b612008-09-25 18:16:18 +00002321 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2322 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2323 DESC_W_MASK | DESC_A_MASK);
2324 } else
2325#endif
2326 {
Blue Swirl20054ef2012-04-28 15:33:48 +00002327 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) |
2328 3, 0, 0xffffffff,
balrog2436b612008-09-25 18:16:18 +00002329 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2330 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2331 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
Blue Swirl20054ef2012-04-28 15:33:48 +00002332 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) |
2333 3, 0, 0xffffffff,
balrog2436b612008-09-25 18:16:18 +00002334 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2335 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2336 DESC_W_MASK | DESC_A_MASK);
2337 }
liguang08b3ded2013-05-28 16:21:04 +08002338 env->regs[R_ESP] = env->regs[R_ECX];
liguanga78d0ea2013-05-28 16:21:07 +08002339 env->eip = env->regs[R_EDX];
bellardeaa728e2008-05-28 12:51:20 +00002340}
2341
Blue Swirl2999a0b2012-04-29 19:47:06 +00002342target_ulong helper_lsl(CPUX86State *env, target_ulong selector1)
bellardeaa728e2008-05-28 12:51:20 +00002343{
2344 unsigned int limit;
2345 uint32_t e1, e2, eflags, selector;
2346 int rpl, dpl, cpl, type;
2347
2348 selector = selector1 & 0xffff;
Blue Swirlf0967a12012-04-29 12:45:34 +00002349 eflags = cpu_cc_compute_all(env, CC_OP);
Blue Swirl20054ef2012-04-28 15:33:48 +00002350 if ((selector & 0xfffc) == 0) {
aliguoridc1ded52009-03-20 16:13:41 +00002351 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002352 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002353 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
bellardeaa728e2008-05-28 12:51:20 +00002354 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002355 }
bellardeaa728e2008-05-28 12:51:20 +00002356 rpl = selector & 3;
2357 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2358 cpl = env->hflags & HF_CPL_MASK;
2359 if (e2 & DESC_S_MASK) {
2360 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2361 /* conforming */
2362 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00002363 if (dpl < cpl || dpl < rpl) {
bellardeaa728e2008-05-28 12:51:20 +00002364 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002365 }
bellardeaa728e2008-05-28 12:51:20 +00002366 }
2367 } else {
2368 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +00002369 switch (type) {
bellardeaa728e2008-05-28 12:51:20 +00002370 case 1:
2371 case 2:
2372 case 3:
2373 case 9:
2374 case 11:
2375 break;
2376 default:
2377 goto fail;
2378 }
2379 if (dpl < cpl || dpl < rpl) {
2380 fail:
2381 CC_SRC = eflags & ~CC_Z;
2382 return 0;
2383 }
2384 }
2385 limit = get_seg_limit(e1, e2);
2386 CC_SRC = eflags | CC_Z;
2387 return limit;
2388}
2389
Blue Swirl2999a0b2012-04-29 19:47:06 +00002390target_ulong helper_lar(CPUX86State *env, target_ulong selector1)
bellardeaa728e2008-05-28 12:51:20 +00002391{
2392 uint32_t e1, e2, eflags, selector;
2393 int rpl, dpl, cpl, type;
2394
2395 selector = selector1 & 0xffff;
Blue Swirlf0967a12012-04-29 12:45:34 +00002396 eflags = cpu_cc_compute_all(env, CC_OP);
Blue Swirl20054ef2012-04-28 15:33:48 +00002397 if ((selector & 0xfffc) == 0) {
bellardeaa728e2008-05-28 12:51:20 +00002398 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002399 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002400 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
bellardeaa728e2008-05-28 12:51:20 +00002401 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002402 }
bellardeaa728e2008-05-28 12:51:20 +00002403 rpl = selector & 3;
2404 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2405 cpl = env->hflags & HF_CPL_MASK;
2406 if (e2 & DESC_S_MASK) {
2407 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2408 /* conforming */
2409 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00002410 if (dpl < cpl || dpl < rpl) {
bellardeaa728e2008-05-28 12:51:20 +00002411 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002412 }
bellardeaa728e2008-05-28 12:51:20 +00002413 }
2414 } else {
2415 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +00002416 switch (type) {
bellardeaa728e2008-05-28 12:51:20 +00002417 case 1:
2418 case 2:
2419 case 3:
2420 case 4:
2421 case 5:
2422 case 9:
2423 case 11:
2424 case 12:
2425 break;
2426 default:
2427 goto fail;
2428 }
2429 if (dpl < cpl || dpl < rpl) {
2430 fail:
2431 CC_SRC = eflags & ~CC_Z;
2432 return 0;
2433 }
2434 }
2435 CC_SRC = eflags | CC_Z;
2436 return e2 & 0x00f0ff00;
2437}
2438
Blue Swirl2999a0b2012-04-29 19:47:06 +00002439void helper_verr(CPUX86State *env, target_ulong selector1)
bellardeaa728e2008-05-28 12:51:20 +00002440{
2441 uint32_t e1, e2, eflags, selector;
2442 int rpl, dpl, cpl;
2443
2444 selector = selector1 & 0xffff;
Blue Swirlf0967a12012-04-29 12:45:34 +00002445 eflags = cpu_cc_compute_all(env, CC_OP);
Blue Swirl20054ef2012-04-28 15:33:48 +00002446 if ((selector & 0xfffc) == 0) {
bellardeaa728e2008-05-28 12:51:20 +00002447 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002448 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002449 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
bellardeaa728e2008-05-28 12:51:20 +00002450 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002451 }
2452 if (!(e2 & DESC_S_MASK)) {
bellardeaa728e2008-05-28 12:51:20 +00002453 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002454 }
bellardeaa728e2008-05-28 12:51:20 +00002455 rpl = selector & 3;
2456 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2457 cpl = env->hflags & HF_CPL_MASK;
2458 if (e2 & DESC_CS_MASK) {
Blue Swirl20054ef2012-04-28 15:33:48 +00002459 if (!(e2 & DESC_R_MASK)) {
bellardeaa728e2008-05-28 12:51:20 +00002460 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002461 }
bellardeaa728e2008-05-28 12:51:20 +00002462 if (!(e2 & DESC_C_MASK)) {
Blue Swirl20054ef2012-04-28 15:33:48 +00002463 if (dpl < cpl || dpl < rpl) {
bellardeaa728e2008-05-28 12:51:20 +00002464 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002465 }
bellardeaa728e2008-05-28 12:51:20 +00002466 }
2467 } else {
2468 if (dpl < cpl || dpl < rpl) {
2469 fail:
2470 CC_SRC = eflags & ~CC_Z;
2471 return;
2472 }
2473 }
2474 CC_SRC = eflags | CC_Z;
2475}
2476
Blue Swirl2999a0b2012-04-29 19:47:06 +00002477void helper_verw(CPUX86State *env, target_ulong selector1)
bellardeaa728e2008-05-28 12:51:20 +00002478{
2479 uint32_t e1, e2, eflags, selector;
2480 int rpl, dpl, cpl;
2481
2482 selector = selector1 & 0xffff;
Blue Swirlf0967a12012-04-29 12:45:34 +00002483 eflags = cpu_cc_compute_all(env, CC_OP);
Blue Swirl20054ef2012-04-28 15:33:48 +00002484 if ((selector & 0xfffc) == 0) {
bellardeaa728e2008-05-28 12:51:20 +00002485 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002486 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002487 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
bellardeaa728e2008-05-28 12:51:20 +00002488 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002489 }
2490 if (!(e2 & DESC_S_MASK)) {
bellardeaa728e2008-05-28 12:51:20 +00002491 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002492 }
bellardeaa728e2008-05-28 12:51:20 +00002493 rpl = selector & 3;
2494 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2495 cpl = env->hflags & HF_CPL_MASK;
2496 if (e2 & DESC_CS_MASK) {
2497 goto fail;
2498 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00002499 if (dpl < cpl || dpl < rpl) {
bellardeaa728e2008-05-28 12:51:20 +00002500 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002501 }
bellardeaa728e2008-05-28 12:51:20 +00002502 if (!(e2 & DESC_W_MASK)) {
2503 fail:
2504 CC_SRC = eflags & ~CC_Z;
2505 return;
2506 }
2507 }
2508 CC_SRC = eflags | CC_Z;
2509}
2510
Blue Swirl3e457172011-07-13 12:44:15 +00002511#if defined(CONFIG_USER_ONLY)
Blue Swirl2999a0b2012-04-29 19:47:06 +00002512void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector)
Blue Swirl3e457172011-07-13 12:44:15 +00002513{
Blue Swirl3e457172011-07-13 12:44:15 +00002514 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
Paolo Bonzinib98dbc92014-05-15 16:07:04 +02002515 int dpl = (env->eflags & VM_MASK) ? 3 : 0;
Blue Swirl3e457172011-07-13 12:44:15 +00002516 selector &= 0xffff;
2517 cpu_x86_load_seg_cache(env, seg_reg, selector,
Paolo Bonzinib98dbc92014-05-15 16:07:04 +02002518 (selector << 4), 0xffff,
2519 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2520 DESC_A_MASK | (dpl << DESC_DPL_SHIFT));
Blue Swirl3e457172011-07-13 12:44:15 +00002521 } else {
Blue Swirl2999a0b2012-04-29 19:47:06 +00002522 helper_load_seg(env, seg_reg, selector);
Blue Swirl3e457172011-07-13 12:44:15 +00002523 }
Blue Swirl3e457172011-07-13 12:44:15 +00002524}
Blue Swirl3e457172011-07-13 12:44:15 +00002525#endif
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002526
2527/* check if Port I/O is allowed in TSS */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002528static inline void check_io(CPUX86State *env, int addr, int size,
2529 uintptr_t retaddr)
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002530{
2531 int io_offset, val, mask;
2532
2533 /* TSS must be a valid 32 bit one */
2534 if (!(env->tr.flags & DESC_P_MASK) ||
2535 ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
2536 env->tr.limit < 103) {
2537 goto fail;
2538 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002539 io_offset = cpu_lduw_kernel_ra(env, env->tr.base + 0x66, retaddr);
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002540 io_offset += (addr >> 3);
2541 /* Note: the check needs two bytes */
2542 if ((io_offset + 1) > env->tr.limit) {
2543 goto fail;
2544 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002545 val = cpu_lduw_kernel_ra(env, env->tr.base + io_offset, retaddr);
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002546 val >>= (addr & 7);
2547 mask = (1 << size) - 1;
2548 /* all bits must be zero to allow the I/O */
2549 if ((val & mask) != 0) {
2550 fail:
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002551 raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr);
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002552 }
2553}
2554
2555void helper_check_iob(CPUX86State *env, uint32_t t0)
2556{
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002557 check_io(env, t0, 1, GETPC());
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002558}
2559
2560void helper_check_iow(CPUX86State *env, uint32_t t0)
2561{
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002562 check_io(env, t0, 2, GETPC());
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002563}
2564
2565void helper_check_iol(CPUX86State *env, uint32_t t0)
2566{
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002567 check_io(env, t0, 4, GETPC());
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002568}