blob: 23c9b9120051a5f9414e8edca7ccc96655a60b11 [file] [log] [blame]
Blue Swirl0cac1b62012-04-09 16:50:52 +00001/*
2 * Common CPU TLB handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
Peter Maydell7b31bbc2016-01-26 18:16:56 +000020#include "qemu/osdep.h"
Blue Swirl0cac1b62012-04-09 16:50:52 +000021#include "cpu.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010022#include "exec/exec-all.h"
23#include "exec/memory.h"
24#include "exec/address-spaces.h"
Paolo Bonzinif08b6172014-03-28 19:42:10 +010025#include "exec/cpu_ldst.h"
Blue Swirl0cac1b62012-04-09 16:50:52 +000026
Paolo Bonzini022c62c2012-12-17 18:19:49 +010027#include "exec/cputlb.h"
Blue Swirl0cac1b62012-04-09 16:50:52 +000028
Paolo Bonzini022c62c2012-12-17 18:19:49 +010029#include "exec/memory-internal.h"
Juan Quintela220c3eb2013-10-14 17:13:59 +020030#include "exec/ram_addr.h"
Paolo Bonzini63c91552016-03-15 13:18:37 +010031#include "exec/exec-all.h"
Paolo Bonzini0f590e742014-03-28 17:55:24 +010032#include "tcg/tcg.h"
Blue Swirl0cac1b62012-04-09 16:50:52 +000033
Alex Bennée8526e1f2016-03-15 14:30:24 +000034/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
35/* #define DEBUG_TLB */
36/* #define DEBUG_TLB_LOG */
37
38#ifdef DEBUG_TLB
39# define DEBUG_TLB_GATE 1
40# ifdef DEBUG_TLB_LOG
41# define DEBUG_TLB_LOG_GATE 1
42# else
43# define DEBUG_TLB_LOG_GATE 0
44# endif
45#else
46# define DEBUG_TLB_GATE 0
47# define DEBUG_TLB_LOG_GATE 0
48#endif
49
50#define tlb_debug(fmt, ...) do { \
51 if (DEBUG_TLB_LOG_GATE) { \
52 qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \
53 ## __VA_ARGS__); \
54 } else if (DEBUG_TLB_GATE) { \
55 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
56 } \
57} while (0)
Blue Swirl0cac1b62012-04-09 16:50:52 +000058
59/* statistics */
60int tlb_flush_count;
61
Blue Swirl0cac1b62012-04-09 16:50:52 +000062/* NOTE:
63 * If flush_global is true (the usual case), flush all tlb entries.
64 * If flush_global is false, flush (at least) all tlb entries not
65 * marked global.
66 *
67 * Since QEMU doesn't currently implement a global/not-global flag
68 * for tlb entries, at the moment tlb_flush() will also flush all
69 * tlb entries in the flush_global == false case. This is OK because
70 * CPU architectures generally permit an implementation to drop
71 * entries from the TLB at any time, so flushing more entries than
72 * required is only an efficiency issue, not a correctness issue.
73 */
Andreas Färber00c8cb02013-09-04 02:19:44 +020074void tlb_flush(CPUState *cpu, int flush_global)
Blue Swirl0cac1b62012-04-09 16:50:52 +000075{
Andreas Färber00c8cb02013-09-04 02:19:44 +020076 CPUArchState *env = cpu->env_ptr;
Blue Swirl0cac1b62012-04-09 16:50:52 +000077
Alex Bennée8526e1f2016-03-15 14:30:24 +000078 tlb_debug("(%d)\n", flush_global);
79
Richard Henderson4fadb3b2013-12-07 10:44:51 +130080 memset(env->tlb_table, -1, sizeof(env->tlb_table));
Xin Tong88e89a52014-08-04 20:35:23 -050081 memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
Andreas Färber8cd70432013-08-26 06:03:38 +020082 memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
Blue Swirl0cac1b62012-04-09 16:50:52 +000083
Xin Tong88e89a52014-08-04 20:35:23 -050084 env->vtlb_index = 0;
Blue Swirl0cac1b62012-04-09 16:50:52 +000085 env->tlb_flush_addr = -1;
86 env->tlb_flush_mask = 0;
87 tlb_flush_count++;
88}
89
Peter Maydelld7a74a92015-08-25 15:45:09 +010090static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp)
91{
92 CPUArchState *env = cpu->env_ptr;
93
Alex Bennée8526e1f2016-03-15 14:30:24 +000094 tlb_debug("start\n");
Peter Maydelld7a74a92015-08-25 15:45:09 +010095
96 for (;;) {
97 int mmu_idx = va_arg(argp, int);
98
99 if (mmu_idx < 0) {
100 break;
101 }
102
Alex Bennée8526e1f2016-03-15 14:30:24 +0000103 tlb_debug("%d\n", mmu_idx);
Peter Maydelld7a74a92015-08-25 15:45:09 +0100104
105 memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0]));
106 memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0]));
107 }
108
Peter Maydelld7a74a92015-08-25 15:45:09 +0100109 memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
110}
111
112void tlb_flush_by_mmuidx(CPUState *cpu, ...)
113{
114 va_list argp;
115 va_start(argp, cpu);
116 v_tlb_flush_by_mmuidx(cpu, argp);
117 va_end(argp);
118}
119
Blue Swirl0cac1b62012-04-09 16:50:52 +0000120static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
121{
122 if (addr == (tlb_entry->addr_read &
123 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
124 addr == (tlb_entry->addr_write &
125 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
126 addr == (tlb_entry->addr_code &
127 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
Richard Henderson4fadb3b2013-12-07 10:44:51 +1300128 memset(tlb_entry, -1, sizeof(*tlb_entry));
Blue Swirl0cac1b62012-04-09 16:50:52 +0000129 }
130}
131
Andreas Färber31b030d2013-09-04 01:29:02 +0200132void tlb_flush_page(CPUState *cpu, target_ulong addr)
Blue Swirl0cac1b62012-04-09 16:50:52 +0000133{
Andreas Färber31b030d2013-09-04 01:29:02 +0200134 CPUArchState *env = cpu->env_ptr;
Blue Swirl0cac1b62012-04-09 16:50:52 +0000135 int i;
136 int mmu_idx;
137
Alex Bennée8526e1f2016-03-15 14:30:24 +0000138 tlb_debug("page :" TARGET_FMT_lx "\n", addr);
139
Blue Swirl0cac1b62012-04-09 16:50:52 +0000140 /* Check if we need to flush due to large pages. */
141 if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
Alex Bennée8526e1f2016-03-15 14:30:24 +0000142 tlb_debug("forcing full flush ("
143 TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
144 env->tlb_flush_addr, env->tlb_flush_mask);
145
Andreas Färber00c8cb02013-09-04 02:19:44 +0200146 tlb_flush(cpu, 1);
Blue Swirl0cac1b62012-04-09 16:50:52 +0000147 return;
148 }
Blue Swirl0cac1b62012-04-09 16:50:52 +0000149
150 addr &= TARGET_PAGE_MASK;
151 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
152 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
153 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
154 }
155
Xin Tong88e89a52014-08-04 20:35:23 -0500156 /* check whether there are entries that need to be flushed in the vtlb */
157 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
158 int k;
159 for (k = 0; k < CPU_VTLB_SIZE; k++) {
160 tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], addr);
161 }
162 }
163
Andreas Färber611d4f92013-09-01 17:52:07 +0200164 tb_flush_jmp_cache(cpu, addr);
Blue Swirl0cac1b62012-04-09 16:50:52 +0000165}
166
Peter Maydelld7a74a92015-08-25 15:45:09 +0100167void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
168{
169 CPUArchState *env = cpu->env_ptr;
170 int i, k;
171 va_list argp;
172
173 va_start(argp, addr);
174
Alex Bennée8526e1f2016-03-15 14:30:24 +0000175 tlb_debug("addr "TARGET_FMT_lx"\n", addr);
176
Peter Maydelld7a74a92015-08-25 15:45:09 +0100177 /* Check if we need to flush due to large pages. */
178 if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
Alex Bennée8526e1f2016-03-15 14:30:24 +0000179 tlb_debug("forced full flush ("
180 TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
181 env->tlb_flush_addr, env->tlb_flush_mask);
182
Peter Maydelld7a74a92015-08-25 15:45:09 +0100183 v_tlb_flush_by_mmuidx(cpu, argp);
184 va_end(argp);
185 return;
186 }
Peter Maydelld7a74a92015-08-25 15:45:09 +0100187
188 addr &= TARGET_PAGE_MASK;
189 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
190
191 for (;;) {
192 int mmu_idx = va_arg(argp, int);
193
194 if (mmu_idx < 0) {
195 break;
196 }
197
Alex Bennée8526e1f2016-03-15 14:30:24 +0000198 tlb_debug("idx %d\n", mmu_idx);
Peter Maydelld7a74a92015-08-25 15:45:09 +0100199
200 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
201
202 /* check whether there are vltb entries that need to be flushed */
203 for (k = 0; k < CPU_VTLB_SIZE; k++) {
204 tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], addr);
205 }
206 }
207 va_end(argp);
208
Peter Maydelld7a74a92015-08-25 15:45:09 +0100209 tb_flush_jmp_cache(cpu, addr);
210}
211
Blue Swirl0cac1b62012-04-09 16:50:52 +0000212/* update the TLBs so that writes to code in the virtual page 'addr'
213 can be detected */
214void tlb_protect_code(ram_addr_t ram_addr)
215{
Stefan Hajnoczi03eebc92014-12-02 11:23:18 +0000216 cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE,
217 DIRTY_MEMORY_CODE);
Blue Swirl0cac1b62012-04-09 16:50:52 +0000218}
219
220/* update the TLB so that writes in physical page 'phys_addr' are no longer
221 tested for self modifying code */
Paolo Bonzini9564f522015-04-22 14:24:54 +0200222void tlb_unprotect_code(ram_addr_t ram_addr)
Blue Swirl0cac1b62012-04-09 16:50:52 +0000223{
Juan Quintela52159192013-10-08 12:44:04 +0200224 cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE);
Blue Swirl0cac1b62012-04-09 16:50:52 +0000225}
226
227static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe)
228{
229 return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0;
230}
231
232void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
233 uintptr_t length)
234{
235 uintptr_t addr;
236
237 if (tlb_is_dirty_ram(tlb_entry)) {
238 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
239 if ((addr - start) < length) {
240 tlb_entry->addr_write |= TLB_NOTDIRTY;
241 }
242 }
243}
244
Paolo Bonzini7443b432013-06-03 12:44:02 +0200245static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
246{
247 ram_addr_t ram_addr;
248
Paolo Bonzini07bdaa42016-03-25 12:55:08 +0100249 ram_addr = qemu_ram_addr_from_host(ptr);
250 if (ram_addr == RAM_ADDR_INVALID) {
Paolo Bonzini7443b432013-06-03 12:44:02 +0200251 fprintf(stderr, "Bad ram pointer %p\n", ptr);
252 abort();
253 }
254 return ram_addr;
255}
256
Peter Crosthwaite9a135652015-09-10 22:39:41 -0700257void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
Blue Swirl0cac1b62012-04-09 16:50:52 +0000258{
259 CPUArchState *env;
260
Peter Crosthwaite9a135652015-09-10 22:39:41 -0700261 int mmu_idx;
Blue Swirl0cac1b62012-04-09 16:50:52 +0000262
Peter Crosthwaite9a135652015-09-10 22:39:41 -0700263 env = cpu->env_ptr;
264 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
265 unsigned int i;
Blue Swirl0cac1b62012-04-09 16:50:52 +0000266
Peter Crosthwaite9a135652015-09-10 22:39:41 -0700267 for (i = 0; i < CPU_TLB_SIZE; i++) {
268 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
269 start1, length);
270 }
Xin Tong88e89a52014-08-04 20:35:23 -0500271
Peter Crosthwaite9a135652015-09-10 22:39:41 -0700272 for (i = 0; i < CPU_VTLB_SIZE; i++) {
273 tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i],
274 start1, length);
Blue Swirl0cac1b62012-04-09 16:50:52 +0000275 }
276 }
277}
278
279static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
280{
281 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
282 tlb_entry->addr_write = vaddr;
283 }
284}
285
286/* update the TLB corresponding to virtual page vaddr
287 so that it is no longer dirty */
Peter Crosthwaitebcae01e2015-09-10 22:39:42 -0700288void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
Blue Swirl0cac1b62012-04-09 16:50:52 +0000289{
Peter Crosthwaitebcae01e2015-09-10 22:39:42 -0700290 CPUArchState *env = cpu->env_ptr;
Blue Swirl0cac1b62012-04-09 16:50:52 +0000291 int i;
292 int mmu_idx;
293
294 vaddr &= TARGET_PAGE_MASK;
295 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
296 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
297 tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
298 }
Xin Tong88e89a52014-08-04 20:35:23 -0500299
300 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
301 int k;
302 for (k = 0; k < CPU_VTLB_SIZE; k++) {
303 tlb_set_dirty1(&env->tlb_v_table[mmu_idx][k], vaddr);
304 }
305 }
Blue Swirl0cac1b62012-04-09 16:50:52 +0000306}
307
308/* Our TLB does not support large pages, so remember the area covered by
309 large pages and trigger a full TLB flush if these are invalidated. */
310static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
311 target_ulong size)
312{
313 target_ulong mask = ~(size - 1);
314
315 if (env->tlb_flush_addr == (target_ulong)-1) {
316 env->tlb_flush_addr = vaddr & mask;
317 env->tlb_flush_mask = mask;
318 return;
319 }
320 /* Extend the existing region to include the new page.
321 This is a compromise between unnecessary flushes and the cost
322 of maintaining a full variable size TLB. */
323 mask &= env->tlb_flush_mask;
324 while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
325 mask <<= 1;
326 }
327 env->tlb_flush_addr &= mask;
328 env->tlb_flush_mask = mask;
329}
330
331/* Add a new TLB entry. At most one entry for a given virtual address
Paolo Bonzini79e2b9a2015-01-21 12:09:14 +0100332 * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
333 * supplied size is only used by tlb_flush_page.
334 *
335 * Called from TCG-generated code, which is under an RCU read-side
336 * critical section.
337 */
Peter Maydellfadc1cb2015-04-26 16:49:24 +0100338void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
339 hwaddr paddr, MemTxAttrs attrs, int prot,
340 int mmu_idx, target_ulong size)
Blue Swirl0cac1b62012-04-09 16:50:52 +0000341{
Andreas Färber0c591eb2013-09-03 13:59:37 +0200342 CPUArchState *env = cpu->env_ptr;
Blue Swirl0cac1b62012-04-09 16:50:52 +0000343 MemoryRegionSection *section;
344 unsigned int index;
345 target_ulong address;
346 target_ulong code_address;
347 uintptr_t addend;
348 CPUTLBEntry *te;
Paolo Bonzini149f54b2013-05-24 12:59:37 +0200349 hwaddr iotlb, xlat, sz;
Xin Tong88e89a52014-08-04 20:35:23 -0500350 unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE;
Peter Maydelld7898cd2016-01-21 14:15:05 +0000351 int asidx = cpu_asidx_from_attrs(cpu, attrs);
Blue Swirl0cac1b62012-04-09 16:50:52 +0000352
353 assert(size >= TARGET_PAGE_SIZE);
354 if (size != TARGET_PAGE_SIZE) {
355 tlb_add_large_page(env, vaddr, size);
356 }
Paolo Bonzini149f54b2013-05-24 12:59:37 +0200357
358 sz = size;
Peter Maydelld7898cd2016-01-21 14:15:05 +0000359 section = address_space_translate_for_iotlb(cpu, asidx, paddr, &xlat, &sz);
Paolo Bonzini149f54b2013-05-24 12:59:37 +0200360 assert(sz >= TARGET_PAGE_SIZE);
361
Alex Bennée8526e1f2016-03-15 14:30:24 +0000362 tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
363 " prot=%x idx=%d\n",
364 vaddr, paddr, prot, mmu_idx);
Blue Swirl0cac1b62012-04-09 16:50:52 +0000365
366 address = vaddr;
Paolo Bonzini8f3e03c2013-05-24 16:45:30 +0200367 if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
368 /* IO memory case */
Blue Swirl0cac1b62012-04-09 16:50:52 +0000369 address |= TLB_MMIO;
Paolo Bonzini8f3e03c2013-05-24 16:45:30 +0200370 addend = 0;
371 } else {
372 /* TLB_MMIO for rom/romd handled below */
Paolo Bonzini149f54b2013-05-24 12:59:37 +0200373 addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
Blue Swirl0cac1b62012-04-09 16:50:52 +0000374 }
Blue Swirl0cac1b62012-04-09 16:50:52 +0000375
376 code_address = address;
Andreas Färberbb0e6272013-09-03 13:32:01 +0200377 iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat,
Paolo Bonzini149f54b2013-05-24 12:59:37 +0200378 prot, &address);
Blue Swirl0cac1b62012-04-09 16:50:52 +0000379
380 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
Blue Swirl0cac1b62012-04-09 16:50:52 +0000381 te = &env->tlb_table[mmu_idx][index];
Xin Tong88e89a52014-08-04 20:35:23 -0500382
383 /* do not discard the translation in te, evict it into a victim tlb */
384 env->tlb_v_table[mmu_idx][vidx] = *te;
385 env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
386
387 /* refill the tlb */
Peter Maydelle469b222015-04-26 16:49:23 +0100388 env->iotlb[mmu_idx][index].addr = iotlb - vaddr;
Peter Maydellfadc1cb2015-04-26 16:49:24 +0100389 env->iotlb[mmu_idx][index].attrs = attrs;
Blue Swirl0cac1b62012-04-09 16:50:52 +0000390 te->addend = addend - vaddr;
391 if (prot & PAGE_READ) {
392 te->addr_read = address;
393 } else {
394 te->addr_read = -1;
395 }
396
397 if (prot & PAGE_EXEC) {
398 te->addr_code = code_address;
399 } else {
400 te->addr_code = -1;
401 }
402 if (prot & PAGE_WRITE) {
403 if ((memory_region_is_ram(section->mr) && section->readonly)
Blue Swirlcc5bea62012-04-14 14:56:48 +0000404 || memory_region_is_romd(section->mr)) {
Blue Swirl0cac1b62012-04-09 16:50:52 +0000405 /* Write access calls the I/O callback. */
406 te->addr_write = address | TLB_MMIO;
407 } else if (memory_region_is_ram(section->mr)
Fam Zheng8e41fb62016-03-01 14:18:21 +0800408 && cpu_physical_memory_is_clean(
409 memory_region_get_ram_addr(section->mr) + xlat)) {
Blue Swirl0cac1b62012-04-09 16:50:52 +0000410 te->addr_write = address | TLB_NOTDIRTY;
411 } else {
412 te->addr_write = address;
413 }
414 } else {
415 te->addr_write = -1;
416 }
417}
418
Peter Maydellfadc1cb2015-04-26 16:49:24 +0100419/* Add a new TLB entry, but without specifying the memory
420 * transaction attributes to be used.
421 */
422void tlb_set_page(CPUState *cpu, target_ulong vaddr,
423 hwaddr paddr, int prot,
424 int mmu_idx, target_ulong size)
425{
426 tlb_set_page_with_attrs(cpu, vaddr, paddr, MEMTXATTRS_UNSPECIFIED,
427 prot, mmu_idx, size);
428}
429
Blue Swirl0cac1b62012-04-09 16:50:52 +0000430/* NOTE: this function can trigger an exception */
431/* NOTE2: the returned address is not exactly the physical address: it
Peter Maydell116aae32012-08-10 17:14:05 +0100432 * is actually a ram_addr_t (in system mode; the user mode emulation
433 * version of this function returns a guest virtual address).
434 */
Blue Swirl0cac1b62012-04-09 16:50:52 +0000435tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
436{
437 int mmu_idx, page_index, pd;
438 void *p;
439 MemoryRegion *mr;
Edgar E. Iglesias09daed82013-12-17 13:06:51 +1000440 CPUState *cpu = ENV_GET_CPU(env1);
Peter Maydella54c87b2016-01-21 14:15:05 +0000441 CPUIOTLBEntry *iotlbentry;
Blue Swirl0cac1b62012-04-09 16:50:52 +0000442
443 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
Benjamin Herrenschmidt97ed5cc2015-08-17 17:34:10 +1000444 mmu_idx = cpu_mmu_index(env1, true);
Blue Swirl0cac1b62012-04-09 16:50:52 +0000445 if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
446 (addr & TARGET_PAGE_MASK))) {
Blue Swirl0cac1b62012-04-09 16:50:52 +0000447 cpu_ldub_code(env1, addr);
Blue Swirl0cac1b62012-04-09 16:50:52 +0000448 }
Peter Maydella54c87b2016-01-21 14:15:05 +0000449 iotlbentry = &env1->iotlb[mmu_idx][page_index];
450 pd = iotlbentry->addr & ~TARGET_PAGE_MASK;
451 mr = iotlb_to_region(cpu, pd, iotlbentry->attrs);
Blue Swirl0cac1b62012-04-09 16:50:52 +0000452 if (memory_region_is_unassigned(mr)) {
Andreas Färberc658b942013-05-27 06:49:53 +0200453 CPUClass *cc = CPU_GET_CLASS(cpu);
454
455 if (cc->do_unassigned_access) {
456 cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
457 } else {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200458 cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x"
Andreas Färberc658b942013-05-27 06:49:53 +0200459 TARGET_FMT_lx "\n", addr);
460 }
Blue Swirl0cac1b62012-04-09 16:50:52 +0000461 }
462 p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
463 return qemu_ram_addr_from_host_nofail(p);
464}
465
Paolo Bonzini0f590e742014-03-28 17:55:24 +0100466#define MMUSUFFIX _mmu
467
468#define SHIFT 0
Paolo Bonzini58ed2702014-03-28 18:00:25 +0100469#include "softmmu_template.h"
Paolo Bonzini0f590e742014-03-28 17:55:24 +0100470
471#define SHIFT 1
Paolo Bonzini58ed2702014-03-28 18:00:25 +0100472#include "softmmu_template.h"
Paolo Bonzini0f590e742014-03-28 17:55:24 +0100473
474#define SHIFT 2
Paolo Bonzini58ed2702014-03-28 18:00:25 +0100475#include "softmmu_template.h"
Paolo Bonzini0f590e742014-03-28 17:55:24 +0100476
477#define SHIFT 3
Paolo Bonzini58ed2702014-03-28 18:00:25 +0100478#include "softmmu_template.h"
Paolo Bonzini0f590e742014-03-28 17:55:24 +0100479#undef MMUSUFFIX
480
Blue Swirl0cac1b62012-04-09 16:50:52 +0000481#define MMUSUFFIX _cmmu
Stefan Weil7e4e8862014-04-28 19:20:00 +0200482#undef GETPC_ADJ
483#define GETPC_ADJ 0
484#undef GETRA
485#define GETRA() ((uintptr_t)0)
Blue Swirl0cac1b62012-04-09 16:50:52 +0000486#define SOFTMMU_CODE_ACCESS
487
488#define SHIFT 0
Paolo Bonzini58ed2702014-03-28 18:00:25 +0100489#include "softmmu_template.h"
Blue Swirl0cac1b62012-04-09 16:50:52 +0000490
491#define SHIFT 1
Paolo Bonzini58ed2702014-03-28 18:00:25 +0100492#include "softmmu_template.h"
Blue Swirl0cac1b62012-04-09 16:50:52 +0000493
494#define SHIFT 2
Paolo Bonzini58ed2702014-03-28 18:00:25 +0100495#include "softmmu_template.h"
Blue Swirl0cac1b62012-04-09 16:50:52 +0000496
497#define SHIFT 3
Paolo Bonzini58ed2702014-03-28 18:00:25 +0100498#include "softmmu_template.h"