ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1 | /* |
| 2 | * CRIS emulation for qemu: main translation routines. |
| 3 | * |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 4 | * Copyright (c) 2008 AXIS Communications AB |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 5 | * Written by Edgar E. Iglesias. |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
Chetan Pant | bf1b52d | 2020-10-23 12:16:48 +0000 | [diff] [blame] | 10 | * version 2.1 of the License, or (at your option) any later version. |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 21 | /* |
| 22 | * FIXME: |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 23 | * The condition code translation is in need of attention. |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 24 | */ |
| 25 | |
Peter Maydell | 23b0d7d | 2016-01-26 18:17:24 +0000 | [diff] [blame] | 26 | #include "qemu/osdep.h" |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 27 | #include "cpu.h" |
Paolo Bonzini | 76cad71 | 2012-10-24 11:12:21 +0200 | [diff] [blame] | 28 | #include "disas/disas.h" |
Paolo Bonzini | 63c9155 | 2016-03-15 13:18:37 +0100 | [diff] [blame] | 29 | #include "exec/exec-all.h" |
Philippe Mathieu-Daudé | dcb32f1 | 2020-01-01 12:23:00 +0100 | [diff] [blame] | 30 | #include "tcg/tcg-op.h" |
Richard Henderson | 2ef6175 | 2014-04-07 22:31:41 -0700 | [diff] [blame] | 31 | #include "exec/helper-proto.h" |
edgar_igl | 5281966 | 2009-01-26 22:21:30 +0000 | [diff] [blame] | 32 | #include "mmu.h" |
Paolo Bonzini | f08b617 | 2014-03-28 19:42:10 +0100 | [diff] [blame] | 33 | #include "exec/cpu_ldst.h" |
Lluís Vilanova | 77fc6f5 | 2017-07-14 11:21:37 +0300 | [diff] [blame] | 34 | #include "exec/translator.h" |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 35 | #include "crisv32-decode.h" |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 36 | #include "qemu/qemu-print.h" |
Richard Henderson | 2ef6175 | 2014-04-07 22:31:41 -0700 | [diff] [blame] | 37 | #include "exec/helper-gen.h" |
Paolo Bonzini | 508127e | 2016-01-07 16:55:28 +0300 | [diff] [blame] | 38 | #include "exec/log.h" |
Lluís Vilanova | a7e30d8 | 2014-05-30 14:12:25 +0200 | [diff] [blame] | 39 | |
Richard Henderson | d53106c | 2023-03-31 10:37:04 -0700 | [diff] [blame] | 40 | #define HELPER_H "helper.h" |
| 41 | #include "exec/helper-info.c.inc" |
| 42 | #undef HELPER_H |
| 43 | |
Lluís Vilanova | a7e30d8 | 2014-05-30 14:12:25 +0200 | [diff] [blame] | 44 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 45 | #define DISAS_CRIS 0 |
| 46 | #if DISAS_CRIS |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 47 | # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 48 | #else |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 49 | # define LOG_DIS(...) do { } while (0) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 50 | #endif |
| 51 | |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 52 | #define D(x) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 53 | #define BUG() (gen_BUG(dc, __FILE__, __LINE__)) |
| 54 | #define BUG_ON(x) ({if (x) BUG();}) |
| 55 | |
Richard Henderson | c967475 | 2021-06-22 07:50:12 -0700 | [diff] [blame] | 56 | /* |
| 57 | * Target-specific is_jmp field values |
| 58 | */ |
| 59 | /* Only pc was modified dynamically */ |
| 60 | #define DISAS_JUMP DISAS_TARGET_0 |
| 61 | /* Cpu state was modified dynamically, including pc */ |
| 62 | #define DISAS_UPDATE DISAS_TARGET_1 |
| 63 | /* Cpu state was modified dynamically, excluding pc -- use npc */ |
| 64 | #define DISAS_UPDATE_NEXT DISAS_TARGET_2 |
Richard Henderson | 3173715 | 2021-06-20 13:43:35 -0700 | [diff] [blame] | 65 | /* PC update for delayed branch, see cpustate_changed otherwise */ |
| 66 | #define DISAS_DBRANCH DISAS_TARGET_3 |
edgar_igl | 4f400ab | 2008-02-28 09:37:58 +0000 | [diff] [blame] | 67 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 68 | /* Used by the decoder. */ |
| 69 | #define EXTRACT_FIELD(src, start, end) \ |
| 70 | (((src) >> start) & ((1 << (end - start + 1)) - 1)) |
| 71 | |
| 72 | #define CC_MASK_NZ 0xc |
| 73 | #define CC_MASK_NZV 0xe |
| 74 | #define CC_MASK_NZVC 0xf |
| 75 | #define CC_MASK_RNZV 0x10e |
| 76 | |
edgar_igl | 9b32fbf | 2008-10-07 22:54:52 +0000 | [diff] [blame] | 77 | static TCGv cpu_R[16]; |
| 78 | static TCGv cpu_PR[16]; |
| 79 | static TCGv cc_x; |
| 80 | static TCGv cc_src; |
| 81 | static TCGv cc_dest; |
| 82 | static TCGv cc_result; |
| 83 | static TCGv cc_op; |
| 84 | static TCGv cc_size; |
| 85 | static TCGv cc_mask; |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 86 | |
edgar_igl | 9b32fbf | 2008-10-07 22:54:52 +0000 | [diff] [blame] | 87 | static TCGv env_btaken; |
| 88 | static TCGv env_btarget; |
| 89 | static TCGv env_pc; |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 90 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 91 | /* This is the state at translation time. */ |
| 92 | typedef struct DisasContext { |
Richard Henderson | 67f69c4 | 2021-06-19 19:17:40 -0700 | [diff] [blame] | 93 | DisasContextBase base; |
| 94 | |
Andreas Färber | 0dd106c | 2013-09-03 18:42:27 +0200 | [diff] [blame] | 95 | CRISCPU *cpu; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 96 | target_ulong pc, ppc; |
Richard Henderson | 97fc0c2 | 2024-01-28 15:05:06 +1000 | [diff] [blame] | 97 | int mem_index; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 98 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 99 | /* Decoder. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 100 | unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 101 | uint32_t ir; |
| 102 | uint32_t opcode; |
| 103 | unsigned int op1; |
| 104 | unsigned int op2; |
| 105 | unsigned int zsize, zzsize; |
| 106 | unsigned int mode; |
| 107 | unsigned int postinc; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 108 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 109 | unsigned int size; |
| 110 | unsigned int src; |
| 111 | unsigned int dst; |
| 112 | unsigned int cond; |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 113 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 114 | int update_cc; |
| 115 | int cc_op; |
| 116 | int cc_size; |
| 117 | uint32_t cc_mask; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 118 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 119 | int cc_size_uptodate; /* -1 invalid or last written value. */ |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 120 | |
Veres Lajos | 67cc32e | 2015-09-08 22:45:14 +0100 | [diff] [blame] | 121 | int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */ |
| 122 | int flags_uptodate; /* Whether or not $ccs is up-to-date. */ |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 123 | int flags_x; |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 124 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 125 | int clear_x; /* Clear x after this insn? */ |
| 126 | int clear_prefix; /* Clear prefix after this insn? */ |
| 127 | int clear_locked_irq; /* Clear the irq lockout. */ |
| 128 | int cpustate_changed; |
| 129 | unsigned int tb_flags; /* tb dependent flags. */ |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 130 | |
Edgar E. Iglesias | 5cabc5c | 2011-01-10 23:24:36 +0100 | [diff] [blame] | 131 | #define JMP_NOJMP 0 |
| 132 | #define JMP_DIRECT 1 |
| 133 | #define JMP_DIRECT_CC 2 |
| 134 | #define JMP_INDIRECT 3 |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 135 | int jmp; /* 0=nojmp, 1=direct, 2=indirect. */ |
| 136 | uint32_t jmp_pc; |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 137 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 138 | int delayed_branch; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 139 | } DisasContext; |
| 140 | |
blueswir1 | 7ccfb2e | 2008-09-14 06:45:34 +0000 | [diff] [blame] | 141 | static void gen_BUG(DisasContext *dc, const char *file, int line) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 142 | { |
Thomas Huth | ba3fa39 | 2018-10-09 09:40:33 +0200 | [diff] [blame] | 143 | cpu_abort(CPU(dc->cpu), "%s:%d pc=%x\n", file, line, dc->pc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 144 | } |
| 145 | |
Richard Henderson | 5899ce6 | 2021-06-19 20:57:31 -0700 | [diff] [blame] | 146 | static const char * const regnames_v32[] = |
edgar_igl | a825e70 | 2008-03-16 16:51:58 +0000 | [diff] [blame] | 147 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 148 | "$r0", "$r1", "$r2", "$r3", |
| 149 | "$r4", "$r5", "$r6", "$r7", |
| 150 | "$r8", "$r9", "$r10", "$r11", |
| 151 | "$r12", "$r13", "$sp", "$acr", |
edgar_igl | a825e70 | 2008-03-16 16:51:58 +0000 | [diff] [blame] | 152 | }; |
Richard Henderson | 5899ce6 | 2021-06-19 20:57:31 -0700 | [diff] [blame] | 153 | |
| 154 | static const char * const pregnames_v32[] = |
edgar_igl | a825e70 | 2008-03-16 16:51:58 +0000 | [diff] [blame] | 155 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 156 | "$bz", "$vr", "$pid", "$srs", |
| 157 | "$wz", "$exs", "$eda", "$mof", |
| 158 | "$dz", "$ebp", "$erp", "$srp", |
| 159 | "$nrp", "$ccs", "$usp", "$spc", |
edgar_igl | a825e70 | 2008-03-16 16:51:58 +0000 | [diff] [blame] | 160 | }; |
| 161 | |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 162 | /* We need this table to handle preg-moves with implicit width. */ |
Richard Henderson | 5899ce6 | 2021-06-19 20:57:31 -0700 | [diff] [blame] | 163 | static const int preg_sizes[] = { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 164 | 1, /* bz. */ |
| 165 | 1, /* vr. */ |
| 166 | 4, /* pid. */ |
| 167 | 1, /* srs. */ |
| 168 | 2, /* wz. */ |
| 169 | 4, 4, 4, |
| 170 | 4, 4, 4, 4, |
| 171 | 4, 4, 4, 4, |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 172 | }; |
| 173 | |
| 174 | #define t_gen_mov_TN_env(tn, member) \ |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 175 | tcg_gen_ld_tl(tn, tcg_env, offsetof(CPUCRISState, member)) |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 176 | #define t_gen_mov_env_TN(member, tn) \ |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 177 | tcg_gen_st_tl(tn, tcg_env, offsetof(CPUCRISState, member)) |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 178 | #define t_gen_movi_env_TN(member, c) \ |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 179 | t_gen_mov_env_TN(member, tcg_constant_tl(c)) |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 180 | |
| 181 | static inline void t_gen_mov_TN_preg(TCGv tn, int r) |
| 182 | { |
zhanghailiang | fae3822 | 2014-11-17 13:57:34 +0800 | [diff] [blame] | 183 | assert(r >= 0 && r <= 15); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 184 | if (r == PR_BZ || r == PR_WZ || r == PR_DZ) { |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 185 | tcg_gen_movi_tl(tn, 0); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 186 | } else if (r == PR_VR) { |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 187 | tcg_gen_movi_tl(tn, 32); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 188 | } else { |
| 189 | tcg_gen_mov_tl(tn, cpu_PR[r]); |
| 190 | } |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 191 | } |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 192 | static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn) |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 193 | { |
zhanghailiang | fae3822 | 2014-11-17 13:57:34 +0800 | [diff] [blame] | 194 | assert(r >= 0 && r <= 15); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 195 | if (r == PR_BZ || r == PR_WZ || r == PR_DZ) { |
| 196 | return; |
| 197 | } else if (r == PR_SRS) { |
| 198 | tcg_gen_andi_tl(cpu_PR[r], tn, 3); |
| 199 | } else { |
| 200 | if (r == PR_PID) { |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 201 | gen_helper_tlb_flush_pid(tcg_env, tn); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 202 | } |
| 203 | if (dc->tb_flags & S_FLAG && r == PR_SPC) { |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 204 | gen_helper_spc_write(tcg_env, tn); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 205 | } else if (r == PR_CCS) { |
| 206 | dc->cpustate_changed = 1; |
| 207 | } |
| 208 | tcg_gen_mov_tl(cpu_PR[r], tn); |
| 209 | } |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 210 | } |
| 211 | |
Edgar E. Iglesias | 1884533 | 2010-06-16 13:46:15 +0200 | [diff] [blame] | 212 | /* Sign extend at translation time. */ |
| 213 | static int sign_extend(unsigned int val, unsigned int width) |
| 214 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 215 | int sval; |
Edgar E. Iglesias | 1884533 | 2010-06-16 13:46:15 +0200 | [diff] [blame] | 216 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 217 | /* LSL. */ |
| 218 | val <<= 31 - width; |
| 219 | sval = val; |
| 220 | /* ASR. */ |
| 221 | sval >>= 31 - width; |
| 222 | return sval; |
Edgar E. Iglesias | 1884533 | 2010-06-16 13:46:15 +0200 | [diff] [blame] | 223 | } |
| 224 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 225 | static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 226 | unsigned int size, unsigned int sign) |
Edgar E. Iglesias | 7de141c | 2010-06-16 11:49:30 +0200 | [diff] [blame] | 227 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 228 | int r; |
Edgar E. Iglesias | 7de141c | 2010-06-16 11:49:30 +0200 | [diff] [blame] | 229 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 230 | switch (size) { |
| 231 | case 4: |
| 232 | { |
| 233 | r = cpu_ldl_code(env, addr); |
| 234 | break; |
| 235 | } |
| 236 | case 2: |
| 237 | { |
| 238 | if (sign) { |
| 239 | r = cpu_ldsw_code(env, addr); |
| 240 | } else { |
| 241 | r = cpu_lduw_code(env, addr); |
| 242 | } |
| 243 | break; |
| 244 | } |
| 245 | case 1: |
| 246 | { |
| 247 | if (sign) { |
| 248 | r = cpu_ldsb_code(env, addr); |
| 249 | } else { |
| 250 | r = cpu_ldub_code(env, addr); |
| 251 | } |
| 252 | break; |
| 253 | } |
| 254 | default: |
Andreas Färber | 0dd106c | 2013-09-03 18:42:27 +0200 | [diff] [blame] | 255 | cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 256 | break; |
| 257 | } |
| 258 | return r; |
Edgar E. Iglesias | 7de141c | 2010-06-16 11:49:30 +0200 | [diff] [blame] | 259 | } |
| 260 | |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 261 | static void cris_lock_irq(DisasContext *dc) |
| 262 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 263 | dc->clear_locked_irq = 0; |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 264 | t_gen_movi_env_TN(locked_irq, 1); |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 265 | } |
| 266 | |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 267 | static inline void t_gen_raise_exception(uint32_t index) |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 268 | { |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 269 | gen_helper_raise_exception(tcg_env, tcg_constant_i32(index)); |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 270 | } |
| 271 | |
| 272 | static void t_gen_lsl(TCGv d, TCGv a, TCGv b) |
| 273 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 274 | TCGv t0, t_31; |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 275 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 276 | t0 = tcg_temp_new(); |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 277 | t_31 = tcg_constant_tl(31); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 278 | tcg_gen_shl_tl(d, a, b); |
edgar_igl | 7dcfb08 | 2008-10-27 12:39:30 +0000 | [diff] [blame] | 279 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 280 | tcg_gen_sub_tl(t0, t_31, b); |
| 281 | tcg_gen_sar_tl(t0, t0, t_31); |
| 282 | tcg_gen_and_tl(t0, t0, d); |
| 283 | tcg_gen_xor_tl(d, d, t0); |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 284 | } |
| 285 | |
| 286 | static void t_gen_lsr(TCGv d, TCGv a, TCGv b) |
| 287 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 288 | TCGv t0, t_31; |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 289 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 290 | t0 = tcg_temp_new(); |
| 291 | t_31 = tcg_temp_new(); |
| 292 | tcg_gen_shr_tl(d, a, b); |
edgar_igl | 7dcfb08 | 2008-10-27 12:39:30 +0000 | [diff] [blame] | 293 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 294 | tcg_gen_movi_tl(t_31, 31); |
| 295 | tcg_gen_sub_tl(t0, t_31, b); |
| 296 | tcg_gen_sar_tl(t0, t0, t_31); |
| 297 | tcg_gen_and_tl(t0, t0, d); |
| 298 | tcg_gen_xor_tl(d, d, t0); |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 299 | } |
| 300 | |
| 301 | static void t_gen_asr(TCGv d, TCGv a, TCGv b) |
| 302 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 303 | TCGv t0, t_31; |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 304 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 305 | t0 = tcg_temp_new(); |
| 306 | t_31 = tcg_temp_new(); |
| 307 | tcg_gen_sar_tl(d, a, b); |
edgar_igl | 7dcfb08 | 2008-10-27 12:39:30 +0000 | [diff] [blame] | 308 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 309 | tcg_gen_movi_tl(t_31, 31); |
| 310 | tcg_gen_sub_tl(t0, t_31, b); |
| 311 | tcg_gen_sar_tl(t0, t0, t_31); |
| 312 | tcg_gen_or_tl(d, d, t0); |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 313 | } |
| 314 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 315 | static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b) |
edgar_igl | aae6b32 | 2008-05-03 21:34:39 +0000 | [diff] [blame] | 316 | { |
Richard Henderson | 8817401 | 2015-09-02 11:38:10 -0700 | [diff] [blame] | 317 | TCGv t = tcg_temp_new(); |
edgar_igl | aae6b32 | 2008-05-03 21:34:39 +0000 | [diff] [blame] | 318 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 319 | /* |
| 320 | * d <<= 1 |
| 321 | * if (d >= s) |
| 322 | * d -= s; |
| 323 | */ |
| 324 | tcg_gen_shli_tl(d, a, 1); |
Richard Henderson | 8817401 | 2015-09-02 11:38:10 -0700 | [diff] [blame] | 325 | tcg_gen_sub_tl(t, d, b); |
| 326 | tcg_gen_movcond_tl(TCG_COND_GEU, d, d, b, t, d); |
edgar_igl | aae6b32 | 2008-05-03 21:34:39 +0000 | [diff] [blame] | 327 | } |
| 328 | |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 329 | static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs) |
| 330 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 331 | TCGv t; |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 332 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 333 | /* |
| 334 | * d <<= 1 |
| 335 | * if (n) |
| 336 | * d += s; |
| 337 | */ |
| 338 | t = tcg_temp_new(); |
| 339 | tcg_gen_shli_tl(d, a, 1); |
| 340 | tcg_gen_shli_tl(t, ccs, 31 - 3); |
| 341 | tcg_gen_sari_tl(t, t, 31); |
| 342 | tcg_gen_and_tl(t, t, b); |
| 343 | tcg_gen_add_tl(d, d, t); |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 344 | } |
| 345 | |
Michael Tokarev | 8b81968 | 2023-07-14 14:23:51 +0300 | [diff] [blame] | 346 | /* Extended arithmetic on CRIS. */ |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 347 | static inline void t_gen_add_flag(TCGv d, int flag) |
| 348 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 349 | TCGv c; |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 350 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 351 | c = tcg_temp_new(); |
| 352 | t_gen_mov_TN_preg(c, PR_CCS); |
| 353 | /* Propagate carry into d. */ |
| 354 | tcg_gen_andi_tl(c, c, 1 << flag); |
| 355 | if (flag) { |
| 356 | tcg_gen_shri_tl(c, c, flag); |
| 357 | } |
| 358 | tcg_gen_add_tl(d, d, c); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 359 | } |
| 360 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 361 | static inline void t_gen_addx_carry(DisasContext *dc, TCGv d) |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 362 | { |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 363 | if (dc->flags_x) { |
| 364 | TCGv c = tcg_temp_new(); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 365 | |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 366 | t_gen_mov_TN_preg(c, PR_CCS); |
| 367 | /* C flag is already at bit 0. */ |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 368 | tcg_gen_andi_tl(c, c, C_FLAG); |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 369 | tcg_gen_add_tl(d, d, c); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 370 | } |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 371 | } |
| 372 | |
edgar_igl | a39f8f3 | 2008-05-12 07:57:23 +0000 | [diff] [blame] | 373 | static inline void t_gen_subx_carry(DisasContext *dc, TCGv d) |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 374 | { |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 375 | if (dc->flags_x) { |
| 376 | TCGv c = tcg_temp_new(); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 377 | |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 378 | t_gen_mov_TN_preg(c, PR_CCS); |
| 379 | /* C flag is already at bit 0. */ |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 380 | tcg_gen_andi_tl(c, c, C_FLAG); |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 381 | tcg_gen_sub_tl(d, d, c); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 382 | } |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 383 | } |
| 384 | |
| 385 | /* Swap the two bytes within each half word of the s operand. |
| 386 | T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */ |
| 387 | static inline void t_gen_swapb(TCGv d, TCGv s) |
| 388 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 389 | TCGv t, org_s; |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 390 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 391 | t = tcg_temp_new(); |
| 392 | org_s = tcg_temp_new(); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 393 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 394 | /* d and s may refer to the same object. */ |
| 395 | tcg_gen_mov_tl(org_s, s); |
| 396 | tcg_gen_shli_tl(t, org_s, 8); |
| 397 | tcg_gen_andi_tl(d, t, 0xff00ff00); |
| 398 | tcg_gen_shri_tl(t, org_s, 8); |
| 399 | tcg_gen_andi_tl(t, t, 0x00ff00ff); |
| 400 | tcg_gen_or_tl(d, d, t); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 401 | } |
| 402 | |
| 403 | /* Swap the halfwords of the s operand. */ |
| 404 | static inline void t_gen_swapw(TCGv d, TCGv s) |
| 405 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 406 | TCGv t; |
| 407 | /* d and s refer the same object. */ |
| 408 | t = tcg_temp_new(); |
| 409 | tcg_gen_mov_tl(t, s); |
| 410 | tcg_gen_shli_tl(d, t, 16); |
| 411 | tcg_gen_shri_tl(t, t, 16); |
| 412 | tcg_gen_or_tl(d, d, t); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 413 | } |
| 414 | |
Philippe Mathieu-Daudé | 2775616 | 2023-08-23 16:55:42 +0200 | [diff] [blame] | 415 | /* |
| 416 | * Reverse the bits within each byte. |
| 417 | * |
| 418 | * T0 = ((T0 << 7) & 0x80808080) |
| 419 | * | ((T0 << 5) & 0x40404040) |
| 420 | * | ((T0 << 3) & 0x20202020) |
| 421 | * | ((T0 << 1) & 0x10101010) |
| 422 | * | ((T0 >> 1) & 0x08080808) |
| 423 | * | ((T0 >> 3) & 0x04040404) |
| 424 | * | ((T0 >> 5) & 0x02020202) |
| 425 | * | ((T0 >> 7) & 0x01010101); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 426 | */ |
Richard Henderson | 5899ce6 | 2021-06-19 20:57:31 -0700 | [diff] [blame] | 427 | static void t_gen_swapr(TCGv d, TCGv s) |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 428 | { |
Richard Henderson | 5899ce6 | 2021-06-19 20:57:31 -0700 | [diff] [blame] | 429 | static const struct { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 430 | int shift; /* LSL when positive, LSR when negative. */ |
| 431 | uint32_t mask; |
| 432 | } bitrev[] = { |
| 433 | {7, 0x80808080}, |
| 434 | {5, 0x40404040}, |
| 435 | {3, 0x20202020}, |
| 436 | {1, 0x10101010}, |
| 437 | {-1, 0x08080808}, |
| 438 | {-3, 0x04040404}, |
| 439 | {-5, 0x02020202}, |
| 440 | {-7, 0x01010101} |
| 441 | }; |
| 442 | int i; |
| 443 | TCGv t, org_s; |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 444 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 445 | /* d and s refer the same object. */ |
| 446 | t = tcg_temp_new(); |
| 447 | org_s = tcg_temp_new(); |
| 448 | tcg_gen_mov_tl(org_s, s); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 449 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 450 | tcg_gen_shli_tl(t, org_s, bitrev[0].shift); |
| 451 | tcg_gen_andi_tl(d, t, bitrev[0].mask); |
| 452 | for (i = 1; i < ARRAY_SIZE(bitrev); i++) { |
| 453 | if (bitrev[i].shift >= 0) { |
| 454 | tcg_gen_shli_tl(t, org_s, bitrev[i].shift); |
| 455 | } else { |
| 456 | tcg_gen_shri_tl(t, org_s, -bitrev[i].shift); |
| 457 | } |
| 458 | tcg_gen_andi_tl(t, t, bitrev[i].mask); |
| 459 | tcg_gen_or_tl(d, d, t); |
| 460 | } |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 461 | } |
| 462 | |
Richard Henderson | 06188c8 | 2021-06-20 11:39:52 -0700 | [diff] [blame] | 463 | static bool use_goto_tb(DisasContext *dc, target_ulong dest) |
Sergey Fedorov | 90aa39a | 2016-04-09 01:00:23 +0300 | [diff] [blame] | 464 | { |
Richard Henderson | ca92d7f | 2021-06-20 16:05:53 -0700 | [diff] [blame] | 465 | return translator_use_goto_tb(&dc->base, dest); |
Sergey Fedorov | 90aa39a | 2016-04-09 01:00:23 +0300 | [diff] [blame] | 466 | } |
| 467 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 468 | static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) |
| 469 | { |
Sergey Fedorov | 90aa39a | 2016-04-09 01:00:23 +0300 | [diff] [blame] | 470 | if (use_goto_tb(dc, dest)) { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 471 | tcg_gen_goto_tb(n); |
| 472 | tcg_gen_movi_tl(env_pc, dest); |
Richard Henderson | 67f69c4 | 2021-06-19 19:17:40 -0700 | [diff] [blame] | 473 | tcg_gen_exit_tb(dc->base.tb, n); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 474 | } else { |
| 475 | tcg_gen_movi_tl(env_pc, dest); |
Richard Henderson | e0a4620 | 2021-06-20 13:49:17 -0700 | [diff] [blame] | 476 | tcg_gen_lookup_and_goto_ptr(); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 477 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 478 | } |
| 479 | |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 480 | static inline void cris_clear_x_flag(DisasContext *dc) |
| 481 | { |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 482 | if (dc->flags_x) { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 483 | dc->flags_uptodate = 0; |
| 484 | } |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 485 | dc->flags_x = 0; |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 486 | } |
| 487 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 488 | static void cris_flush_cc_state(DisasContext *dc) |
| 489 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 490 | if (dc->cc_size_uptodate != dc->cc_size) { |
| 491 | tcg_gen_movi_tl(cc_size, dc->cc_size); |
| 492 | dc->cc_size_uptodate = dc->cc_size; |
| 493 | } |
| 494 | tcg_gen_movi_tl(cc_op, dc->cc_op); |
| 495 | tcg_gen_movi_tl(cc_mask, dc->cc_mask); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 496 | } |
| 497 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 498 | static void cris_evaluate_flags(DisasContext *dc) |
| 499 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 500 | if (dc->flags_uptodate) { |
| 501 | return; |
| 502 | } |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 503 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 504 | cris_flush_cc_state(dc); |
edgar_igl | 6231868 | 2009-01-07 23:38:41 +0000 | [diff] [blame] | 505 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 506 | switch (dc->cc_op) { |
| 507 | case CC_OP_MCP: |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 508 | gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], tcg_env, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 509 | cpu_PR[PR_CCS], cc_src, |
| 510 | cc_dest, cc_result); |
| 511 | break; |
| 512 | case CC_OP_MULS: |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 513 | gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], tcg_env, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 514 | cpu_PR[PR_CCS], cc_result, |
| 515 | cpu_PR[PR_MOF]); |
| 516 | break; |
| 517 | case CC_OP_MULU: |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 518 | gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], tcg_env, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 519 | cpu_PR[PR_CCS], cc_result, |
| 520 | cpu_PR[PR_MOF]); |
| 521 | break; |
| 522 | case CC_OP_MOVE: |
| 523 | case CC_OP_AND: |
| 524 | case CC_OP_OR: |
| 525 | case CC_OP_XOR: |
| 526 | case CC_OP_ASR: |
| 527 | case CC_OP_LSR: |
| 528 | case CC_OP_LSL: |
| 529 | switch (dc->cc_size) { |
| 530 | case 4: |
| 531 | gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 532 | tcg_env, cpu_PR[PR_CCS], cc_result); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 533 | break; |
| 534 | case 2: |
| 535 | gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 536 | tcg_env, cpu_PR[PR_CCS], cc_result); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 537 | break; |
| 538 | default: |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 539 | gen_helper_evaluate_flags(tcg_env); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 540 | break; |
edgar_igl | 6231868 | 2009-01-07 23:38:41 +0000 | [diff] [blame] | 541 | } |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 542 | break; |
| 543 | case CC_OP_FLAGS: |
| 544 | /* live. */ |
| 545 | break; |
| 546 | case CC_OP_SUB: |
| 547 | case CC_OP_CMP: |
| 548 | if (dc->cc_size == 4) { |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 549 | gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], tcg_env, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 550 | cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); |
| 551 | } else { |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 552 | gen_helper_evaluate_flags(tcg_env); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 553 | } |
| 554 | |
| 555 | break; |
| 556 | default: |
| 557 | switch (dc->cc_size) { |
| 558 | case 4: |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 559 | gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], tcg_env, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 560 | cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); |
| 561 | break; |
| 562 | default: |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 563 | gen_helper_evaluate_flags(tcg_env); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 564 | break; |
| 565 | } |
| 566 | break; |
| 567 | } |
| 568 | |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 569 | if (dc->flags_x) { |
| 570 | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG); |
| 571 | } else if (dc->cc_op == CC_OP_FLAGS) { |
| 572 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 573 | } |
| 574 | dc->flags_uptodate = 1; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 575 | } |
| 576 | |
| 577 | static void cris_cc_mask(DisasContext *dc, unsigned int mask) |
| 578 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 579 | uint32_t ovl; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 580 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 581 | if (!mask) { |
| 582 | dc->update_cc = 0; |
| 583 | return; |
| 584 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 585 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 586 | /* Check if we need to evaluate the condition codes due to |
| 587 | CC overlaying. */ |
| 588 | ovl = (dc->cc_mask ^ mask) & ~mask; |
| 589 | if (ovl) { |
| 590 | /* TODO: optimize this case. It trigs all the time. */ |
| 591 | cris_evaluate_flags(dc); |
| 592 | } |
| 593 | dc->cc_mask = mask; |
| 594 | dc->update_cc = 1; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 595 | } |
| 596 | |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 597 | static void cris_update_cc_op(DisasContext *dc, int op, int size) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 598 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 599 | dc->cc_op = op; |
| 600 | dc->cc_size = size; |
| 601 | dc->flags_uptodate = 0; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 602 | } |
| 603 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 604 | static inline void cris_update_cc_x(DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 605 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 606 | /* Save the x flag state at the time of the cc snapshot. */ |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 607 | if (dc->cc_x_uptodate == (2 | dc->flags_x)) { |
| 608 | return; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 609 | } |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 610 | tcg_gen_movi_tl(cc_x, dc->flags_x); |
| 611 | dc->cc_x_uptodate = 2 | dc->flags_x; |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 612 | } |
| 613 | |
| 614 | /* Update cc prior to executing ALU op. Needs source operands untouched. */ |
| 615 | static void cris_pre_alu_update_cc(DisasContext *dc, int op, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 616 | TCGv dst, TCGv src, int size) |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 617 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 618 | if (dc->update_cc) { |
| 619 | cris_update_cc_op(dc, op, size); |
| 620 | tcg_gen_mov_tl(cc_src, src); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 621 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 622 | if (op != CC_OP_MOVE |
| 623 | && op != CC_OP_AND |
| 624 | && op != CC_OP_OR |
| 625 | && op != CC_OP_XOR |
| 626 | && op != CC_OP_ASR |
| 627 | && op != CC_OP_LSR |
| 628 | && op != CC_OP_LSL) { |
| 629 | tcg_gen_mov_tl(cc_dest, dst); |
| 630 | } |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 631 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 632 | cris_update_cc_x(dc); |
| 633 | } |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 634 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 635 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 636 | /* Update cc after executing ALU op. needs the result. */ |
| 637 | static inline void cris_update_result(DisasContext *dc, TCGv res) |
| 638 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 639 | if (dc->update_cc) { |
| 640 | tcg_gen_mov_tl(cc_result, res); |
| 641 | } |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 642 | } |
| 643 | |
| 644 | /* Returns one if the write back stage should execute. */ |
| 645 | static void cris_alu_op_exec(DisasContext *dc, int op, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 646 | TCGv dst, TCGv a, TCGv b, int size) |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 647 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 648 | /* Emit the ALU insns. */ |
| 649 | switch (op) { |
| 650 | case CC_OP_ADD: |
| 651 | tcg_gen_add_tl(dst, a, b); |
Michael Tokarev | 8b81968 | 2023-07-14 14:23:51 +0300 | [diff] [blame] | 652 | /* Extended arithmetic. */ |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 653 | t_gen_addx_carry(dc, dst); |
| 654 | break; |
| 655 | case CC_OP_ADDC: |
| 656 | tcg_gen_add_tl(dst, a, b); |
| 657 | t_gen_add_flag(dst, 0); /* C_FLAG. */ |
| 658 | break; |
| 659 | case CC_OP_MCP: |
| 660 | tcg_gen_add_tl(dst, a, b); |
| 661 | t_gen_add_flag(dst, 8); /* R_FLAG. */ |
| 662 | break; |
| 663 | case CC_OP_SUB: |
| 664 | tcg_gen_sub_tl(dst, a, b); |
Michael Tokarev | 8b81968 | 2023-07-14 14:23:51 +0300 | [diff] [blame] | 665 | /* Extended arithmetic. */ |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 666 | t_gen_subx_carry(dc, dst); |
| 667 | break; |
| 668 | case CC_OP_MOVE: |
| 669 | tcg_gen_mov_tl(dst, b); |
| 670 | break; |
| 671 | case CC_OP_OR: |
| 672 | tcg_gen_or_tl(dst, a, b); |
| 673 | break; |
| 674 | case CC_OP_AND: |
| 675 | tcg_gen_and_tl(dst, a, b); |
| 676 | break; |
| 677 | case CC_OP_XOR: |
| 678 | tcg_gen_xor_tl(dst, a, b); |
| 679 | break; |
| 680 | case CC_OP_LSL: |
| 681 | t_gen_lsl(dst, a, b); |
| 682 | break; |
| 683 | case CC_OP_LSR: |
| 684 | t_gen_lsr(dst, a, b); |
| 685 | break; |
| 686 | case CC_OP_ASR: |
| 687 | t_gen_asr(dst, a, b); |
| 688 | break; |
| 689 | case CC_OP_NEG: |
| 690 | tcg_gen_neg_tl(dst, b); |
Michael Tokarev | 8b81968 | 2023-07-14 14:23:51 +0300 | [diff] [blame] | 691 | /* Extended arithmetic. */ |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 692 | t_gen_subx_carry(dc, dst); |
| 693 | break; |
| 694 | case CC_OP_LZ: |
Richard Henderson | 272694a | 2016-11-16 10:54:57 +0100 | [diff] [blame] | 695 | tcg_gen_clzi_tl(dst, b, TARGET_LONG_BITS); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 696 | break; |
| 697 | case CC_OP_MULS: |
Richard Henderson | bf45f97 | 2013-02-19 23:52:11 -0800 | [diff] [blame] | 698 | tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 699 | break; |
| 700 | case CC_OP_MULU: |
Richard Henderson | bf45f97 | 2013-02-19 23:52:11 -0800 | [diff] [blame] | 701 | tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 702 | break; |
| 703 | case CC_OP_DSTEP: |
| 704 | t_gen_cris_dstep(dst, a, b); |
| 705 | break; |
| 706 | case CC_OP_MSTEP: |
| 707 | t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]); |
| 708 | break; |
| 709 | case CC_OP_BOUND: |
Richard Henderson | 8817401 | 2015-09-02 11:38:10 -0700 | [diff] [blame] | 710 | tcg_gen_movcond_tl(TCG_COND_LEU, dst, a, b, a, b); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 711 | break; |
| 712 | case CC_OP_CMP: |
| 713 | tcg_gen_sub_tl(dst, a, b); |
Michael Tokarev | 8b81968 | 2023-07-14 14:23:51 +0300 | [diff] [blame] | 714 | /* Extended arithmetic. */ |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 715 | t_gen_subx_carry(dc, dst); |
| 716 | break; |
| 717 | default: |
Paolo Bonzini | 79e8ed3 | 2015-11-13 13:24:26 +0100 | [diff] [blame] | 718 | qemu_log_mask(LOG_GUEST_ERROR, "illegal ALU op.\n"); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 719 | BUG(); |
| 720 | break; |
| 721 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 722 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 723 | if (size == 1) { |
| 724 | tcg_gen_andi_tl(dst, dst, 0xff); |
| 725 | } else if (size == 2) { |
| 726 | tcg_gen_andi_tl(dst, dst, 0xffff); |
| 727 | } |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 728 | } |
| 729 | |
| 730 | static void cris_alu(DisasContext *dc, int op, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 731 | TCGv d, TCGv op_a, TCGv op_b, int size) |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 732 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 733 | TCGv tmp; |
| 734 | int writeback; |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 735 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 736 | writeback = 1; |
edgar_igl | 31c18d8 | 2008-10-27 20:24:59 +0000 | [diff] [blame] | 737 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 738 | if (op == CC_OP_CMP) { |
| 739 | tmp = tcg_temp_new(); |
| 740 | writeback = 0; |
| 741 | } else if (size == 4) { |
| 742 | tmp = d; |
| 743 | writeback = 0; |
| 744 | } else { |
| 745 | tmp = tcg_temp_new(); |
| 746 | } |
edgar_igl | 4469629 | 2008-10-28 00:13:15 +0000 | [diff] [blame] | 747 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 748 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 749 | cris_pre_alu_update_cc(dc, op, op_a, op_b, size); |
| 750 | cris_alu_op_exec(dc, op, tmp, op_a, op_b, size); |
| 751 | cris_update_result(dc, tmp); |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 752 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 753 | /* Writeback. */ |
| 754 | if (writeback) { |
| 755 | if (size == 1) { |
| 756 | tcg_gen_andi_tl(d, d, ~0xff); |
| 757 | } else { |
| 758 | tcg_gen_andi_tl(d, d, ~0xffff); |
| 759 | } |
| 760 | tcg_gen_or_tl(d, d, tmp); |
| 761 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 762 | } |
| 763 | |
| 764 | static int arith_cc(DisasContext *dc) |
| 765 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 766 | if (dc->update_cc) { |
| 767 | switch (dc->cc_op) { |
| 768 | case CC_OP_ADDC: return 1; |
| 769 | case CC_OP_ADD: return 1; |
| 770 | case CC_OP_SUB: return 1; |
| 771 | case CC_OP_DSTEP: return 1; |
| 772 | case CC_OP_LSL: return 1; |
| 773 | case CC_OP_LSR: return 1; |
| 774 | case CC_OP_ASR: return 1; |
| 775 | case CC_OP_CMP: return 1; |
| 776 | case CC_OP_NEG: return 1; |
| 777 | case CC_OP_OR: return 1; |
| 778 | case CC_OP_AND: return 1; |
| 779 | case CC_OP_XOR: return 1; |
| 780 | case CC_OP_MULU: return 1; |
| 781 | case CC_OP_MULS: return 1; |
| 782 | default: |
| 783 | return 0; |
| 784 | } |
| 785 | } |
| 786 | return 0; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 787 | } |
| 788 | |
edgar_igl | c5631f4 | 2008-10-27 13:52:44 +0000 | [diff] [blame] | 789 | static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 790 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 791 | int arith_opt, move_opt; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 792 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 793 | /* TODO: optimize more condition codes. */ |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 794 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 795 | /* |
| 796 | * If the flags are live, we've gotta look into the bits of CCS. |
| 797 | * Otherwise, if we just did an arithmetic operation we try to |
| 798 | * evaluate the condition code faster. |
| 799 | * |
| 800 | * When this function is done, T0 should be non-zero if the condition |
| 801 | * code is true. |
| 802 | */ |
| 803 | arith_opt = arith_cc(dc) && !dc->flags_uptodate; |
| 804 | move_opt = (dc->cc_op == CC_OP_MOVE); |
| 805 | switch (cond) { |
| 806 | case CC_EQ: |
| 807 | if ((arith_opt || move_opt) |
| 808 | && dc->cc_x_uptodate != (2 | X_FLAG)) { |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 809 | tcg_gen_setcondi_tl(TCG_COND_EQ, cc, cc_result, 0); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 810 | } else { |
| 811 | cris_evaluate_flags(dc); |
| 812 | tcg_gen_andi_tl(cc, |
| 813 | cpu_PR[PR_CCS], Z_FLAG); |
| 814 | } |
| 815 | break; |
| 816 | case CC_NE: |
| 817 | if ((arith_opt || move_opt) |
| 818 | && dc->cc_x_uptodate != (2 | X_FLAG)) { |
| 819 | tcg_gen_mov_tl(cc, cc_result); |
| 820 | } else { |
| 821 | cris_evaluate_flags(dc); |
| 822 | tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], |
| 823 | Z_FLAG); |
| 824 | tcg_gen_andi_tl(cc, cc, Z_FLAG); |
| 825 | } |
| 826 | break; |
| 827 | case CC_CS: |
| 828 | cris_evaluate_flags(dc); |
| 829 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG); |
| 830 | break; |
| 831 | case CC_CC: |
| 832 | cris_evaluate_flags(dc); |
| 833 | tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG); |
| 834 | tcg_gen_andi_tl(cc, cc, C_FLAG); |
| 835 | break; |
| 836 | case CC_VS: |
| 837 | cris_evaluate_flags(dc); |
| 838 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG); |
| 839 | break; |
| 840 | case CC_VC: |
| 841 | cris_evaluate_flags(dc); |
| 842 | tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], |
| 843 | V_FLAG); |
| 844 | tcg_gen_andi_tl(cc, cc, V_FLAG); |
| 845 | break; |
| 846 | case CC_PL: |
| 847 | if (arith_opt || move_opt) { |
| 848 | int bits = 31; |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 849 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 850 | if (dc->cc_size == 1) { |
| 851 | bits = 7; |
| 852 | } else if (dc->cc_size == 2) { |
| 853 | bits = 15; |
| 854 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 855 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 856 | tcg_gen_shri_tl(cc, cc_result, bits); |
| 857 | tcg_gen_xori_tl(cc, cc, 1); |
| 858 | } else { |
| 859 | cris_evaluate_flags(dc); |
| 860 | tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], |
| 861 | N_FLAG); |
| 862 | tcg_gen_andi_tl(cc, cc, N_FLAG); |
| 863 | } |
| 864 | break; |
| 865 | case CC_MI: |
| 866 | if (arith_opt || move_opt) { |
| 867 | int bits = 31; |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 868 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 869 | if (dc->cc_size == 1) { |
| 870 | bits = 7; |
| 871 | } else if (dc->cc_size == 2) { |
| 872 | bits = 15; |
| 873 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 874 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 875 | tcg_gen_shri_tl(cc, cc_result, bits); |
| 876 | tcg_gen_andi_tl(cc, cc, 1); |
| 877 | } else { |
| 878 | cris_evaluate_flags(dc); |
| 879 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], |
| 880 | N_FLAG); |
| 881 | } |
| 882 | break; |
| 883 | case CC_LS: |
| 884 | cris_evaluate_flags(dc); |
| 885 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], |
| 886 | C_FLAG | Z_FLAG); |
| 887 | break; |
| 888 | case CC_HI: |
| 889 | cris_evaluate_flags(dc); |
| 890 | { |
| 891 | TCGv tmp; |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 892 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 893 | tmp = tcg_temp_new(); |
| 894 | tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS], |
| 895 | C_FLAG | Z_FLAG); |
| 896 | /* Overlay the C flag on top of the Z. */ |
| 897 | tcg_gen_shli_tl(cc, tmp, 2); |
| 898 | tcg_gen_and_tl(cc, tmp, cc); |
| 899 | tcg_gen_andi_tl(cc, cc, Z_FLAG); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 900 | } |
| 901 | break; |
| 902 | case CC_GE: |
| 903 | cris_evaluate_flags(dc); |
| 904 | /* Overlay the V flag on top of the N. */ |
| 905 | tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2); |
| 906 | tcg_gen_xor_tl(cc, |
| 907 | cpu_PR[PR_CCS], cc); |
| 908 | tcg_gen_andi_tl(cc, cc, N_FLAG); |
| 909 | tcg_gen_xori_tl(cc, cc, N_FLAG); |
| 910 | break; |
| 911 | case CC_LT: |
| 912 | cris_evaluate_flags(dc); |
| 913 | /* Overlay the V flag on top of the N. */ |
| 914 | tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2); |
| 915 | tcg_gen_xor_tl(cc, |
| 916 | cpu_PR[PR_CCS], cc); |
| 917 | tcg_gen_andi_tl(cc, cc, N_FLAG); |
| 918 | break; |
| 919 | case CC_GT: |
| 920 | cris_evaluate_flags(dc); |
| 921 | { |
| 922 | TCGv n, z; |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 923 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 924 | n = tcg_temp_new(); |
| 925 | z = tcg_temp_new(); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 926 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 927 | /* To avoid a shift we overlay everything on |
| 928 | the V flag. */ |
| 929 | tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2); |
| 930 | tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1); |
| 931 | /* invert Z. */ |
| 932 | tcg_gen_xori_tl(z, z, 2); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 933 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 934 | tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); |
| 935 | tcg_gen_xori_tl(n, n, 2); |
| 936 | tcg_gen_and_tl(cc, z, n); |
| 937 | tcg_gen_andi_tl(cc, cc, 2); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 938 | } |
| 939 | break; |
| 940 | case CC_LE: |
| 941 | cris_evaluate_flags(dc); |
| 942 | { |
| 943 | TCGv n, z; |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 944 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 945 | n = tcg_temp_new(); |
| 946 | z = tcg_temp_new(); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 947 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 948 | /* To avoid a shift we overlay everything on |
| 949 | the V flag. */ |
| 950 | tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2); |
| 951 | tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 952 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 953 | tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); |
| 954 | tcg_gen_or_tl(cc, z, n); |
| 955 | tcg_gen_andi_tl(cc, cc, 2); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 956 | } |
| 957 | break; |
| 958 | case CC_P: |
| 959 | cris_evaluate_flags(dc); |
| 960 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG); |
| 961 | break; |
| 962 | case CC_A: |
| 963 | tcg_gen_movi_tl(cc, 1); |
| 964 | break; |
| 965 | default: |
| 966 | BUG(); |
| 967 | break; |
| 968 | }; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 969 | } |
| 970 | |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 971 | static void cris_store_direct_jmp(DisasContext *dc) |
| 972 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 973 | /* Store the direct jmp state into the cpu-state. */ |
| 974 | if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { |
| 975 | if (dc->jmp == JMP_DIRECT) { |
| 976 | tcg_gen_movi_tl(env_btaken, 1); |
| 977 | } |
| 978 | tcg_gen_movi_tl(env_btarget, dc->jmp_pc); |
| 979 | dc->jmp = JMP_INDIRECT; |
| 980 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 981 | } |
| 982 | |
| 983 | static void cris_prepare_cc_branch (DisasContext *dc, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 984 | int offset, int cond) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 985 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 986 | /* This helps us re-schedule the micro-code to insns in delay-slots |
| 987 | before the actual jump. */ |
| 988 | dc->delayed_branch = 2; |
| 989 | dc->jmp = JMP_DIRECT_CC; |
| 990 | dc->jmp_pc = dc->pc + offset; |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 991 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 992 | gen_tst_cc(dc, env_btaken, cond); |
| 993 | tcg_gen_movi_tl(env_btarget, dc->jmp_pc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 994 | } |
| 995 | |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 996 | |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 997 | /* jumps, when the dest is in a live reg for example. Direct should be set |
| 998 | when the dest addr is constant to allow tb chaining. */ |
| 999 | static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1000 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1001 | /* This helps us re-schedule the micro-code to insns in delay-slots |
| 1002 | before the actual jump. */ |
| 1003 | dc->delayed_branch = 2; |
| 1004 | dc->jmp = type; |
| 1005 | if (type == JMP_INDIRECT) { |
| 1006 | tcg_gen_movi_tl(env_btaken, 1); |
| 1007 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1008 | } |
| 1009 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1010 | static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr) |
| 1011 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1012 | /* If we get a fault on a delayslot we must keep the jmp state in |
| 1013 | the cpu-state to be able to re-execute the jmp. */ |
| 1014 | if (dc->delayed_branch == 1) { |
| 1015 | cris_store_direct_jmp(dc); |
| 1016 | } |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1017 | |
Richard Henderson | 97fc0c2 | 2024-01-28 15:05:06 +1000 | [diff] [blame] | 1018 | tcg_gen_qemu_ld_i64(dst, addr, dc->mem_index, MO_TEUQ); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1019 | } |
| 1020 | |
edgar_igl | 9b32fbf | 2008-10-07 22:54:52 +0000 | [diff] [blame] | 1021 | static void gen_load(DisasContext *dc, TCGv dst, TCGv addr, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1022 | unsigned int size, int sign) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1023 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1024 | /* If we get a fault on a delayslot we must keep the jmp state in |
| 1025 | the cpu-state to be able to re-execute the jmp. */ |
| 1026 | if (dc->delayed_branch == 1) { |
| 1027 | cris_store_direct_jmp(dc); |
| 1028 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1029 | |
Richard Henderson | 97fc0c2 | 2024-01-28 15:05:06 +1000 | [diff] [blame] | 1030 | tcg_gen_qemu_ld_tl(dst, addr, dc->mem_index, |
Richard Henderson | a1d22a3 | 2013-12-07 14:52:34 +1300 | [diff] [blame] | 1031 | MO_TE + ctz32(size) + (sign ? MO_SIGN : 0)); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1032 | } |
| 1033 | |
edgar_igl | 9b32fbf | 2008-10-07 22:54:52 +0000 | [diff] [blame] | 1034 | static void gen_store (DisasContext *dc, TCGv addr, TCGv val, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1035 | unsigned int size) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1036 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1037 | /* If we get a fault on a delayslot we must keep the jmp state in |
| 1038 | the cpu-state to be able to re-execute the jmp. */ |
| 1039 | if (dc->delayed_branch == 1) { |
| 1040 | cris_store_direct_jmp(dc); |
| 1041 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1042 | |
| 1043 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1044 | /* Conditional writes. We only support the kind were X and P are known |
| 1045 | at translation time. */ |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 1046 | if (dc->flags_x && (dc->tb_flags & P_FLAG)) { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1047 | dc->postinc = 0; |
| 1048 | cris_evaluate_flags(dc); |
| 1049 | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG); |
| 1050 | return; |
| 1051 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1052 | |
Richard Henderson | 97fc0c2 | 2024-01-28 15:05:06 +1000 | [diff] [blame] | 1053 | tcg_gen_qemu_st_tl(val, addr, dc->mem_index, MO_TE + ctz32(size)); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1054 | |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 1055 | if (dc->flags_x) { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1056 | cris_evaluate_flags(dc); |
| 1057 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG); |
| 1058 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1059 | } |
| 1060 | |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 1061 | static inline void t_gen_sext(TCGv d, TCGv s, int size) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1062 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1063 | if (size == 1) { |
| 1064 | tcg_gen_ext8s_i32(d, s); |
| 1065 | } else if (size == 2) { |
| 1066 | tcg_gen_ext16s_i32(d, s); |
Richard Henderson | 11f4e8f | 2017-10-19 20:27:27 -0700 | [diff] [blame] | 1067 | } else { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1068 | tcg_gen_mov_tl(d, s); |
| 1069 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1070 | } |
| 1071 | |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 1072 | static inline void t_gen_zext(TCGv d, TCGv s, int size) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1073 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1074 | if (size == 1) { |
| 1075 | tcg_gen_ext8u_i32(d, s); |
| 1076 | } else if (size == 2) { |
| 1077 | tcg_gen_ext16u_i32(d, s); |
Richard Henderson | 11f4e8f | 2017-10-19 20:27:27 -0700 | [diff] [blame] | 1078 | } else { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1079 | tcg_gen_mov_tl(d, s); |
| 1080 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1081 | } |
| 1082 | |
| 1083 | #if DISAS_CRIS |
| 1084 | static char memsize_char(int size) |
| 1085 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1086 | switch (size) { |
Liao Pingfang | 8ff1e46 | 2020-07-13 17:05:50 +0800 | [diff] [blame] | 1087 | case 1: return 'b'; |
| 1088 | case 2: return 'w'; |
| 1089 | case 4: return 'd'; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1090 | default: |
| 1091 | return 'x'; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1092 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1093 | } |
| 1094 | #endif |
| 1095 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1096 | static inline unsigned int memsize_z(DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1097 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1098 | return dc->zsize + 1; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1099 | } |
| 1100 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1101 | static inline unsigned int memsize_zz(DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1102 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1103 | switch (dc->zzsize) { |
| 1104 | case 0: return 1; |
| 1105 | case 1: return 2; |
| 1106 | default: |
| 1107 | return 4; |
| 1108 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1109 | } |
| 1110 | |
edgar_igl | c7d0569 | 2008-05-03 06:54:52 +0000 | [diff] [blame] | 1111 | static inline void do_postinc (DisasContext *dc, int size) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1112 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1113 | if (dc->postinc) { |
| 1114 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size); |
| 1115 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1116 | } |
| 1117 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1118 | static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1119 | int size, int s_ext, TCGv dst) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1120 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1121 | if (s_ext) { |
| 1122 | t_gen_sext(dst, cpu_R[rs], size); |
| 1123 | } else { |
| 1124 | t_gen_zext(dst, cpu_R[rs], size); |
| 1125 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1126 | } |
| 1127 | |
| 1128 | /* Prepare T0 and T1 for a register alu operation. |
| 1129 | s_ext decides if the operand1 should be sign-extended or zero-extended when |
| 1130 | needed. */ |
| 1131 | static void dec_prep_alu_r(DisasContext *dc, int rs, int rd, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1132 | int size, int s_ext, TCGv dst, TCGv src) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1133 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1134 | dec_prep_move_r(dc, rs, rd, size, s_ext, src); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1135 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1136 | if (s_ext) { |
| 1137 | t_gen_sext(dst, cpu_R[rd], size); |
| 1138 | } else { |
| 1139 | t_gen_zext(dst, cpu_R[rd], size); |
| 1140 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1141 | } |
| 1142 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1143 | static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc, |
| 1144 | int s_ext, int memsize, TCGv dst) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1145 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1146 | unsigned int rs; |
| 1147 | uint32_t imm; |
| 1148 | int is_imm; |
| 1149 | int insn_len = 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1150 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1151 | rs = dc->op1; |
| 1152 | is_imm = rs == 15 && dc->postinc; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1153 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1154 | /* Load [$rs] onto T1. */ |
| 1155 | if (is_imm) { |
| 1156 | insn_len = 2 + memsize; |
| 1157 | if (memsize == 1) { |
| 1158 | insn_len++; |
| 1159 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1160 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1161 | imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext); |
| 1162 | tcg_gen_movi_tl(dst, imm); |
| 1163 | dc->postinc = 0; |
| 1164 | } else { |
| 1165 | cris_flush_cc_state(dc); |
| 1166 | gen_load(dc, dst, cpu_R[rs], memsize, 0); |
| 1167 | if (s_ext) { |
| 1168 | t_gen_sext(dst, dst, memsize); |
| 1169 | } else { |
| 1170 | t_gen_zext(dst, dst, memsize); |
| 1171 | } |
| 1172 | } |
| 1173 | return insn_len; |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 1174 | } |
| 1175 | |
| 1176 | /* Prepare T0 and T1 for a memory + alu operation. |
| 1177 | s_ext decides if the operand1 should be sign-extended or zero-extended when |
| 1178 | needed. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1179 | static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc, |
| 1180 | int s_ext, int memsize, TCGv dst, TCGv src) |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 1181 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1182 | int insn_len; |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 1183 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1184 | insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src); |
| 1185 | tcg_gen_mov_tl(dst, cpu_R[dc->op2]); |
| 1186 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1187 | } |
| 1188 | |
| 1189 | #if DISAS_CRIS |
| 1190 | static const char *cc_name(int cc) |
| 1191 | { |
Richard Henderson | 5899ce6 | 2021-06-19 20:57:31 -0700 | [diff] [blame] | 1192 | static const char * const cc_names[16] = { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1193 | "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi", |
| 1194 | "ls", "hi", "ge", "lt", "gt", "le", "a", "p" |
| 1195 | }; |
| 1196 | assert(cc < 16); |
| 1197 | return cc_names[cc]; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1198 | } |
| 1199 | #endif |
| 1200 | |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 1201 | /* Start of insn decoders. */ |
| 1202 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1203 | static int dec_bccq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1204 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1205 | int32_t offset; |
| 1206 | int sign; |
| 1207 | uint32_t cond = dc->op2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1208 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1209 | offset = EXTRACT_FIELD(dc->ir, 1, 7); |
| 1210 | sign = EXTRACT_FIELD(dc->ir, 0, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1211 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1212 | offset *= 2; |
| 1213 | offset |= sign << 8; |
| 1214 | offset = sign_extend(offset, 8); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1215 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1216 | LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1217 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1218 | /* op2 holds the condition-code. */ |
| 1219 | cris_cc_mask(dc, 0); |
| 1220 | cris_prepare_cc_branch(dc, offset, cond); |
| 1221 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1222 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1223 | static int dec_addoq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1224 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1225 | int32_t imm; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1226 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1227 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7); |
| 1228 | imm = sign_extend(dc->op1, 7); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1229 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1230 | LOG_DIS("addoq %d, $r%u\n", imm, dc->op2); |
| 1231 | cris_cc_mask(dc, 0); |
| 1232 | /* Fetch register operand, */ |
| 1233 | tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm); |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 1234 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1235 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1236 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1237 | static int dec_addq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1238 | { |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1239 | TCGv c; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1240 | LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1241 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1242 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1243 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1244 | cris_cc_mask(dc, CC_MASK_NZVC); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1245 | |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 1246 | c = tcg_constant_tl(dc->op1); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1247 | cris_alu(dc, CC_OP_ADD, |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1248 | cpu_R[dc->op2], cpu_R[dc->op2], c, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1249 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1250 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1251 | static int dec_moveq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1252 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1253 | uint32_t imm; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1254 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1255 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1256 | imm = sign_extend(dc->op1, 5); |
| 1257 | LOG_DIS("moveq %d, $r%u\n", imm, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1258 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1259 | tcg_gen_movi_tl(cpu_R[dc->op2], imm); |
| 1260 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1261 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1262 | static int dec_subq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1263 | { |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1264 | TCGv c; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1265 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1266 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1267 | LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1268 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1269 | cris_cc_mask(dc, CC_MASK_NZVC); |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 1270 | c = tcg_constant_tl(dc->op1); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1271 | cris_alu(dc, CC_OP_SUB, |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1272 | cpu_R[dc->op2], cpu_R[dc->op2], c, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1273 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1274 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1275 | static int dec_cmpq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1276 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1277 | uint32_t imm; |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1278 | TCGv c; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1279 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1280 | imm = sign_extend(dc->op1, 5); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1281 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1282 | LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2); |
| 1283 | cris_cc_mask(dc, CC_MASK_NZVC); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1284 | |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 1285 | c = tcg_constant_tl(imm); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1286 | cris_alu(dc, CC_OP_CMP, |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1287 | cpu_R[dc->op2], cpu_R[dc->op2], c, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1288 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1289 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1290 | static int dec_andq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1291 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1292 | uint32_t imm; |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1293 | TCGv c; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1294 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1295 | imm = sign_extend(dc->op1, 5); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1296 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1297 | LOG_DIS("andq %d, $r%d\n", imm, dc->op2); |
| 1298 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1299 | |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 1300 | c = tcg_constant_tl(imm); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1301 | cris_alu(dc, CC_OP_AND, |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1302 | cpu_R[dc->op2], cpu_R[dc->op2], c, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1303 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1304 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1305 | static int dec_orq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1306 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1307 | uint32_t imm; |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1308 | TCGv c; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1309 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1310 | imm = sign_extend(dc->op1, 5); |
| 1311 | LOG_DIS("orq %d, $r%d\n", imm, dc->op2); |
| 1312 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1313 | |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 1314 | c = tcg_constant_tl(imm); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1315 | cris_alu(dc, CC_OP_OR, |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1316 | cpu_R[dc->op2], cpu_R[dc->op2], c, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1317 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1318 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1319 | static int dec_btstq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1320 | { |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1321 | TCGv c; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1322 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 1323 | LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2); |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 1324 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1325 | cris_cc_mask(dc, CC_MASK_NZ); |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 1326 | c = tcg_constant_tl(dc->op1); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1327 | cris_evaluate_flags(dc); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 1328 | gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->op2], |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1329 | c, cpu_PR[PR_CCS]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1330 | cris_alu(dc, CC_OP_MOVE, |
| 1331 | cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); |
| 1332 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
| 1333 | dc->flags_uptodate = 1; |
| 1334 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1335 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1336 | static int dec_asrq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1337 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1338 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 1339 | LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2); |
| 1340 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1341 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1342 | tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); |
| 1343 | cris_alu(dc, CC_OP_MOVE, |
| 1344 | cpu_R[dc->op2], |
| 1345 | cpu_R[dc->op2], cpu_R[dc->op2], 4); |
| 1346 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1347 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1348 | static int dec_lslq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1349 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1350 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 1351 | LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1352 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1353 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1354 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1355 | tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1356 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1357 | cris_alu(dc, CC_OP_MOVE, |
| 1358 | cpu_R[dc->op2], |
| 1359 | cpu_R[dc->op2], cpu_R[dc->op2], 4); |
| 1360 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1361 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1362 | static int dec_lsrq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1363 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1364 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 1365 | LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1366 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1367 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1368 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1369 | tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); |
| 1370 | cris_alu(dc, CC_OP_MOVE, |
| 1371 | cpu_R[dc->op2], |
| 1372 | cpu_R[dc->op2], cpu_R[dc->op2], 4); |
| 1373 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1374 | } |
| 1375 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1376 | static int dec_move_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1377 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1378 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1379 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1380 | LOG_DIS("move.%c $r%u, $r%u\n", |
| 1381 | memsize_char(size), dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1382 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1383 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1384 | if (size == 4) { |
| 1385 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]); |
| 1386 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1387 | cris_update_cc_op(dc, CC_OP_MOVE, 4); |
| 1388 | cris_update_cc_x(dc); |
| 1389 | cris_update_result(dc, cpu_R[dc->op2]); |
| 1390 | } else { |
| 1391 | TCGv t0; |
edgar_igl | 43d7ac4 | 2008-10-27 13:55:28 +0000 | [diff] [blame] | 1392 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1393 | t0 = tcg_temp_new(); |
| 1394 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); |
| 1395 | cris_alu(dc, CC_OP_MOVE, |
| 1396 | cpu_R[dc->op2], |
| 1397 | cpu_R[dc->op2], t0, size); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1398 | } |
| 1399 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1400 | } |
| 1401 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1402 | static int dec_scc_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1403 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1404 | int cond = dc->op2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1405 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1406 | LOG_DIS("s%s $r%u\n", |
| 1407 | cc_name(cond), dc->op1); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1408 | |
Richard Henderson | 8817401 | 2015-09-02 11:38:10 -0700 | [diff] [blame] | 1409 | gen_tst_cc(dc, cpu_R[dc->op1], cond); |
| 1410 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->op1], cpu_R[dc->op1], 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1411 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1412 | cris_cc_mask(dc, 0); |
| 1413 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1414 | } |
| 1415 | |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 1416 | static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t) |
| 1417 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1418 | if (size == 4) { |
| 1419 | t[0] = cpu_R[dc->op2]; |
| 1420 | t[1] = cpu_R[dc->op1]; |
| 1421 | } else { |
| 1422 | t[0] = tcg_temp_new(); |
| 1423 | t[1] = tcg_temp_new(); |
| 1424 | } |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 1425 | } |
| 1426 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1427 | static int dec_and_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1428 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1429 | TCGv t[2]; |
| 1430 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1431 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1432 | LOG_DIS("and.%c $r%u, $r%u\n", |
| 1433 | memsize_char(size), dc->op1, dc->op2); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1434 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1435 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 1436 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1437 | cris_alu_alloc_temps(dc, size, t); |
| 1438 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
| 1439 | cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1440 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1441 | } |
| 1442 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1443 | static int dec_lz_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1444 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1445 | TCGv t0; |
| 1446 | LOG_DIS("lz $r%u, $r%u\n", |
| 1447 | dc->op1, dc->op2); |
| 1448 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1449 | t0 = tcg_temp_new(); |
| 1450 | dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0); |
| 1451 | cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1452 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1453 | } |
| 1454 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1455 | static int dec_lsl_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1456 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1457 | TCGv t[2]; |
| 1458 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1459 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1460 | LOG_DIS("lsl.%c $r%u, $r%u\n", |
| 1461 | memsize_char(size), dc->op1, dc->op2); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1462 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1463 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1464 | cris_alu_alloc_temps(dc, size, t); |
| 1465 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
| 1466 | tcg_gen_andi_tl(t[1], t[1], 63); |
| 1467 | cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1468 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1469 | } |
| 1470 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1471 | static int dec_lsr_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1472 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1473 | TCGv t[2]; |
| 1474 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1475 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1476 | LOG_DIS("lsr.%c $r%u, $r%u\n", |
| 1477 | memsize_char(size), dc->op1, dc->op2); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1478 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1479 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1480 | cris_alu_alloc_temps(dc, size, t); |
| 1481 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
| 1482 | tcg_gen_andi_tl(t[1], t[1], 63); |
| 1483 | cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1484 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1485 | } |
| 1486 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1487 | static int dec_asr_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1488 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1489 | TCGv t[2]; |
| 1490 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1491 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1492 | LOG_DIS("asr.%c $r%u, $r%u\n", |
| 1493 | memsize_char(size), dc->op1, dc->op2); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1494 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1495 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1496 | cris_alu_alloc_temps(dc, size, t); |
| 1497 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); |
| 1498 | tcg_gen_andi_tl(t[1], t[1], 63); |
| 1499 | cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1500 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1501 | } |
| 1502 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1503 | static int dec_muls_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1504 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1505 | TCGv t[2]; |
| 1506 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1507 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1508 | LOG_DIS("muls.%c $r%u, $r%u\n", |
| 1509 | memsize_char(size), dc->op1, dc->op2); |
| 1510 | cris_cc_mask(dc, CC_MASK_NZV); |
| 1511 | cris_alu_alloc_temps(dc, size, t); |
| 1512 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1513 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1514 | cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1515 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1516 | } |
| 1517 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1518 | static int dec_mulu_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1519 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1520 | TCGv t[2]; |
| 1521 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1522 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1523 | LOG_DIS("mulu.%c $r%u, $r%u\n", |
| 1524 | memsize_char(size), dc->op1, dc->op2); |
| 1525 | cris_cc_mask(dc, CC_MASK_NZV); |
| 1526 | cris_alu_alloc_temps(dc, size, t); |
| 1527 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1528 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1529 | cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1530 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1531 | } |
| 1532 | |
| 1533 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1534 | static int dec_dstep_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1535 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1536 | LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2); |
| 1537 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1538 | cris_alu(dc, CC_OP_DSTEP, |
| 1539 | cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); |
| 1540 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1541 | } |
| 1542 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1543 | static int dec_xor_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1544 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1545 | TCGv t[2]; |
| 1546 | int size = memsize_zz(dc); |
| 1547 | LOG_DIS("xor.%c $r%u, $r%u\n", |
| 1548 | memsize_char(size), dc->op1, dc->op2); |
| 1549 | BUG_ON(size != 4); /* xor is dword. */ |
| 1550 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1551 | cris_alu_alloc_temps(dc, size, t); |
| 1552 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1553 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1554 | cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1555 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1556 | } |
| 1557 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1558 | static int dec_bound_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1559 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1560 | TCGv l0; |
| 1561 | int size = memsize_zz(dc); |
| 1562 | LOG_DIS("bound.%c $r%u, $r%u\n", |
| 1563 | memsize_char(size), dc->op1, dc->op2); |
| 1564 | cris_cc_mask(dc, CC_MASK_NZ); |
Richard Henderson | 5f153b1 | 2023-01-29 14:40:21 -1000 | [diff] [blame] | 1565 | l0 = tcg_temp_new(); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1566 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0); |
| 1567 | cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1568 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1569 | } |
| 1570 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1571 | static int dec_cmp_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1572 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1573 | TCGv t[2]; |
| 1574 | int size = memsize_zz(dc); |
| 1575 | LOG_DIS("cmp.%c $r%u, $r%u\n", |
| 1576 | memsize_char(size), dc->op1, dc->op2); |
| 1577 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1578 | cris_alu_alloc_temps(dc, size, t); |
| 1579 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1580 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1581 | cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1582 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1583 | } |
| 1584 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1585 | static int dec_abs_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1586 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1587 | LOG_DIS("abs $r%u, $r%u\n", |
| 1588 | dc->op1, dc->op2); |
| 1589 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 1590 | |
Richard Henderson | 73f671f | 2019-04-17 14:32:37 -1000 | [diff] [blame] | 1591 | tcg_gen_abs_tl(cpu_R[dc->op2], cpu_R[dc->op1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1592 | cris_alu(dc, CC_OP_MOVE, |
| 1593 | cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); |
| 1594 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1595 | } |
| 1596 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1597 | static int dec_add_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1598 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1599 | TCGv t[2]; |
| 1600 | int size = memsize_zz(dc); |
| 1601 | LOG_DIS("add.%c $r%u, $r%u\n", |
| 1602 | memsize_char(size), dc->op1, dc->op2); |
| 1603 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1604 | cris_alu_alloc_temps(dc, size, t); |
| 1605 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1606 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1607 | cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1608 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1609 | } |
| 1610 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1611 | static int dec_addc_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1612 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1613 | LOG_DIS("addc $r%u, $r%u\n", |
| 1614 | dc->op1, dc->op2); |
| 1615 | cris_evaluate_flags(dc); |
Richard Henderson | 0ce97a3 | 2021-06-22 08:18:12 -0700 | [diff] [blame] | 1616 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1617 | /* Set for this insn. */ |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1618 | dc->flags_x = X_FLAG; |
edgar_igl | a8cf66b | 2009-01-07 12:25:15 +0000 | [diff] [blame] | 1619 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1620 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1621 | cris_alu(dc, CC_OP_ADDC, |
| 1622 | cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); |
| 1623 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1624 | } |
| 1625 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1626 | static int dec_mcp_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1627 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1628 | LOG_DIS("mcp $p%u, $r%u\n", |
| 1629 | dc->op2, dc->op1); |
| 1630 | cris_evaluate_flags(dc); |
| 1631 | cris_cc_mask(dc, CC_MASK_RNZV); |
| 1632 | cris_alu(dc, CC_OP_MCP, |
| 1633 | cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4); |
| 1634 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1635 | } |
| 1636 | |
| 1637 | #if DISAS_CRIS |
| 1638 | static char * swapmode_name(int mode, char *modename) { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1639 | int i = 0; |
| 1640 | if (mode & 8) { |
| 1641 | modename[i++] = 'n'; |
| 1642 | } |
| 1643 | if (mode & 4) { |
| 1644 | modename[i++] = 'w'; |
| 1645 | } |
| 1646 | if (mode & 2) { |
| 1647 | modename[i++] = 'b'; |
| 1648 | } |
| 1649 | if (mode & 1) { |
| 1650 | modename[i++] = 'r'; |
| 1651 | } |
| 1652 | modename[i++] = 0; |
| 1653 | return modename; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1654 | } |
| 1655 | #endif |
| 1656 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1657 | static int dec_swap_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1658 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1659 | TCGv t0; |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 1660 | #if DISAS_CRIS |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1661 | char modename[4]; |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 1662 | #endif |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1663 | LOG_DIS("swap%s $r%u\n", |
| 1664 | swapmode_name(dc->op2, modename), dc->op1); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1665 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1666 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1667 | t0 = tcg_temp_new(); |
Peter Maydell | 08397c4 | 2014-06-07 18:03:01 +0100 | [diff] [blame] | 1668 | tcg_gen_mov_tl(t0, cpu_R[dc->op1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1669 | if (dc->op2 & 8) { |
| 1670 | tcg_gen_not_tl(t0, t0); |
| 1671 | } |
| 1672 | if (dc->op2 & 4) { |
| 1673 | t_gen_swapw(t0, t0); |
| 1674 | } |
| 1675 | if (dc->op2 & 2) { |
| 1676 | t_gen_swapb(t0, t0); |
| 1677 | } |
| 1678 | if (dc->op2 & 1) { |
| 1679 | t_gen_swapr(t0, t0); |
| 1680 | } |
| 1681 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1682 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1683 | } |
| 1684 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1685 | static int dec_or_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1686 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1687 | TCGv t[2]; |
| 1688 | int size = memsize_zz(dc); |
| 1689 | LOG_DIS("or.%c $r%u, $r%u\n", |
| 1690 | memsize_char(size), dc->op1, dc->op2); |
| 1691 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1692 | cris_alu_alloc_temps(dc, size, t); |
| 1693 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
| 1694 | cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1695 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1696 | } |
| 1697 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1698 | static int dec_addi_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1699 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1700 | TCGv t0; |
| 1701 | LOG_DIS("addi.%c $r%u, $r%u\n", |
| 1702 | memsize_char(memsize_zz(dc)), dc->op2, dc->op1); |
| 1703 | cris_cc_mask(dc, 0); |
| 1704 | t0 = tcg_temp_new(); |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1705 | tcg_gen_shli_tl(t0, cpu_R[dc->op2], dc->zzsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1706 | tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1707 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1708 | } |
| 1709 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1710 | static int dec_addi_acr(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1711 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1712 | TCGv t0; |
| 1713 | LOG_DIS("addi.%c $r%u, $r%u, $acr\n", |
| 1714 | memsize_char(memsize_zz(dc)), dc->op2, dc->op1); |
| 1715 | cris_cc_mask(dc, 0); |
| 1716 | t0 = tcg_temp_new(); |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1717 | tcg_gen_shli_tl(t0, cpu_R[dc->op2], dc->zzsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1718 | tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1719 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1720 | } |
| 1721 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1722 | static int dec_neg_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1723 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1724 | TCGv t[2]; |
| 1725 | int size = memsize_zz(dc); |
| 1726 | LOG_DIS("neg.%c $r%u, $r%u\n", |
| 1727 | memsize_char(size), dc->op1, dc->op2); |
| 1728 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1729 | cris_alu_alloc_temps(dc, size, t); |
| 1730 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1731 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1732 | cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1733 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1734 | } |
| 1735 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1736 | static int dec_btst_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1737 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1738 | LOG_DIS("btst $r%u, $r%u\n", |
| 1739 | dc->op1, dc->op2); |
| 1740 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1741 | cris_evaluate_flags(dc); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 1742 | gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->op2], |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1743 | cpu_R[dc->op1], cpu_PR[PR_CCS]); |
| 1744 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], |
| 1745 | cpu_R[dc->op2], cpu_R[dc->op2], 4); |
| 1746 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
| 1747 | dc->flags_uptodate = 1; |
| 1748 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1749 | } |
| 1750 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1751 | static int dec_sub_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1752 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1753 | TCGv t[2]; |
| 1754 | int size = memsize_zz(dc); |
| 1755 | LOG_DIS("sub.%c $r%u, $r%u\n", |
| 1756 | memsize_char(size), dc->op1, dc->op2); |
| 1757 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1758 | cris_alu_alloc_temps(dc, size, t); |
| 1759 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
| 1760 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1761 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1762 | } |
| 1763 | |
| 1764 | /* Zero extension. From size to dword. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1765 | static int dec_movu_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1766 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1767 | TCGv t0; |
| 1768 | int size = memsize_z(dc); |
| 1769 | LOG_DIS("movu.%c $r%u, $r%u\n", |
| 1770 | memsize_char(size), |
| 1771 | dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1772 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1773 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1774 | t0 = tcg_temp_new(); |
| 1775 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); |
| 1776 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1777 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1778 | } |
| 1779 | |
| 1780 | /* Sign extension. From size to dword. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1781 | static int dec_movs_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1782 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1783 | TCGv t0; |
| 1784 | int size = memsize_z(dc); |
| 1785 | LOG_DIS("movs.%c $r%u, $r%u\n", |
| 1786 | memsize_char(size), |
| 1787 | dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1788 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1789 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1790 | t0 = tcg_temp_new(); |
| 1791 | /* Size can only be qi or hi. */ |
| 1792 | t_gen_sext(t0, cpu_R[dc->op1], size); |
| 1793 | cris_alu(dc, CC_OP_MOVE, |
| 1794 | cpu_R[dc->op2], cpu_R[dc->op1], t0, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1795 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1796 | } |
| 1797 | |
| 1798 | /* zero extension. From size to dword. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1799 | static int dec_addu_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1800 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1801 | TCGv t0; |
| 1802 | int size = memsize_z(dc); |
| 1803 | LOG_DIS("addu.%c $r%u, $r%u\n", |
| 1804 | memsize_char(size), |
| 1805 | dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1806 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1807 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1808 | t0 = tcg_temp_new(); |
| 1809 | /* Size can only be qi or hi. */ |
| 1810 | t_gen_zext(t0, cpu_R[dc->op1], size); |
| 1811 | cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1812 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1813 | } |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 1814 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1815 | /* Sign extension. From size to dword. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1816 | static int dec_adds_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1817 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1818 | TCGv t0; |
| 1819 | int size = memsize_z(dc); |
| 1820 | LOG_DIS("adds.%c $r%u, $r%u\n", |
| 1821 | memsize_char(size), |
| 1822 | dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1823 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1824 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1825 | t0 = tcg_temp_new(); |
| 1826 | /* Size can only be qi or hi. */ |
| 1827 | t_gen_sext(t0, cpu_R[dc->op1], size); |
| 1828 | cris_alu(dc, CC_OP_ADD, |
| 1829 | cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1830 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1831 | } |
| 1832 | |
| 1833 | /* Zero extension. From size to dword. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1834 | static int dec_subu_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1835 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1836 | TCGv t0; |
| 1837 | int size = memsize_z(dc); |
| 1838 | LOG_DIS("subu.%c $r%u, $r%u\n", |
| 1839 | memsize_char(size), |
| 1840 | dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1841 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1842 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1843 | t0 = tcg_temp_new(); |
| 1844 | /* Size can only be qi or hi. */ |
| 1845 | t_gen_zext(t0, cpu_R[dc->op1], size); |
| 1846 | cris_alu(dc, CC_OP_SUB, |
| 1847 | cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1848 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1849 | } |
| 1850 | |
| 1851 | /* Sign extension. From size to dword. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1852 | static int dec_subs_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1853 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1854 | TCGv t0; |
| 1855 | int size = memsize_z(dc); |
| 1856 | LOG_DIS("subs.%c $r%u, $r%u\n", |
| 1857 | memsize_char(size), |
| 1858 | dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1859 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1860 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1861 | t0 = tcg_temp_new(); |
| 1862 | /* Size can only be qi or hi. */ |
| 1863 | t_gen_sext(t0, cpu_R[dc->op1], size); |
| 1864 | cris_alu(dc, CC_OP_SUB, |
| 1865 | cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1866 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1867 | } |
| 1868 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1869 | static int dec_setclrf(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1870 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1871 | uint32_t flags; |
| 1872 | int set = (~dc->opcode >> 2) & 1; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1873 | |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 1874 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1875 | flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4) |
| 1876 | | EXTRACT_FIELD(dc->ir, 0, 3); |
| 1877 | if (set && flags == 0) { |
| 1878 | LOG_DIS("nop\n"); |
| 1879 | return 2; |
| 1880 | } else if (!set && (flags & 0x20)) { |
| 1881 | LOG_DIS("di\n"); |
| 1882 | } else { |
| 1883 | LOG_DIS("%sf %x\n", set ? "set" : "clr", flags); |
| 1884 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1885 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1886 | /* User space is not allowed to touch these. Silently ignore. */ |
| 1887 | if (dc->tb_flags & U_FLAG) { |
| 1888 | flags &= ~(S_FLAG | I_FLAG | U_FLAG); |
| 1889 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1890 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1891 | if (flags & X_FLAG) { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1892 | if (set) { |
| 1893 | dc->flags_x = X_FLAG; |
| 1894 | } else { |
| 1895 | dc->flags_x = 0; |
| 1896 | } |
| 1897 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1898 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1899 | /* Break the TB if any of the SPI flag changes. */ |
| 1900 | if (flags & (P_FLAG | S_FLAG)) { |
| 1901 | tcg_gen_movi_tl(env_pc, dc->pc + 2); |
Richard Henderson | 67f69c4 | 2021-06-19 19:17:40 -0700 | [diff] [blame] | 1902 | dc->base.is_jmp = DISAS_UPDATE; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1903 | dc->cpustate_changed = 1; |
| 1904 | } |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 1905 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1906 | /* For the I flag, only act on posedge. */ |
| 1907 | if ((flags & I_FLAG)) { |
| 1908 | tcg_gen_movi_tl(env_pc, dc->pc + 2); |
Richard Henderson | 67f69c4 | 2021-06-19 19:17:40 -0700 | [diff] [blame] | 1909 | dc->base.is_jmp = DISAS_UPDATE; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1910 | dc->cpustate_changed = 1; |
| 1911 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1912 | |
| 1913 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1914 | /* Simply decode the flags. */ |
| 1915 | cris_evaluate_flags(dc); |
| 1916 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
| 1917 | cris_update_cc_x(dc); |
| 1918 | tcg_gen_movi_tl(cc_op, dc->cc_op); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 1919 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1920 | if (set) { |
| 1921 | if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) { |
| 1922 | /* Enter user mode. */ |
| 1923 | t_gen_mov_env_TN(ksp, cpu_R[R_SP]); |
| 1924 | tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]); |
| 1925 | dc->cpustate_changed = 1; |
| 1926 | } |
| 1927 | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags); |
| 1928 | } else { |
| 1929 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags); |
| 1930 | } |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 1931 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1932 | dc->flags_uptodate = 1; |
| 1933 | dc->clear_x = 0; |
| 1934 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1935 | } |
| 1936 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1937 | static int dec_move_rs(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1938 | { |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1939 | TCGv c2, c1; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1940 | LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2); |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 1941 | c1 = tcg_constant_tl(dc->op1); |
| 1942 | c2 = tcg_constant_tl(dc->op2); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1943 | cris_cc_mask(dc, 0); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 1944 | gen_helper_movl_sreg_reg(tcg_env, c2, c1); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1945 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1946 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1947 | static int dec_move_sr(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1948 | { |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 1949 | TCGv c2, c1; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1950 | LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1); |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 1951 | c1 = tcg_constant_tl(dc->op1); |
| 1952 | c2 = tcg_constant_tl(dc->op2); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1953 | cris_cc_mask(dc, 0); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 1954 | gen_helper_movl_reg_sreg(tcg_env, c1, c2); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1955 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1956 | } |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 1957 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1958 | static int dec_move_rp(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1959 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1960 | TCGv t[2]; |
| 1961 | LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2); |
| 1962 | cris_cc_mask(dc, 0); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 1963 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1964 | t[0] = tcg_temp_new(); |
| 1965 | if (dc->op2 == PR_CCS) { |
| 1966 | cris_evaluate_flags(dc); |
Peter Maydell | 08397c4 | 2014-06-07 18:03:01 +0100 | [diff] [blame] | 1967 | tcg_gen_mov_tl(t[0], cpu_R[dc->op1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1968 | if (dc->tb_flags & U_FLAG) { |
| 1969 | t[1] = tcg_temp_new(); |
| 1970 | /* User space is not allowed to touch all flags. */ |
| 1971 | tcg_gen_andi_tl(t[0], t[0], 0x39f); |
| 1972 | tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f); |
| 1973 | tcg_gen_or_tl(t[0], t[1], t[0]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1974 | } |
| 1975 | } else { |
Peter Maydell | 08397c4 | 2014-06-07 18:03:01 +0100 | [diff] [blame] | 1976 | tcg_gen_mov_tl(t[0], cpu_R[dc->op1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1977 | } |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 1978 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1979 | t_gen_mov_preg_TN(dc, dc->op2, t[0]); |
| 1980 | if (dc->op2 == PR_CCS) { |
| 1981 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
| 1982 | dc->flags_uptodate = 1; |
| 1983 | } |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1984 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1985 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1986 | static int dec_move_pr(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1987 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1988 | TCGv t0; |
| 1989 | LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1); |
| 1990 | cris_cc_mask(dc, 0); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1991 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1992 | if (dc->op2 == PR_CCS) { |
| 1993 | cris_evaluate_flags(dc); |
| 1994 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1995 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1996 | if (dc->op2 == PR_DZ) { |
| 1997 | tcg_gen_movi_tl(cpu_R[dc->op1], 0); |
| 1998 | } else { |
| 1999 | t0 = tcg_temp_new(); |
| 2000 | t_gen_mov_TN_preg(t0, dc->op2); |
| 2001 | cris_alu(dc, CC_OP_MOVE, |
| 2002 | cpu_R[dc->op1], cpu_R[dc->op1], t0, |
| 2003 | preg_sizes[dc->op2]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2004 | } |
| 2005 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2006 | } |
| 2007 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2008 | static int dec_move_mr(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2009 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2010 | int memsize = memsize_zz(dc); |
| 2011 | int insn_len; |
| 2012 | LOG_DIS("move.%c [$r%u%s, $r%u\n", |
| 2013 | memsize_char(memsize), |
| 2014 | dc->op1, dc->postinc ? "+]" : "]", |
| 2015 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2016 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2017 | if (memsize == 4) { |
| 2018 | insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]); |
| 2019 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2020 | cris_update_cc_op(dc, CC_OP_MOVE, 4); |
| 2021 | cris_update_cc_x(dc); |
| 2022 | cris_update_result(dc, cpu_R[dc->op2]); |
| 2023 | } else { |
| 2024 | TCGv t0; |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 2025 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2026 | t0 = tcg_temp_new(); |
| 2027 | insn_len = dec_prep_move_m(env, dc, 0, memsize, t0); |
| 2028 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2029 | cris_alu(dc, CC_OP_MOVE, |
| 2030 | cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2031 | } |
| 2032 | do_postinc(dc, memsize); |
| 2033 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2034 | } |
| 2035 | |
edgar_igl | 31c18d8 | 2008-10-27 20:24:59 +0000 | [diff] [blame] | 2036 | static inline void cris_alu_m_alloc_temps(TCGv *t) |
| 2037 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2038 | t[0] = tcg_temp_new(); |
| 2039 | t[1] = tcg_temp_new(); |
edgar_igl | 31c18d8 | 2008-10-27 20:24:59 +0000 | [diff] [blame] | 2040 | } |
| 2041 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2042 | static int dec_movs_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2043 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2044 | TCGv t[2]; |
| 2045 | int memsize = memsize_z(dc); |
| 2046 | int insn_len; |
| 2047 | LOG_DIS("movs.%c [$r%u%s, $r%u\n", |
| 2048 | memsize_char(memsize), |
| 2049 | dc->op1, dc->postinc ? "+]" : "]", |
| 2050 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2051 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2052 | cris_alu_m_alloc_temps(t); |
| 2053 | /* sign extend. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2054 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2055 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2056 | cris_alu(dc, CC_OP_MOVE, |
| 2057 | cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2058 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2059 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2060 | } |
| 2061 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2062 | static int dec_addu_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2063 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2064 | TCGv t[2]; |
| 2065 | int memsize = memsize_z(dc); |
| 2066 | int insn_len; |
| 2067 | LOG_DIS("addu.%c [$r%u%s, $r%u\n", |
| 2068 | memsize_char(memsize), |
| 2069 | dc->op1, dc->postinc ? "+]" : "]", |
| 2070 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2071 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2072 | cris_alu_m_alloc_temps(t); |
| 2073 | /* sign extend. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2074 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2075 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2076 | cris_alu(dc, CC_OP_ADD, |
| 2077 | cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2078 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2079 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2080 | } |
| 2081 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2082 | static int dec_adds_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2083 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2084 | TCGv t[2]; |
| 2085 | int memsize = memsize_z(dc); |
| 2086 | int insn_len; |
| 2087 | LOG_DIS("adds.%c [$r%u%s, $r%u\n", |
| 2088 | memsize_char(memsize), |
| 2089 | dc->op1, dc->postinc ? "+]" : "]", |
| 2090 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2091 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2092 | cris_alu_m_alloc_temps(t); |
| 2093 | /* sign extend. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2094 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2095 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2096 | cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2097 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2098 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2099 | } |
| 2100 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2101 | static int dec_subu_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2102 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2103 | TCGv t[2]; |
| 2104 | int memsize = memsize_z(dc); |
| 2105 | int insn_len; |
| 2106 | LOG_DIS("subu.%c [$r%u%s, $r%u\n", |
| 2107 | memsize_char(memsize), |
| 2108 | dc->op1, dc->postinc ? "+]" : "]", |
| 2109 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2110 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2111 | cris_alu_m_alloc_temps(t); |
| 2112 | /* sign extend. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2113 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2114 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2115 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2116 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2117 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2118 | } |
| 2119 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2120 | static int dec_subs_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2121 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2122 | TCGv t[2]; |
| 2123 | int memsize = memsize_z(dc); |
| 2124 | int insn_len; |
| 2125 | LOG_DIS("subs.%c [$r%u%s, $r%u\n", |
| 2126 | memsize_char(memsize), |
| 2127 | dc->op1, dc->postinc ? "+]" : "]", |
| 2128 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2129 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2130 | cris_alu_m_alloc_temps(t); |
| 2131 | /* sign extend. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2132 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2133 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2134 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2135 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2136 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2137 | } |
| 2138 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2139 | static int dec_movu_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2140 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2141 | TCGv t[2]; |
| 2142 | int memsize = memsize_z(dc); |
| 2143 | int insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2144 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2145 | LOG_DIS("movu.%c [$r%u%s, $r%u\n", |
| 2146 | memsize_char(memsize), |
| 2147 | dc->op1, dc->postinc ? "+]" : "]", |
| 2148 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2149 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2150 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2151 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2152 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2153 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2154 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2155 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2156 | } |
| 2157 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2158 | static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2159 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2160 | TCGv t[2]; |
| 2161 | int memsize = memsize_z(dc); |
| 2162 | int insn_len; |
| 2163 | LOG_DIS("cmpu.%c [$r%u%s, $r%u\n", |
| 2164 | memsize_char(memsize), |
| 2165 | dc->op1, dc->postinc ? "+]" : "]", |
| 2166 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2167 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2168 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2169 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2170 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2171 | cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2172 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2173 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2174 | } |
| 2175 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2176 | static int dec_cmps_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2177 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2178 | TCGv t[2]; |
| 2179 | int memsize = memsize_z(dc); |
| 2180 | int insn_len; |
| 2181 | LOG_DIS("cmps.%c [$r%u%s, $r%u\n", |
| 2182 | memsize_char(memsize), |
| 2183 | dc->op1, dc->postinc ? "+]" : "]", |
| 2184 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2185 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2186 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2187 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2188 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2189 | cris_alu(dc, CC_OP_CMP, |
| 2190 | cpu_R[dc->op2], cpu_R[dc->op2], t[1], |
| 2191 | memsize_zz(dc)); |
| 2192 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2193 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2194 | } |
| 2195 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2196 | static int dec_cmp_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2197 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2198 | TCGv t[2]; |
| 2199 | int memsize = memsize_zz(dc); |
| 2200 | int insn_len; |
| 2201 | LOG_DIS("cmp.%c [$r%u%s, $r%u\n", |
| 2202 | memsize_char(memsize), |
| 2203 | dc->op1, dc->postinc ? "+]" : "]", |
| 2204 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2205 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2206 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2207 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2208 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2209 | cris_alu(dc, CC_OP_CMP, |
| 2210 | cpu_R[dc->op2], cpu_R[dc->op2], t[1], |
| 2211 | memsize_zz(dc)); |
| 2212 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2213 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2214 | } |
| 2215 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2216 | static int dec_test_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2217 | { |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2218 | TCGv t[2], c; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2219 | int memsize = memsize_zz(dc); |
| 2220 | int insn_len; |
| 2221 | LOG_DIS("test.%c [$r%u%s] op2=%x\n", |
| 2222 | memsize_char(memsize), |
| 2223 | dc->op1, dc->postinc ? "+]" : "]", |
| 2224 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2225 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2226 | cris_evaluate_flags(dc); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 2227 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2228 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2229 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2230 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2231 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2232 | |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 2233 | c = tcg_constant_tl(0); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2234 | cris_alu(dc, CC_OP_CMP, |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2235 | cpu_R[dc->op2], t[1], c, memsize_zz(dc)); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2236 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2237 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2238 | } |
| 2239 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2240 | static int dec_and_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2241 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2242 | TCGv t[2]; |
| 2243 | int memsize = memsize_zz(dc); |
| 2244 | int insn_len; |
| 2245 | LOG_DIS("and.%c [$r%u%s, $r%u\n", |
| 2246 | memsize_char(memsize), |
| 2247 | dc->op1, dc->postinc ? "+]" : "]", |
| 2248 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2249 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2250 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2251 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2252 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2253 | cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); |
| 2254 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2255 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2256 | } |
| 2257 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2258 | static int dec_add_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2259 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2260 | TCGv t[2]; |
| 2261 | int memsize = memsize_zz(dc); |
| 2262 | int insn_len; |
| 2263 | LOG_DIS("add.%c [$r%u%s, $r%u\n", |
| 2264 | memsize_char(memsize), |
| 2265 | dc->op1, dc->postinc ? "+]" : "]", |
| 2266 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2267 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2268 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2269 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2270 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2271 | cris_alu(dc, CC_OP_ADD, |
| 2272 | cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); |
| 2273 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2274 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2275 | } |
| 2276 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2277 | static int dec_addo_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2278 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2279 | TCGv t[2]; |
| 2280 | int memsize = memsize_zz(dc); |
| 2281 | int insn_len; |
| 2282 | LOG_DIS("add.%c [$r%u%s, $r%u\n", |
| 2283 | memsize_char(memsize), |
| 2284 | dc->op1, dc->postinc ? "+]" : "]", |
| 2285 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2286 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2287 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2288 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2289 | cris_cc_mask(dc, 0); |
| 2290 | cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4); |
| 2291 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2292 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2293 | } |
| 2294 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2295 | static int dec_bound_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2296 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2297 | TCGv l[2]; |
| 2298 | int memsize = memsize_zz(dc); |
| 2299 | int insn_len; |
| 2300 | LOG_DIS("bound.%c [$r%u%s, $r%u\n", |
| 2301 | memsize_char(memsize), |
| 2302 | dc->op1, dc->postinc ? "+]" : "]", |
| 2303 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2304 | |
Richard Henderson | 5f153b1 | 2023-01-29 14:40:21 -1000 | [diff] [blame] | 2305 | l[0] = tcg_temp_new(); |
| 2306 | l[1] = tcg_temp_new(); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2307 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2308 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2309 | cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4); |
| 2310 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2311 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2312 | } |
| 2313 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2314 | static int dec_addc_mr(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2315 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2316 | TCGv t[2]; |
| 2317 | int insn_len = 2; |
| 2318 | LOG_DIS("addc [$r%u%s, $r%u\n", |
| 2319 | dc->op1, dc->postinc ? "+]" : "]", |
| 2320 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2321 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2322 | cris_evaluate_flags(dc); |
edgar_igl | a8cf66b | 2009-01-07 12:25:15 +0000 | [diff] [blame] | 2323 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2324 | /* Set for this insn. */ |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2325 | dc->flags_x = X_FLAG; |
edgar_igl | a8cf66b | 2009-01-07 12:25:15 +0000 | [diff] [blame] | 2326 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2327 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2328 | insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2329 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2330 | cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4); |
| 2331 | do_postinc(dc, 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2332 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2333 | } |
| 2334 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2335 | static int dec_sub_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2336 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2337 | TCGv t[2]; |
| 2338 | int memsize = memsize_zz(dc); |
| 2339 | int insn_len; |
| 2340 | LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n", |
| 2341 | memsize_char(memsize), |
| 2342 | dc->op1, dc->postinc ? "+]" : "]", |
| 2343 | dc->op2, dc->ir, dc->zzsize); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2344 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2345 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2346 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2347 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2348 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize); |
| 2349 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2350 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2351 | } |
| 2352 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2353 | static int dec_or_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2354 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2355 | TCGv t[2]; |
| 2356 | int memsize = memsize_zz(dc); |
| 2357 | int insn_len; |
| 2358 | LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n", |
| 2359 | memsize_char(memsize), |
| 2360 | dc->op1, dc->postinc ? "+]" : "]", |
| 2361 | dc->op2, dc->pc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2362 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2363 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2364 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2365 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2366 | cris_alu(dc, CC_OP_OR, |
| 2367 | cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); |
| 2368 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2369 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2370 | } |
| 2371 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2372 | static int dec_move_mp(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2373 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2374 | TCGv t[2]; |
| 2375 | int memsize = memsize_zz(dc); |
| 2376 | int insn_len = 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2377 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2378 | LOG_DIS("move.%c [$r%u%s, $p%u\n", |
| 2379 | memsize_char(memsize), |
| 2380 | dc->op1, |
| 2381 | dc->postinc ? "+]" : "]", |
| 2382 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2383 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2384 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2385 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2386 | cris_cc_mask(dc, 0); |
| 2387 | if (dc->op2 == PR_CCS) { |
| 2388 | cris_evaluate_flags(dc); |
| 2389 | if (dc->tb_flags & U_FLAG) { |
| 2390 | /* User space is not allowed to touch all flags. */ |
| 2391 | tcg_gen_andi_tl(t[1], t[1], 0x39f); |
| 2392 | tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f); |
| 2393 | tcg_gen_or_tl(t[1], t[0], t[1]); |
| 2394 | } |
| 2395 | } |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2396 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2397 | t_gen_mov_preg_TN(dc, dc->op2, t[1]); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2398 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2399 | do_postinc(dc, memsize); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2400 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2401 | } |
| 2402 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2403 | static int dec_move_pm(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2404 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2405 | TCGv t0; |
| 2406 | int memsize; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2407 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2408 | memsize = preg_sizes[dc->op2]; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2409 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2410 | LOG_DIS("move.%c $p%u, [$r%u%s\n", |
| 2411 | memsize_char(memsize), |
| 2412 | dc->op2, dc->op1, dc->postinc ? "+]" : "]"); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2413 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2414 | /* prepare store. Address in T0, value in T1. */ |
| 2415 | if (dc->op2 == PR_CCS) { |
| 2416 | cris_evaluate_flags(dc); |
| 2417 | } |
| 2418 | t0 = tcg_temp_new(); |
| 2419 | t_gen_mov_TN_preg(t0, dc->op2); |
| 2420 | cris_flush_cc_state(dc); |
| 2421 | gen_store(dc, cpu_R[dc->op1], t0, memsize); |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 2422 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2423 | cris_cc_mask(dc, 0); |
| 2424 | if (dc->postinc) { |
| 2425 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize); |
| 2426 | } |
| 2427 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2428 | } |
| 2429 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2430 | static int dec_movem_mr(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2431 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2432 | TCGv_i64 tmp[16]; |
| 2433 | TCGv tmp32; |
| 2434 | TCGv addr; |
| 2435 | int i; |
| 2436 | int nr = dc->op2 + 1; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2437 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2438 | LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1, |
| 2439 | dc->postinc ? "+]" : "]", dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2440 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2441 | addr = tcg_temp_new(); |
| 2442 | /* There are probably better ways of doing this. */ |
| 2443 | cris_flush_cc_state(dc); |
| 2444 | for (i = 0; i < (nr >> 1); i++) { |
| 2445 | tmp[i] = tcg_temp_new_i64(); |
| 2446 | tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); |
| 2447 | gen_load64(dc, tmp[i], addr); |
| 2448 | } |
| 2449 | if (nr & 1) { |
| 2450 | tmp32 = tcg_temp_new_i32(); |
| 2451 | tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); |
| 2452 | gen_load(dc, tmp32, addr, 4, 0); |
| 2453 | } else { |
Richard Henderson | f764718 | 2017-11-02 12:47:37 +0100 | [diff] [blame] | 2454 | tmp32 = NULL; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2455 | } |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 2456 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2457 | for (i = 0; i < (nr >> 1); i++) { |
Richard Henderson | ecc7b3a | 2015-07-24 11:49:53 -0700 | [diff] [blame] | 2458 | tcg_gen_extrl_i64_i32(cpu_R[i * 2], tmp[i]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2459 | tcg_gen_shri_i64(tmp[i], tmp[i], 32); |
Richard Henderson | ecc7b3a | 2015-07-24 11:49:53 -0700 | [diff] [blame] | 2460 | tcg_gen_extrl_i64_i32(cpu_R[i * 2 + 1], tmp[i]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2461 | } |
| 2462 | if (nr & 1) { |
| 2463 | tcg_gen_mov_tl(cpu_R[dc->op2], tmp32); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2464 | } |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 2465 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2466 | /* writeback the updated pointer value. */ |
| 2467 | if (dc->postinc) { |
| 2468 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4); |
| 2469 | } |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2470 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2471 | /* gen_load might want to evaluate the previous insns flags. */ |
| 2472 | cris_cc_mask(dc, 0); |
| 2473 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2474 | } |
| 2475 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2476 | static int dec_movem_rm(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2477 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2478 | TCGv tmp; |
| 2479 | TCGv addr; |
| 2480 | int i; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2481 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2482 | LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1, |
| 2483 | dc->postinc ? "+]" : "]"); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2484 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2485 | cris_flush_cc_state(dc); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 2486 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2487 | tmp = tcg_temp_new(); |
| 2488 | addr = tcg_temp_new(); |
| 2489 | tcg_gen_movi_tl(tmp, 4); |
| 2490 | tcg_gen_mov_tl(addr, cpu_R[dc->op1]); |
| 2491 | for (i = 0; i <= dc->op2; i++) { |
| 2492 | /* Displace addr. */ |
| 2493 | /* Perform the store. */ |
| 2494 | gen_store(dc, addr, cpu_R[i], 4); |
| 2495 | tcg_gen_add_tl(addr, addr, tmp); |
| 2496 | } |
| 2497 | if (dc->postinc) { |
| 2498 | tcg_gen_mov_tl(cpu_R[dc->op1], addr); |
| 2499 | } |
| 2500 | cris_cc_mask(dc, 0); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2501 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2502 | } |
| 2503 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2504 | static int dec_move_rm(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2505 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2506 | int memsize; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2507 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2508 | memsize = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2509 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2510 | LOG_DIS("move.%c $r%u, [$r%u]\n", |
| 2511 | memsize_char(memsize), dc->op2, dc->op1); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2512 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2513 | /* prepare store. */ |
| 2514 | cris_flush_cc_state(dc); |
| 2515 | gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize); |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 2516 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2517 | if (dc->postinc) { |
| 2518 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize); |
| 2519 | } |
| 2520 | cris_cc_mask(dc, 0); |
| 2521 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2522 | } |
| 2523 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2524 | static int dec_lapcq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2525 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2526 | LOG_DIS("lapcq %x, $r%u\n", |
| 2527 | dc->pc + dc->op1*2, dc->op2); |
| 2528 | cris_cc_mask(dc, 0); |
| 2529 | tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2); |
| 2530 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2531 | } |
| 2532 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2533 | static int dec_lapc_im(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2534 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2535 | unsigned int rd; |
| 2536 | int32_t imm; |
| 2537 | int32_t pc; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2538 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2539 | rd = dc->op2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2540 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2541 | cris_cc_mask(dc, 0); |
| 2542 | imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
| 2543 | LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2544 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2545 | pc = dc->pc; |
| 2546 | pc += imm; |
| 2547 | tcg_gen_movi_tl(cpu_R[rd], pc); |
| 2548 | return 6; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2549 | } |
| 2550 | |
| 2551 | /* Jump to special reg. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2552 | static int dec_jump_p(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2553 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2554 | LOG_DIS("jump $p%u\n", dc->op2); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2555 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2556 | if (dc->op2 == PR_CCS) { |
| 2557 | cris_evaluate_flags(dc); |
| 2558 | } |
| 2559 | t_gen_mov_TN_preg(env_btarget, dc->op2); |
| 2560 | /* rete will often have low bit set to indicate delayslot. */ |
| 2561 | tcg_gen_andi_tl(env_btarget, env_btarget, ~1); |
| 2562 | cris_cc_mask(dc, 0); |
| 2563 | cris_prepare_jmp(dc, JMP_INDIRECT); |
| 2564 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2565 | } |
| 2566 | |
| 2567 | /* Jump and save. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2568 | static int dec_jas_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2569 | { |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2570 | TCGv c; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2571 | LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2); |
| 2572 | cris_cc_mask(dc, 0); |
| 2573 | /* Store the return address in Pd. */ |
| 2574 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); |
| 2575 | if (dc->op2 > 15) { |
| 2576 | abort(); |
| 2577 | } |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 2578 | c = tcg_constant_tl(dc->pc + 4); |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2579 | t_gen_mov_preg_TN(dc, dc->op2, c); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2580 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2581 | cris_prepare_jmp(dc, JMP_INDIRECT); |
| 2582 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2583 | } |
| 2584 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2585 | static int dec_jas_im(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2586 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2587 | uint32_t imm; |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2588 | TCGv c; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2589 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2590 | imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2591 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2592 | LOG_DIS("jas 0x%x\n", imm); |
| 2593 | cris_cc_mask(dc, 0); |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 2594 | c = tcg_constant_tl(dc->pc + 8); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2595 | /* Store the return address in Pd. */ |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2596 | t_gen_mov_preg_TN(dc, dc->op2, c); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 2597 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2598 | dc->jmp_pc = imm; |
| 2599 | cris_prepare_jmp(dc, JMP_DIRECT); |
| 2600 | return 6; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2601 | } |
| 2602 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2603 | static int dec_jasc_im(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2604 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2605 | uint32_t imm; |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2606 | TCGv c; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2607 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2608 | imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2609 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2610 | LOG_DIS("jasc 0x%x\n", imm); |
| 2611 | cris_cc_mask(dc, 0); |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 2612 | c = tcg_constant_tl(dc->pc + 8 + 4); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2613 | /* Store the return address in Pd. */ |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2614 | t_gen_mov_preg_TN(dc, dc->op2, c); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 2615 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2616 | dc->jmp_pc = imm; |
| 2617 | cris_prepare_jmp(dc, JMP_DIRECT); |
| 2618 | return 6; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2619 | } |
| 2620 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2621 | static int dec_jasc_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2622 | { |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2623 | TCGv c; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2624 | LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2); |
| 2625 | cris_cc_mask(dc, 0); |
| 2626 | /* Store the return address in Pd. */ |
| 2627 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 2628 | c = tcg_constant_tl(dc->pc + 4 + 4); |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2629 | t_gen_mov_preg_TN(dc, dc->op2, c); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2630 | cris_prepare_jmp(dc, JMP_INDIRECT); |
| 2631 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2632 | } |
| 2633 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2634 | static int dec_bcc_im(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2635 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2636 | int32_t offset; |
| 2637 | uint32_t cond = dc->op2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2638 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2639 | offset = cris_fetch(env, dc, dc->pc + 2, 2, 1); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2640 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2641 | LOG_DIS("b%s %d pc=%x dst=%x\n", |
| 2642 | cc_name(cond), offset, |
| 2643 | dc->pc, dc->pc + offset); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2644 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2645 | cris_cc_mask(dc, 0); |
| 2646 | /* op2 holds the condition-code. */ |
| 2647 | cris_prepare_cc_branch(dc, offset, cond); |
| 2648 | return 4; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2649 | } |
| 2650 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2651 | static int dec_bas_im(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2652 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2653 | int32_t simm; |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2654 | TCGv c; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2655 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2656 | simm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2657 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2658 | LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2); |
| 2659 | cris_cc_mask(dc, 0); |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 2660 | c = tcg_constant_tl(dc->pc + 8); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2661 | /* Store the return address in Pd. */ |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2662 | t_gen_mov_preg_TN(dc, dc->op2, c); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2663 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2664 | dc->jmp_pc = dc->pc + simm; |
| 2665 | cris_prepare_jmp(dc, JMP_DIRECT); |
| 2666 | return 6; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2667 | } |
| 2668 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2669 | static int dec_basc_im(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2670 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2671 | int32_t simm; |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2672 | TCGv c; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2673 | simm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2674 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2675 | LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2); |
| 2676 | cris_cc_mask(dc, 0); |
Richard Henderson | ab554f1 | 2023-02-25 12:44:04 -1000 | [diff] [blame] | 2677 | c = tcg_constant_tl(dc->pc + 12); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2678 | /* Store the return address in Pd. */ |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2679 | t_gen_mov_preg_TN(dc, dc->op2, c); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 2680 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2681 | dc->jmp_pc = dc->pc + simm; |
| 2682 | cris_prepare_jmp(dc, JMP_DIRECT); |
| 2683 | return 6; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2684 | } |
| 2685 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2686 | static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2687 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2688 | cris_cc_mask(dc, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2689 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2690 | if (dc->op2 == 15) { |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 2691 | tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 2692 | -offsetof(CRISCPU, env) + offsetof(CPUState, halted)); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2693 | tcg_gen_movi_tl(env_pc, dc->pc + 2); |
| 2694 | t_gen_raise_exception(EXCP_HLT); |
Richard Henderson | 1dd09c4 | 2021-06-19 20:24:37 -0700 | [diff] [blame] | 2695 | dc->base.is_jmp = DISAS_NORETURN; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2696 | return 2; |
| 2697 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2698 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2699 | switch (dc->op2 & 7) { |
| 2700 | case 2: |
| 2701 | /* rfe. */ |
| 2702 | LOG_DIS("rfe\n"); |
| 2703 | cris_evaluate_flags(dc); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 2704 | gen_helper_rfe(tcg_env); |
Richard Henderson | 67f69c4 | 2021-06-19 19:17:40 -0700 | [diff] [blame] | 2705 | dc->base.is_jmp = DISAS_UPDATE; |
Richard Henderson | 9e9f5ba | 2021-06-23 07:08:40 -0700 | [diff] [blame] | 2706 | dc->cpustate_changed = true; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2707 | break; |
| 2708 | case 5: |
| 2709 | /* rfn. */ |
| 2710 | LOG_DIS("rfn\n"); |
| 2711 | cris_evaluate_flags(dc); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 2712 | gen_helper_rfn(tcg_env); |
Richard Henderson | 67f69c4 | 2021-06-19 19:17:40 -0700 | [diff] [blame] | 2713 | dc->base.is_jmp = DISAS_UPDATE; |
Richard Henderson | 9e9f5ba | 2021-06-23 07:08:40 -0700 | [diff] [blame] | 2714 | dc->cpustate_changed = true; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2715 | break; |
| 2716 | case 6: |
| 2717 | LOG_DIS("break %d\n", dc->op1); |
| 2718 | cris_evaluate_flags(dc); |
| 2719 | /* break. */ |
| 2720 | tcg_gen_movi_tl(env_pc, dc->pc + 2); |
edgar_igl | a1aebcb | 2008-10-07 22:48:41 +0000 | [diff] [blame] | 2721 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2722 | /* Breaks start at 16 in the exception vector. */ |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2723 | t_gen_movi_env_TN(trap_vector, dc->op1 + 16); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2724 | t_gen_raise_exception(EXCP_BREAK); |
Richard Henderson | 1dd09c4 | 2021-06-19 20:24:37 -0700 | [diff] [blame] | 2725 | dc->base.is_jmp = DISAS_NORETURN; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2726 | break; |
| 2727 | default: |
| 2728 | printf("op2=%x\n", dc->op2); |
| 2729 | BUG(); |
| 2730 | break; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2731 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2732 | } |
| 2733 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2734 | } |
| 2735 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2736 | static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc) |
edgar_igl | 5d4a534 | 2008-02-25 09:58:22 +0000 | [diff] [blame] | 2737 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2738 | return 2; |
edgar_igl | 5d4a534 | 2008-02-25 09:58:22 +0000 | [diff] [blame] | 2739 | } |
| 2740 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2741 | static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc) |
edgar_igl | 5d4a534 | 2008-02-25 09:58:22 +0000 | [diff] [blame] | 2742 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2743 | return 2; |
edgar_igl | 5d4a534 | 2008-02-25 09:58:22 +0000 | [diff] [blame] | 2744 | } |
| 2745 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2746 | static int dec_null(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2747 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2748 | printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n", |
| 2749 | dc->pc, dc->opcode, dc->op1, dc->op2); |
| 2750 | fflush(NULL); |
| 2751 | BUG(); |
| 2752 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2753 | } |
| 2754 | |
Richard Henderson | 5899ce6 | 2021-06-19 20:57:31 -0700 | [diff] [blame] | 2755 | static const struct decoder_info { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2756 | struct { |
| 2757 | uint32_t bits; |
| 2758 | uint32_t mask; |
| 2759 | }; |
| 2760 | int (*dec)(CPUCRISState *env, DisasContext *dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2761 | } decinfo[] = { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2762 | /* Order matters here. */ |
| 2763 | {DEC_MOVEQ, dec_moveq}, |
| 2764 | {DEC_BTSTQ, dec_btstq}, |
| 2765 | {DEC_CMPQ, dec_cmpq}, |
| 2766 | {DEC_ADDOQ, dec_addoq}, |
| 2767 | {DEC_ADDQ, dec_addq}, |
| 2768 | {DEC_SUBQ, dec_subq}, |
| 2769 | {DEC_ANDQ, dec_andq}, |
| 2770 | {DEC_ORQ, dec_orq}, |
| 2771 | {DEC_ASRQ, dec_asrq}, |
| 2772 | {DEC_LSLQ, dec_lslq}, |
| 2773 | {DEC_LSRQ, dec_lsrq}, |
| 2774 | {DEC_BCCQ, dec_bccq}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2775 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2776 | {DEC_BCC_IM, dec_bcc_im}, |
| 2777 | {DEC_JAS_IM, dec_jas_im}, |
| 2778 | {DEC_JAS_R, dec_jas_r}, |
| 2779 | {DEC_JASC_IM, dec_jasc_im}, |
| 2780 | {DEC_JASC_R, dec_jasc_r}, |
| 2781 | {DEC_BAS_IM, dec_bas_im}, |
| 2782 | {DEC_BASC_IM, dec_basc_im}, |
| 2783 | {DEC_JUMP_P, dec_jump_p}, |
| 2784 | {DEC_LAPC_IM, dec_lapc_im}, |
| 2785 | {DEC_LAPCQ, dec_lapcq}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2786 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2787 | {DEC_RFE_ETC, dec_rfe_etc}, |
| 2788 | {DEC_ADDC_MR, dec_addc_mr}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2789 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2790 | {DEC_MOVE_MP, dec_move_mp}, |
| 2791 | {DEC_MOVE_PM, dec_move_pm}, |
| 2792 | {DEC_MOVEM_MR, dec_movem_mr}, |
| 2793 | {DEC_MOVEM_RM, dec_movem_rm}, |
| 2794 | {DEC_MOVE_PR, dec_move_pr}, |
| 2795 | {DEC_SCC_R, dec_scc_r}, |
| 2796 | {DEC_SETF, dec_setclrf}, |
| 2797 | {DEC_CLEARF, dec_setclrf}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2798 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2799 | {DEC_MOVE_SR, dec_move_sr}, |
| 2800 | {DEC_MOVE_RP, dec_move_rp}, |
| 2801 | {DEC_SWAP_R, dec_swap_r}, |
| 2802 | {DEC_ABS_R, dec_abs_r}, |
| 2803 | {DEC_LZ_R, dec_lz_r}, |
| 2804 | {DEC_MOVE_RS, dec_move_rs}, |
| 2805 | {DEC_BTST_R, dec_btst_r}, |
| 2806 | {DEC_ADDC_R, dec_addc_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2807 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2808 | {DEC_DSTEP_R, dec_dstep_r}, |
| 2809 | {DEC_XOR_R, dec_xor_r}, |
| 2810 | {DEC_MCP_R, dec_mcp_r}, |
| 2811 | {DEC_CMP_R, dec_cmp_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2812 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2813 | {DEC_ADDI_R, dec_addi_r}, |
| 2814 | {DEC_ADDI_ACR, dec_addi_acr}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2815 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2816 | {DEC_ADD_R, dec_add_r}, |
| 2817 | {DEC_SUB_R, dec_sub_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2818 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2819 | {DEC_ADDU_R, dec_addu_r}, |
| 2820 | {DEC_ADDS_R, dec_adds_r}, |
| 2821 | {DEC_SUBU_R, dec_subu_r}, |
| 2822 | {DEC_SUBS_R, dec_subs_r}, |
| 2823 | {DEC_LSL_R, dec_lsl_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2824 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2825 | {DEC_AND_R, dec_and_r}, |
| 2826 | {DEC_OR_R, dec_or_r}, |
| 2827 | {DEC_BOUND_R, dec_bound_r}, |
| 2828 | {DEC_ASR_R, dec_asr_r}, |
| 2829 | {DEC_LSR_R, dec_lsr_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2830 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2831 | {DEC_MOVU_R, dec_movu_r}, |
| 2832 | {DEC_MOVS_R, dec_movs_r}, |
| 2833 | {DEC_NEG_R, dec_neg_r}, |
| 2834 | {DEC_MOVE_R, dec_move_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2835 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2836 | {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m}, |
| 2837 | {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2838 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2839 | {DEC_MULS_R, dec_muls_r}, |
| 2840 | {DEC_MULU_R, dec_mulu_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2841 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2842 | {DEC_ADDU_M, dec_addu_m}, |
| 2843 | {DEC_ADDS_M, dec_adds_m}, |
| 2844 | {DEC_SUBU_M, dec_subu_m}, |
| 2845 | {DEC_SUBS_M, dec_subs_m}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2846 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2847 | {DEC_CMPU_M, dec_cmpu_m}, |
| 2848 | {DEC_CMPS_M, dec_cmps_m}, |
| 2849 | {DEC_MOVU_M, dec_movu_m}, |
| 2850 | {DEC_MOVS_M, dec_movs_m}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2851 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2852 | {DEC_CMP_M, dec_cmp_m}, |
| 2853 | {DEC_ADDO_M, dec_addo_m}, |
| 2854 | {DEC_BOUND_M, dec_bound_m}, |
| 2855 | {DEC_ADD_M, dec_add_m}, |
| 2856 | {DEC_SUB_M, dec_sub_m}, |
| 2857 | {DEC_AND_M, dec_and_m}, |
| 2858 | {DEC_OR_M, dec_or_m}, |
| 2859 | {DEC_MOVE_RM, dec_move_rm}, |
| 2860 | {DEC_TEST_M, dec_test_m}, |
| 2861 | {DEC_MOVE_MR, dec_move_mr}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2862 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2863 | {{0, 0}, dec_null} |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2864 | }; |
| 2865 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2866 | static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2867 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2868 | int insn_len = 2; |
| 2869 | int i; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2870 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2871 | /* Load a halfword onto the instruction register. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2872 | dc->ir = cris_fetch(env, dc, dc->pc, 2, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2873 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2874 | /* Now decode it. */ |
| 2875 | dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11); |
| 2876 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3); |
| 2877 | dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15); |
| 2878 | dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4); |
| 2879 | dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5); |
| 2880 | dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2881 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2882 | /* Large switch for all insns. */ |
| 2883 | for (i = 0; i < ARRAY_SIZE(decinfo); i++) { |
| 2884 | if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { |
| 2885 | insn_len = decinfo[i].dec(env, dc); |
| 2886 | break; |
| 2887 | } |
| 2888 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2889 | |
edgar_igl | dd20fcd | 2008-10-08 08:28:16 +0000 | [diff] [blame] | 2890 | #if !defined(CONFIG_USER_ONLY) |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2891 | /* Single-stepping ? */ |
| 2892 | if (dc->tb_flags & S_FLAG) { |
Richard Henderson | 42a268c | 2015-02-13 12:51:55 -0800 | [diff] [blame] | 2893 | TCGLabel *l1 = gen_new_label(); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2894 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1); |
| 2895 | /* We treat SPC as a break with an odd trap vector. */ |
| 2896 | cris_evaluate_flags(dc); |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 2897 | t_gen_movi_env_TN(trap_vector, 3); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2898 | tcg_gen_movi_tl(env_pc, dc->pc + insn_len); |
| 2899 | tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len); |
| 2900 | t_gen_raise_exception(EXCP_BREAK); |
| 2901 | gen_set_label(l1); |
| 2902 | } |
edgar_igl | a1aebcb | 2008-10-07 22:48:41 +0000 | [diff] [blame] | 2903 | #endif |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2904 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2905 | } |
| 2906 | |
Paolo Bonzini | 139c183 | 2020-02-04 12:41:01 +0100 | [diff] [blame] | 2907 | #include "translate_v10.c.inc" |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 2908 | |
| 2909 | /* |
| 2910 | * Delay slots on QEMU/CRIS. |
| 2911 | * |
| 2912 | * If an exception hits on a delayslot, the core will let ERP (the Exception |
| 2913 | * Return Pointer) point to the branch (the previous) insn and set the lsb to |
| 2914 | * to give SW a hint that the exception actually hit on the dslot. |
| 2915 | * |
| 2916 | * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by |
| 2917 | * the core and any jmp to an odd addresses will mask off that lsb. It is |
| 2918 | * simply there to let sw know there was an exception on a dslot. |
| 2919 | * |
| 2920 | * When the software returns from an exception, the branch will re-execute. |
| 2921 | * On QEMU care needs to be taken when a branch+delayslot sequence is broken |
Stefan Weil | cb8d4c8 | 2016-03-23 15:59:57 +0100 | [diff] [blame] | 2922 | * and the branch and delayslot don't share pages. |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 2923 | * |
Michael Tokarev | 8b81968 | 2023-07-14 14:23:51 +0300 | [diff] [blame] | 2924 | * The TB containing the branch insn will set up env->btarget and evaluate |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 2925 | * env->btaken. When the translation loop exits we will note that the branch |
| 2926 | * sequence is broken and let env->dslot be the size of the branch insn (those |
| 2927 | * vary in length). |
| 2928 | * |
Michael Tokarev | 8b81968 | 2023-07-14 14:23:51 +0300 | [diff] [blame] | 2929 | * The TB containing the delayslot will have the PC of its real insn (i.e no lsb |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 2930 | * set). It will also expect to have env->dslot setup with the size of the |
| 2931 | * delay slot so that env->pc - env->dslot point to the branch insn. This TB |
| 2932 | * will execute the dslot and take the branch, either to btarget or just one |
| 2933 | * insn ahead. |
| 2934 | * |
| 2935 | * When exceptions occur, we check for env->dslot in do_interrupt to detect |
| 2936 | * broken branch sequences and setup $erp accordingly (i.e let it point to the |
| 2937 | * branch and set lsb). Then env->dslot gets cleared so that the exception |
| 2938 | * handler can enter. When returning from exceptions (jump $erp) the lsb gets |
| 2939 | * masked off and we will reexecute the branch insn. |
| 2940 | * |
| 2941 | */ |
| 2942 | |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 2943 | static void cris_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2944 | { |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 2945 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
Richard Henderson | b77af26 | 2023-09-13 17:22:49 -0700 | [diff] [blame] | 2946 | CPUCRISState *env = cpu_env(cs); |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 2947 | uint32_t tb_flags = dc->base.tb->flags; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2948 | uint32_t pc_start; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2949 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2950 | if (env->pregs[PR_VR] == 32) { |
| 2951 | dc->decoder = crisv32_decoder; |
| 2952 | dc->clear_locked_irq = 0; |
| 2953 | } else { |
| 2954 | dc->decoder = crisv10_decoder; |
| 2955 | dc->clear_locked_irq = 1; |
| 2956 | } |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 2957 | |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 2958 | /* |
| 2959 | * Odd PC indicates that branch is rexecuting due to exception in the |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2960 | * delayslot, like in real hw. |
| 2961 | */ |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 2962 | pc_start = dc->base.pc_first & ~1; |
Richard Henderson | 67f69c4 | 2021-06-19 19:17:40 -0700 | [diff] [blame] | 2963 | dc->base.pc_first = pc_start; |
| 2964 | dc->base.pc_next = pc_start; |
Richard Henderson | 67f69c4 | 2021-06-19 19:17:40 -0700 | [diff] [blame] | 2965 | |
| 2966 | dc->cpu = env_archcpu(env); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2967 | dc->ppc = pc_start; |
| 2968 | dc->pc = pc_start; |
Richard Henderson | 3b91614 | 2024-01-29 20:35:06 +1000 | [diff] [blame] | 2969 | dc->mem_index = cpu_mmu_index(cs, false); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2970 | dc->flags_uptodate = 1; |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 2971 | dc->flags_x = tb_flags & X_FLAG; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2972 | dc->cc_x_uptodate = 0; |
| 2973 | dc->cc_mask = 0; |
| 2974 | dc->update_cc = 0; |
| 2975 | dc->clear_prefix = 0; |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 2976 | dc->cpustate_changed = 0; |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 2977 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2978 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
| 2979 | dc->cc_size_uptodate = -1; |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2980 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2981 | /* Decode TB flags. */ |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 2982 | dc->tb_flags = tb_flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG | PFIX_FLAG); |
| 2983 | dc->delayed_branch = !!(tb_flags & 7); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2984 | if (dc->delayed_branch) { |
| 2985 | dc->jmp = JMP_INDIRECT; |
| 2986 | } else { |
| 2987 | dc->jmp = JMP_NOJMP; |
| 2988 | } |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 2989 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 2990 | |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 2991 | static void cris_tr_tb_start(DisasContextBase *db, CPUState *cpu) |
| 2992 | { |
| 2993 | } |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2994 | |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 2995 | static void cris_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
| 2996 | { |
| 2997 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 2998 | |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 2999 | tcg_gen_insn_start(dc->delayed_branch == 1 ? dc->ppc | 1 : dc->pc); |
| 3000 | } |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 3001 | |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3002 | static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) |
| 3003 | { |
| 3004 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3005 | unsigned int insn_len; |
| 3006 | |
| 3007 | /* Pretty disas. */ |
| 3008 | LOG_DIS("%8.8x:\t", dc->pc); |
| 3009 | |
| 3010 | dc->clear_x = 1; |
| 3011 | |
Philippe Mathieu-Daudé | 2df4ab2 | 2024-01-29 17:44:52 +0100 | [diff] [blame] | 3012 | insn_len = dc->decoder(cpu_env(cs), dc); |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3013 | dc->ppc = dc->pc; |
| 3014 | dc->pc += insn_len; |
| 3015 | dc->base.pc_next += insn_len; |
| 3016 | |
| 3017 | if (dc->base.is_jmp == DISAS_NORETURN) { |
| 3018 | return; |
| 3019 | } |
| 3020 | |
| 3021 | if (dc->clear_x) { |
| 3022 | cris_clear_x_flag(dc); |
| 3023 | } |
| 3024 | |
| 3025 | /* |
Richard Henderson | 3173715 | 2021-06-20 13:43:35 -0700 | [diff] [blame] | 3026 | * All branches are delayed branches, handled immediately below. |
| 3027 | * We don't expect to see odd combinations of exit conditions. |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3028 | */ |
Richard Henderson | 3173715 | 2021-06-20 13:43:35 -0700 | [diff] [blame] | 3029 | assert(dc->base.is_jmp == DISAS_NEXT || dc->cpustate_changed); |
| 3030 | |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3031 | if (dc->delayed_branch && --dc->delayed_branch == 0) { |
Richard Henderson | 3173715 | 2021-06-20 13:43:35 -0700 | [diff] [blame] | 3032 | dc->base.is_jmp = DISAS_DBRANCH; |
| 3033 | return; |
| 3034 | } |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3035 | |
Richard Henderson | 3173715 | 2021-06-20 13:43:35 -0700 | [diff] [blame] | 3036 | if (dc->base.is_jmp != DISAS_NEXT) { |
| 3037 | return; |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3038 | } |
Richard Henderson | b933066 | 2015-09-17 15:58:10 -0700 | [diff] [blame] | 3039 | |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3040 | /* Force an update if the per-tb cpu state has changed. */ |
Richard Henderson | 3173715 | 2021-06-20 13:43:35 -0700 | [diff] [blame] | 3041 | if (dc->cpustate_changed) { |
Richard Henderson | c967475 | 2021-06-22 07:50:12 -0700 | [diff] [blame] | 3042 | dc->base.is_jmp = DISAS_UPDATE_NEXT; |
| 3043 | return; |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3044 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3045 | |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3046 | /* |
| 3047 | * FIXME: Only the first insn in the TB should cross a page boundary. |
| 3048 | * If we can detect the length of the next insn easily, we should. |
| 3049 | * In the meantime, simply stop when we do cross. |
| 3050 | */ |
Richard Henderson | 3173715 | 2021-06-20 13:43:35 -0700 | [diff] [blame] | 3051 | if ((dc->pc ^ dc->base.pc_first) & TARGET_PAGE_MASK) { |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3052 | dc->base.is_jmp = DISAS_TOO_MANY; |
| 3053 | } |
| 3054 | } |
edgar_igl | 28de16d | 2008-09-22 20:51:28 +0000 | [diff] [blame] | 3055 | |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3056 | static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) |
| 3057 | { |
| 3058 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
| 3059 | DisasJumpType is_jmp = dc->base.is_jmp; |
| 3060 | target_ulong npc = dc->pc; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3061 | |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3062 | if (is_jmp == DISAS_NORETURN) { |
| 3063 | /* If we have a broken branch+delayslot sequence, it's too late. */ |
| 3064 | assert(dc->delayed_branch != 1); |
| 3065 | return; |
| 3066 | } |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 3067 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3068 | if (dc->clear_locked_irq) { |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 3069 | t_gen_movi_env_TN(locked_irq, 0); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3070 | } |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 3071 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3072 | /* Broken branch+delayslot sequence. */ |
| 3073 | if (dc->delayed_branch == 1) { |
| 3074 | /* Set env->dslot to the size of the branch insn. */ |
Stefan Sandstrom | fd52dee | 2021-02-19 13:44:16 +0100 | [diff] [blame] | 3075 | t_gen_movi_env_TN(dslot, dc->pc - dc->ppc); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3076 | cris_store_direct_jmp(dc); |
| 3077 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3078 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3079 | cris_evaluate_flags(dc); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 3080 | |
Richard Henderson | 3173715 | 2021-06-20 13:43:35 -0700 | [diff] [blame] | 3081 | /* Evaluate delayed branch destination and fold to another is_jmp case. */ |
| 3082 | if (is_jmp == DISAS_DBRANCH) { |
| 3083 | if (dc->base.tb->flags & 7) { |
| 3084 | t_gen_movi_env_TN(dslot, 0); |
| 3085 | } |
| 3086 | |
| 3087 | switch (dc->jmp) { |
| 3088 | case JMP_DIRECT: |
| 3089 | npc = dc->jmp_pc; |
| 3090 | is_jmp = dc->cpustate_changed ? DISAS_UPDATE_NEXT : DISAS_TOO_MANY; |
| 3091 | break; |
| 3092 | |
| 3093 | case JMP_DIRECT_CC: |
| 3094 | /* |
| 3095 | * Use a conditional branch if either taken or not-taken path |
| 3096 | * can use goto_tb. If neither can, then treat it as indirect. |
| 3097 | */ |
Richard Henderson | ca92d7f | 2021-06-20 16:05:53 -0700 | [diff] [blame] | 3098 | if (likely(!dc->cpustate_changed) |
Richard Henderson | 3173715 | 2021-06-20 13:43:35 -0700 | [diff] [blame] | 3099 | && (use_goto_tb(dc, dc->jmp_pc) || use_goto_tb(dc, npc))) { |
| 3100 | TCGLabel *not_taken = gen_new_label(); |
| 3101 | |
| 3102 | tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, not_taken); |
| 3103 | gen_goto_tb(dc, 1, dc->jmp_pc); |
| 3104 | gen_set_label(not_taken); |
| 3105 | |
| 3106 | /* not-taken case handled below. */ |
| 3107 | is_jmp = DISAS_TOO_MANY; |
| 3108 | break; |
| 3109 | } |
| 3110 | tcg_gen_movi_tl(env_btarget, dc->jmp_pc); |
| 3111 | /* fall through */ |
| 3112 | |
| 3113 | case JMP_INDIRECT: |
Richard Henderson | 3a1a80c | 2021-06-20 14:06:01 -0700 | [diff] [blame] | 3114 | tcg_gen_movcond_tl(TCG_COND_NE, env_pc, |
| 3115 | env_btaken, tcg_constant_tl(0), |
| 3116 | env_btarget, tcg_constant_tl(npc)); |
Richard Henderson | 3173715 | 2021-06-20 13:43:35 -0700 | [diff] [blame] | 3117 | is_jmp = dc->cpustate_changed ? DISAS_UPDATE : DISAS_JUMP; |
Richard Henderson | 3a1a80c | 2021-06-20 14:06:01 -0700 | [diff] [blame] | 3118 | |
| 3119 | /* |
| 3120 | * We have now consumed btaken and btarget. Hint to the |
| 3121 | * tcg compiler that the writeback to env may be dropped. |
| 3122 | */ |
| 3123 | tcg_gen_discard_tl(env_btaken); |
| 3124 | tcg_gen_discard_tl(env_btarget); |
Richard Henderson | 3173715 | 2021-06-20 13:43:35 -0700 | [diff] [blame] | 3125 | break; |
| 3126 | |
| 3127 | default: |
| 3128 | g_assert_not_reached(); |
| 3129 | } |
| 3130 | } |
| 3131 | |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3132 | switch (is_jmp) { |
| 3133 | case DISAS_TOO_MANY: |
| 3134 | gen_goto_tb(dc, 0, npc); |
| 3135 | break; |
Richard Henderson | c967475 | 2021-06-22 07:50:12 -0700 | [diff] [blame] | 3136 | case DISAS_UPDATE_NEXT: |
| 3137 | tcg_gen_movi_tl(env_pc, npc); |
| 3138 | /* fall through */ |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3139 | case DISAS_JUMP: |
Richard Henderson | e0a4620 | 2021-06-20 13:49:17 -0700 | [diff] [blame] | 3140 | tcg_gen_lookup_and_goto_ptr(); |
| 3141 | break; |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3142 | case DISAS_UPDATE: |
Michael Tokarev | 8b81968 | 2023-07-14 14:23:51 +0300 | [diff] [blame] | 3143 | /* Indicate that interrupts must be re-evaluated before the next TB. */ |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3144 | tcg_gen_exit_tb(NULL, 0); |
| 3145 | break; |
| 3146 | default: |
| 3147 | g_assert_not_reached(); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3148 | } |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3149 | } |
| 3150 | |
Richard Henderson | 8eb806a | 2022-04-17 11:29:52 -0700 | [diff] [blame] | 3151 | static void cris_tr_disas_log(const DisasContextBase *dcbase, |
| 3152 | CPUState *cpu, FILE *logfile) |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3153 | { |
| 3154 | if (!DISAS_CRIS) { |
Richard Henderson | 8eb806a | 2022-04-17 11:29:52 -0700 | [diff] [blame] | 3155 | fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); |
| 3156 | target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3157 | } |
| 3158 | } |
| 3159 | |
| 3160 | static const TranslatorOps cris_tr_ops = { |
| 3161 | .init_disas_context = cris_tr_init_disas_context, |
| 3162 | .tb_start = cris_tr_tb_start, |
| 3163 | .insn_start = cris_tr_insn_start, |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3164 | .translate_insn = cris_tr_translate_insn, |
| 3165 | .tb_stop = cris_tr_tb_stop, |
| 3166 | .disas_log = cris_tr_disas_log, |
| 3167 | }; |
| 3168 | |
Richard Henderson | 597f9b2 | 2023-01-28 15:19:22 -1000 | [diff] [blame] | 3169 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, |
Anton Johansson | 32f0c39 | 2024-01-19 15:39:58 +0100 | [diff] [blame] | 3170 | vaddr pc, void *host_pc) |
Richard Henderson | 330ca14 | 2021-06-19 20:49:26 -0700 | [diff] [blame] | 3171 | { |
| 3172 | DisasContext dc; |
Richard Henderson | 306c872 | 2022-08-11 13:48:03 -0700 | [diff] [blame] | 3173 | translator_loop(cs, tb, max_insns, pc, host_pc, &cris_tr_ops, &dc.base); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3174 | } |
| 3175 | |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 3176 | void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3177 | { |
Philippe Mathieu-Daudé | 2df4ab2 | 2024-01-29 17:44:52 +0100 | [diff] [blame] | 3178 | CPUCRISState *env = cpu_env(cs); |
Richard Henderson | 5899ce6 | 2021-06-19 20:57:31 -0700 | [diff] [blame] | 3179 | const char * const *regnames; |
| 3180 | const char * const *pregnames; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3181 | int i; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3182 | |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 3183 | if (!env) { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3184 | return; |
| 3185 | } |
Hans-Peter Nilsson | 17bc37b7 | 2016-08-15 13:44:46 +0200 | [diff] [blame] | 3186 | if (env->pregs[PR_VR] < 32) { |
| 3187 | pregnames = pregnames_v10; |
| 3188 | regnames = regnames_v10; |
| 3189 | } else { |
| 3190 | pregnames = pregnames_v32; |
| 3191 | regnames = regnames_v32; |
| 3192 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3193 | |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 3194 | qemu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n" |
| 3195 | "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n", |
| 3196 | env->pc, env->pregs[PR_CCS], env->btaken, env->btarget, |
| 3197 | env->cc_op, |
| 3198 | env->cc_src, env->cc_dest, env->cc_result, env->cc_mask); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 3199 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3200 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3201 | for (i = 0; i < 16; i++) { |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 3202 | qemu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3203 | if ((i + 1) % 4 == 0) { |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 3204 | qemu_fprintf(f, "\n"); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3205 | } |
| 3206 | } |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 3207 | qemu_fprintf(f, "\nspecial regs:\n"); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3208 | for (i = 0; i < 16; i++) { |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 3209 | qemu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3210 | if ((i + 1) % 4 == 0) { |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 3211 | qemu_fprintf(f, "\n"); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3212 | } |
| 3213 | } |
Hans-Peter Nilsson | 17bc37b7 | 2016-08-15 13:44:46 +0200 | [diff] [blame] | 3214 | if (env->pregs[PR_VR] >= 32) { |
| 3215 | uint32_t srs = env->pregs[PR_SRS]; |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 3216 | qemu_fprintf(f, "\nsupport function regs bank %x:\n", srs); |
Hans-Peter Nilsson | 17bc37b7 | 2016-08-15 13:44:46 +0200 | [diff] [blame] | 3217 | if (srs < ARRAY_SIZE(env->sregs)) { |
| 3218 | for (i = 0; i < 16; i++) { |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 3219 | qemu_fprintf(f, "s%2.2d=%8.8x ", |
| 3220 | i, env->sregs[srs][i]); |
Hans-Peter Nilsson | 17bc37b7 | 2016-08-15 13:44:46 +0200 | [diff] [blame] | 3221 | if ((i + 1) % 4 == 0) { |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 3222 | qemu_fprintf(f, "\n"); |
Hans-Peter Nilsson | 17bc37b7 | 2016-08-15 13:44:46 +0200 | [diff] [blame] | 3223 | } |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3224 | } |
| 3225 | } |
| 3226 | } |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 3227 | qemu_fprintf(f, "\n\n"); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3228 | |
| 3229 | } |
| 3230 | |
Andreas Färber | d1a94fe | 2013-01-19 23:55:42 +0100 | [diff] [blame] | 3231 | void cris_initialize_tcg(void) |
| 3232 | { |
| 3233 | int i; |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 3234 | |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 3235 | cc_x = tcg_global_mem_new(tcg_env, |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3236 | offsetof(CPUCRISState, cc_x), "cc_x"); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 3237 | cc_src = tcg_global_mem_new(tcg_env, |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3238 | offsetof(CPUCRISState, cc_src), "cc_src"); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 3239 | cc_dest = tcg_global_mem_new(tcg_env, |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3240 | offsetof(CPUCRISState, cc_dest), |
| 3241 | "cc_dest"); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 3242 | cc_result = tcg_global_mem_new(tcg_env, |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3243 | offsetof(CPUCRISState, cc_result), |
| 3244 | "cc_result"); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 3245 | cc_op = tcg_global_mem_new(tcg_env, |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3246 | offsetof(CPUCRISState, cc_op), "cc_op"); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 3247 | cc_size = tcg_global_mem_new(tcg_env, |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3248 | offsetof(CPUCRISState, cc_size), |
| 3249 | "cc_size"); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 3250 | cc_mask = tcg_global_mem_new(tcg_env, |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3251 | offsetof(CPUCRISState, cc_mask), |
| 3252 | "cc_mask"); |
edgar_igl | a825e70 | 2008-03-16 16:51:58 +0000 | [diff] [blame] | 3253 | |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 3254 | env_pc = tcg_global_mem_new(tcg_env, |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3255 | offsetof(CPUCRISState, pc), |
| 3256 | "pc"); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 3257 | env_btarget = tcg_global_mem_new(tcg_env, |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3258 | offsetof(CPUCRISState, btarget), |
| 3259 | "btarget"); |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 3260 | env_btaken = tcg_global_mem_new(tcg_env, |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3261 | offsetof(CPUCRISState, btaken), |
| 3262 | "btaken"); |
| 3263 | for (i = 0; i < 16; i++) { |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 3264 | cpu_R[i] = tcg_global_mem_new(tcg_env, |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3265 | offsetof(CPUCRISState, regs[i]), |
Hans-Peter Nilsson | 17bc37b7 | 2016-08-15 13:44:46 +0200 | [diff] [blame] | 3266 | regnames_v32[i]); |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3267 | } |
| 3268 | for (i = 0; i < 16; i++) { |
Richard Henderson | ad75a51 | 2023-09-13 16:37:36 -0700 | [diff] [blame] | 3269 | cpu_PR[i] = tcg_global_mem_new(tcg_env, |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3270 | offsetof(CPUCRISState, pregs[i]), |
Hans-Peter Nilsson | 17bc37b7 | 2016-08-15 13:44:46 +0200 | [diff] [blame] | 3271 | pregnames_v32[i]); |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3272 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3273 | } |