bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 1 | /* |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 2 | * virtual page mapping and translated block handling |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 18 | */ |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 19 | #include "config.h" |
bellard | d5a8f07 | 2004-09-29 21:15:28 +0000 | [diff] [blame] | 20 | #ifdef _WIN32 |
| 21 | #include <windows.h> |
| 22 | #else |
bellard | a98d49b | 2004-11-14 16:22:05 +0000 | [diff] [blame] | 23 | #include <sys/types.h> |
bellard | d5a8f07 | 2004-09-29 21:15:28 +0000 | [diff] [blame] | 24 | #include <sys/mman.h> |
| 25 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 26 | |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 27 | #include "qemu-common.h" |
bellard | 6180a18 | 2003-09-30 21:04:53 +0000 | [diff] [blame] | 28 | #include "cpu.h" |
bellard | b67d9a5 | 2008-05-23 09:57:34 +0000 | [diff] [blame] | 29 | #include "tcg.h" |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 30 | #include "hw/hw.h" |
Alex Williamson | cc9e98c | 2010-06-25 11:09:43 -0600 | [diff] [blame] | 31 | #include "hw/qdev.h" |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 32 | #include "osdep.h" |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 33 | #include "kvm.h" |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 34 | #include "hw/xen.h" |
Blue Swirl | 29e922b | 2010-03-29 19:24:00 +0000 | [diff] [blame] | 35 | #include "qemu-timer.h" |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 36 | #include "memory.h" |
| 37 | #include "exec-memory.h" |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 38 | #if defined(CONFIG_USER_ONLY) |
| 39 | #include <qemu.h> |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 40 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
| 41 | #include <sys/param.h> |
| 42 | #if __FreeBSD_version >= 700104 |
| 43 | #define HAVE_KINFO_GETVMMAP |
| 44 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ |
| 45 | #include <sys/time.h> |
| 46 | #include <sys/proc.h> |
| 47 | #include <machine/profile.h> |
| 48 | #define _KERNEL |
| 49 | #include <sys/user.h> |
| 50 | #undef _KERNEL |
| 51 | #undef sigqueue |
| 52 | #include <libutil.h> |
| 53 | #endif |
| 54 | #endif |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 55 | #else /* !CONFIG_USER_ONLY */ |
| 56 | #include "xen-mapcache.h" |
Stefano Stabellini | 6506e4f | 2011-05-19 18:35:44 +0100 | [diff] [blame] | 57 | #include "trace.h" |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 58 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 59 | |
Avi Kivity | 67d95c1 | 2011-12-15 15:25:22 +0200 | [diff] [blame] | 60 | #define WANT_EXEC_OBSOLETE |
| 61 | #include "exec-obsolete.h" |
| 62 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 63 | //#define DEBUG_TB_INVALIDATE |
bellard | 66e85a2 | 2003-06-24 13:28:12 +0000 | [diff] [blame] | 64 | //#define DEBUG_FLUSH |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 65 | //#define DEBUG_TLB |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 66 | //#define DEBUG_UNASSIGNED |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 67 | |
| 68 | /* make various TB consistency checks */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 69 | //#define DEBUG_TB_CHECK |
| 70 | //#define DEBUG_TLB_CHECK |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 71 | |
ths | 1196be3 | 2007-03-17 15:17:58 +0000 | [diff] [blame] | 72 | //#define DEBUG_IOPORT |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 73 | //#define DEBUG_SUBPAGE |
ths | 1196be3 | 2007-03-17 15:17:58 +0000 | [diff] [blame] | 74 | |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 75 | #if !defined(CONFIG_USER_ONLY) |
| 76 | /* TB consistency checks only implemented for usermode emulation. */ |
| 77 | #undef DEBUG_TB_CHECK |
| 78 | #endif |
| 79 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 80 | #define SMC_BITMAP_USE_THRESHOLD 10 |
| 81 | |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 82 | static TranslationBlock *tbs; |
Stefan Weil | 24ab68a | 2010-07-19 18:23:17 +0200 | [diff] [blame] | 83 | static int code_gen_max_blocks; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 84 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 85 | static int nb_tbs; |
bellard | eb51d10 | 2003-05-14 21:51:13 +0000 | [diff] [blame] | 86 | /* any access to the tbs or the page table must use this lock */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 87 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 88 | |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 89 | #if defined(__arm__) || defined(__sparc_v9__) |
| 90 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 |
| 91 | have limited branch ranges (possibly also PPC) so place it in a |
blueswir1 | d03d860 | 2008-07-10 17:21:31 +0000 | [diff] [blame] | 92 | section close to code segment. */ |
| 93 | #define code_gen_section \ |
| 94 | __attribute__((__section__(".gen_code"))) \ |
| 95 | __attribute__((aligned (32))) |
Stefan Weil | f8e2af1 | 2009-06-18 23:04:48 +0200 | [diff] [blame] | 96 | #elif defined(_WIN32) |
| 97 | /* Maximum alignment for Win32 is 16. */ |
| 98 | #define code_gen_section \ |
| 99 | __attribute__((aligned (16))) |
blueswir1 | d03d860 | 2008-07-10 17:21:31 +0000 | [diff] [blame] | 100 | #else |
| 101 | #define code_gen_section \ |
| 102 | __attribute__((aligned (32))) |
| 103 | #endif |
| 104 | |
| 105 | uint8_t code_gen_prologue[1024] code_gen_section; |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 106 | static uint8_t *code_gen_buffer; |
| 107 | static unsigned long code_gen_buffer_size; |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 108 | /* threshold to flush the translated code buffer */ |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 109 | static unsigned long code_gen_buffer_max_size; |
Stefan Weil | 24ab68a | 2010-07-19 18:23:17 +0200 | [diff] [blame] | 110 | static uint8_t *code_gen_ptr; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 111 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 112 | #if !defined(CONFIG_USER_ONLY) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 113 | int phys_ram_fd; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 114 | static int in_migration; |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 115 | |
Paolo Bonzini | 85d59fe | 2011-08-12 13:18:14 +0200 | [diff] [blame] | 116 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 117 | |
| 118 | static MemoryRegion *system_memory; |
Avi Kivity | 309cb47 | 2011-08-08 16:09:03 +0300 | [diff] [blame] | 119 | static MemoryRegion *system_io; |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 120 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 121 | MemoryRegion io_mem_ram, io_mem_rom, io_mem_unassigned, io_mem_notdirty; |
Avi Kivity | de712f9 | 2012-01-02 12:41:07 +0200 | [diff] [blame] | 122 | static MemoryRegion io_mem_subpage_ram; |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 123 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 124 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 125 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 126 | CPUState *first_cpu; |
| 127 | /* current CPU in the current thread. It is only valid inside |
| 128 | cpu_exec() */ |
Paolo Bonzini | b3c4bbe | 2011-10-28 10:52:42 +0100 | [diff] [blame] | 129 | DEFINE_TLS(CPUState *,cpu_single_env); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 130 | /* 0 = Do not count executed instructions. |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 131 | 1 = Precise instruction counting. |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 132 | 2 = Adaptive rate instruction counting. */ |
| 133 | int use_icount = 0; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 134 | |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 135 | typedef struct PageDesc { |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 136 | /* list of TBs intersecting this ram page */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 137 | TranslationBlock *first_tb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 138 | /* in order to optimize self modifying code, we count the number |
| 139 | of lookups we do to a given page to use a bitmap */ |
| 140 | unsigned int code_write_count; |
| 141 | uint8_t *code_bitmap; |
| 142 | #if defined(CONFIG_USER_ONLY) |
| 143 | unsigned long flags; |
| 144 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 145 | } PageDesc; |
| 146 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 147 | /* In system mode we want L1_MAP to be based on ram offsets, |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 148 | while in user mode we want it to be based on virtual addresses. */ |
| 149 | #if !defined(CONFIG_USER_ONLY) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 150 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS |
| 151 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS |
| 152 | #else |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 153 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 154 | #endif |
j_mayer | bedb69e | 2007-04-05 20:08:21 +0000 | [diff] [blame] | 155 | #else |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 156 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS |
j_mayer | bedb69e | 2007-04-05 20:08:21 +0000 | [diff] [blame] | 157 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 158 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 159 | /* Size of the L2 (and L3, etc) page tables. */ |
| 160 | #define L2_BITS 10 |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 161 | #define L2_SIZE (1 << L2_BITS) |
| 162 | |
Avi Kivity | 3eef53d | 2012-02-10 14:57:31 +0200 | [diff] [blame] | 163 | #define P_L2_LEVELS \ |
| 164 | (((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / L2_BITS) + 1) |
| 165 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 166 | /* The bits remaining after N lower levels of page tables. */ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 167 | #define V_L1_BITS_REM \ |
| 168 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) |
| 169 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 170 | #if V_L1_BITS_REM < 4 |
| 171 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS) |
| 172 | #else |
| 173 | #define V_L1_BITS V_L1_BITS_REM |
| 174 | #endif |
| 175 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 176 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) |
| 177 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 178 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) |
| 179 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 180 | unsigned long qemu_real_host_page_size; |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 181 | unsigned long qemu_host_page_size; |
| 182 | unsigned long qemu_host_page_mask; |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 183 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 184 | /* This is a multi-level map on the virtual address space. |
| 185 | The bottom level has pointers to PageDesc. */ |
| 186 | static void *l1_map[V_L1_SIZE]; |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 187 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 188 | #if !defined(CONFIG_USER_ONLY) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 189 | typedef struct PhysPageDesc { |
| 190 | /* offset in host memory of the page + io_index in the low bits */ |
| 191 | ram_addr_t phys_offset; |
| 192 | ram_addr_t region_offset; |
| 193 | } PhysPageDesc; |
| 194 | |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 195 | typedef struct PhysPageEntry PhysPageEntry; |
| 196 | |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 197 | static MemoryRegionSection *phys_sections; |
| 198 | static unsigned phys_sections_nb, phys_sections_nb_alloc; |
| 199 | static uint16_t phys_section_unassigned; |
| 200 | |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 201 | struct PhysPageEntry { |
| 202 | union { |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 203 | uint16_t leaf; /* index into phys_sections */ |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 204 | uint16_t node; /* index into phys_map_nodes */ |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 205 | } u; |
| 206 | }; |
| 207 | |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 208 | /* Simple allocator for PhysPageEntry nodes */ |
| 209 | static PhysPageEntry (*phys_map_nodes)[L2_SIZE]; |
| 210 | static unsigned phys_map_nodes_nb, phys_map_nodes_nb_alloc; |
| 211 | |
| 212 | #define PHYS_MAP_NODE_NIL ((uint16_t)~0) |
| 213 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 214 | /* This is a multi-level map on the physical address space. |
| 215 | The bottom level has pointers to PhysPageDesc. */ |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 216 | static PhysPageEntry phys_map = { .u.node = PHYS_MAP_NODE_NIL }; |
Paul Brook | 6d9a130 | 2010-02-28 23:55:53 +0000 | [diff] [blame] | 217 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 218 | static void io_mem_init(void); |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 219 | static void memory_map_init(void); |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 220 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 221 | /* io memory support */ |
Avi Kivity | a621f38 | 2012-01-02 13:12:08 +0200 | [diff] [blame] | 222 | MemoryRegion *io_mem_region[IO_MEM_NB_ENTRIES]; |
blueswir1 | 511d2b1 | 2009-03-07 15:32:56 +0000 | [diff] [blame] | 223 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 224 | static MemoryRegion io_mem_watch; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 225 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 226 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 227 | /* log support */ |
Juha Riihimäki | 1e8b27c | 2009-12-03 15:56:02 +0200 | [diff] [blame] | 228 | #ifdef WIN32 |
| 229 | static const char *logfilename = "qemu.log"; |
| 230 | #else |
blueswir1 | d9b630f | 2008-10-05 09:57:08 +0000 | [diff] [blame] | 231 | static const char *logfilename = "/tmp/qemu.log"; |
Juha Riihimäki | 1e8b27c | 2009-12-03 15:56:02 +0200 | [diff] [blame] | 232 | #endif |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 233 | FILE *logfile; |
| 234 | int loglevel; |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 235 | static int log_append = 0; |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 236 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 237 | /* statistics */ |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 238 | #if !defined(CONFIG_USER_ONLY) |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 239 | static int tlb_flush_count; |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 240 | #endif |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 241 | static int tb_flush_count; |
| 242 | static int tb_phys_invalidate_count; |
| 243 | |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 244 | #ifdef _WIN32 |
| 245 | static void map_exec(void *addr, long size) |
| 246 | { |
| 247 | DWORD old_protect; |
| 248 | VirtualProtect(addr, size, |
| 249 | PAGE_EXECUTE_READWRITE, &old_protect); |
| 250 | |
| 251 | } |
| 252 | #else |
| 253 | static void map_exec(void *addr, long size) |
| 254 | { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 255 | unsigned long start, end, page_size; |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 256 | |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 257 | page_size = getpagesize(); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 258 | start = (unsigned long)addr; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 259 | start &= ~(page_size - 1); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 260 | |
| 261 | end = (unsigned long)addr + size; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 262 | end += page_size - 1; |
| 263 | end &= ~(page_size - 1); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 264 | |
| 265 | mprotect((void *)start, end - start, |
| 266 | PROT_READ | PROT_WRITE | PROT_EXEC); |
| 267 | } |
| 268 | #endif |
| 269 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 270 | static void page_init(void) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 271 | { |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 272 | /* NOTE: we can always suppose that qemu_host_page_size >= |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 273 | TARGET_PAGE_SIZE */ |
aliguori | c2b48b6 | 2008-11-11 22:06:42 +0000 | [diff] [blame] | 274 | #ifdef _WIN32 |
| 275 | { |
| 276 | SYSTEM_INFO system_info; |
| 277 | |
| 278 | GetSystemInfo(&system_info); |
| 279 | qemu_real_host_page_size = system_info.dwPageSize; |
| 280 | } |
| 281 | #else |
| 282 | qemu_real_host_page_size = getpagesize(); |
| 283 | #endif |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 284 | if (qemu_host_page_size == 0) |
| 285 | qemu_host_page_size = qemu_real_host_page_size; |
| 286 | if (qemu_host_page_size < TARGET_PAGE_SIZE) |
| 287 | qemu_host_page_size = TARGET_PAGE_SIZE; |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 288 | qemu_host_page_mask = ~(qemu_host_page_size - 1); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 289 | |
Paul Brook | 2e9a571 | 2010-05-05 16:32:59 +0100 | [diff] [blame] | 290 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 291 | { |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 292 | #ifdef HAVE_KINFO_GETVMMAP |
| 293 | struct kinfo_vmentry *freep; |
| 294 | int i, cnt; |
| 295 | |
| 296 | freep = kinfo_getvmmap(getpid(), &cnt); |
| 297 | if (freep) { |
| 298 | mmap_lock(); |
| 299 | for (i = 0; i < cnt; i++) { |
| 300 | unsigned long startaddr, endaddr; |
| 301 | |
| 302 | startaddr = freep[i].kve_start; |
| 303 | endaddr = freep[i].kve_end; |
| 304 | if (h2g_valid(startaddr)) { |
| 305 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; |
| 306 | |
| 307 | if (h2g_valid(endaddr)) { |
| 308 | endaddr = h2g(endaddr); |
Aurelien Jarno | fd43690 | 2010-04-10 17:20:36 +0200 | [diff] [blame] | 309 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 310 | } else { |
| 311 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS |
| 312 | endaddr = ~0ul; |
Aurelien Jarno | fd43690 | 2010-04-10 17:20:36 +0200 | [diff] [blame] | 313 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 314 | #endif |
| 315 | } |
| 316 | } |
| 317 | } |
| 318 | free(freep); |
| 319 | mmap_unlock(); |
| 320 | } |
| 321 | #else |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 322 | FILE *f; |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 323 | |
pbrook | 0776590 | 2008-05-31 16:33:53 +0000 | [diff] [blame] | 324 | last_brk = (unsigned long)sbrk(0); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 325 | |
Aurelien Jarno | fd43690 | 2010-04-10 17:20:36 +0200 | [diff] [blame] | 326 | f = fopen("/compat/linux/proc/self/maps", "r"); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 327 | if (f) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 328 | mmap_lock(); |
| 329 | |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 330 | do { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 331 | unsigned long startaddr, endaddr; |
| 332 | int n; |
| 333 | |
| 334 | n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); |
| 335 | |
| 336 | if (n == 2 && h2g_valid(startaddr)) { |
| 337 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; |
| 338 | |
| 339 | if (h2g_valid(endaddr)) { |
| 340 | endaddr = h2g(endaddr); |
| 341 | } else { |
| 342 | endaddr = ~0ul; |
| 343 | } |
| 344 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 345 | } |
| 346 | } while (!feof(f)); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 347 | |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 348 | fclose(f); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 349 | mmap_unlock(); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 350 | } |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 351 | #endif |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 352 | } |
| 353 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 354 | } |
| 355 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 356 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 357 | { |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 358 | PageDesc *pd; |
| 359 | void **lp; |
| 360 | int i; |
| 361 | |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 362 | #if defined(CONFIG_USER_ONLY) |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 363 | /* We can't use g_malloc because it may recurse into a locked mutex. */ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 364 | # define ALLOC(P, SIZE) \ |
| 365 | do { \ |
| 366 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \ |
| 367 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 368 | } while (0) |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 369 | #else |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 370 | # define ALLOC(P, SIZE) \ |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 371 | do { P = g_malloc0(SIZE); } while (0) |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 372 | #endif |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 373 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 374 | /* Level 1. Always allocated. */ |
| 375 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); |
| 376 | |
| 377 | /* Level 2..N-1. */ |
| 378 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) { |
| 379 | void **p = *lp; |
| 380 | |
| 381 | if (p == NULL) { |
| 382 | if (!alloc) { |
| 383 | return NULL; |
| 384 | } |
| 385 | ALLOC(p, sizeof(void *) * L2_SIZE); |
| 386 | *lp = p; |
| 387 | } |
| 388 | |
| 389 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 390 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 391 | |
| 392 | pd = *lp; |
| 393 | if (pd == NULL) { |
| 394 | if (!alloc) { |
| 395 | return NULL; |
| 396 | } |
| 397 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE); |
| 398 | *lp = pd; |
| 399 | } |
| 400 | |
| 401 | #undef ALLOC |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 402 | |
| 403 | return pd + (index & (L2_SIZE - 1)); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 404 | } |
| 405 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 406 | static inline PageDesc *page_find(tb_page_addr_t index) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 407 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 408 | return page_find_alloc(index, 0); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 409 | } |
| 410 | |
Paul Brook | 6d9a130 | 2010-02-28 23:55:53 +0000 | [diff] [blame] | 411 | #if !defined(CONFIG_USER_ONLY) |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 412 | |
| 413 | static PhysPageEntry *phys_map_node_alloc(uint16_t *ptr) |
| 414 | { |
| 415 | unsigned i; |
| 416 | uint16_t ret; |
| 417 | |
| 418 | /* Assign early to avoid the pointer being invalidated by g_renew() */ |
| 419 | *ptr = ret = phys_map_nodes_nb++; |
| 420 | assert(ret != PHYS_MAP_NODE_NIL); |
| 421 | if (ret == phys_map_nodes_nb_alloc) { |
| 422 | typedef PhysPageEntry Node[L2_SIZE]; |
| 423 | phys_map_nodes_nb_alloc = MAX(phys_map_nodes_nb_alloc * 2, 16); |
| 424 | phys_map_nodes = g_renew(Node, phys_map_nodes, |
| 425 | phys_map_nodes_nb_alloc); |
| 426 | } |
| 427 | for (i = 0; i < L2_SIZE; ++i) { |
| 428 | phys_map_nodes[ret][i].u.node = PHYS_MAP_NODE_NIL; |
| 429 | } |
| 430 | return phys_map_nodes[ret]; |
| 431 | } |
| 432 | |
| 433 | static void phys_map_nodes_reset(void) |
| 434 | { |
| 435 | phys_map_nodes_nb = 0; |
| 436 | } |
| 437 | |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 438 | static uint16_t *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 439 | { |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 440 | PhysPageEntry *lp, *p; |
| 441 | int i, j; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 442 | |
Avi Kivity | 3eef53d | 2012-02-10 14:57:31 +0200 | [diff] [blame] | 443 | lp = &phys_map; |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 444 | |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 445 | /* Level 1..N. */ |
| 446 | for (i = P_L2_LEVELS - 1; i >= 0; i--) { |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 447 | if (lp->u.node == PHYS_MAP_NODE_NIL) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 448 | if (!alloc) { |
| 449 | return NULL; |
| 450 | } |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 451 | p = phys_map_node_alloc(&lp->u.node); |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 452 | if (i == 0) { |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 453 | for (j = 0; j < L2_SIZE; j++) { |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 454 | p[j].u.leaf = phys_section_unassigned; |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 455 | } |
| 456 | } |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 457 | } else { |
| 458 | p = phys_map_nodes[lp->u.node]; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 459 | } |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 460 | lp = &p[(index >> (i * L2_BITS)) & (L2_SIZE - 1)]; |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 461 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 462 | |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 463 | return &lp->u.leaf; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 464 | } |
| 465 | |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 466 | static inline PhysPageDesc phys_page_find(target_phys_addr_t index) |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 467 | { |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 468 | uint16_t *p = phys_page_find_alloc(index, 0); |
| 469 | uint16_t s_index = phys_section_unassigned; |
| 470 | MemoryRegionSection *section; |
| 471 | PhysPageDesc pd; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 472 | |
| 473 | if (p) { |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 474 | s_index = *p; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 475 | } |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 476 | section = &phys_sections[s_index]; |
| 477 | index <<= TARGET_PAGE_BITS; |
| 478 | assert(section->offset_within_address_space <= index |
| 479 | && index <= section->offset_within_address_space + section->size-1); |
| 480 | pd.phys_offset = section->mr->ram_addr; |
| 481 | pd.region_offset = (index - section->offset_within_address_space) |
| 482 | + section->offset_within_region; |
| 483 | if (memory_region_is_ram(section->mr)) { |
| 484 | pd.phys_offset += pd.region_offset; |
| 485 | pd.region_offset = 0; |
| 486 | } else if (section->mr->rom_device) { |
| 487 | pd.phys_offset += pd.region_offset; |
| 488 | } |
| 489 | if (section->readonly) { |
| 490 | pd.phys_offset |= io_mem_rom.ram_addr; |
| 491 | } |
| 492 | return pd; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 493 | } |
| 494 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 495 | static void tlb_protect_code(ram_addr_t ram_addr); |
| 496 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 497 | target_ulong vaddr); |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 498 | #define mmap_lock() do { } while(0) |
| 499 | #define mmap_unlock() do { } while(0) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 500 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 501 | |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 502 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
| 503 | |
| 504 | #if defined(CONFIG_USER_ONLY) |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 505 | /* Currently it is not recommended to allocate big chunks of data in |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 506 | user mode. It will change when a dedicated libc will be used */ |
| 507 | #define USE_STATIC_CODE_GEN_BUFFER |
| 508 | #endif |
| 509 | |
| 510 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
Aurelien Jarno | ebf50fb | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 511 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] |
| 512 | __attribute__((aligned (CODE_GEN_ALIGN))); |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 513 | #endif |
| 514 | |
blueswir1 | 8fcd369 | 2008-08-17 20:26:25 +0000 | [diff] [blame] | 515 | static void code_gen_alloc(unsigned long tb_size) |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 516 | { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 517 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
| 518 | code_gen_buffer = static_code_gen_buffer; |
| 519 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; |
| 520 | map_exec(code_gen_buffer, code_gen_buffer_size); |
| 521 | #else |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 522 | code_gen_buffer_size = tb_size; |
| 523 | if (code_gen_buffer_size == 0) { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 524 | #if defined(CONFIG_USER_ONLY) |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 525 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; |
| 526 | #else |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 527 | /* XXX: needs adjustments */ |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 528 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 529 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 530 | } |
| 531 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) |
| 532 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; |
| 533 | /* The code gen buffer location may have constraints depending on |
| 534 | the host cpu and OS */ |
| 535 | #if defined(__linux__) |
| 536 | { |
| 537 | int flags; |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 538 | void *start = NULL; |
| 539 | |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 540 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
| 541 | #if defined(__x86_64__) |
| 542 | flags |= MAP_32BIT; |
| 543 | /* Cannot map more than that */ |
| 544 | if (code_gen_buffer_size > (800 * 1024 * 1024)) |
| 545 | code_gen_buffer_size = (800 * 1024 * 1024); |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 546 | #elif defined(__sparc_v9__) |
| 547 | // Map the buffer below 2G, so we can use direct calls and branches |
| 548 | flags |= MAP_FIXED; |
| 549 | start = (void *) 0x60000000UL; |
| 550 | if (code_gen_buffer_size > (512 * 1024 * 1024)) |
| 551 | code_gen_buffer_size = (512 * 1024 * 1024); |
balrog | 1cb0661 | 2008-12-01 02:10:17 +0000 | [diff] [blame] | 552 | #elif defined(__arm__) |
Aurelien Jarno | 5c84bd9 | 2012-01-07 21:00:25 +0100 | [diff] [blame] | 553 | /* Keep the buffer no bigger than 16MB to branch between blocks */ |
balrog | 1cb0661 | 2008-12-01 02:10:17 +0000 | [diff] [blame] | 554 | if (code_gen_buffer_size > 16 * 1024 * 1024) |
| 555 | code_gen_buffer_size = 16 * 1024 * 1024; |
Richard Henderson | eba0b89 | 2010-06-04 12:14:14 -0700 | [diff] [blame] | 556 | #elif defined(__s390x__) |
| 557 | /* Map the buffer so that we can use direct calls and branches. */ |
| 558 | /* We have a +- 4GB range on the branches; leave some slop. */ |
| 559 | if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) { |
| 560 | code_gen_buffer_size = 3ul * 1024 * 1024 * 1024; |
| 561 | } |
| 562 | start = (void *)0x90000000UL; |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 563 | #endif |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 564 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
| 565 | PROT_WRITE | PROT_READ | PROT_EXEC, |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 566 | flags, -1, 0); |
| 567 | if (code_gen_buffer == MAP_FAILED) { |
| 568 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
| 569 | exit(1); |
| 570 | } |
| 571 | } |
Brad | cbb608a | 2010-12-20 21:25:40 -0500 | [diff] [blame] | 572 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ |
Tobias Nygren | 9f4b09a | 2011-08-07 09:57:05 +0000 | [diff] [blame] | 573 | || defined(__DragonFly__) || defined(__OpenBSD__) \ |
| 574 | || defined(__NetBSD__) |
aliguori | 06e67a8 | 2008-09-27 15:32:41 +0000 | [diff] [blame] | 575 | { |
| 576 | int flags; |
| 577 | void *addr = NULL; |
| 578 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
| 579 | #if defined(__x86_64__) |
| 580 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume |
| 581 | * 0x40000000 is free */ |
| 582 | flags |= MAP_FIXED; |
| 583 | addr = (void *)0x40000000; |
| 584 | /* Cannot map more than that */ |
| 585 | if (code_gen_buffer_size > (800 * 1024 * 1024)) |
| 586 | code_gen_buffer_size = (800 * 1024 * 1024); |
Blue Swirl | 4cd31ad | 2011-01-16 08:32:27 +0000 | [diff] [blame] | 587 | #elif defined(__sparc_v9__) |
| 588 | // Map the buffer below 2G, so we can use direct calls and branches |
| 589 | flags |= MAP_FIXED; |
| 590 | addr = (void *) 0x60000000UL; |
| 591 | if (code_gen_buffer_size > (512 * 1024 * 1024)) { |
| 592 | code_gen_buffer_size = (512 * 1024 * 1024); |
| 593 | } |
aliguori | 06e67a8 | 2008-09-27 15:32:41 +0000 | [diff] [blame] | 594 | #endif |
| 595 | code_gen_buffer = mmap(addr, code_gen_buffer_size, |
| 596 | PROT_WRITE | PROT_READ | PROT_EXEC, |
| 597 | flags, -1, 0); |
| 598 | if (code_gen_buffer == MAP_FAILED) { |
| 599 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
| 600 | exit(1); |
| 601 | } |
| 602 | } |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 603 | #else |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 604 | code_gen_buffer = g_malloc(code_gen_buffer_size); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 605 | map_exec(code_gen_buffer, code_gen_buffer_size); |
| 606 | #endif |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 607 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 608 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
Peter Maydell | a884da8 | 2011-06-22 11:58:25 +0100 | [diff] [blame] | 609 | code_gen_buffer_max_size = code_gen_buffer_size - |
| 610 | (TCG_MAX_OP_SIZE * OPC_BUF_SIZE); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 611 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 612 | tbs = g_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 613 | } |
| 614 | |
| 615 | /* Must be called before using the QEMU cpus. 'tb_size' is the size |
| 616 | (in bytes) allocated to the translation buffer. Zero means default |
| 617 | size. */ |
Jan Kiszka | d5ab971 | 2011-08-02 16:10:21 +0200 | [diff] [blame] | 618 | void tcg_exec_init(unsigned long tb_size) |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 619 | { |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 620 | cpu_gen_init(); |
| 621 | code_gen_alloc(tb_size); |
| 622 | code_gen_ptr = code_gen_buffer; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 623 | page_init(); |
Richard Henderson | 9002ec7 | 2010-05-06 08:50:41 -0700 | [diff] [blame] | 624 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) |
| 625 | /* There's no guest base to take into account, so go ahead and |
| 626 | initialize the prologue now. */ |
| 627 | tcg_prologue_init(&tcg_ctx); |
| 628 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 629 | } |
| 630 | |
Jan Kiszka | d5ab971 | 2011-08-02 16:10:21 +0200 | [diff] [blame] | 631 | bool tcg_enabled(void) |
| 632 | { |
| 633 | return code_gen_buffer != NULL; |
| 634 | } |
| 635 | |
| 636 | void cpu_exec_init_all(void) |
| 637 | { |
| 638 | #if !defined(CONFIG_USER_ONLY) |
| 639 | memory_map_init(); |
| 640 | io_mem_init(); |
| 641 | #endif |
| 642 | } |
| 643 | |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 644 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
| 645 | |
Juan Quintela | e59fb37 | 2009-09-29 22:48:21 +0200 | [diff] [blame] | 646 | static int cpu_common_post_load(void *opaque, int version_id) |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 647 | { |
| 648 | CPUState *env = opaque; |
| 649 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 650 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
| 651 | version_id is increased. */ |
| 652 | env->interrupt_request &= ~0x01; |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 653 | tlb_flush(env, 1); |
| 654 | |
| 655 | return 0; |
| 656 | } |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 657 | |
| 658 | static const VMStateDescription vmstate_cpu_common = { |
| 659 | .name = "cpu_common", |
| 660 | .version_id = 1, |
| 661 | .minimum_version_id = 1, |
| 662 | .minimum_version_id_old = 1, |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 663 | .post_load = cpu_common_post_load, |
| 664 | .fields = (VMStateField []) { |
| 665 | VMSTATE_UINT32(halted, CPUState), |
| 666 | VMSTATE_UINT32(interrupt_request, CPUState), |
| 667 | VMSTATE_END_OF_LIST() |
| 668 | } |
| 669 | }; |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 670 | #endif |
| 671 | |
Glauber Costa | 950f147 | 2009-06-09 12:15:18 -0400 | [diff] [blame] | 672 | CPUState *qemu_get_cpu(int cpu) |
| 673 | { |
| 674 | CPUState *env = first_cpu; |
| 675 | |
| 676 | while (env) { |
| 677 | if (env->cpu_index == cpu) |
| 678 | break; |
| 679 | env = env->next_cpu; |
| 680 | } |
| 681 | |
| 682 | return env; |
| 683 | } |
| 684 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 685 | void cpu_exec_init(CPUState *env) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 686 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 687 | CPUState **penv; |
| 688 | int cpu_index; |
| 689 | |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 690 | #if defined(CONFIG_USER_ONLY) |
| 691 | cpu_list_lock(); |
| 692 | #endif |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 693 | env->next_cpu = NULL; |
| 694 | penv = &first_cpu; |
| 695 | cpu_index = 0; |
| 696 | while (*penv != NULL) { |
Nathan Froyd | 1e9fa73 | 2009-06-03 11:33:08 -0700 | [diff] [blame] | 697 | penv = &(*penv)->next_cpu; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 698 | cpu_index++; |
| 699 | } |
| 700 | env->cpu_index = cpu_index; |
aliguori | 268a362 | 2009-04-21 22:30:27 +0000 | [diff] [blame] | 701 | env->numa_node = 0; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 702 | QTAILQ_INIT(&env->breakpoints); |
| 703 | QTAILQ_INIT(&env->watchpoints); |
Jan Kiszka | dc7a09c | 2011-03-15 12:26:31 +0100 | [diff] [blame] | 704 | #ifndef CONFIG_USER_ONLY |
| 705 | env->thread_id = qemu_get_thread_id(); |
| 706 | #endif |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 707 | *penv = env; |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 708 | #if defined(CONFIG_USER_ONLY) |
| 709 | cpu_list_unlock(); |
| 710 | #endif |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 711 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
Alex Williamson | 0be71e3 | 2010-06-25 11:09:07 -0600 | [diff] [blame] | 712 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env); |
| 713 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 714 | cpu_save, cpu_load, env); |
| 715 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 716 | } |
| 717 | |
Tristan Gingold | d1a1eb7 | 2011-02-10 10:04:57 +0100 | [diff] [blame] | 718 | /* Allocate a new translation block. Flush the translation buffer if |
| 719 | too many translation blocks or too much generated code. */ |
| 720 | static TranslationBlock *tb_alloc(target_ulong pc) |
| 721 | { |
| 722 | TranslationBlock *tb; |
| 723 | |
| 724 | if (nb_tbs >= code_gen_max_blocks || |
| 725 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) |
| 726 | return NULL; |
| 727 | tb = &tbs[nb_tbs++]; |
| 728 | tb->pc = pc; |
| 729 | tb->cflags = 0; |
| 730 | return tb; |
| 731 | } |
| 732 | |
| 733 | void tb_free(TranslationBlock *tb) |
| 734 | { |
| 735 | /* In practice this is mostly used for single use temporary TB |
| 736 | Ignore the hard cases and just back up if this TB happens to |
| 737 | be the last one generated. */ |
| 738 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { |
| 739 | code_gen_ptr = tb->tc_ptr; |
| 740 | nb_tbs--; |
| 741 | } |
| 742 | } |
| 743 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 744 | static inline void invalidate_page_bitmap(PageDesc *p) |
| 745 | { |
| 746 | if (p->code_bitmap) { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 747 | g_free(p->code_bitmap); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 748 | p->code_bitmap = NULL; |
| 749 | } |
| 750 | p->code_write_count = 0; |
| 751 | } |
| 752 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 753 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ |
| 754 | |
| 755 | static void page_flush_tb_1 (int level, void **lp) |
| 756 | { |
| 757 | int i; |
| 758 | |
| 759 | if (*lp == NULL) { |
| 760 | return; |
| 761 | } |
| 762 | if (level == 0) { |
| 763 | PageDesc *pd = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 764 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 765 | pd[i].first_tb = NULL; |
| 766 | invalidate_page_bitmap(pd + i); |
| 767 | } |
| 768 | } else { |
| 769 | void **pp = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 770 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 771 | page_flush_tb_1 (level - 1, pp + i); |
| 772 | } |
| 773 | } |
| 774 | } |
| 775 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 776 | static void page_flush_tb(void) |
| 777 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 778 | int i; |
| 779 | for (i = 0; i < V_L1_SIZE; i++) { |
| 780 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 781 | } |
| 782 | } |
| 783 | |
| 784 | /* flush all the translation blocks */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 785 | /* XXX: tb_flush is currently not thread safe */ |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 786 | void tb_flush(CPUState *env1) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 787 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 788 | CPUState *env; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 789 | #if defined(DEBUG_FLUSH) |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 790 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
| 791 | (unsigned long)(code_gen_ptr - code_gen_buffer), |
| 792 | nb_tbs, nb_tbs > 0 ? |
| 793 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 794 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 795 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
pbrook | a208e54 | 2008-03-31 17:07:36 +0000 | [diff] [blame] | 796 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
| 797 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 798 | nb_tbs = 0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 799 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 800 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 801 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
| 802 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 803 | |
bellard | 8a8a608 | 2004-10-03 13:36:49 +0000 | [diff] [blame] | 804 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 805 | page_flush_tb(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 806 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 807 | code_gen_ptr = code_gen_buffer; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 808 | /* XXX: flush processor icache at this point if cache flush is |
| 809 | expensive */ |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 810 | tb_flush_count++; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 811 | } |
| 812 | |
| 813 | #ifdef DEBUG_TB_CHECK |
| 814 | |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 815 | static void tb_invalidate_check(target_ulong address) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 816 | { |
| 817 | TranslationBlock *tb; |
| 818 | int i; |
| 819 | address &= TARGET_PAGE_MASK; |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 820 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
| 821 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 822 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
| 823 | address >= tb->pc + tb->size)) { |
Blue Swirl | 0bf9e31 | 2009-07-20 17:19:25 +0000 | [diff] [blame] | 824 | printf("ERROR invalidate: address=" TARGET_FMT_lx |
| 825 | " PC=%08lx size=%04x\n", |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 826 | address, (long)tb->pc, tb->size); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 827 | } |
| 828 | } |
| 829 | } |
| 830 | } |
| 831 | |
| 832 | /* verify that all the pages have correct rights for code */ |
| 833 | static void tb_page_check(void) |
| 834 | { |
| 835 | TranslationBlock *tb; |
| 836 | int i, flags1, flags2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 837 | |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 838 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
| 839 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 840 | flags1 = page_get_flags(tb->pc); |
| 841 | flags2 = page_get_flags(tb->pc + tb->size - 1); |
| 842 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { |
| 843 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 844 | (long)tb->pc, tb->size, flags1, flags2); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 845 | } |
| 846 | } |
| 847 | } |
| 848 | } |
| 849 | |
| 850 | #endif |
| 851 | |
| 852 | /* invalidate one TB */ |
| 853 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, |
| 854 | int next_offset) |
| 855 | { |
| 856 | TranslationBlock *tb1; |
| 857 | for(;;) { |
| 858 | tb1 = *ptb; |
| 859 | if (tb1 == tb) { |
| 860 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); |
| 861 | break; |
| 862 | } |
| 863 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); |
| 864 | } |
| 865 | } |
| 866 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 867 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
| 868 | { |
| 869 | TranslationBlock *tb1; |
| 870 | unsigned int n1; |
| 871 | |
| 872 | for(;;) { |
| 873 | tb1 = *ptb; |
| 874 | n1 = (long)tb1 & 3; |
| 875 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 876 | if (tb1 == tb) { |
| 877 | *ptb = tb1->page_next[n1]; |
| 878 | break; |
| 879 | } |
| 880 | ptb = &tb1->page_next[n1]; |
| 881 | } |
| 882 | } |
| 883 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 884 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
| 885 | { |
| 886 | TranslationBlock *tb1, **ptb; |
| 887 | unsigned int n1; |
| 888 | |
| 889 | ptb = &tb->jmp_next[n]; |
| 890 | tb1 = *ptb; |
| 891 | if (tb1) { |
| 892 | /* find tb(n) in circular list */ |
| 893 | for(;;) { |
| 894 | tb1 = *ptb; |
| 895 | n1 = (long)tb1 & 3; |
| 896 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 897 | if (n1 == n && tb1 == tb) |
| 898 | break; |
| 899 | if (n1 == 2) { |
| 900 | ptb = &tb1->jmp_first; |
| 901 | } else { |
| 902 | ptb = &tb1->jmp_next[n1]; |
| 903 | } |
| 904 | } |
| 905 | /* now we can suppress tb(n) from the list */ |
| 906 | *ptb = tb->jmp_next[n]; |
| 907 | |
| 908 | tb->jmp_next[n] = NULL; |
| 909 | } |
| 910 | } |
| 911 | |
| 912 | /* reset the jump entry 'n' of a TB so that it is not chained to |
| 913 | another TB */ |
| 914 | static inline void tb_reset_jump(TranslationBlock *tb, int n) |
| 915 | { |
| 916 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); |
| 917 | } |
| 918 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 919 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 920 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 921 | CPUState *env; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 922 | PageDesc *p; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 923 | unsigned int h, n1; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 924 | tb_page_addr_t phys_pc; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 925 | TranslationBlock *tb1, *tb2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 926 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 927 | /* remove the TB from the hash list */ |
| 928 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); |
| 929 | h = tb_phys_hash_func(phys_pc); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 930 | tb_remove(&tb_phys_hash[h], tb, |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 931 | offsetof(TranslationBlock, phys_hash_next)); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 932 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 933 | /* remove the TB from the page list */ |
| 934 | if (tb->page_addr[0] != page_addr) { |
| 935 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); |
| 936 | tb_page_remove(&p->first_tb, tb); |
| 937 | invalidate_page_bitmap(p); |
| 938 | } |
| 939 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { |
| 940 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); |
| 941 | tb_page_remove(&p->first_tb, tb); |
| 942 | invalidate_page_bitmap(p); |
| 943 | } |
| 944 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 945 | tb_invalidated_flag = 1; |
| 946 | |
| 947 | /* remove the TB from the hash list */ |
| 948 | h = tb_jmp_cache_hash_func(tb->pc); |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 949 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 950 | if (env->tb_jmp_cache[h] == tb) |
| 951 | env->tb_jmp_cache[h] = NULL; |
| 952 | } |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 953 | |
| 954 | /* suppress this TB from the two jump lists */ |
| 955 | tb_jmp_remove(tb, 0); |
| 956 | tb_jmp_remove(tb, 1); |
| 957 | |
| 958 | /* suppress any remaining jumps to this TB */ |
| 959 | tb1 = tb->jmp_first; |
| 960 | for(;;) { |
| 961 | n1 = (long)tb1 & 3; |
| 962 | if (n1 == 2) |
| 963 | break; |
| 964 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 965 | tb2 = tb1->jmp_next[n1]; |
| 966 | tb_reset_jump(tb1, n1); |
| 967 | tb1->jmp_next[n1] = NULL; |
| 968 | tb1 = tb2; |
| 969 | } |
| 970 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ |
| 971 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 972 | tb_phys_invalidate_count++; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 973 | } |
| 974 | |
| 975 | static inline void set_bits(uint8_t *tab, int start, int len) |
| 976 | { |
| 977 | int end, mask, end1; |
| 978 | |
| 979 | end = start + len; |
| 980 | tab += start >> 3; |
| 981 | mask = 0xff << (start & 7); |
| 982 | if ((start & ~7) == (end & ~7)) { |
| 983 | if (start < end) { |
| 984 | mask &= ~(0xff << (end & 7)); |
| 985 | *tab |= mask; |
| 986 | } |
| 987 | } else { |
| 988 | *tab++ |= mask; |
| 989 | start = (start + 8) & ~7; |
| 990 | end1 = end & ~7; |
| 991 | while (start < end1) { |
| 992 | *tab++ = 0xff; |
| 993 | start += 8; |
| 994 | } |
| 995 | if (start < end) { |
| 996 | mask = ~(0xff << (end & 7)); |
| 997 | *tab |= mask; |
| 998 | } |
| 999 | } |
| 1000 | } |
| 1001 | |
| 1002 | static void build_page_bitmap(PageDesc *p) |
| 1003 | { |
| 1004 | int n, tb_start, tb_end; |
| 1005 | TranslationBlock *tb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1006 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1007 | p->code_bitmap = g_malloc0(TARGET_PAGE_SIZE / 8); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1008 | |
| 1009 | tb = p->first_tb; |
| 1010 | while (tb != NULL) { |
| 1011 | n = (long)tb & 3; |
| 1012 | tb = (TranslationBlock *)((long)tb & ~3); |
| 1013 | /* NOTE: this is subtle as a TB may span two physical pages */ |
| 1014 | if (n == 0) { |
| 1015 | /* NOTE: tb_end may be after the end of the page, but |
| 1016 | it is not a problem */ |
| 1017 | tb_start = tb->pc & ~TARGET_PAGE_MASK; |
| 1018 | tb_end = tb_start + tb->size; |
| 1019 | if (tb_end > TARGET_PAGE_SIZE) |
| 1020 | tb_end = TARGET_PAGE_SIZE; |
| 1021 | } else { |
| 1022 | tb_start = 0; |
| 1023 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); |
| 1024 | } |
| 1025 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); |
| 1026 | tb = tb->page_next[n]; |
| 1027 | } |
| 1028 | } |
| 1029 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1030 | TranslationBlock *tb_gen_code(CPUState *env, |
| 1031 | target_ulong pc, target_ulong cs_base, |
| 1032 | int flags, int cflags) |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1033 | { |
| 1034 | TranslationBlock *tb; |
| 1035 | uint8_t *tc_ptr; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1036 | tb_page_addr_t phys_pc, phys_page2; |
| 1037 | target_ulong virt_page2; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1038 | int code_gen_size; |
| 1039 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1040 | phys_pc = get_page_addr_code(env, pc); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1041 | tb = tb_alloc(pc); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1042 | if (!tb) { |
| 1043 | /* flush must be done */ |
| 1044 | tb_flush(env); |
| 1045 | /* cannot fail at this point */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1046 | tb = tb_alloc(pc); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1047 | /* Don't forget to invalidate previous TB info. */ |
| 1048 | tb_invalidated_flag = 1; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1049 | } |
| 1050 | tc_ptr = code_gen_ptr; |
| 1051 | tb->tc_ptr = tc_ptr; |
| 1052 | tb->cs_base = cs_base; |
| 1053 | tb->flags = flags; |
| 1054 | tb->cflags = cflags; |
blueswir1 | d07bde8 | 2007-12-11 19:35:45 +0000 | [diff] [blame] | 1055 | cpu_gen_code(env, tb, &code_gen_size); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1056 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1057 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1058 | /* check next page if needed */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1059 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1060 | phys_page2 = -1; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1061 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1062 | phys_page2 = get_page_addr_code(env, virt_page2); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1063 | } |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1064 | tb_link_page(tb, phys_pc, phys_page2); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1065 | return tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1066 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1067 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1068 | /* invalidate all TBs which intersect with the target physical page |
| 1069 | starting in range [start;end[. NOTE: start and end must refer to |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1070 | the same physical page. 'is_cpu_write_access' should be true if called |
| 1071 | from a real cpu write access: the virtual CPU will exit the current |
| 1072 | TB if code is modified inside this TB. */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1073 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1074 | int is_cpu_write_access) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1075 | { |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1076 | TranslationBlock *tb, *tb_next, *saved_tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1077 | CPUState *env = cpu_single_env; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1078 | tb_page_addr_t tb_start, tb_end; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1079 | PageDesc *p; |
| 1080 | int n; |
| 1081 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1082 | int current_tb_not_found = is_cpu_write_access; |
| 1083 | TranslationBlock *current_tb = NULL; |
| 1084 | int current_tb_modified = 0; |
| 1085 | target_ulong current_pc = 0; |
| 1086 | target_ulong current_cs_base = 0; |
| 1087 | int current_flags = 0; |
| 1088 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1089 | |
| 1090 | p = page_find(start >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1091 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1092 | return; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1093 | if (!p->code_bitmap && |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1094 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
| 1095 | is_cpu_write_access) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1096 | /* build code bitmap */ |
| 1097 | build_page_bitmap(p); |
| 1098 | } |
| 1099 | |
| 1100 | /* we remove all the TBs in the range [start, end[ */ |
| 1101 | /* XXX: see if in some cases it could be faster to invalidate all the code */ |
| 1102 | tb = p->first_tb; |
| 1103 | while (tb != NULL) { |
| 1104 | n = (long)tb & 3; |
| 1105 | tb = (TranslationBlock *)((long)tb & ~3); |
| 1106 | tb_next = tb->page_next[n]; |
| 1107 | /* NOTE: this is subtle as a TB may span two physical pages */ |
| 1108 | if (n == 0) { |
| 1109 | /* NOTE: tb_end may be after the end of the page, but |
| 1110 | it is not a problem */ |
| 1111 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); |
| 1112 | tb_end = tb_start + tb->size; |
| 1113 | } else { |
| 1114 | tb_start = tb->page_addr[1]; |
| 1115 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); |
| 1116 | } |
| 1117 | if (!(tb_end <= start || tb_start >= end)) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1118 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1119 | if (current_tb_not_found) { |
| 1120 | current_tb_not_found = 0; |
| 1121 | current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1122 | if (env->mem_io_pc) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1123 | /* now we have a real cpu fault */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1124 | current_tb = tb_find_pc(env->mem_io_pc); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1125 | } |
| 1126 | } |
| 1127 | if (current_tb == tb && |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1128 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1129 | /* If we are modifying the current TB, we must stop |
| 1130 | its execution. We could be more precise by checking |
| 1131 | that the modification is after the current PC, but it |
| 1132 | would require a specialized function to partially |
| 1133 | restore the CPU state */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1134 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1135 | current_tb_modified = 1; |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 1136 | cpu_restore_state(current_tb, env, env->mem_io_pc); |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1137 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
| 1138 | ¤t_flags); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1139 | } |
| 1140 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 6f5a9f7 | 2005-11-26 20:12:28 +0000 | [diff] [blame] | 1141 | /* we need to do that to handle the case where a signal |
| 1142 | occurs while doing tb_phys_invalidate() */ |
| 1143 | saved_tb = NULL; |
| 1144 | if (env) { |
| 1145 | saved_tb = env->current_tb; |
| 1146 | env->current_tb = NULL; |
| 1147 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1148 | tb_phys_invalidate(tb, -1); |
bellard | 6f5a9f7 | 2005-11-26 20:12:28 +0000 | [diff] [blame] | 1149 | if (env) { |
| 1150 | env->current_tb = saved_tb; |
| 1151 | if (env->interrupt_request && env->current_tb) |
| 1152 | cpu_interrupt(env, env->interrupt_request); |
| 1153 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1154 | } |
| 1155 | tb = tb_next; |
| 1156 | } |
| 1157 | #if !defined(CONFIG_USER_ONLY) |
| 1158 | /* if no code remaining, no need to continue to use slow writes */ |
| 1159 | if (!p->first_tb) { |
| 1160 | invalidate_page_bitmap(p); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1161 | if (is_cpu_write_access) { |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1162 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1163 | } |
| 1164 | } |
| 1165 | #endif |
| 1166 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1167 | if (current_tb_modified) { |
| 1168 | /* we generate a block containing just the instruction |
| 1169 | modifying the memory. It will ensure that it cannot modify |
| 1170 | itself */ |
bellard | ea1c180 | 2004-06-14 18:56:36 +0000 | [diff] [blame] | 1171 | env->current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1172 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1173 | cpu_resume_from_signal(env, NULL); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1174 | } |
| 1175 | #endif |
| 1176 | } |
| 1177 | |
| 1178 | /* len must be <= 8 and start must be a multiple of len */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1179 | static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1180 | { |
| 1181 | PageDesc *p; |
| 1182 | int offset, b; |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 1183 | #if 0 |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 1184 | if (1) { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1185 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
| 1186 | cpu_single_env->mem_io_vaddr, len, |
| 1187 | cpu_single_env->eip, |
| 1188 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 1189 | } |
| 1190 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1191 | p = page_find(start >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1192 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1193 | return; |
| 1194 | if (p->code_bitmap) { |
| 1195 | offset = start & ~TARGET_PAGE_MASK; |
| 1196 | b = p->code_bitmap[offset >> 3] >> (offset & 7); |
| 1197 | if (b & ((1 << len) - 1)) |
| 1198 | goto do_invalidate; |
| 1199 | } else { |
| 1200 | do_invalidate: |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1201 | tb_invalidate_phys_page_range(start, start + len, 1); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1202 | } |
| 1203 | } |
| 1204 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1205 | #if !defined(CONFIG_SOFTMMU) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1206 | static void tb_invalidate_phys_page(tb_page_addr_t addr, |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1207 | unsigned long pc, void *puc) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1208 | { |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1209 | TranslationBlock *tb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1210 | PageDesc *p; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1211 | int n; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1212 | #ifdef TARGET_HAS_PRECISE_SMC |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1213 | TranslationBlock *current_tb = NULL; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1214 | CPUState *env = cpu_single_env; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1215 | int current_tb_modified = 0; |
| 1216 | target_ulong current_pc = 0; |
| 1217 | target_ulong current_cs_base = 0; |
| 1218 | int current_flags = 0; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1219 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1220 | |
| 1221 | addr &= TARGET_PAGE_MASK; |
| 1222 | p = page_find(addr >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1223 | if (!p) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1224 | return; |
| 1225 | tb = p->first_tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1226 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1227 | if (tb && pc != 0) { |
| 1228 | current_tb = tb_find_pc(pc); |
| 1229 | } |
| 1230 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1231 | while (tb != NULL) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1232 | n = (long)tb & 3; |
| 1233 | tb = (TranslationBlock *)((long)tb & ~3); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1234 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1235 | if (current_tb == tb && |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1236 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1237 | /* If we are modifying the current TB, we must stop |
| 1238 | its execution. We could be more precise by checking |
| 1239 | that the modification is after the current PC, but it |
| 1240 | would require a specialized function to partially |
| 1241 | restore the CPU state */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1242 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1243 | current_tb_modified = 1; |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 1244 | cpu_restore_state(current_tb, env, pc); |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1245 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
| 1246 | ¤t_flags); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1247 | } |
| 1248 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1249 | tb_phys_invalidate(tb, addr); |
| 1250 | tb = tb->page_next[n]; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1251 | } |
| 1252 | p->first_tb = NULL; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1253 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1254 | if (current_tb_modified) { |
| 1255 | /* we generate a block containing just the instruction |
| 1256 | modifying the memory. It will ensure that it cannot modify |
| 1257 | itself */ |
bellard | ea1c180 | 2004-06-14 18:56:36 +0000 | [diff] [blame] | 1258 | env->current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1259 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1260 | cpu_resume_from_signal(env, puc); |
| 1261 | } |
| 1262 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1263 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1264 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1265 | |
| 1266 | /* add the tb in the target page and protect it if necessary */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1267 | static inline void tb_alloc_page(TranslationBlock *tb, |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1268 | unsigned int n, tb_page_addr_t page_addr) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1269 | { |
| 1270 | PageDesc *p; |
Juan Quintela | 4429ab4 | 2011-06-02 01:53:44 +0000 | [diff] [blame] | 1271 | #ifndef CONFIG_USER_ONLY |
| 1272 | bool page_already_protected; |
| 1273 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1274 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1275 | tb->page_addr[n] = page_addr; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1276 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1277 | tb->page_next[n] = p->first_tb; |
Juan Quintela | 4429ab4 | 2011-06-02 01:53:44 +0000 | [diff] [blame] | 1278 | #ifndef CONFIG_USER_ONLY |
| 1279 | page_already_protected = p->first_tb != NULL; |
| 1280 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1281 | p->first_tb = (TranslationBlock *)((long)tb | n); |
| 1282 | invalidate_page_bitmap(p); |
| 1283 | |
bellard | 107db44 | 2004-06-22 18:48:46 +0000 | [diff] [blame] | 1284 | #if defined(TARGET_HAS_SMC) || 1 |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1285 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1286 | #if defined(CONFIG_USER_ONLY) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1287 | if (p->flags & PAGE_WRITE) { |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1288 | target_ulong addr; |
| 1289 | PageDesc *p2; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1290 | int prot; |
| 1291 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1292 | /* force the host page as non writable (writes will have a |
| 1293 | page fault + mprotect overhead) */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1294 | page_addr &= qemu_host_page_mask; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1295 | prot = 0; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1296 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
| 1297 | addr += TARGET_PAGE_SIZE) { |
| 1298 | |
| 1299 | p2 = page_find (addr >> TARGET_PAGE_BITS); |
| 1300 | if (!p2) |
| 1301 | continue; |
| 1302 | prot |= p2->flags; |
| 1303 | p2->flags &= ~PAGE_WRITE; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1304 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1305 | mprotect(g2h(page_addr), qemu_host_page_size, |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1306 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
| 1307 | #ifdef DEBUG_TB_INVALIDATE |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 1308 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1309 | page_addr); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1310 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1311 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1312 | #else |
| 1313 | /* if some code is already present, then the pages are already |
| 1314 | protected. So we handle the case where only the first TB is |
| 1315 | allocated in a physical page */ |
Juan Quintela | 4429ab4 | 2011-06-02 01:53:44 +0000 | [diff] [blame] | 1316 | if (!page_already_protected) { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 1317 | tlb_protect_code(page_addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1318 | } |
| 1319 | #endif |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1320 | |
| 1321 | #endif /* TARGET_HAS_SMC */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1322 | } |
| 1323 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1324 | /* add a new TB and link it to the physical page tables. phys_page2 is |
| 1325 | (-1) to indicate that only one page contains the TB. */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1326 | void tb_link_page(TranslationBlock *tb, |
| 1327 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1328 | { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1329 | unsigned int h; |
| 1330 | TranslationBlock **ptb; |
| 1331 | |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 1332 | /* Grab the mmap lock to stop another thread invalidating this TB |
| 1333 | before we are done. */ |
| 1334 | mmap_lock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1335 | /* add in the physical hash table */ |
| 1336 | h = tb_phys_hash_func(phys_pc); |
| 1337 | ptb = &tb_phys_hash[h]; |
| 1338 | tb->phys_hash_next = *ptb; |
| 1339 | *ptb = tb; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1340 | |
| 1341 | /* add in the page list */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1342 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
| 1343 | if (phys_page2 != -1) |
| 1344 | tb_alloc_page(tb, 1, phys_page2); |
| 1345 | else |
| 1346 | tb->page_addr[1] = -1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1347 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1348 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
| 1349 | tb->jmp_next[0] = NULL; |
| 1350 | tb->jmp_next[1] = NULL; |
| 1351 | |
| 1352 | /* init original jump addresses */ |
| 1353 | if (tb->tb_next_offset[0] != 0xffff) |
| 1354 | tb_reset_jump(tb, 0); |
| 1355 | if (tb->tb_next_offset[1] != 0xffff) |
| 1356 | tb_reset_jump(tb, 1); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1357 | |
| 1358 | #ifdef DEBUG_TB_CHECK |
| 1359 | tb_page_check(); |
| 1360 | #endif |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 1361 | mmap_unlock(); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1362 | } |
| 1363 | |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 1364 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
| 1365 | tb[1].tc_ptr. Return NULL if not found */ |
| 1366 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) |
| 1367 | { |
| 1368 | int m_min, m_max, m; |
| 1369 | unsigned long v; |
| 1370 | TranslationBlock *tb; |
| 1371 | |
| 1372 | if (nb_tbs <= 0) |
| 1373 | return NULL; |
| 1374 | if (tc_ptr < (unsigned long)code_gen_buffer || |
| 1375 | tc_ptr >= (unsigned long)code_gen_ptr) |
| 1376 | return NULL; |
| 1377 | /* binary search (cf Knuth) */ |
| 1378 | m_min = 0; |
| 1379 | m_max = nb_tbs - 1; |
| 1380 | while (m_min <= m_max) { |
| 1381 | m = (m_min + m_max) >> 1; |
| 1382 | tb = &tbs[m]; |
| 1383 | v = (unsigned long)tb->tc_ptr; |
| 1384 | if (v == tc_ptr) |
| 1385 | return tb; |
| 1386 | else if (tc_ptr < v) { |
| 1387 | m_max = m - 1; |
| 1388 | } else { |
| 1389 | m_min = m + 1; |
| 1390 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1391 | } |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 1392 | return &tbs[m_max]; |
| 1393 | } |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1394 | |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1395 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
| 1396 | |
| 1397 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) |
| 1398 | { |
| 1399 | TranslationBlock *tb1, *tb_next, **ptb; |
| 1400 | unsigned int n1; |
| 1401 | |
| 1402 | tb1 = tb->jmp_next[n]; |
| 1403 | if (tb1 != NULL) { |
| 1404 | /* find head of list */ |
| 1405 | for(;;) { |
| 1406 | n1 = (long)tb1 & 3; |
| 1407 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 1408 | if (n1 == 2) |
| 1409 | break; |
| 1410 | tb1 = tb1->jmp_next[n1]; |
| 1411 | } |
| 1412 | /* we are now sure now that tb jumps to tb1 */ |
| 1413 | tb_next = tb1; |
| 1414 | |
| 1415 | /* remove tb from the jmp_first list */ |
| 1416 | ptb = &tb_next->jmp_first; |
| 1417 | for(;;) { |
| 1418 | tb1 = *ptb; |
| 1419 | n1 = (long)tb1 & 3; |
| 1420 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 1421 | if (n1 == n && tb1 == tb) |
| 1422 | break; |
| 1423 | ptb = &tb1->jmp_next[n1]; |
| 1424 | } |
| 1425 | *ptb = tb->jmp_next[n]; |
| 1426 | tb->jmp_next[n] = NULL; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1427 | |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1428 | /* suppress the jump to next tb in generated code */ |
| 1429 | tb_reset_jump(tb, n); |
| 1430 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1431 | /* suppress jumps in the tb on which we could have jumped */ |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1432 | tb_reset_jump_recursive(tb_next); |
| 1433 | } |
| 1434 | } |
| 1435 | |
| 1436 | static void tb_reset_jump_recursive(TranslationBlock *tb) |
| 1437 | { |
| 1438 | tb_reset_jump_recursive2(tb, 0); |
| 1439 | tb_reset_jump_recursive2(tb, 1); |
| 1440 | } |
| 1441 | |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1442 | #if defined(TARGET_HAS_ICE) |
Paul Brook | 94df27f | 2010-02-28 23:47:45 +0000 | [diff] [blame] | 1443 | #if defined(CONFIG_USER_ONLY) |
| 1444 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
| 1445 | { |
| 1446 | tb_invalidate_phys_page_range(pc, pc + 1, 0); |
| 1447 | } |
| 1448 | #else |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1449 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
| 1450 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1451 | target_phys_addr_t addr; |
j_mayer | 9b3c35e | 2007-04-07 11:21:28 +0000 | [diff] [blame] | 1452 | target_ulong pd; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1453 | ram_addr_t ram_addr; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 1454 | PhysPageDesc p; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1455 | |
pbrook | c2f07f8 | 2006-04-08 17:14:56 +0000 | [diff] [blame] | 1456 | addr = cpu_get_phys_page_debug(env, pc); |
| 1457 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 1458 | pd = p.phys_offset; |
pbrook | c2f07f8 | 2006-04-08 17:14:56 +0000 | [diff] [blame] | 1459 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); |
pbrook | 706cd4b | 2006-04-08 17:36:21 +0000 | [diff] [blame] | 1460 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1461 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1462 | #endif |
Paul Brook | 94df27f | 2010-02-28 23:47:45 +0000 | [diff] [blame] | 1463 | #endif /* TARGET_HAS_ICE */ |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1464 | |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 1465 | #if defined(CONFIG_USER_ONLY) |
| 1466 | void cpu_watchpoint_remove_all(CPUState *env, int mask) |
| 1467 | |
| 1468 | { |
| 1469 | } |
| 1470 | |
| 1471 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
| 1472 | int flags, CPUWatchpoint **watchpoint) |
| 1473 | { |
| 1474 | return -ENOSYS; |
| 1475 | } |
| 1476 | #else |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1477 | /* Add a watchpoint. */ |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1478 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
| 1479 | int flags, CPUWatchpoint **watchpoint) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1480 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1481 | target_ulong len_mask = ~(len - 1); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1482 | CPUWatchpoint *wp; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1483 | |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1484 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
| 1485 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { |
| 1486 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " |
| 1487 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); |
| 1488 | return -EINVAL; |
| 1489 | } |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1490 | wp = g_malloc(sizeof(*wp)); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1491 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1492 | wp->vaddr = addr; |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1493 | wp->len_mask = len_mask; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1494 | wp->flags = flags; |
| 1495 | |
aliguori | 2dc9f41 | 2008-11-18 20:56:59 +0000 | [diff] [blame] | 1496 | /* keep all GDB-injected watchpoints in front */ |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1497 | if (flags & BP_GDB) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1498 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1499 | else |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1500 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1501 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1502 | tlb_flush_page(env, addr); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1503 | |
| 1504 | if (watchpoint) |
| 1505 | *watchpoint = wp; |
| 1506 | return 0; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1507 | } |
| 1508 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1509 | /* Remove a specific watchpoint. */ |
| 1510 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, |
| 1511 | int flags) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1512 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1513 | target_ulong len_mask = ~(len - 1); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1514 | CPUWatchpoint *wp; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1515 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1516 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1517 | if (addr == wp->vaddr && len_mask == wp->len_mask |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 1518 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1519 | cpu_watchpoint_remove_by_ref(env, wp); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1520 | return 0; |
| 1521 | } |
| 1522 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1523 | return -ENOENT; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1524 | } |
| 1525 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1526 | /* Remove a specific watchpoint by reference. */ |
| 1527 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) |
| 1528 | { |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1529 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
edgar_igl | 7d03f82 | 2008-05-17 18:58:29 +0000 | [diff] [blame] | 1530 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1531 | tlb_flush_page(env, watchpoint->vaddr); |
| 1532 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1533 | g_free(watchpoint); |
edgar_igl | 7d03f82 | 2008-05-17 18:58:29 +0000 | [diff] [blame] | 1534 | } |
| 1535 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1536 | /* Remove all matching watchpoints. */ |
| 1537 | void cpu_watchpoint_remove_all(CPUState *env, int mask) |
| 1538 | { |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1539 | CPUWatchpoint *wp, *next; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1540 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1541 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1542 | if (wp->flags & mask) |
| 1543 | cpu_watchpoint_remove_by_ref(env, wp); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1544 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1545 | } |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 1546 | #endif |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1547 | |
| 1548 | /* Add a breakpoint. */ |
| 1549 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, |
| 1550 | CPUBreakpoint **breakpoint) |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1551 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1552 | #if defined(TARGET_HAS_ICE) |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1553 | CPUBreakpoint *bp; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1554 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1555 | bp = g_malloc(sizeof(*bp)); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1556 | |
| 1557 | bp->pc = pc; |
| 1558 | bp->flags = flags; |
| 1559 | |
aliguori | 2dc9f41 | 2008-11-18 20:56:59 +0000 | [diff] [blame] | 1560 | /* keep all GDB-injected breakpoints in front */ |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1561 | if (flags & BP_GDB) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1562 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1563 | else |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1564 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1565 | |
| 1566 | breakpoint_invalidate(env, pc); |
| 1567 | |
| 1568 | if (breakpoint) |
| 1569 | *breakpoint = bp; |
| 1570 | return 0; |
| 1571 | #else |
| 1572 | return -ENOSYS; |
| 1573 | #endif |
| 1574 | } |
| 1575 | |
| 1576 | /* Remove a specific breakpoint. */ |
| 1577 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) |
| 1578 | { |
| 1579 | #if defined(TARGET_HAS_ICE) |
| 1580 | CPUBreakpoint *bp; |
| 1581 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1582 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1583 | if (bp->pc == pc && bp->flags == flags) { |
| 1584 | cpu_breakpoint_remove_by_ref(env, bp); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1585 | return 0; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1586 | } |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1587 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1588 | return -ENOENT; |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1589 | #else |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1590 | return -ENOSYS; |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1591 | #endif |
| 1592 | } |
| 1593 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1594 | /* Remove a specific breakpoint by reference. */ |
| 1595 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1596 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1597 | #if defined(TARGET_HAS_ICE) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1598 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1599 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1600 | breakpoint_invalidate(env, breakpoint->pc); |
| 1601 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1602 | g_free(breakpoint); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1603 | #endif |
| 1604 | } |
| 1605 | |
| 1606 | /* Remove all matching breakpoints. */ |
| 1607 | void cpu_breakpoint_remove_all(CPUState *env, int mask) |
| 1608 | { |
| 1609 | #if defined(TARGET_HAS_ICE) |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1610 | CPUBreakpoint *bp, *next; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1611 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1612 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1613 | if (bp->flags & mask) |
| 1614 | cpu_breakpoint_remove_by_ref(env, bp); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1615 | } |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1616 | #endif |
| 1617 | } |
| 1618 | |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1619 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
| 1620 | CPU loop after each instruction */ |
| 1621 | void cpu_single_step(CPUState *env, int enabled) |
| 1622 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1623 | #if defined(TARGET_HAS_ICE) |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1624 | if (env->singlestep_enabled != enabled) { |
| 1625 | env->singlestep_enabled = enabled; |
aliguori | e22a25c | 2009-03-12 20:12:48 +0000 | [diff] [blame] | 1626 | if (kvm_enabled()) |
| 1627 | kvm_update_guest_debug(env, 0); |
| 1628 | else { |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 1629 | /* must flush all the translated code to avoid inconsistencies */ |
aliguori | e22a25c | 2009-03-12 20:12:48 +0000 | [diff] [blame] | 1630 | /* XXX: only flush what is necessary */ |
| 1631 | tb_flush(env); |
| 1632 | } |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1633 | } |
| 1634 | #endif |
| 1635 | } |
| 1636 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1637 | /* enable or disable low levels log */ |
| 1638 | void cpu_set_log(int log_flags) |
| 1639 | { |
| 1640 | loglevel = log_flags; |
| 1641 | if (loglevel && !logfile) { |
pbrook | 11fcfab | 2007-07-01 18:21:11 +0000 | [diff] [blame] | 1642 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1643 | if (!logfile) { |
| 1644 | perror(logfilename); |
| 1645 | _exit(1); |
| 1646 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1647 | #if !defined(CONFIG_SOFTMMU) |
| 1648 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ |
| 1649 | { |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 1650 | static char logfile_buf[4096]; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1651 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
| 1652 | } |
Stefan Weil | daf767b | 2011-12-03 22:32:37 +0100 | [diff] [blame] | 1653 | #elif defined(_WIN32) |
| 1654 | /* Win32 doesn't support line-buffering, so use unbuffered output. */ |
| 1655 | setvbuf(logfile, NULL, _IONBF, 0); |
| 1656 | #else |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1657 | setvbuf(logfile, NULL, _IOLBF, 0); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1658 | #endif |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 1659 | log_append = 1; |
| 1660 | } |
| 1661 | if (!loglevel && logfile) { |
| 1662 | fclose(logfile); |
| 1663 | logfile = NULL; |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1664 | } |
| 1665 | } |
| 1666 | |
| 1667 | void cpu_set_log_filename(const char *filename) |
| 1668 | { |
| 1669 | logfilename = strdup(filename); |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 1670 | if (logfile) { |
| 1671 | fclose(logfile); |
| 1672 | logfile = NULL; |
| 1673 | } |
| 1674 | cpu_set_log(loglevel); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1675 | } |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1676 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1677 | static void cpu_unlink_tb(CPUState *env) |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1678 | { |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 1679 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
| 1680 | problem and hope the cpu will stop of its own accord. For userspace |
| 1681 | emulation this often isn't actually as bad as it sounds. Often |
| 1682 | signals are used primarily to interrupt blocking syscalls. */ |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1683 | TranslationBlock *tb; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1684 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1685 | |
Riku Voipio | cab1b4b | 2010-01-20 12:56:27 +0200 | [diff] [blame] | 1686 | spin_lock(&interrupt_lock); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1687 | tb = env->current_tb; |
| 1688 | /* if the cpu is currently executing code, we must unlink it and |
| 1689 | all the potentially executing TB */ |
Riku Voipio | f76cfe5 | 2009-12-04 15:16:30 +0200 | [diff] [blame] | 1690 | if (tb) { |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1691 | env->current_tb = NULL; |
| 1692 | tb_reset_jump_recursive(tb); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1693 | } |
Riku Voipio | cab1b4b | 2010-01-20 12:56:27 +0200 | [diff] [blame] | 1694 | spin_unlock(&interrupt_lock); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1695 | } |
| 1696 | |
Jan Kiszka | 97ffbd8 | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 1697 | #ifndef CONFIG_USER_ONLY |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1698 | /* mask must never be zero, except for A20 change call */ |
Jan Kiszka | ec6959d | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 1699 | static void tcg_handle_interrupt(CPUState *env, int mask) |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1700 | { |
| 1701 | int old_mask; |
| 1702 | |
| 1703 | old_mask = env->interrupt_request; |
| 1704 | env->interrupt_request |= mask; |
| 1705 | |
aliguori | 8edac96 | 2009-04-24 18:03:45 +0000 | [diff] [blame] | 1706 | /* |
| 1707 | * If called from iothread context, wake the target cpu in |
| 1708 | * case its halted. |
| 1709 | */ |
Jan Kiszka | b7680cb | 2011-03-12 17:43:51 +0100 | [diff] [blame] | 1710 | if (!qemu_cpu_is_self(env)) { |
aliguori | 8edac96 | 2009-04-24 18:03:45 +0000 | [diff] [blame] | 1711 | qemu_cpu_kick(env); |
| 1712 | return; |
| 1713 | } |
aliguori | 8edac96 | 2009-04-24 18:03:45 +0000 | [diff] [blame] | 1714 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1715 | if (use_icount) { |
pbrook | 266910c | 2008-07-09 15:31:50 +0000 | [diff] [blame] | 1716 | env->icount_decr.u16.high = 0xffff; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1717 | if (!can_do_io(env) |
aurel32 | be214e6 | 2009-03-06 21:48:00 +0000 | [diff] [blame] | 1718 | && (mask & ~old_mask) != 0) { |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1719 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
| 1720 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1721 | } else { |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1722 | cpu_unlink_tb(env); |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1723 | } |
| 1724 | } |
| 1725 | |
Jan Kiszka | ec6959d | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 1726 | CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; |
| 1727 | |
Jan Kiszka | 97ffbd8 | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 1728 | #else /* CONFIG_USER_ONLY */ |
| 1729 | |
| 1730 | void cpu_interrupt(CPUState *env, int mask) |
| 1731 | { |
| 1732 | env->interrupt_request |= mask; |
| 1733 | cpu_unlink_tb(env); |
| 1734 | } |
| 1735 | #endif /* CONFIG_USER_ONLY */ |
| 1736 | |
bellard | b54ad04 | 2004-05-20 13:42:52 +0000 | [diff] [blame] | 1737 | void cpu_reset_interrupt(CPUState *env, int mask) |
| 1738 | { |
| 1739 | env->interrupt_request &= ~mask; |
| 1740 | } |
| 1741 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1742 | void cpu_exit(CPUState *env) |
| 1743 | { |
| 1744 | env->exit_request = 1; |
| 1745 | cpu_unlink_tb(env); |
| 1746 | } |
| 1747 | |
blueswir1 | c7cd6a3 | 2008-10-02 18:27:46 +0000 | [diff] [blame] | 1748 | const CPULogItem cpu_log_items[] = { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1749 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1750 | "show generated host assembly code for each compiled TB" }, |
| 1751 | { CPU_LOG_TB_IN_ASM, "in_asm", |
| 1752 | "show target assembly code for each compiled TB" }, |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1753 | { CPU_LOG_TB_OP, "op", |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 1754 | "show micro ops for each compiled TB" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1755 | { CPU_LOG_TB_OP_OPT, "op_opt", |
blueswir1 | e01a115 | 2008-03-14 17:37:11 +0000 | [diff] [blame] | 1756 | "show micro ops " |
| 1757 | #ifdef TARGET_I386 |
| 1758 | "before eflags optimization and " |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1759 | #endif |
blueswir1 | e01a115 | 2008-03-14 17:37:11 +0000 | [diff] [blame] | 1760 | "after liveness analysis" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1761 | { CPU_LOG_INT, "int", |
| 1762 | "show interrupts/exceptions in short format" }, |
| 1763 | { CPU_LOG_EXEC, "exec", |
| 1764 | "show trace before each executed TB (lots of logs)" }, |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1765 | { CPU_LOG_TB_CPU, "cpu", |
ths | e91c8a7 | 2007-06-03 13:35:16 +0000 | [diff] [blame] | 1766 | "show CPU state before block translation" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1767 | #ifdef TARGET_I386 |
| 1768 | { CPU_LOG_PCALL, "pcall", |
| 1769 | "show protected mode far calls/returns/exceptions" }, |
aliguori | eca1bdf | 2009-01-26 19:54:31 +0000 | [diff] [blame] | 1770 | { CPU_LOG_RESET, "cpu_reset", |
| 1771 | "show CPU state before CPU resets" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1772 | #endif |
bellard | 8e3a9fd | 2004-10-09 17:32:58 +0000 | [diff] [blame] | 1773 | #ifdef DEBUG_IOPORT |
bellard | fd87259 | 2004-05-12 19:11:15 +0000 | [diff] [blame] | 1774 | { CPU_LOG_IOPORT, "ioport", |
| 1775 | "show all i/o ports accesses" }, |
bellard | 8e3a9fd | 2004-10-09 17:32:58 +0000 | [diff] [blame] | 1776 | #endif |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1777 | { 0, NULL, NULL }, |
| 1778 | }; |
| 1779 | |
| 1780 | static int cmp1(const char *s1, int n, const char *s2) |
| 1781 | { |
| 1782 | if (strlen(s2) != n) |
| 1783 | return 0; |
| 1784 | return memcmp(s1, s2, n) == 0; |
| 1785 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1786 | |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1787 | /* takes a comma separated list of log masks. Return 0 if error. */ |
| 1788 | int cpu_str_to_log_mask(const char *str) |
| 1789 | { |
blueswir1 | c7cd6a3 | 2008-10-02 18:27:46 +0000 | [diff] [blame] | 1790 | const CPULogItem *item; |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1791 | int mask; |
| 1792 | const char *p, *p1; |
| 1793 | |
| 1794 | p = str; |
| 1795 | mask = 0; |
| 1796 | for(;;) { |
| 1797 | p1 = strchr(p, ','); |
| 1798 | if (!p1) |
| 1799 | p1 = p + strlen(p); |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1800 | if(cmp1(p,p1-p,"all")) { |
| 1801 | for(item = cpu_log_items; item->mask != 0; item++) { |
| 1802 | mask |= item->mask; |
| 1803 | } |
| 1804 | } else { |
| 1805 | for(item = cpu_log_items; item->mask != 0; item++) { |
| 1806 | if (cmp1(p, p1 - p, item->name)) |
| 1807 | goto found; |
| 1808 | } |
| 1809 | return 0; |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1810 | } |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1811 | found: |
| 1812 | mask |= item->mask; |
| 1813 | if (*p1 != ',') |
| 1814 | break; |
| 1815 | p = p1 + 1; |
| 1816 | } |
| 1817 | return mask; |
| 1818 | } |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1819 | |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1820 | void cpu_abort(CPUState *env, const char *fmt, ...) |
| 1821 | { |
| 1822 | va_list ap; |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1823 | va_list ap2; |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1824 | |
| 1825 | va_start(ap, fmt); |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1826 | va_copy(ap2, ap); |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1827 | fprintf(stderr, "qemu: fatal: "); |
| 1828 | vfprintf(stderr, fmt, ap); |
| 1829 | fprintf(stderr, "\n"); |
| 1830 | #ifdef TARGET_I386 |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 1831 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
| 1832 | #else |
| 1833 | cpu_dump_state(env, stderr, fprintf, 0); |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1834 | #endif |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1835 | if (qemu_log_enabled()) { |
| 1836 | qemu_log("qemu: fatal: "); |
| 1837 | qemu_log_vprintf(fmt, ap2); |
| 1838 | qemu_log("\n"); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1839 | #ifdef TARGET_I386 |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1840 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1841 | #else |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1842 | log_cpu_state(env, 0); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1843 | #endif |
aliguori | 31b1a7b | 2009-01-15 22:35:09 +0000 | [diff] [blame] | 1844 | qemu_log_flush(); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1845 | qemu_log_close(); |
balrog | 924edca | 2007-06-10 14:07:13 +0000 | [diff] [blame] | 1846 | } |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1847 | va_end(ap2); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1848 | va_end(ap); |
Riku Voipio | fd052bf | 2010-01-25 14:30:49 +0200 | [diff] [blame] | 1849 | #if defined(CONFIG_USER_ONLY) |
| 1850 | { |
| 1851 | struct sigaction act; |
| 1852 | sigfillset(&act.sa_mask); |
| 1853 | act.sa_handler = SIG_DFL; |
| 1854 | sigaction(SIGABRT, &act, NULL); |
| 1855 | } |
| 1856 | #endif |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1857 | abort(); |
| 1858 | } |
| 1859 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1860 | CPUState *cpu_copy(CPUState *env) |
| 1861 | { |
ths | 01ba981 | 2007-12-09 02:22:57 +0000 | [diff] [blame] | 1862 | CPUState *new_env = cpu_init(env->cpu_model_str); |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1863 | CPUState *next_cpu = new_env->next_cpu; |
| 1864 | int cpu_index = new_env->cpu_index; |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1865 | #if defined(TARGET_HAS_ICE) |
| 1866 | CPUBreakpoint *bp; |
| 1867 | CPUWatchpoint *wp; |
| 1868 | #endif |
| 1869 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1870 | memcpy(new_env, env, sizeof(CPUState)); |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1871 | |
| 1872 | /* Preserve chaining and index. */ |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1873 | new_env->next_cpu = next_cpu; |
| 1874 | new_env->cpu_index = cpu_index; |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1875 | |
| 1876 | /* Clone all break/watchpoints. |
| 1877 | Note: Once we support ptrace with hw-debug register access, make sure |
| 1878 | BP_CPU break/watchpoints are handled correctly on clone. */ |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1879 | QTAILQ_INIT(&env->breakpoints); |
| 1880 | QTAILQ_INIT(&env->watchpoints); |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1881 | #if defined(TARGET_HAS_ICE) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1882 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1883 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
| 1884 | } |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1885 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1886 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
| 1887 | wp->flags, NULL); |
| 1888 | } |
| 1889 | #endif |
| 1890 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1891 | return new_env; |
| 1892 | } |
| 1893 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1894 | #if !defined(CONFIG_USER_ONLY) |
| 1895 | |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1896 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
| 1897 | { |
| 1898 | unsigned int i; |
| 1899 | |
| 1900 | /* Discard jump cache entries for any tb which might potentially |
| 1901 | overlap the flushed page. */ |
| 1902 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); |
| 1903 | memset (&env->tb_jmp_cache[i], 0, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1904 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1905 | |
| 1906 | i = tb_jmp_cache_hash_page(addr); |
| 1907 | memset (&env->tb_jmp_cache[i], 0, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1908 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1909 | } |
| 1910 | |
Igor Kovalenko | 0873898 | 2009-07-12 02:15:40 +0400 | [diff] [blame] | 1911 | static CPUTLBEntry s_cputlb_empty_entry = { |
| 1912 | .addr_read = -1, |
| 1913 | .addr_write = -1, |
| 1914 | .addr_code = -1, |
| 1915 | .addend = -1, |
| 1916 | }; |
| 1917 | |
Peter Maydell | 771124e | 2012-01-17 13:23:13 +0000 | [diff] [blame] | 1918 | /* NOTE: |
| 1919 | * If flush_global is true (the usual case), flush all tlb entries. |
| 1920 | * If flush_global is false, flush (at least) all tlb entries not |
| 1921 | * marked global. |
| 1922 | * |
| 1923 | * Since QEMU doesn't currently implement a global/not-global flag |
| 1924 | * for tlb entries, at the moment tlb_flush() will also flush all |
| 1925 | * tlb entries in the flush_global == false case. This is OK because |
| 1926 | * CPU architectures generally permit an implementation to drop |
| 1927 | * entries from the TLB at any time, so flushing more entries than |
| 1928 | * required is only an efficiency issue, not a correctness issue. |
| 1929 | */ |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 1930 | void tlb_flush(CPUState *env, int flush_global) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1931 | { |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1932 | int i; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1933 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1934 | #if defined(DEBUG_TLB) |
| 1935 | printf("tlb_flush:\n"); |
| 1936 | #endif |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1937 | /* must reset current TB so that interrupts cannot modify the |
| 1938 | links while we are modifying them */ |
| 1939 | env->current_tb = NULL; |
| 1940 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1941 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 1942 | int mmu_idx; |
| 1943 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
Igor Kovalenko | 0873898 | 2009-07-12 02:15:40 +0400 | [diff] [blame] | 1944 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 1945 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1946 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1947 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1948 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1949 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 1950 | env->tlb_flush_addr = -1; |
| 1951 | env->tlb_flush_mask = 0; |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 1952 | tlb_flush_count++; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1953 | } |
| 1954 | |
bellard | 274da6b | 2004-05-20 21:56:27 +0000 | [diff] [blame] | 1955 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1956 | { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1957 | if (addr == (tlb_entry->addr_read & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1958 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1959 | addr == (tlb_entry->addr_write & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1960 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1961 | addr == (tlb_entry->addr_code & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1962 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
Igor Kovalenko | 0873898 | 2009-07-12 02:15:40 +0400 | [diff] [blame] | 1963 | *tlb_entry = s_cputlb_empty_entry; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1964 | } |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1965 | } |
| 1966 | |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 1967 | void tlb_flush_page(CPUState *env, target_ulong addr) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1968 | { |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1969 | int i; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 1970 | int mmu_idx; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1971 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1972 | #if defined(DEBUG_TLB) |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 1973 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1974 | #endif |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 1975 | /* Check if we need to flush due to large pages. */ |
| 1976 | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) { |
| 1977 | #if defined(DEBUG_TLB) |
| 1978 | printf("tlb_flush_page: forced full flush (" |
| 1979 | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", |
| 1980 | env->tlb_flush_addr, env->tlb_flush_mask); |
| 1981 | #endif |
| 1982 | tlb_flush(env, 1); |
| 1983 | return; |
| 1984 | } |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1985 | /* must reset current TB so that interrupts cannot modify the |
| 1986 | links while we are modifying them */ |
| 1987 | env->current_tb = NULL; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1988 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1989 | addr &= TARGET_PAGE_MASK; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1990 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 1991 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
| 1992 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1993 | |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1994 | tlb_flush_jmp_cache(env, addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1995 | } |
| 1996 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1997 | /* update the TLBs so that writes to code in the virtual page 'addr' |
| 1998 | can be detected */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1999 | static void tlb_protect_code(ram_addr_t ram_addr) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 2000 | { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2001 | cpu_physical_memory_reset_dirty(ram_addr, |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2002 | ram_addr + TARGET_PAGE_SIZE, |
| 2003 | CODE_DIRTY_FLAG); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2004 | } |
| 2005 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2006 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2007 | tested for self modifying code */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2008 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2009 | target_ulong vaddr) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2010 | { |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 2011 | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2012 | } |
| 2013 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2014 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2015 | unsigned long start, unsigned long length) |
| 2016 | { |
| 2017 | unsigned long addr; |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 2018 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr) { |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2019 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2020 | if ((addr - start) < length) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2021 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2022 | } |
| 2023 | } |
| 2024 | } |
| 2025 | |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2026 | /* Note: start and end must be within the same ram block. */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2027 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 2028 | int dirty_flags) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2029 | { |
| 2030 | CPUState *env; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 2031 | unsigned long length, start1; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 2032 | int i; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2033 | |
| 2034 | start &= TARGET_PAGE_MASK; |
| 2035 | end = TARGET_PAGE_ALIGN(end); |
| 2036 | |
| 2037 | length = end - start; |
| 2038 | if (length == 0) |
| 2039 | return; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 2040 | cpu_physical_memory_mask_dirty_range(start, length, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 2041 | |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2042 | /* we modify the TLB cache so that the dirty bit will be set again |
| 2043 | when accessing the range */ |
Michael S. Tsirkin | b2e0a13 | 2010-11-22 19:52:34 +0200 | [diff] [blame] | 2044 | start1 = (unsigned long)qemu_safe_ram_ptr(start); |
Stefan Weil | a57d23e | 2011-04-30 22:49:26 +0200 | [diff] [blame] | 2045 | /* Check that we don't span multiple blocks - this breaks the |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2046 | address comparisons below. */ |
Michael S. Tsirkin | b2e0a13 | 2010-11-22 19:52:34 +0200 | [diff] [blame] | 2047 | if ((unsigned long)qemu_safe_ram_ptr(end - 1) - start1 |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2048 | != (end - 1) - start) { |
| 2049 | abort(); |
| 2050 | } |
| 2051 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2052 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2053 | int mmu_idx; |
| 2054 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
| 2055 | for(i = 0; i < CPU_TLB_SIZE; i++) |
| 2056 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], |
| 2057 | start1, length); |
| 2058 | } |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2059 | } |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2060 | } |
| 2061 | |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2062 | int cpu_physical_memory_set_dirty_tracking(int enable) |
| 2063 | { |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2064 | int ret = 0; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2065 | in_migration = enable; |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2066 | return ret; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2067 | } |
| 2068 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2069 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
| 2070 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2071 | ram_addr_t ram_addr; |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2072 | void *p; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2073 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 2074 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr) { |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2075 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
| 2076 | + tlb_entry->addend); |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 2077 | ram_addr = qemu_ram_addr_from_host_nofail(p); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2078 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2079 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2080 | } |
| 2081 | } |
| 2082 | } |
| 2083 | |
| 2084 | /* update the TLB according to the current state of the dirty bits */ |
| 2085 | void cpu_tlb_update_dirty(CPUState *env) |
| 2086 | { |
| 2087 | int i; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2088 | int mmu_idx; |
| 2089 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
| 2090 | for(i = 0; i < CPU_TLB_SIZE; i++) |
| 2091 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); |
| 2092 | } |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2093 | } |
| 2094 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2095 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2096 | { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2097 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
| 2098 | tlb_entry->addr_write = vaddr; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2099 | } |
| 2100 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2101 | /* update the TLB corresponding to virtual page vaddr |
| 2102 | so that it is no longer dirty */ |
| 2103 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2104 | { |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2105 | int i; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2106 | int mmu_idx; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2107 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2108 | vaddr &= TARGET_PAGE_MASK; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2109 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2110 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
| 2111 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2112 | } |
| 2113 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 2114 | /* Our TLB does not support large pages, so remember the area covered by |
| 2115 | large pages and trigger a full TLB flush if these are invalidated. */ |
| 2116 | static void tlb_add_large_page(CPUState *env, target_ulong vaddr, |
| 2117 | target_ulong size) |
| 2118 | { |
| 2119 | target_ulong mask = ~(size - 1); |
| 2120 | |
| 2121 | if (env->tlb_flush_addr == (target_ulong)-1) { |
| 2122 | env->tlb_flush_addr = vaddr & mask; |
| 2123 | env->tlb_flush_mask = mask; |
| 2124 | return; |
| 2125 | } |
| 2126 | /* Extend the existing region to include the new page. |
| 2127 | This is a compromise between unnecessary flushes and the cost |
| 2128 | of maintaining a full variable size TLB. */ |
| 2129 | mask &= env->tlb_flush_mask; |
| 2130 | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { |
| 2131 | mask <<= 1; |
| 2132 | } |
| 2133 | env->tlb_flush_addr &= mask; |
| 2134 | env->tlb_flush_mask = mask; |
| 2135 | } |
| 2136 | |
Avi Kivity | 1d393fa | 2012-01-01 21:15:42 +0200 | [diff] [blame] | 2137 | static bool is_ram_rom(ram_addr_t pd) |
| 2138 | { |
| 2139 | pd &= ~TARGET_PAGE_MASK; |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 2140 | return pd == io_mem_ram.ram_addr || pd == io_mem_rom.ram_addr; |
Avi Kivity | 1d393fa | 2012-01-01 21:15:42 +0200 | [diff] [blame] | 2141 | } |
| 2142 | |
Avi Kivity | 75c578d | 2012-01-02 15:40:52 +0200 | [diff] [blame] | 2143 | static bool is_romd(ram_addr_t pd) |
| 2144 | { |
| 2145 | MemoryRegion *mr; |
| 2146 | |
| 2147 | pd &= ~TARGET_PAGE_MASK; |
Avi Kivity | 11c7ef0 | 2012-01-02 17:21:07 +0200 | [diff] [blame] | 2148 | mr = io_mem_region[pd]; |
Avi Kivity | 75c578d | 2012-01-02 15:40:52 +0200 | [diff] [blame] | 2149 | return mr->rom_device && mr->readable; |
| 2150 | } |
| 2151 | |
Avi Kivity | 1d393fa | 2012-01-01 21:15:42 +0200 | [diff] [blame] | 2152 | static bool is_ram_rom_romd(ram_addr_t pd) |
| 2153 | { |
Avi Kivity | 75c578d | 2012-01-02 15:40:52 +0200 | [diff] [blame] | 2154 | return is_ram_rom(pd) || is_romd(pd); |
Avi Kivity | 1d393fa | 2012-01-01 21:15:42 +0200 | [diff] [blame] | 2155 | } |
| 2156 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 2157 | /* Add a new TLB entry. At most one entry for a given virtual address |
| 2158 | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the |
| 2159 | supplied size is only used by tlb_flush_page. */ |
| 2160 | void tlb_set_page(CPUState *env, target_ulong vaddr, |
| 2161 | target_phys_addr_t paddr, int prot, |
| 2162 | int mmu_idx, target_ulong size) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2163 | { |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 2164 | PhysPageDesc p; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 2165 | unsigned long pd; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2166 | unsigned int index; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 2167 | target_ulong address; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2168 | target_ulong code_address; |
Paul Brook | 355b194 | 2010-04-05 00:28:53 +0100 | [diff] [blame] | 2169 | unsigned long addend; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2170 | CPUTLBEntry *te; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 2171 | CPUWatchpoint *wp; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2172 | target_phys_addr_t iotlb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2173 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 2174 | assert(size >= TARGET_PAGE_SIZE); |
| 2175 | if (size != TARGET_PAGE_SIZE) { |
| 2176 | tlb_add_large_page(env, vaddr, size); |
| 2177 | } |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2178 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 2179 | pd = p.phys_offset; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2180 | #if defined(DEBUG_TLB) |
Stefan Weil | 7fd3f49 | 2010-09-30 22:39:51 +0200 | [diff] [blame] | 2181 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx |
| 2182 | " prot=%x idx=%d pd=0x%08lx\n", |
| 2183 | vaddr, paddr, prot, mmu_idx, pd); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2184 | #endif |
| 2185 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2186 | address = vaddr; |
Avi Kivity | 1d393fa | 2012-01-01 21:15:42 +0200 | [diff] [blame] | 2187 | if (!is_ram_rom_romd(pd)) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2188 | /* IO memory case (romd handled later) */ |
| 2189 | address |= TLB_MMIO; |
| 2190 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2191 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
Avi Kivity | 1d393fa | 2012-01-01 21:15:42 +0200 | [diff] [blame] | 2192 | if (is_ram_rom(pd)) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2193 | /* Normal RAM. */ |
| 2194 | iotlb = pd & TARGET_PAGE_MASK; |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 2195 | if ((pd & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr) |
| 2196 | iotlb |= io_mem_notdirty.ram_addr; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2197 | else |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 2198 | iotlb |= io_mem_rom.ram_addr; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2199 | } else { |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 2200 | /* IO handlers are currently passed a physical address. |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2201 | It would be nice to pass an offset from the base address |
| 2202 | of that region. This would avoid having to special case RAM, |
| 2203 | and avoid full address decoding in every device. |
| 2204 | We can't use the high bits of pd for this because |
| 2205 | IO_MEM_ROMD uses these as a ram address. */ |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2206 | iotlb = (pd & ~TARGET_PAGE_MASK); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 2207 | iotlb += p.region_offset; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2208 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2209 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2210 | code_address = address; |
| 2211 | /* Make accesses to pages with watchpoints go via the |
| 2212 | watchpoint trap routines. */ |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 2213 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 2214 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
Jun Koi | bf298f8 | 2010-05-06 14:36:59 +0900 | [diff] [blame] | 2215 | /* Avoid trapping reads of pages with a write breakpoint. */ |
| 2216 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 2217 | iotlb = io_mem_watch.ram_addr + paddr; |
Jun Koi | bf298f8 | 2010-05-06 14:36:59 +0900 | [diff] [blame] | 2218 | address |= TLB_MMIO; |
| 2219 | break; |
| 2220 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2221 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2222 | } |
balrog | d79acba | 2007-06-26 20:01:13 +0000 | [diff] [blame] | 2223 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2224 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
| 2225 | env->iotlb[mmu_idx][index] = iotlb - vaddr; |
| 2226 | te = &env->tlb_table[mmu_idx][index]; |
| 2227 | te->addend = addend - vaddr; |
| 2228 | if (prot & PAGE_READ) { |
| 2229 | te->addr_read = address; |
| 2230 | } else { |
| 2231 | te->addr_read = -1; |
| 2232 | } |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 2233 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2234 | if (prot & PAGE_EXEC) { |
| 2235 | te->addr_code = code_address; |
| 2236 | } else { |
| 2237 | te->addr_code = -1; |
| 2238 | } |
| 2239 | if (prot & PAGE_WRITE) { |
Avi Kivity | 75c578d | 2012-01-02 15:40:52 +0200 | [diff] [blame] | 2240 | if ((pd & ~TARGET_PAGE_MASK) == io_mem_rom.ram_addr || is_romd(pd)) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2241 | /* Write access calls the I/O callback. */ |
| 2242 | te->addr_write = address | TLB_MMIO; |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 2243 | } else if ((pd & ~TARGET_PAGE_MASK) == io_mem_ram.ram_addr && |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2244 | !cpu_physical_memory_is_dirty(pd)) { |
| 2245 | te->addr_write = address | TLB_NOTDIRTY; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2246 | } else { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2247 | te->addr_write = address; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2248 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2249 | } else { |
| 2250 | te->addr_write = -1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2251 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2252 | } |
| 2253 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2254 | #else |
| 2255 | |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 2256 | void tlb_flush(CPUState *env, int flush_global) |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2257 | { |
| 2258 | } |
| 2259 | |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 2260 | void tlb_flush_page(CPUState *env, target_ulong addr) |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2261 | { |
| 2262 | } |
| 2263 | |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2264 | /* |
| 2265 | * Walks guest process memory "regions" one by one |
| 2266 | * and calls callback function 'fn' for each region. |
| 2267 | */ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2268 | |
| 2269 | struct walk_memory_regions_data |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2270 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2271 | walk_memory_regions_fn fn; |
| 2272 | void *priv; |
| 2273 | unsigned long start; |
| 2274 | int prot; |
| 2275 | }; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2276 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2277 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2278 | abi_ulong end, int new_prot) |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2279 | { |
| 2280 | if (data->start != -1ul) { |
| 2281 | int rc = data->fn(data->priv, data->start, end, data->prot); |
| 2282 | if (rc != 0) { |
| 2283 | return rc; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2284 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2285 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2286 | |
| 2287 | data->start = (new_prot ? end : -1ul); |
| 2288 | data->prot = new_prot; |
| 2289 | |
| 2290 | return 0; |
| 2291 | } |
| 2292 | |
| 2293 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2294 | abi_ulong base, int level, void **lp) |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2295 | { |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2296 | abi_ulong pa; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2297 | int i, rc; |
| 2298 | |
| 2299 | if (*lp == NULL) { |
| 2300 | return walk_memory_regions_end(data, base, 0); |
| 2301 | } |
| 2302 | |
| 2303 | if (level == 0) { |
| 2304 | PageDesc *pd = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 2305 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2306 | int prot = pd[i].flags; |
| 2307 | |
| 2308 | pa = base | (i << TARGET_PAGE_BITS); |
| 2309 | if (prot != data->prot) { |
| 2310 | rc = walk_memory_regions_end(data, pa, prot); |
| 2311 | if (rc != 0) { |
| 2312 | return rc; |
| 2313 | } |
| 2314 | } |
| 2315 | } |
| 2316 | } else { |
| 2317 | void **pp = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 2318 | for (i = 0; i < L2_SIZE; ++i) { |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2319 | pa = base | ((abi_ulong)i << |
| 2320 | (TARGET_PAGE_BITS + L2_BITS * level)); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2321 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
| 2322 | if (rc != 0) { |
| 2323 | return rc; |
| 2324 | } |
| 2325 | } |
| 2326 | } |
| 2327 | |
| 2328 | return 0; |
| 2329 | } |
| 2330 | |
| 2331 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) |
| 2332 | { |
| 2333 | struct walk_memory_regions_data data; |
| 2334 | unsigned long i; |
| 2335 | |
| 2336 | data.fn = fn; |
| 2337 | data.priv = priv; |
| 2338 | data.start = -1ul; |
| 2339 | data.prot = 0; |
| 2340 | |
| 2341 | for (i = 0; i < V_L1_SIZE; i++) { |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2342 | int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT, |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2343 | V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
| 2344 | if (rc != 0) { |
| 2345 | return rc; |
| 2346 | } |
| 2347 | } |
| 2348 | |
| 2349 | return walk_memory_regions_end(&data, 0, 0); |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2350 | } |
| 2351 | |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2352 | static int dump_region(void *priv, abi_ulong start, |
| 2353 | abi_ulong end, unsigned long prot) |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2354 | { |
| 2355 | FILE *f = (FILE *)priv; |
| 2356 | |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2357 | (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx |
| 2358 | " "TARGET_ABI_FMT_lx" %c%c%c\n", |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2359 | start, end, end - start, |
| 2360 | ((prot & PAGE_READ) ? 'r' : '-'), |
| 2361 | ((prot & PAGE_WRITE) ? 'w' : '-'), |
| 2362 | ((prot & PAGE_EXEC) ? 'x' : '-')); |
| 2363 | |
| 2364 | return (0); |
| 2365 | } |
| 2366 | |
| 2367 | /* dump memory mappings */ |
| 2368 | void page_dump(FILE *f) |
| 2369 | { |
| 2370 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", |
| 2371 | "start", "end", "size", "prot"); |
| 2372 | walk_memory_regions(f, dump_region); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2373 | } |
| 2374 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2375 | int page_get_flags(target_ulong address) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2376 | { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2377 | PageDesc *p; |
| 2378 | |
| 2379 | p = page_find(address >> TARGET_PAGE_BITS); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2380 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2381 | return 0; |
| 2382 | return p->flags; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2383 | } |
| 2384 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2385 | /* Modify the flags of a page and invalidate the code if necessary. |
| 2386 | The flag PAGE_WRITE_ORG is positioned automatically depending |
| 2387 | on PAGE_WRITE. The mmap_lock should already be held. */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2388 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2389 | { |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2390 | target_ulong addr, len; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2391 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2392 | /* This function should never be called with addresses outside the |
| 2393 | guest address space. If this assert fires, it probably indicates |
| 2394 | a missing call to h2g_valid. */ |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2395 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
| 2396 | assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2397 | #endif |
| 2398 | assert(start < end); |
| 2399 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2400 | start = start & TARGET_PAGE_MASK; |
| 2401 | end = TARGET_PAGE_ALIGN(end); |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2402 | |
| 2403 | if (flags & PAGE_WRITE) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2404 | flags |= PAGE_WRITE_ORG; |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2405 | } |
| 2406 | |
| 2407 | for (addr = start, len = end - start; |
| 2408 | len != 0; |
| 2409 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { |
| 2410 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); |
| 2411 | |
| 2412 | /* If the write protection bit is set, then we invalidate |
| 2413 | the code inside. */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2414 | if (!(p->flags & PAGE_WRITE) && |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2415 | (flags & PAGE_WRITE) && |
| 2416 | p->first_tb) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 2417 | tb_invalidate_phys_page(addr, 0, NULL); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2418 | } |
| 2419 | p->flags = flags; |
| 2420 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2421 | } |
| 2422 | |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2423 | int page_check_range(target_ulong start, target_ulong len, int flags) |
| 2424 | { |
| 2425 | PageDesc *p; |
| 2426 | target_ulong end; |
| 2427 | target_ulong addr; |
| 2428 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2429 | /* This function should never be called with addresses outside the |
| 2430 | guest address space. If this assert fires, it probably indicates |
| 2431 | a missing call to h2g_valid. */ |
Blue Swirl | 338e9e6 | 2010-03-13 09:48:08 +0000 | [diff] [blame] | 2432 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
| 2433 | assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2434 | #endif |
| 2435 | |
Richard Henderson | 3e0650a | 2010-03-29 10:54:42 -0700 | [diff] [blame] | 2436 | if (len == 0) { |
| 2437 | return 0; |
| 2438 | } |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2439 | if (start + len - 1 < start) { |
| 2440 | /* We've wrapped around. */ |
balrog | 55f280c | 2008-10-28 10:24:11 +0000 | [diff] [blame] | 2441 | return -1; |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2442 | } |
balrog | 55f280c | 2008-10-28 10:24:11 +0000 | [diff] [blame] | 2443 | |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2444 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
| 2445 | start = start & TARGET_PAGE_MASK; |
| 2446 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2447 | for (addr = start, len = end - start; |
| 2448 | len != 0; |
| 2449 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2450 | p = page_find(addr >> TARGET_PAGE_BITS); |
| 2451 | if( !p ) |
| 2452 | return -1; |
| 2453 | if( !(p->flags & PAGE_VALID) ) |
| 2454 | return -1; |
| 2455 | |
bellard | dae3270 | 2007-11-14 10:51:00 +0000 | [diff] [blame] | 2456 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2457 | return -1; |
bellard | dae3270 | 2007-11-14 10:51:00 +0000 | [diff] [blame] | 2458 | if (flags & PAGE_WRITE) { |
| 2459 | if (!(p->flags & PAGE_WRITE_ORG)) |
| 2460 | return -1; |
| 2461 | /* unprotect the page if it was put read-only because it |
| 2462 | contains translated code */ |
| 2463 | if (!(p->flags & PAGE_WRITE)) { |
| 2464 | if (!page_unprotect(addr, 0, NULL)) |
| 2465 | return -1; |
| 2466 | } |
| 2467 | return 0; |
| 2468 | } |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2469 | } |
| 2470 | return 0; |
| 2471 | } |
| 2472 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2473 | /* called from signal handler: invalidate the code and unprotect the |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 2474 | page. Return TRUE if the fault was successfully handled. */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2475 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2476 | { |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2477 | unsigned int prot; |
| 2478 | PageDesc *p; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2479 | target_ulong host_start, host_end, addr; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2480 | |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2481 | /* Technically this isn't safe inside a signal handler. However we |
| 2482 | know this only ever happens in a synchronous SEGV handler, so in |
| 2483 | practice it seems to be ok. */ |
| 2484 | mmap_lock(); |
| 2485 | |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2486 | p = page_find(address >> TARGET_PAGE_BITS); |
| 2487 | if (!p) { |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2488 | mmap_unlock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2489 | return 0; |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2490 | } |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2491 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2492 | /* if the page was really writable, then we change its |
| 2493 | protection back to writable */ |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2494 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { |
| 2495 | host_start = address & qemu_host_page_mask; |
| 2496 | host_end = host_start + qemu_host_page_size; |
| 2497 | |
| 2498 | prot = 0; |
| 2499 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { |
| 2500 | p = page_find(addr >> TARGET_PAGE_BITS); |
| 2501 | p->flags |= PAGE_WRITE; |
| 2502 | prot |= p->flags; |
| 2503 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2504 | /* and since the content will be modified, we must invalidate |
| 2505 | the corresponding translated code. */ |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2506 | tb_invalidate_phys_page(addr, pc, puc); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2507 | #ifdef DEBUG_TB_CHECK |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2508 | tb_invalidate_check(addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2509 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2510 | } |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2511 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
| 2512 | prot & PAGE_BITS); |
| 2513 | |
| 2514 | mmap_unlock(); |
| 2515 | return 1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2516 | } |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2517 | mmap_unlock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2518 | return 0; |
| 2519 | } |
| 2520 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2521 | static inline void tlb_set_dirty(CPUState *env, |
| 2522 | unsigned long addr, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2523 | { |
| 2524 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2525 | #endif /* defined(CONFIG_USER_ONLY) */ |
| 2526 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 2527 | #if !defined(CONFIG_USER_ONLY) |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2528 | |
Paul Brook | c04b2b7 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 2529 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
| 2530 | typedef struct subpage_t { |
Avi Kivity | 70c68e4 | 2012-01-02 12:32:48 +0200 | [diff] [blame] | 2531 | MemoryRegion iomem; |
Paul Brook | c04b2b7 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 2532 | target_phys_addr_t base; |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2533 | uint16_t sub_section[TARGET_PAGE_SIZE]; |
Paul Brook | c04b2b7 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 2534 | } subpage_t; |
| 2535 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2536 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2537 | uint16_t section); |
| 2538 | static subpage_t *subpage_init (target_phys_addr_t base, uint16_t *section, |
| 2539 | uint16_t orig_section); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2540 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
| 2541 | need_subpage) \ |
| 2542 | do { \ |
| 2543 | if (addr > start_addr) \ |
| 2544 | start_addr2 = 0; \ |
| 2545 | else { \ |
| 2546 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ |
| 2547 | if (start_addr2 > 0) \ |
| 2548 | need_subpage = 1; \ |
| 2549 | } \ |
| 2550 | \ |
blueswir1 | 49e9fba | 2007-05-30 17:25:06 +0000 | [diff] [blame] | 2551 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2552 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
| 2553 | else { \ |
| 2554 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ |
| 2555 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ |
| 2556 | need_subpage = 1; \ |
| 2557 | } \ |
| 2558 | } while (0) |
| 2559 | |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2560 | static void destroy_page_desc(uint16_t section_index) |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 2561 | { |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2562 | MemoryRegionSection *section = &phys_sections[section_index]; |
| 2563 | MemoryRegion *mr = section->mr; |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 2564 | |
| 2565 | if (mr->subpage) { |
| 2566 | subpage_t *subpage = container_of(mr, subpage_t, iomem); |
| 2567 | memory_region_destroy(&subpage->iomem); |
| 2568 | g_free(subpage); |
| 2569 | } |
| 2570 | } |
| 2571 | |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 2572 | static void destroy_l2_mapping(PhysPageEntry *lp, unsigned level) |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 2573 | { |
| 2574 | unsigned i; |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 2575 | PhysPageEntry *p; |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 2576 | |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 2577 | if (lp->u.node == PHYS_MAP_NODE_NIL) { |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 2578 | return; |
| 2579 | } |
| 2580 | |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 2581 | p = phys_map_nodes[lp->u.node]; |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 2582 | for (i = 0; i < L2_SIZE; ++i) { |
| 2583 | if (level > 0) { |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 2584 | destroy_l2_mapping(&p[i], level - 1); |
Avi Kivity | 4346ae3 | 2012-02-10 17:00:01 +0200 | [diff] [blame] | 2585 | } else { |
| 2586 | destroy_page_desc(p[i].u.leaf); |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 2587 | } |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 2588 | } |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 2589 | lp->u.node = PHYS_MAP_NODE_NIL; |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 2590 | } |
| 2591 | |
| 2592 | static void destroy_all_mappings(void) |
| 2593 | { |
Avi Kivity | 3eef53d | 2012-02-10 14:57:31 +0200 | [diff] [blame] | 2594 | destroy_l2_mapping(&phys_map, P_L2_LEVELS - 1); |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 2595 | phys_map_nodes_reset(); |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 2596 | } |
| 2597 | |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2598 | static uint16_t phys_section_add(MemoryRegionSection *section) |
| 2599 | { |
| 2600 | if (phys_sections_nb == phys_sections_nb_alloc) { |
| 2601 | phys_sections_nb_alloc = MAX(phys_sections_nb_alloc * 2, 16); |
| 2602 | phys_sections = g_renew(MemoryRegionSection, phys_sections, |
| 2603 | phys_sections_nb_alloc); |
| 2604 | } |
| 2605 | phys_sections[phys_sections_nb] = *section; |
| 2606 | return phys_sections_nb++; |
| 2607 | } |
| 2608 | |
| 2609 | static void phys_sections_clear(void) |
| 2610 | { |
| 2611 | phys_sections_nb = 0; |
| 2612 | } |
| 2613 | |
Michael S. Tsirkin | 8f2498f | 2009-09-29 18:53:16 +0200 | [diff] [blame] | 2614 | /* register physical memory. |
| 2615 | For RAM, 'size' must be a multiple of the target page size. |
| 2616 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2617 | io memory page. The address used when calling the IO function is |
| 2618 | the offset from the start of the region, plus region_offset. Both |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 2619 | start_addr and region_offset are rounded down to a page boundary |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2620 | before calculating this offset. This should not be a problem unless |
| 2621 | the low bits of start_addr and region_offset differ. */ |
Avi Kivity | dd81124 | 2012-01-02 12:17:03 +0200 | [diff] [blame] | 2622 | void cpu_register_physical_memory_log(MemoryRegionSection *section, |
Avi Kivity | d7ec83e | 2012-02-08 17:07:26 +0200 | [diff] [blame] | 2623 | bool readonly) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2624 | { |
Avi Kivity | dd81124 | 2012-01-02 12:17:03 +0200 | [diff] [blame] | 2625 | target_phys_addr_t start_addr = section->offset_within_address_space; |
| 2626 | ram_addr_t size = section->size; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2627 | target_phys_addr_t addr, end_addr; |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2628 | uint16_t *p; |
bellard | 9d42037 | 2006-06-25 22:25:22 +0000 | [diff] [blame] | 2629 | CPUState *env; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2630 | ram_addr_t orig_size = size; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2631 | subpage_t *subpage; |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2632 | uint16_t section_index = phys_section_add(section); |
Avi Kivity | dd81124 | 2012-01-02 12:17:03 +0200 | [diff] [blame] | 2633 | |
Edgar E. Iglesias | 3b8e6a2 | 2011-04-05 13:00:36 +0200 | [diff] [blame] | 2634 | assert(size); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2635 | |
bellard | 5fd386f | 2004-05-23 21:11:22 +0000 | [diff] [blame] | 2636 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2637 | end_addr = start_addr + (target_phys_addr_t)size; |
Edgar E. Iglesias | 3b8e6a2 | 2011-04-05 13:00:36 +0200 | [diff] [blame] | 2638 | |
| 2639 | addr = start_addr; |
| 2640 | do { |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 2641 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 0); |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2642 | if (p && *p != phys_section_unassigned) { |
| 2643 | uint16_t orig_memory= *p; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2644 | target_phys_addr_t start_addr2, end_addr2; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2645 | int need_subpage = 0; |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2646 | MemoryRegion *mr = phys_sections[orig_memory].mr; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2647 | |
| 2648 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, |
| 2649 | need_subpage); |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2650 | if (need_subpage) { |
Avi Kivity | b3b00c7 | 2012-01-02 13:20:11 +0200 | [diff] [blame] | 2651 | if (!(mr->subpage)) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2652 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2653 | p, orig_memory); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2654 | } else { |
Avi Kivity | a621f38 | 2012-01-02 13:12:08 +0200 | [diff] [blame] | 2655 | subpage = container_of(mr, subpage_t, iomem); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2656 | } |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2657 | subpage_register(subpage, start_addr2, end_addr2, |
| 2658 | section_index); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2659 | } else { |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2660 | *p = section_index; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2661 | } |
| 2662 | } else { |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2663 | MemoryRegion *mr = section->mr; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2664 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2665 | *p = section_index; |
| 2666 | if (!(memory_region_is_ram(mr) || mr->rom_device)) { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2667 | target_phys_addr_t start_addr2, end_addr2; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2668 | int need_subpage = 0; |
| 2669 | |
| 2670 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, |
| 2671 | end_addr2, need_subpage); |
| 2672 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2673 | if (need_subpage) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2674 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2675 | p, phys_section_unassigned); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2676 | subpage_register(subpage, start_addr2, end_addr2, |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 2677 | section_index); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2678 | } |
| 2679 | } |
| 2680 | } |
Edgar E. Iglesias | 3b8e6a2 | 2011-04-05 13:00:36 +0200 | [diff] [blame] | 2681 | addr += TARGET_PAGE_SIZE; |
| 2682 | } while (addr != end_addr); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2683 | |
bellard | 9d42037 | 2006-06-25 22:25:22 +0000 | [diff] [blame] | 2684 | /* since each CPU stores ram addresses in its TLB cache, we must |
| 2685 | reset the modified entries */ |
| 2686 | /* XXX: slow ! */ |
| 2687 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 2688 | tlb_flush(env, 1); |
| 2689 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2690 | } |
| 2691 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2692 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
aliguori | f65ed4c | 2008-12-09 20:09:57 +0000 | [diff] [blame] | 2693 | { |
| 2694 | if (kvm_enabled()) |
| 2695 | kvm_coalesce_mmio_region(addr, size); |
| 2696 | } |
| 2697 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2698 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
aliguori | f65ed4c | 2008-12-09 20:09:57 +0000 | [diff] [blame] | 2699 | { |
| 2700 | if (kvm_enabled()) |
| 2701 | kvm_uncoalesce_mmio_region(addr, size); |
| 2702 | } |
| 2703 | |
Sheng Yang | 62a2744 | 2010-01-26 19:21:16 +0800 | [diff] [blame] | 2704 | void qemu_flush_coalesced_mmio_buffer(void) |
| 2705 | { |
| 2706 | if (kvm_enabled()) |
| 2707 | kvm_flush_coalesced_mmio_buffer(); |
| 2708 | } |
| 2709 | |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2710 | #if defined(__linux__) && !defined(TARGET_S390X) |
| 2711 | |
| 2712 | #include <sys/vfs.h> |
| 2713 | |
| 2714 | #define HUGETLBFS_MAGIC 0x958458f6 |
| 2715 | |
| 2716 | static long gethugepagesize(const char *path) |
| 2717 | { |
| 2718 | struct statfs fs; |
| 2719 | int ret; |
| 2720 | |
| 2721 | do { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2722 | ret = statfs(path, &fs); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2723 | } while (ret != 0 && errno == EINTR); |
| 2724 | |
| 2725 | if (ret != 0) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2726 | perror(path); |
| 2727 | return 0; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2728 | } |
| 2729 | |
| 2730 | if (fs.f_type != HUGETLBFS_MAGIC) |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2731 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2732 | |
| 2733 | return fs.f_bsize; |
| 2734 | } |
| 2735 | |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2736 | static void *file_ram_alloc(RAMBlock *block, |
| 2737 | ram_addr_t memory, |
| 2738 | const char *path) |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2739 | { |
| 2740 | char *filename; |
| 2741 | void *area; |
| 2742 | int fd; |
| 2743 | #ifdef MAP_POPULATE |
| 2744 | int flags; |
| 2745 | #endif |
| 2746 | unsigned long hpagesize; |
| 2747 | |
| 2748 | hpagesize = gethugepagesize(path); |
| 2749 | if (!hpagesize) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2750 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2751 | } |
| 2752 | |
| 2753 | if (memory < hpagesize) { |
| 2754 | return NULL; |
| 2755 | } |
| 2756 | |
| 2757 | if (kvm_enabled() && !kvm_has_sync_mmu()) { |
| 2758 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); |
| 2759 | return NULL; |
| 2760 | } |
| 2761 | |
| 2762 | if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2763 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2764 | } |
| 2765 | |
| 2766 | fd = mkstemp(filename); |
| 2767 | if (fd < 0) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2768 | perror("unable to create backing store for hugepages"); |
| 2769 | free(filename); |
| 2770 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2771 | } |
| 2772 | unlink(filename); |
| 2773 | free(filename); |
| 2774 | |
| 2775 | memory = (memory+hpagesize-1) & ~(hpagesize-1); |
| 2776 | |
| 2777 | /* |
| 2778 | * ftruncate is not supported by hugetlbfs in older |
| 2779 | * hosts, so don't bother bailing out on errors. |
| 2780 | * If anything goes wrong with it under other filesystems, |
| 2781 | * mmap will fail. |
| 2782 | */ |
| 2783 | if (ftruncate(fd, memory)) |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2784 | perror("ftruncate"); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2785 | |
| 2786 | #ifdef MAP_POPULATE |
| 2787 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case |
| 2788 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED |
| 2789 | * to sidestep this quirk. |
| 2790 | */ |
| 2791 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE; |
| 2792 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0); |
| 2793 | #else |
| 2794 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); |
| 2795 | #endif |
| 2796 | if (area == MAP_FAILED) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2797 | perror("file_ram_alloc: can't mmap RAM pages"); |
| 2798 | close(fd); |
| 2799 | return (NULL); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2800 | } |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2801 | block->fd = fd; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2802 | return area; |
| 2803 | } |
| 2804 | #endif |
| 2805 | |
Alex Williamson | d17b528 | 2010-06-25 11:08:38 -0600 | [diff] [blame] | 2806 | static ram_addr_t find_ram_offset(ram_addr_t size) |
| 2807 | { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2808 | RAMBlock *block, *next_block; |
Alex Williamson | 3e837b2 | 2011-10-31 08:54:09 -0600 | [diff] [blame] | 2809 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2810 | |
| 2811 | if (QLIST_EMPTY(&ram_list.blocks)) |
| 2812 | return 0; |
| 2813 | |
| 2814 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
Anthony PERARD | f15fbc4 | 2011-07-20 08:17:42 +0000 | [diff] [blame] | 2815 | ram_addr_t end, next = RAM_ADDR_MAX; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2816 | |
| 2817 | end = block->offset + block->length; |
| 2818 | |
| 2819 | QLIST_FOREACH(next_block, &ram_list.blocks, next) { |
| 2820 | if (next_block->offset >= end) { |
| 2821 | next = MIN(next, next_block->offset); |
| 2822 | } |
| 2823 | } |
| 2824 | if (next - end >= size && next - end < mingap) { |
Alex Williamson | 3e837b2 | 2011-10-31 08:54:09 -0600 | [diff] [blame] | 2825 | offset = end; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2826 | mingap = next - end; |
| 2827 | } |
| 2828 | } |
Alex Williamson | 3e837b2 | 2011-10-31 08:54:09 -0600 | [diff] [blame] | 2829 | |
| 2830 | if (offset == RAM_ADDR_MAX) { |
| 2831 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", |
| 2832 | (uint64_t)size); |
| 2833 | abort(); |
| 2834 | } |
| 2835 | |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2836 | return offset; |
| 2837 | } |
| 2838 | |
| 2839 | static ram_addr_t last_ram_offset(void) |
| 2840 | { |
Alex Williamson | d17b528 | 2010-06-25 11:08:38 -0600 | [diff] [blame] | 2841 | RAMBlock *block; |
| 2842 | ram_addr_t last = 0; |
| 2843 | |
| 2844 | QLIST_FOREACH(block, &ram_list.blocks, next) |
| 2845 | last = MAX(last, block->offset + block->length); |
| 2846 | |
| 2847 | return last; |
| 2848 | } |
| 2849 | |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 2850 | void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev) |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2851 | { |
| 2852 | RAMBlock *new_block, *block; |
| 2853 | |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 2854 | new_block = NULL; |
| 2855 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2856 | if (block->offset == addr) { |
| 2857 | new_block = block; |
| 2858 | break; |
| 2859 | } |
| 2860 | } |
| 2861 | assert(new_block); |
| 2862 | assert(!new_block->idstr[0]); |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2863 | |
| 2864 | if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) { |
| 2865 | char *id = dev->parent_bus->info->get_dev_path(dev); |
| 2866 | if (id) { |
| 2867 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 2868 | g_free(id); |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2869 | } |
| 2870 | } |
| 2871 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); |
| 2872 | |
| 2873 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 2874 | if (block != new_block && !strcmp(block->idstr, new_block->idstr)) { |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2875 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
| 2876 | new_block->idstr); |
| 2877 | abort(); |
| 2878 | } |
| 2879 | } |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 2880 | } |
| 2881 | |
| 2882 | ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, |
| 2883 | MemoryRegion *mr) |
| 2884 | { |
| 2885 | RAMBlock *new_block; |
| 2886 | |
| 2887 | size = TARGET_PAGE_ALIGN(size); |
| 2888 | new_block = g_malloc0(sizeof(*new_block)); |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2889 | |
Avi Kivity | 7c63736 | 2011-12-21 13:09:49 +0200 | [diff] [blame] | 2890 | new_block->mr = mr; |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 2891 | new_block->offset = find_ram_offset(size); |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2892 | if (host) { |
| 2893 | new_block->host = host; |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 2894 | new_block->flags |= RAM_PREALLOC_MASK; |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2895 | } else { |
| 2896 | if (mem_path) { |
| 2897 | #if defined (__linux__) && !defined(TARGET_S390X) |
| 2898 | new_block->host = file_ram_alloc(new_block, size, mem_path); |
| 2899 | if (!new_block->host) { |
| 2900 | new_block->host = qemu_vmalloc(size); |
Andreas Färber | e78815a | 2010-09-25 11:26:05 +0000 | [diff] [blame] | 2901 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2902 | } |
| 2903 | #else |
| 2904 | fprintf(stderr, "-mem-path option unsupported\n"); |
| 2905 | exit(1); |
| 2906 | #endif |
| 2907 | } else { |
| 2908 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
Christian Borntraeger | ff83678 | 2011-05-10 14:49:10 +0200 | [diff] [blame] | 2909 | /* S390 KVM requires the topmost vma of the RAM to be smaller than |
| 2910 | an system defined value, which is at least 256GB. Larger systems |
| 2911 | have larger values. We put the guest between the end of data |
| 2912 | segment (system break) and this value. We use 32GB as a base to |
| 2913 | have enough room for the system break to grow. */ |
| 2914 | new_block->host = mmap((void*)0x800000000, size, |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2915 | PROT_EXEC|PROT_READ|PROT_WRITE, |
Christian Borntraeger | ff83678 | 2011-05-10 14:49:10 +0200 | [diff] [blame] | 2916 | MAP_SHARED | MAP_ANONYMOUS | MAP_FIXED, -1, 0); |
Alexander Graf | fb8b273 | 2011-05-20 17:33:28 +0200 | [diff] [blame] | 2917 | if (new_block->host == MAP_FAILED) { |
| 2918 | fprintf(stderr, "Allocating RAM failed\n"); |
| 2919 | abort(); |
| 2920 | } |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2921 | #else |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 2922 | if (xen_enabled()) { |
Avi Kivity | fce537d | 2011-12-18 15:48:55 +0200 | [diff] [blame] | 2923 | xen_ram_alloc(new_block->offset, size, mr); |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 2924 | } else { |
| 2925 | new_block->host = qemu_vmalloc(size); |
| 2926 | } |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2927 | #endif |
Andreas Färber | e78815a | 2010-09-25 11:26:05 +0000 | [diff] [blame] | 2928 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2929 | } |
| 2930 | } |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2931 | new_block->length = size; |
| 2932 | |
| 2933 | QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next); |
| 2934 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 2935 | ram_list.phys_dirty = g_realloc(ram_list.phys_dirty, |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2936 | last_ram_offset() >> TARGET_PAGE_BITS); |
| 2937 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), |
| 2938 | 0xff, size >> TARGET_PAGE_BITS); |
| 2939 | |
| 2940 | if (kvm_enabled()) |
| 2941 | kvm_setup_guest_memory(new_block->host, size); |
| 2942 | |
| 2943 | return new_block->offset; |
| 2944 | } |
| 2945 | |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 2946 | ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr) |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 2947 | { |
Avi Kivity | c5705a7 | 2011-12-20 15:59:12 +0200 | [diff] [blame] | 2948 | return qemu_ram_alloc_from_ptr(size, NULL, mr); |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 2949 | } |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 2950 | |
Alex Williamson | 1f2e98b | 2011-05-03 12:48:09 -0600 | [diff] [blame] | 2951 | void qemu_ram_free_from_ptr(ram_addr_t addr) |
| 2952 | { |
| 2953 | RAMBlock *block; |
| 2954 | |
| 2955 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2956 | if (addr == block->offset) { |
| 2957 | QLIST_REMOVE(block, next); |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 2958 | g_free(block); |
Alex Williamson | 1f2e98b | 2011-05-03 12:48:09 -0600 | [diff] [blame] | 2959 | return; |
| 2960 | } |
| 2961 | } |
| 2962 | } |
| 2963 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2964 | void qemu_ram_free(ram_addr_t addr) |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 2965 | { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2966 | RAMBlock *block; |
| 2967 | |
| 2968 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2969 | if (addr == block->offset) { |
| 2970 | QLIST_REMOVE(block, next); |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 2971 | if (block->flags & RAM_PREALLOC_MASK) { |
| 2972 | ; |
| 2973 | } else if (mem_path) { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2974 | #if defined (__linux__) && !defined(TARGET_S390X) |
| 2975 | if (block->fd) { |
| 2976 | munmap(block->host, block->length); |
| 2977 | close(block->fd); |
| 2978 | } else { |
| 2979 | qemu_vfree(block->host); |
| 2980 | } |
Jan Kiszka | fd28aa1 | 2011-03-15 12:26:14 +0100 | [diff] [blame] | 2981 | #else |
| 2982 | abort(); |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2983 | #endif |
| 2984 | } else { |
| 2985 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
| 2986 | munmap(block->host, block->length); |
| 2987 | #else |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 2988 | if (xen_enabled()) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 2989 | xen_invalidate_map_cache_entry(block->host); |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 2990 | } else { |
| 2991 | qemu_vfree(block->host); |
| 2992 | } |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2993 | #endif |
| 2994 | } |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 2995 | g_free(block); |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2996 | return; |
| 2997 | } |
| 2998 | } |
| 2999 | |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 3000 | } |
| 3001 | |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 3002 | #ifndef _WIN32 |
| 3003 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) |
| 3004 | { |
| 3005 | RAMBlock *block; |
| 3006 | ram_addr_t offset; |
| 3007 | int flags; |
| 3008 | void *area, *vaddr; |
| 3009 | |
| 3010 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 3011 | offset = addr - block->offset; |
| 3012 | if (offset < block->length) { |
| 3013 | vaddr = block->host + offset; |
| 3014 | if (block->flags & RAM_PREALLOC_MASK) { |
| 3015 | ; |
| 3016 | } else { |
| 3017 | flags = MAP_FIXED; |
| 3018 | munmap(vaddr, length); |
| 3019 | if (mem_path) { |
| 3020 | #if defined(__linux__) && !defined(TARGET_S390X) |
| 3021 | if (block->fd) { |
| 3022 | #ifdef MAP_POPULATE |
| 3023 | flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED : |
| 3024 | MAP_PRIVATE; |
| 3025 | #else |
| 3026 | flags |= MAP_PRIVATE; |
| 3027 | #endif |
| 3028 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 3029 | flags, block->fd, offset); |
| 3030 | } else { |
| 3031 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
| 3032 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 3033 | flags, -1, 0); |
| 3034 | } |
Jan Kiszka | fd28aa1 | 2011-03-15 12:26:14 +0100 | [diff] [blame] | 3035 | #else |
| 3036 | abort(); |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 3037 | #endif |
| 3038 | } else { |
| 3039 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
| 3040 | flags |= MAP_SHARED | MAP_ANONYMOUS; |
| 3041 | area = mmap(vaddr, length, PROT_EXEC|PROT_READ|PROT_WRITE, |
| 3042 | flags, -1, 0); |
| 3043 | #else |
| 3044 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
| 3045 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 3046 | flags, -1, 0); |
| 3047 | #endif |
| 3048 | } |
| 3049 | if (area != vaddr) { |
Anthony PERARD | f15fbc4 | 2011-07-20 08:17:42 +0000 | [diff] [blame] | 3050 | fprintf(stderr, "Could not remap addr: " |
| 3051 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n", |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 3052 | length, addr); |
| 3053 | exit(1); |
| 3054 | } |
| 3055 | qemu_madvise(vaddr, length, QEMU_MADV_MERGEABLE); |
| 3056 | } |
| 3057 | return; |
| 3058 | } |
| 3059 | } |
| 3060 | } |
| 3061 | #endif /* !_WIN32 */ |
| 3062 | |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 3063 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3064 | With the exception of the softmmu code in this file, this should |
| 3065 | only be used for local memory (e.g. video ram) that the device owns, |
| 3066 | and knows it isn't going to access beyond the end of the block. |
| 3067 | |
| 3068 | It should not be used for general purpose DMA. |
| 3069 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. |
| 3070 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3071 | void *qemu_get_ram_ptr(ram_addr_t addr) |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 3072 | { |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3073 | RAMBlock *block; |
| 3074 | |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3075 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 3076 | if (addr - block->offset < block->length) { |
Vincent Palatin | 7d82af3 | 2011-03-10 15:47:46 -0500 | [diff] [blame] | 3077 | /* Move this entry to to start of the list. */ |
| 3078 | if (block != QLIST_FIRST(&ram_list.blocks)) { |
| 3079 | QLIST_REMOVE(block, next); |
| 3080 | QLIST_INSERT_HEAD(&ram_list.blocks, block, next); |
| 3081 | } |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 3082 | if (xen_enabled()) { |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3083 | /* We need to check if the requested address is in the RAM |
| 3084 | * because we don't want to map the entire memory in QEMU. |
Stefano Stabellini | 712c2b4 | 2011-05-19 18:35:46 +0100 | [diff] [blame] | 3085 | * In that case just map until the end of the page. |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3086 | */ |
| 3087 | if (block->offset == 0) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3088 | return xen_map_cache(addr, 0, 0); |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3089 | } else if (block->host == NULL) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3090 | block->host = |
| 3091 | xen_map_cache(block->offset, block->length, 1); |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3092 | } |
| 3093 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3094 | return block->host + (addr - block->offset); |
| 3095 | } |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3096 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3097 | |
| 3098 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 3099 | abort(); |
| 3100 | |
| 3101 | return NULL; |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 3102 | } |
| 3103 | |
Michael S. Tsirkin | b2e0a13 | 2010-11-22 19:52:34 +0200 | [diff] [blame] | 3104 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
| 3105 | * Same as qemu_get_ram_ptr but avoid reordering ramblocks. |
| 3106 | */ |
| 3107 | void *qemu_safe_ram_ptr(ram_addr_t addr) |
| 3108 | { |
| 3109 | RAMBlock *block; |
| 3110 | |
| 3111 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 3112 | if (addr - block->offset < block->length) { |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 3113 | if (xen_enabled()) { |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3114 | /* We need to check if the requested address is in the RAM |
| 3115 | * because we don't want to map the entire memory in QEMU. |
Stefano Stabellini | 712c2b4 | 2011-05-19 18:35:46 +0100 | [diff] [blame] | 3116 | * In that case just map until the end of the page. |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3117 | */ |
| 3118 | if (block->offset == 0) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3119 | return xen_map_cache(addr, 0, 0); |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3120 | } else if (block->host == NULL) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3121 | block->host = |
| 3122 | xen_map_cache(block->offset, block->length, 1); |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3123 | } |
| 3124 | } |
Michael S. Tsirkin | b2e0a13 | 2010-11-22 19:52:34 +0200 | [diff] [blame] | 3125 | return block->host + (addr - block->offset); |
| 3126 | } |
| 3127 | } |
| 3128 | |
| 3129 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 3130 | abort(); |
| 3131 | |
| 3132 | return NULL; |
| 3133 | } |
| 3134 | |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 3135 | /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr |
| 3136 | * but takes a size argument */ |
Stefano Stabellini | 8ab934f | 2011-06-27 18:26:06 +0100 | [diff] [blame] | 3137 | void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size) |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 3138 | { |
Stefano Stabellini | 8ab934f | 2011-06-27 18:26:06 +0100 | [diff] [blame] | 3139 | if (*size == 0) { |
| 3140 | return NULL; |
| 3141 | } |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 3142 | if (xen_enabled()) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3143 | return xen_map_cache(addr, *size, 1); |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 3144 | } else { |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 3145 | RAMBlock *block; |
| 3146 | |
| 3147 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 3148 | if (addr - block->offset < block->length) { |
| 3149 | if (addr - block->offset + *size > block->length) |
| 3150 | *size = block->length - addr + block->offset; |
| 3151 | return block->host + (addr - block->offset); |
| 3152 | } |
| 3153 | } |
| 3154 | |
| 3155 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 3156 | abort(); |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 3157 | } |
| 3158 | } |
| 3159 | |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 3160 | void qemu_put_ram_ptr(void *addr) |
| 3161 | { |
| 3162 | trace_qemu_put_ram_ptr(addr); |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 3163 | } |
| 3164 | |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3165 | int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3166 | { |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3167 | RAMBlock *block; |
| 3168 | uint8_t *host = ptr; |
| 3169 | |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 3170 | if (xen_enabled()) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3171 | *ram_addr = xen_ram_addr_from_mapcache(ptr); |
Stefano Stabellini | 712c2b4 | 2011-05-19 18:35:46 +0100 | [diff] [blame] | 3172 | return 0; |
| 3173 | } |
| 3174 | |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3175 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3176 | /* This case append when the block is not mapped. */ |
| 3177 | if (block->host == NULL) { |
| 3178 | continue; |
| 3179 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3180 | if (host - block->host < block->length) { |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3181 | *ram_addr = block->offset + (host - block->host); |
| 3182 | return 0; |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3183 | } |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3184 | } |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3185 | |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3186 | return -1; |
| 3187 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3188 | |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3189 | /* Some of the softmmu routines need to translate from a host pointer |
| 3190 | (typically a TLB entry) back to a ram offset. */ |
| 3191 | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) |
| 3192 | { |
| 3193 | ram_addr_t ram_addr; |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3194 | |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3195 | if (qemu_ram_addr_from_host(ptr, &ram_addr)) { |
| 3196 | fprintf(stderr, "Bad ram pointer %p\n", ptr); |
| 3197 | abort(); |
| 3198 | } |
| 3199 | return ram_addr; |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3200 | } |
| 3201 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3202 | static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr, |
| 3203 | unsigned size) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3204 | { |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 3205 | #ifdef DEBUG_UNASSIGNED |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 3206 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 3207 | #endif |
Richard Henderson | 5b45040 | 2011-04-18 16:13:12 -0700 | [diff] [blame] | 3208 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3209 | cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size); |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3210 | #endif |
| 3211 | return 0; |
| 3212 | } |
| 3213 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3214 | static void unassigned_mem_write(void *opaque, target_phys_addr_t addr, |
| 3215 | uint64_t val, unsigned size) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3216 | { |
| 3217 | #ifdef DEBUG_UNASSIGNED |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3218 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val); |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3219 | #endif |
Richard Henderson | 5b45040 | 2011-04-18 16:13:12 -0700 | [diff] [blame] | 3220 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3221 | cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size); |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3222 | #endif |
| 3223 | } |
| 3224 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3225 | static const MemoryRegionOps unassigned_mem_ops = { |
| 3226 | .read = unassigned_mem_read, |
| 3227 | .write = unassigned_mem_write, |
| 3228 | .endianness = DEVICE_NATIVE_ENDIAN, |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3229 | }; |
| 3230 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3231 | static uint64_t error_mem_read(void *opaque, target_phys_addr_t addr, |
| 3232 | unsigned size) |
| 3233 | { |
| 3234 | abort(); |
| 3235 | } |
| 3236 | |
| 3237 | static void error_mem_write(void *opaque, target_phys_addr_t addr, |
| 3238 | uint64_t value, unsigned size) |
| 3239 | { |
| 3240 | abort(); |
| 3241 | } |
| 3242 | |
| 3243 | static const MemoryRegionOps error_mem_ops = { |
| 3244 | .read = error_mem_read, |
| 3245 | .write = error_mem_write, |
| 3246 | .endianness = DEVICE_NATIVE_ENDIAN, |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3247 | }; |
| 3248 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3249 | static const MemoryRegionOps rom_mem_ops = { |
| 3250 | .read = error_mem_read, |
| 3251 | .write = unassigned_mem_write, |
| 3252 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 3253 | }; |
| 3254 | |
| 3255 | static void notdirty_mem_write(void *opaque, target_phys_addr_t ram_addr, |
| 3256 | uint64_t val, unsigned size) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3257 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3258 | int dirty_flags; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3259 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3260 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 3261 | #if !defined(CONFIG_USER_ONLY) |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3262 | tb_invalidate_phys_page_fast(ram_addr, size); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3263 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3264 | #endif |
| 3265 | } |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3266 | switch (size) { |
| 3267 | case 1: |
| 3268 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
| 3269 | break; |
| 3270 | case 2: |
| 3271 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
| 3272 | break; |
| 3273 | case 4: |
| 3274 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
| 3275 | break; |
| 3276 | default: |
| 3277 | abort(); |
| 3278 | } |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3279 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3280 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3281 | /* we remove the notdirty callback only if the code has been |
| 3282 | flushed */ |
| 3283 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3284 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3285 | } |
| 3286 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3287 | static const MemoryRegionOps notdirty_mem_ops = { |
| 3288 | .read = error_mem_read, |
| 3289 | .write = notdirty_mem_write, |
| 3290 | .endianness = DEVICE_NATIVE_ENDIAN, |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3291 | }; |
| 3292 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3293 | /* Generate a debug exception if a watchpoint has been hit. */ |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3294 | static void check_watchpoint(int offset, int len_mask, int flags) |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3295 | { |
| 3296 | CPUState *env = cpu_single_env; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3297 | target_ulong pc, cs_base; |
| 3298 | TranslationBlock *tb; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3299 | target_ulong vaddr; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 3300 | CPUWatchpoint *wp; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3301 | int cpu_flags; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3302 | |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3303 | if (env->watchpoint_hit) { |
| 3304 | /* We re-entered the check after replacing the TB. Now raise |
| 3305 | * the debug interrupt so that is will trigger after the |
| 3306 | * current instruction. */ |
| 3307 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); |
| 3308 | return; |
| 3309 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3310 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3311 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3312 | if ((vaddr == (wp->vaddr & len_mask) || |
| 3313 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 3314 | wp->flags |= BP_WATCHPOINT_HIT; |
| 3315 | if (!env->watchpoint_hit) { |
| 3316 | env->watchpoint_hit = wp; |
| 3317 | tb = tb_find_pc(env->mem_io_pc); |
| 3318 | if (!tb) { |
| 3319 | cpu_abort(env, "check_watchpoint: could not find TB for " |
| 3320 | "pc=%p", (void *)env->mem_io_pc); |
| 3321 | } |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 3322 | cpu_restore_state(tb, env, env->mem_io_pc); |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 3323 | tb_phys_invalidate(tb, -1); |
| 3324 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
| 3325 | env->exception_index = EXCP_DEBUG; |
| 3326 | } else { |
| 3327 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); |
| 3328 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); |
| 3329 | } |
| 3330 | cpu_resume_from_signal(env, NULL); |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3331 | } |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 3332 | } else { |
| 3333 | wp->flags &= ~BP_WATCHPOINT_HIT; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3334 | } |
| 3335 | } |
| 3336 | } |
| 3337 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3338 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
| 3339 | so these check for a hit then pass through to the normal out-of-line |
| 3340 | phys routines. */ |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 3341 | static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr, |
| 3342 | unsigned size) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3343 | { |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 3344 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ); |
| 3345 | switch (size) { |
| 3346 | case 1: return ldub_phys(addr); |
| 3347 | case 2: return lduw_phys(addr); |
| 3348 | case 4: return ldl_phys(addr); |
| 3349 | default: abort(); |
| 3350 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3351 | } |
| 3352 | |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 3353 | static void watch_mem_write(void *opaque, target_phys_addr_t addr, |
| 3354 | uint64_t val, unsigned size) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3355 | { |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 3356 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE); |
| 3357 | switch (size) { |
| 3358 | case 1: stb_phys(addr, val); |
| 3359 | case 2: stw_phys(addr, val); |
| 3360 | case 4: stl_phys(addr, val); |
| 3361 | default: abort(); |
| 3362 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3363 | } |
| 3364 | |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 3365 | static const MemoryRegionOps watch_mem_ops = { |
| 3366 | .read = watch_mem_read, |
| 3367 | .write = watch_mem_write, |
| 3368 | .endianness = DEVICE_NATIVE_ENDIAN, |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3369 | }; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3370 | |
Avi Kivity | 70c68e4 | 2012-01-02 12:32:48 +0200 | [diff] [blame] | 3371 | static uint64_t subpage_read(void *opaque, target_phys_addr_t addr, |
| 3372 | unsigned len) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3373 | { |
Avi Kivity | 70c68e4 | 2012-01-02 12:32:48 +0200 | [diff] [blame] | 3374 | subpage_t *mmio = opaque; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3375 | unsigned int idx = SUBPAGE_IDX(addr); |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3376 | MemoryRegionSection *section; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3377 | #if defined(DEBUG_SUBPAGE) |
| 3378 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, |
| 3379 | mmio, len, addr, idx); |
| 3380 | #endif |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3381 | |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3382 | section = &phys_sections[mmio->sub_section[idx]]; |
| 3383 | addr += mmio->base; |
| 3384 | addr -= section->offset_within_address_space; |
| 3385 | addr += section->offset_within_region; |
| 3386 | return io_mem_read(section->mr->ram_addr, addr, len); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3387 | } |
| 3388 | |
Avi Kivity | 70c68e4 | 2012-01-02 12:32:48 +0200 | [diff] [blame] | 3389 | static void subpage_write(void *opaque, target_phys_addr_t addr, |
| 3390 | uint64_t value, unsigned len) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3391 | { |
Avi Kivity | 70c68e4 | 2012-01-02 12:32:48 +0200 | [diff] [blame] | 3392 | subpage_t *mmio = opaque; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3393 | unsigned int idx = SUBPAGE_IDX(addr); |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3394 | MemoryRegionSection *section; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3395 | #if defined(DEBUG_SUBPAGE) |
Avi Kivity | 70c68e4 | 2012-01-02 12:32:48 +0200 | [diff] [blame] | 3396 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx |
| 3397 | " idx %d value %"PRIx64"\n", |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3398 | __func__, mmio, len, addr, idx, value); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3399 | #endif |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3400 | |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3401 | section = &phys_sections[mmio->sub_section[idx]]; |
| 3402 | addr += mmio->base; |
| 3403 | addr -= section->offset_within_address_space; |
| 3404 | addr += section->offset_within_region; |
| 3405 | io_mem_write(section->mr->ram_addr, addr, value, len); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3406 | } |
| 3407 | |
Avi Kivity | 70c68e4 | 2012-01-02 12:32:48 +0200 | [diff] [blame] | 3408 | static const MemoryRegionOps subpage_ops = { |
| 3409 | .read = subpage_read, |
| 3410 | .write = subpage_write, |
| 3411 | .endianness = DEVICE_NATIVE_ENDIAN, |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3412 | }; |
| 3413 | |
Avi Kivity | de712f9 | 2012-01-02 12:41:07 +0200 | [diff] [blame] | 3414 | static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr, |
| 3415 | unsigned size) |
Andreas Färber | 56384e8 | 2011-11-30 16:26:21 +0100 | [diff] [blame] | 3416 | { |
| 3417 | ram_addr_t raddr = addr; |
| 3418 | void *ptr = qemu_get_ram_ptr(raddr); |
Avi Kivity | de712f9 | 2012-01-02 12:41:07 +0200 | [diff] [blame] | 3419 | switch (size) { |
| 3420 | case 1: return ldub_p(ptr); |
| 3421 | case 2: return lduw_p(ptr); |
| 3422 | case 4: return ldl_p(ptr); |
| 3423 | default: abort(); |
| 3424 | } |
Andreas Färber | 56384e8 | 2011-11-30 16:26:21 +0100 | [diff] [blame] | 3425 | } |
| 3426 | |
Avi Kivity | de712f9 | 2012-01-02 12:41:07 +0200 | [diff] [blame] | 3427 | static void subpage_ram_write(void *opaque, target_phys_addr_t addr, |
| 3428 | uint64_t value, unsigned size) |
Andreas Färber | 56384e8 | 2011-11-30 16:26:21 +0100 | [diff] [blame] | 3429 | { |
| 3430 | ram_addr_t raddr = addr; |
| 3431 | void *ptr = qemu_get_ram_ptr(raddr); |
Avi Kivity | de712f9 | 2012-01-02 12:41:07 +0200 | [diff] [blame] | 3432 | switch (size) { |
| 3433 | case 1: return stb_p(ptr, value); |
| 3434 | case 2: return stw_p(ptr, value); |
| 3435 | case 4: return stl_p(ptr, value); |
| 3436 | default: abort(); |
| 3437 | } |
Andreas Färber | 56384e8 | 2011-11-30 16:26:21 +0100 | [diff] [blame] | 3438 | } |
| 3439 | |
Avi Kivity | de712f9 | 2012-01-02 12:41:07 +0200 | [diff] [blame] | 3440 | static const MemoryRegionOps subpage_ram_ops = { |
| 3441 | .read = subpage_ram_read, |
| 3442 | .write = subpage_ram_write, |
| 3443 | .endianness = DEVICE_NATIVE_ENDIAN, |
Andreas Färber | 56384e8 | 2011-11-30 16:26:21 +0100 | [diff] [blame] | 3444 | }; |
| 3445 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3446 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3447 | uint16_t section) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3448 | { |
| 3449 | int idx, eidx; |
| 3450 | |
| 3451 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) |
| 3452 | return -1; |
| 3453 | idx = SUBPAGE_IDX(start); |
| 3454 | eidx = SUBPAGE_IDX(end); |
| 3455 | #if defined(DEBUG_SUBPAGE) |
Blue Swirl | 0bf9e31 | 2009-07-20 17:19:25 +0000 | [diff] [blame] | 3456 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3457 | mmio, start, end, idx, eidx, memory); |
| 3458 | #endif |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3459 | if (memory_region_is_ram(phys_sections[section].mr)) { |
| 3460 | MemoryRegionSection new_section = phys_sections[section]; |
| 3461 | new_section.mr = &io_mem_subpage_ram; |
| 3462 | section = phys_section_add(&new_section); |
Andreas Färber | 56384e8 | 2011-11-30 16:26:21 +0100 | [diff] [blame] | 3463 | } |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3464 | for (; idx <= eidx; idx++) { |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3465 | mmio->sub_section[idx] = section; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3466 | } |
| 3467 | |
| 3468 | return 0; |
| 3469 | } |
| 3470 | |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3471 | static subpage_t *subpage_init (target_phys_addr_t base, uint16_t *section_ind, |
| 3472 | uint16_t orig_section) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3473 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3474 | subpage_t *mmio; |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3475 | MemoryRegionSection section = { |
| 3476 | .offset_within_address_space = base, |
| 3477 | .size = TARGET_PAGE_SIZE, |
| 3478 | }; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3479 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 3480 | mmio = g_malloc0(sizeof(subpage_t)); |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 3481 | |
| 3482 | mmio->base = base; |
Avi Kivity | 70c68e4 | 2012-01-02 12:32:48 +0200 | [diff] [blame] | 3483 | memory_region_init_io(&mmio->iomem, &subpage_ops, mmio, |
| 3484 | "subpage", TARGET_PAGE_SIZE); |
Avi Kivity | b3b00c7 | 2012-01-02 13:20:11 +0200 | [diff] [blame] | 3485 | mmio->iomem.subpage = true; |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3486 | section.mr = &mmio->iomem; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3487 | #if defined(DEBUG_SUBPAGE) |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 3488 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
| 3489 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3490 | #endif |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3491 | *section_ind = phys_section_add(§ion); |
| 3492 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_section); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3493 | |
| 3494 | return mmio; |
| 3495 | } |
| 3496 | |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3497 | static int get_free_io_mem_idx(void) |
| 3498 | { |
| 3499 | int i; |
| 3500 | |
| 3501 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) |
| 3502 | if (!io_mem_used[i]) { |
| 3503 | io_mem_used[i] = 1; |
| 3504 | return i; |
| 3505 | } |
Riku Voipio | c6703b4 | 2009-12-03 15:56:05 +0200 | [diff] [blame] | 3506 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3507 | return -1; |
| 3508 | } |
| 3509 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3510 | /* mem_read and mem_write are arrays of functions containing the |
| 3511 | function to access byte (index 0), word (index 1) and dword (index |
Paul Brook | 0b4e6e3 | 2009-04-30 18:37:55 +0100 | [diff] [blame] | 3512 | 2). Functions can be omitted with a NULL function pointer. |
blueswir1 | 3ee8992 | 2008-01-02 19:45:26 +0000 | [diff] [blame] | 3513 | If io_index is non zero, the corresponding io zone is |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 3514 | modified. If it is zero, a new io zone is allocated. The return |
| 3515 | value can be used with cpu_register_physical_memory(). (-1) is |
| 3516 | returned if error. */ |
Avi Kivity | a621f38 | 2012-01-02 13:12:08 +0200 | [diff] [blame] | 3517 | static int cpu_register_io_memory_fixed(int io_index, MemoryRegion *mr) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3518 | { |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3519 | if (io_index <= 0) { |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3520 | io_index = get_free_io_mem_idx(); |
| 3521 | if (io_index == -1) |
| 3522 | return io_index; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3523 | } else { |
| 3524 | if (io_index >= IO_MEM_NB_ENTRIES) |
| 3525 | return -1; |
| 3526 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3527 | |
Avi Kivity | a621f38 | 2012-01-02 13:12:08 +0200 | [diff] [blame] | 3528 | io_mem_region[io_index] = mr; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3529 | |
Avi Kivity | 11c7ef0 | 2012-01-02 17:21:07 +0200 | [diff] [blame] | 3530 | return io_index; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3531 | } |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 3532 | |
Avi Kivity | a621f38 | 2012-01-02 13:12:08 +0200 | [diff] [blame] | 3533 | int cpu_register_io_memory(MemoryRegion *mr) |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3534 | { |
Avi Kivity | a621f38 | 2012-01-02 13:12:08 +0200 | [diff] [blame] | 3535 | return cpu_register_io_memory_fixed(0, mr); |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3536 | } |
| 3537 | |
Avi Kivity | 11c7ef0 | 2012-01-02 17:21:07 +0200 | [diff] [blame] | 3538 | void cpu_unregister_io_memory(int io_index) |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3539 | { |
Avi Kivity | a621f38 | 2012-01-02 13:12:08 +0200 | [diff] [blame] | 3540 | io_mem_region[io_index] = NULL; |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3541 | io_mem_used[io_index] = 0; |
| 3542 | } |
| 3543 | |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3544 | static uint16_t dummy_section(MemoryRegion *mr) |
| 3545 | { |
| 3546 | MemoryRegionSection section = { |
| 3547 | .mr = mr, |
| 3548 | .offset_within_address_space = 0, |
| 3549 | .offset_within_region = 0, |
| 3550 | .size = UINT64_MAX, |
| 3551 | }; |
| 3552 | |
| 3553 | return phys_section_add(§ion); |
| 3554 | } |
| 3555 | |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 3556 | static void io_mem_init(void) |
| 3557 | { |
| 3558 | int i; |
| 3559 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3560 | /* Must be first: */ |
| 3561 | memory_region_init_io(&io_mem_ram, &error_mem_ops, NULL, "ram", UINT64_MAX); |
| 3562 | assert(io_mem_ram.ram_addr == 0); |
| 3563 | memory_region_init_io(&io_mem_rom, &rom_mem_ops, NULL, "rom", UINT64_MAX); |
| 3564 | memory_region_init_io(&io_mem_unassigned, &unassigned_mem_ops, NULL, |
| 3565 | "unassigned", UINT64_MAX); |
| 3566 | memory_region_init_io(&io_mem_notdirty, ¬dirty_mem_ops, NULL, |
| 3567 | "notdirty", UINT64_MAX); |
Avi Kivity | de712f9 | 2012-01-02 12:41:07 +0200 | [diff] [blame] | 3568 | memory_region_init_io(&io_mem_subpage_ram, &subpage_ram_ops, NULL, |
| 3569 | "subpage-ram", UINT64_MAX); |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 3570 | for (i=0; i<5; i++) |
| 3571 | io_mem_used[i] = 1; |
| 3572 | |
Avi Kivity | 1ec9b90 | 2012-01-02 12:47:48 +0200 | [diff] [blame] | 3573 | memory_region_init_io(&io_mem_watch, &watch_mem_ops, NULL, |
| 3574 | "watch", UINT64_MAX); |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 3575 | } |
| 3576 | |
Avi Kivity | 50c1e14 | 2012-02-08 21:36:02 +0200 | [diff] [blame] | 3577 | static void core_begin(MemoryListener *listener) |
| 3578 | { |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 3579 | destroy_all_mappings(); |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3580 | phys_sections_clear(); |
Avi Kivity | d6f2ea2 | 2012-02-12 20:12:49 +0200 | [diff] [blame^] | 3581 | phys_map.u.node = PHYS_MAP_NODE_NIL; |
Avi Kivity | 5312bd8 | 2012-02-12 18:32:55 +0200 | [diff] [blame] | 3582 | phys_section_unassigned = dummy_section(&io_mem_unassigned); |
Avi Kivity | 50c1e14 | 2012-02-08 21:36:02 +0200 | [diff] [blame] | 3583 | } |
| 3584 | |
| 3585 | static void core_commit(MemoryListener *listener) |
| 3586 | { |
| 3587 | } |
| 3588 | |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 3589 | static void core_region_add(MemoryListener *listener, |
| 3590 | MemoryRegionSection *section) |
| 3591 | { |
Avi Kivity | 4855d41 | 2012-02-08 21:16:05 +0200 | [diff] [blame] | 3592 | cpu_register_physical_memory_log(section, section->readonly); |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 3593 | } |
| 3594 | |
| 3595 | static void core_region_del(MemoryListener *listener, |
| 3596 | MemoryRegionSection *section) |
| 3597 | { |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 3598 | } |
| 3599 | |
Avi Kivity | 50c1e14 | 2012-02-08 21:36:02 +0200 | [diff] [blame] | 3600 | static void core_region_nop(MemoryListener *listener, |
| 3601 | MemoryRegionSection *section) |
| 3602 | { |
Avi Kivity | 54688b1 | 2012-02-09 17:34:32 +0200 | [diff] [blame] | 3603 | cpu_register_physical_memory_log(section, section->readonly); |
Avi Kivity | 50c1e14 | 2012-02-08 21:36:02 +0200 | [diff] [blame] | 3604 | } |
| 3605 | |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 3606 | static void core_log_start(MemoryListener *listener, |
| 3607 | MemoryRegionSection *section) |
| 3608 | { |
| 3609 | } |
| 3610 | |
| 3611 | static void core_log_stop(MemoryListener *listener, |
| 3612 | MemoryRegionSection *section) |
| 3613 | { |
| 3614 | } |
| 3615 | |
| 3616 | static void core_log_sync(MemoryListener *listener, |
| 3617 | MemoryRegionSection *section) |
| 3618 | { |
| 3619 | } |
| 3620 | |
| 3621 | static void core_log_global_start(MemoryListener *listener) |
| 3622 | { |
| 3623 | cpu_physical_memory_set_dirty_tracking(1); |
| 3624 | } |
| 3625 | |
| 3626 | static void core_log_global_stop(MemoryListener *listener) |
| 3627 | { |
| 3628 | cpu_physical_memory_set_dirty_tracking(0); |
| 3629 | } |
| 3630 | |
| 3631 | static void core_eventfd_add(MemoryListener *listener, |
| 3632 | MemoryRegionSection *section, |
| 3633 | bool match_data, uint64_t data, int fd) |
| 3634 | { |
| 3635 | } |
| 3636 | |
| 3637 | static void core_eventfd_del(MemoryListener *listener, |
| 3638 | MemoryRegionSection *section, |
| 3639 | bool match_data, uint64_t data, int fd) |
| 3640 | { |
| 3641 | } |
| 3642 | |
Avi Kivity | 50c1e14 | 2012-02-08 21:36:02 +0200 | [diff] [blame] | 3643 | static void io_begin(MemoryListener *listener) |
| 3644 | { |
| 3645 | } |
| 3646 | |
| 3647 | static void io_commit(MemoryListener *listener) |
| 3648 | { |
| 3649 | } |
| 3650 | |
Avi Kivity | 4855d41 | 2012-02-08 21:16:05 +0200 | [diff] [blame] | 3651 | static void io_region_add(MemoryListener *listener, |
| 3652 | MemoryRegionSection *section) |
| 3653 | { |
| 3654 | iorange_init(§ion->mr->iorange, &memory_region_iorange_ops, |
| 3655 | section->offset_within_address_space, section->size); |
| 3656 | ioport_register(§ion->mr->iorange); |
| 3657 | } |
| 3658 | |
| 3659 | static void io_region_del(MemoryListener *listener, |
| 3660 | MemoryRegionSection *section) |
| 3661 | { |
| 3662 | isa_unassign_ioport(section->offset_within_address_space, section->size); |
| 3663 | } |
| 3664 | |
Avi Kivity | 50c1e14 | 2012-02-08 21:36:02 +0200 | [diff] [blame] | 3665 | static void io_region_nop(MemoryListener *listener, |
| 3666 | MemoryRegionSection *section) |
| 3667 | { |
| 3668 | } |
| 3669 | |
Avi Kivity | 4855d41 | 2012-02-08 21:16:05 +0200 | [diff] [blame] | 3670 | static void io_log_start(MemoryListener *listener, |
| 3671 | MemoryRegionSection *section) |
| 3672 | { |
| 3673 | } |
| 3674 | |
| 3675 | static void io_log_stop(MemoryListener *listener, |
| 3676 | MemoryRegionSection *section) |
| 3677 | { |
| 3678 | } |
| 3679 | |
| 3680 | static void io_log_sync(MemoryListener *listener, |
| 3681 | MemoryRegionSection *section) |
| 3682 | { |
| 3683 | } |
| 3684 | |
| 3685 | static void io_log_global_start(MemoryListener *listener) |
| 3686 | { |
| 3687 | } |
| 3688 | |
| 3689 | static void io_log_global_stop(MemoryListener *listener) |
| 3690 | { |
| 3691 | } |
| 3692 | |
| 3693 | static void io_eventfd_add(MemoryListener *listener, |
| 3694 | MemoryRegionSection *section, |
| 3695 | bool match_data, uint64_t data, int fd) |
| 3696 | { |
| 3697 | } |
| 3698 | |
| 3699 | static void io_eventfd_del(MemoryListener *listener, |
| 3700 | MemoryRegionSection *section, |
| 3701 | bool match_data, uint64_t data, int fd) |
| 3702 | { |
| 3703 | } |
| 3704 | |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 3705 | static MemoryListener core_memory_listener = { |
Avi Kivity | 50c1e14 | 2012-02-08 21:36:02 +0200 | [diff] [blame] | 3706 | .begin = core_begin, |
| 3707 | .commit = core_commit, |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 3708 | .region_add = core_region_add, |
| 3709 | .region_del = core_region_del, |
Avi Kivity | 50c1e14 | 2012-02-08 21:36:02 +0200 | [diff] [blame] | 3710 | .region_nop = core_region_nop, |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 3711 | .log_start = core_log_start, |
| 3712 | .log_stop = core_log_stop, |
| 3713 | .log_sync = core_log_sync, |
| 3714 | .log_global_start = core_log_global_start, |
| 3715 | .log_global_stop = core_log_global_stop, |
| 3716 | .eventfd_add = core_eventfd_add, |
| 3717 | .eventfd_del = core_eventfd_del, |
| 3718 | .priority = 0, |
| 3719 | }; |
| 3720 | |
Avi Kivity | 4855d41 | 2012-02-08 21:16:05 +0200 | [diff] [blame] | 3721 | static MemoryListener io_memory_listener = { |
Avi Kivity | 50c1e14 | 2012-02-08 21:36:02 +0200 | [diff] [blame] | 3722 | .begin = io_begin, |
| 3723 | .commit = io_commit, |
Avi Kivity | 4855d41 | 2012-02-08 21:16:05 +0200 | [diff] [blame] | 3724 | .region_add = io_region_add, |
| 3725 | .region_del = io_region_del, |
Avi Kivity | 50c1e14 | 2012-02-08 21:36:02 +0200 | [diff] [blame] | 3726 | .region_nop = io_region_nop, |
Avi Kivity | 4855d41 | 2012-02-08 21:16:05 +0200 | [diff] [blame] | 3727 | .log_start = io_log_start, |
| 3728 | .log_stop = io_log_stop, |
| 3729 | .log_sync = io_log_sync, |
| 3730 | .log_global_start = io_log_global_start, |
| 3731 | .log_global_stop = io_log_global_stop, |
| 3732 | .eventfd_add = io_eventfd_add, |
| 3733 | .eventfd_del = io_eventfd_del, |
| 3734 | .priority = 0, |
| 3735 | }; |
| 3736 | |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 3737 | static void memory_map_init(void) |
| 3738 | { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 3739 | system_memory = g_malloc(sizeof(*system_memory)); |
Avi Kivity | 8417ceb | 2011-08-03 11:56:14 +0300 | [diff] [blame] | 3740 | memory_region_init(system_memory, "system", INT64_MAX); |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 3741 | set_system_memory_map(system_memory); |
Avi Kivity | 309cb47 | 2011-08-08 16:09:03 +0300 | [diff] [blame] | 3742 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 3743 | system_io = g_malloc(sizeof(*system_io)); |
Avi Kivity | 309cb47 | 2011-08-08 16:09:03 +0300 | [diff] [blame] | 3744 | memory_region_init(system_io, "io", 65536); |
| 3745 | set_system_io_map(system_io); |
Avi Kivity | 9363274 | 2012-02-08 16:54:16 +0200 | [diff] [blame] | 3746 | |
Avi Kivity | 4855d41 | 2012-02-08 21:16:05 +0200 | [diff] [blame] | 3747 | memory_listener_register(&core_memory_listener, system_memory); |
| 3748 | memory_listener_register(&io_memory_listener, system_io); |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 3749 | } |
| 3750 | |
| 3751 | MemoryRegion *get_system_memory(void) |
| 3752 | { |
| 3753 | return system_memory; |
| 3754 | } |
| 3755 | |
Avi Kivity | 309cb47 | 2011-08-08 16:09:03 +0300 | [diff] [blame] | 3756 | MemoryRegion *get_system_io(void) |
| 3757 | { |
| 3758 | return system_io; |
| 3759 | } |
| 3760 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 3761 | #endif /* !defined(CONFIG_USER_ONLY) */ |
| 3762 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3763 | /* physical memory access (slow version, mainly for debug) */ |
| 3764 | #if defined(CONFIG_USER_ONLY) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3765 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
| 3766 | uint8_t *buf, int len, int is_write) |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3767 | { |
| 3768 | int l, flags; |
| 3769 | target_ulong page; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 3770 | void * p; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3771 | |
| 3772 | while (len > 0) { |
| 3773 | page = addr & TARGET_PAGE_MASK; |
| 3774 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3775 | if (l > len) |
| 3776 | l = len; |
| 3777 | flags = page_get_flags(page); |
| 3778 | if (!(flags & PAGE_VALID)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3779 | return -1; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3780 | if (is_write) { |
| 3781 | if (!(flags & PAGE_WRITE)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3782 | return -1; |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 3783 | /* XXX: this code should not depend on lock_user */ |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3784 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3785 | return -1; |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3786 | memcpy(p, buf, l); |
| 3787 | unlock_user(p, addr, l); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3788 | } else { |
| 3789 | if (!(flags & PAGE_READ)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3790 | return -1; |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 3791 | /* XXX: this code should not depend on lock_user */ |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3792 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3793 | return -1; |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3794 | memcpy(buf, p, l); |
aurel32 | 5b25757 | 2008-04-28 08:54:59 +0000 | [diff] [blame] | 3795 | unlock_user(p, addr, 0); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3796 | } |
| 3797 | len -= l; |
| 3798 | buf += l; |
| 3799 | addr += l; |
| 3800 | } |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3801 | return 0; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3802 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3803 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3804 | #else |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3805 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3806 | int len, int is_write) |
| 3807 | { |
| 3808 | int l, io_index; |
| 3809 | uint8_t *ptr; |
| 3810 | uint32_t val; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3811 | target_phys_addr_t page; |
Anthony PERARD | 8ca5692 | 2011-07-15 04:32:53 +0000 | [diff] [blame] | 3812 | ram_addr_t pd; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 3813 | PhysPageDesc p; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3814 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3815 | while (len > 0) { |
| 3816 | page = addr & TARGET_PAGE_MASK; |
| 3817 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3818 | if (l > len) |
| 3819 | l = len; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 3820 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 3821 | pd = p.phys_offset; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3822 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3823 | if (is_write) { |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 3824 | if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) { |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 3825 | target_phys_addr_t addr1; |
Avi Kivity | 11c7ef0 | 2012-01-02 17:21:07 +0200 | [diff] [blame] | 3826 | io_index = pd & (IO_MEM_NB_ENTRIES - 1); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 3827 | addr1 = (addr & ~TARGET_PAGE_MASK) + p.region_offset; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 3828 | /* XXX: could force cpu_single_env to NULL to avoid |
| 3829 | potential bugs */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3830 | if (l >= 4 && ((addr1 & 3) == 0)) { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3831 | /* 32 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3832 | val = ldl_p(buf); |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 3833 | io_mem_write(io_index, addr1, val, 4); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3834 | l = 4; |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3835 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3836 | /* 16 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3837 | val = lduw_p(buf); |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 3838 | io_mem_write(io_index, addr1, val, 2); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3839 | l = 2; |
| 3840 | } else { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3841 | /* 8 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3842 | val = ldub_p(buf); |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 3843 | io_mem_write(io_index, addr1, val, 1); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3844 | l = 1; |
| 3845 | } |
| 3846 | } else { |
Anthony PERARD | 8ca5692 | 2011-07-15 04:32:53 +0000 | [diff] [blame] | 3847 | ram_addr_t addr1; |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 3848 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3849 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3850 | ptr = qemu_get_ram_ptr(addr1); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3851 | memcpy(ptr, buf, l); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3852 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 3853 | /* invalidate code */ |
| 3854 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); |
| 3855 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3856 | cpu_physical_memory_set_dirty_flags( |
| 3857 | addr1, (0xff & ~CODE_DIRTY_FLAG)); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3858 | } |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 3859 | qemu_put_ram_ptr(ptr); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3860 | } |
| 3861 | } else { |
Avi Kivity | 1d393fa | 2012-01-01 21:15:42 +0200 | [diff] [blame] | 3862 | if (!is_ram_rom_romd(pd)) { |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 3863 | target_phys_addr_t addr1; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3864 | /* I/O case */ |
Avi Kivity | 11c7ef0 | 2012-01-02 17:21:07 +0200 | [diff] [blame] | 3865 | io_index = pd & (IO_MEM_NB_ENTRIES - 1); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 3866 | addr1 = (addr & ~TARGET_PAGE_MASK) + p.region_offset; |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3867 | if (l >= 4 && ((addr1 & 3) == 0)) { |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3868 | /* 32 bit read access */ |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 3869 | val = io_mem_read(io_index, addr1, 4); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3870 | stl_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3871 | l = 4; |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3872 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3873 | /* 16 bit read access */ |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 3874 | val = io_mem_read(io_index, addr1, 2); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3875 | stw_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3876 | l = 2; |
| 3877 | } else { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3878 | /* 8 bit read access */ |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 3879 | val = io_mem_read(io_index, addr1, 1); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3880 | stb_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3881 | l = 1; |
| 3882 | } |
| 3883 | } else { |
| 3884 | /* RAM case */ |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 3885 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
| 3886 | memcpy(buf, ptr + (addr & ~TARGET_PAGE_MASK), l); |
| 3887 | qemu_put_ram_ptr(ptr); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3888 | } |
| 3889 | } |
| 3890 | len -= l; |
| 3891 | buf += l; |
| 3892 | addr += l; |
| 3893 | } |
| 3894 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3895 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3896 | /* used for ROM loading : can write in RAM and ROM */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3897 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3898 | const uint8_t *buf, int len) |
| 3899 | { |
| 3900 | int l; |
| 3901 | uint8_t *ptr; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3902 | target_phys_addr_t page; |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3903 | unsigned long pd; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 3904 | PhysPageDesc p; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3905 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3906 | while (len > 0) { |
| 3907 | page = addr & TARGET_PAGE_MASK; |
| 3908 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3909 | if (l > len) |
| 3910 | l = len; |
| 3911 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 3912 | pd = p.phys_offset; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3913 | |
Avi Kivity | 1d393fa | 2012-01-01 21:15:42 +0200 | [diff] [blame] | 3914 | if (!is_ram_rom_romd(pd)) { |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3915 | /* do nothing */ |
| 3916 | } else { |
| 3917 | unsigned long addr1; |
| 3918 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 3919 | /* ROM/RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3920 | ptr = qemu_get_ram_ptr(addr1); |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3921 | memcpy(ptr, buf, l); |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 3922 | qemu_put_ram_ptr(ptr); |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3923 | } |
| 3924 | len -= l; |
| 3925 | buf += l; |
| 3926 | addr += l; |
| 3927 | } |
| 3928 | } |
| 3929 | |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3930 | typedef struct { |
| 3931 | void *buffer; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3932 | target_phys_addr_t addr; |
| 3933 | target_phys_addr_t len; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3934 | } BounceBuffer; |
| 3935 | |
| 3936 | static BounceBuffer bounce; |
| 3937 | |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3938 | typedef struct MapClient { |
| 3939 | void *opaque; |
| 3940 | void (*callback)(void *opaque); |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3941 | QLIST_ENTRY(MapClient) link; |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3942 | } MapClient; |
| 3943 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3944 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
| 3945 | = QLIST_HEAD_INITIALIZER(map_client_list); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3946 | |
| 3947 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) |
| 3948 | { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 3949 | MapClient *client = g_malloc(sizeof(*client)); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3950 | |
| 3951 | client->opaque = opaque; |
| 3952 | client->callback = callback; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3953 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3954 | return client; |
| 3955 | } |
| 3956 | |
| 3957 | void cpu_unregister_map_client(void *_client) |
| 3958 | { |
| 3959 | MapClient *client = (MapClient *)_client; |
| 3960 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3961 | QLIST_REMOVE(client, link); |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 3962 | g_free(client); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3963 | } |
| 3964 | |
| 3965 | static void cpu_notify_map_clients(void) |
| 3966 | { |
| 3967 | MapClient *client; |
| 3968 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3969 | while (!QLIST_EMPTY(&map_client_list)) { |
| 3970 | client = QLIST_FIRST(&map_client_list); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3971 | client->callback(client->opaque); |
Isaku Yamahata | 34d5e94 | 2009-06-26 18:57:18 +0900 | [diff] [blame] | 3972 | cpu_unregister_map_client(client); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3973 | } |
| 3974 | } |
| 3975 | |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3976 | /* Map a physical memory region into a host virtual address. |
| 3977 | * May map a subset of the requested range, given by and returned in *plen. |
| 3978 | * May return NULL if resources needed to perform the mapping are exhausted. |
| 3979 | * Use only for reads OR writes - not for read-modify-write operations. |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3980 | * Use cpu_register_map_client() to know when retrying the map operation is |
| 3981 | * likely to succeed. |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3982 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3983 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
| 3984 | target_phys_addr_t *plen, |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3985 | int is_write) |
| 3986 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3987 | target_phys_addr_t len = *plen; |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 3988 | target_phys_addr_t todo = 0; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3989 | int l; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3990 | target_phys_addr_t page; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3991 | unsigned long pd; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 3992 | PhysPageDesc p; |
Anthony PERARD | f15fbc4 | 2011-07-20 08:17:42 +0000 | [diff] [blame] | 3993 | ram_addr_t raddr = RAM_ADDR_MAX; |
Stefano Stabellini | 8ab934f | 2011-06-27 18:26:06 +0100 | [diff] [blame] | 3994 | ram_addr_t rlen; |
| 3995 | void *ret; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3996 | |
| 3997 | while (len > 0) { |
| 3998 | page = addr & TARGET_PAGE_MASK; |
| 3999 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 4000 | if (l > len) |
| 4001 | l = len; |
| 4002 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4003 | pd = p.phys_offset; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4004 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 4005 | if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) { |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 4006 | if (todo || bounce.buffer) { |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4007 | break; |
| 4008 | } |
| 4009 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); |
| 4010 | bounce.addr = addr; |
| 4011 | bounce.len = l; |
| 4012 | if (!is_write) { |
Stefan Weil | 54f7b4a | 2011-04-10 18:23:39 +0200 | [diff] [blame] | 4013 | cpu_physical_memory_read(addr, bounce.buffer, l); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4014 | } |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 4015 | |
| 4016 | *plen = l; |
| 4017 | return bounce.buffer; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4018 | } |
Stefano Stabellini | 8ab934f | 2011-06-27 18:26:06 +0100 | [diff] [blame] | 4019 | if (!todo) { |
| 4020 | raddr = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 4021 | } |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4022 | |
| 4023 | len -= l; |
| 4024 | addr += l; |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 4025 | todo += l; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4026 | } |
Stefano Stabellini | 8ab934f | 2011-06-27 18:26:06 +0100 | [diff] [blame] | 4027 | rlen = todo; |
| 4028 | ret = qemu_ram_ptr_length(raddr, &rlen); |
| 4029 | *plen = rlen; |
| 4030 | return ret; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4031 | } |
| 4032 | |
| 4033 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). |
| 4034 | * Will also mark the memory as dirty if is_write == 1. access_len gives |
| 4035 | * the amount of memory that was actually read or written by the caller. |
| 4036 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4037 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
| 4038 | int is_write, target_phys_addr_t access_len) |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4039 | { |
| 4040 | if (buffer != bounce.buffer) { |
| 4041 | if (is_write) { |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 4042 | ram_addr_t addr1 = qemu_ram_addr_from_host_nofail(buffer); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4043 | while (access_len) { |
| 4044 | unsigned l; |
| 4045 | l = TARGET_PAGE_SIZE; |
| 4046 | if (l > access_len) |
| 4047 | l = access_len; |
| 4048 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 4049 | /* invalidate code */ |
| 4050 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); |
| 4051 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 4052 | cpu_physical_memory_set_dirty_flags( |
| 4053 | addr1, (0xff & ~CODE_DIRTY_FLAG)); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4054 | } |
| 4055 | addr1 += l; |
| 4056 | access_len -= l; |
| 4057 | } |
| 4058 | } |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 4059 | if (xen_enabled()) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 4060 | xen_invalidate_map_cache_entry(buffer); |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 4061 | } |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4062 | return; |
| 4063 | } |
| 4064 | if (is_write) { |
| 4065 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); |
| 4066 | } |
Herve Poussineau | f8a8324 | 2010-01-24 21:23:56 +0000 | [diff] [blame] | 4067 | qemu_vfree(bounce.buffer); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4068 | bounce.buffer = NULL; |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 4069 | cpu_notify_map_clients(); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4070 | } |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 4071 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4072 | /* warning: addr must be aligned */ |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4073 | static inline uint32_t ldl_phys_internal(target_phys_addr_t addr, |
| 4074 | enum device_endian endian) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4075 | { |
| 4076 | int io_index; |
| 4077 | uint8_t *ptr; |
| 4078 | uint32_t val; |
| 4079 | unsigned long pd; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4080 | PhysPageDesc p; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4081 | |
| 4082 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4083 | pd = p.phys_offset; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4084 | |
Avi Kivity | 1d393fa | 2012-01-01 21:15:42 +0200 | [diff] [blame] | 4085 | if (!is_ram_rom_romd(pd)) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4086 | /* I/O case */ |
Avi Kivity | 11c7ef0 | 2012-01-02 17:21:07 +0200 | [diff] [blame] | 4087 | io_index = pd & (IO_MEM_NB_ENTRIES - 1); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4088 | addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset; |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 4089 | val = io_mem_read(io_index, addr, 4); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4090 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 4091 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 4092 | val = bswap32(val); |
| 4093 | } |
| 4094 | #else |
| 4095 | if (endian == DEVICE_BIG_ENDIAN) { |
| 4096 | val = bswap32(val); |
| 4097 | } |
| 4098 | #endif |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4099 | } else { |
| 4100 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4101 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4102 | (addr & ~TARGET_PAGE_MASK); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4103 | switch (endian) { |
| 4104 | case DEVICE_LITTLE_ENDIAN: |
| 4105 | val = ldl_le_p(ptr); |
| 4106 | break; |
| 4107 | case DEVICE_BIG_ENDIAN: |
| 4108 | val = ldl_be_p(ptr); |
| 4109 | break; |
| 4110 | default: |
| 4111 | val = ldl_p(ptr); |
| 4112 | break; |
| 4113 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4114 | } |
| 4115 | return val; |
| 4116 | } |
| 4117 | |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4118 | uint32_t ldl_phys(target_phys_addr_t addr) |
| 4119 | { |
| 4120 | return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN); |
| 4121 | } |
| 4122 | |
| 4123 | uint32_t ldl_le_phys(target_phys_addr_t addr) |
| 4124 | { |
| 4125 | return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN); |
| 4126 | } |
| 4127 | |
| 4128 | uint32_t ldl_be_phys(target_phys_addr_t addr) |
| 4129 | { |
| 4130 | return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN); |
| 4131 | } |
| 4132 | |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4133 | /* warning: addr must be aligned */ |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4134 | static inline uint64_t ldq_phys_internal(target_phys_addr_t addr, |
| 4135 | enum device_endian endian) |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4136 | { |
| 4137 | int io_index; |
| 4138 | uint8_t *ptr; |
| 4139 | uint64_t val; |
| 4140 | unsigned long pd; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4141 | PhysPageDesc p; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4142 | |
| 4143 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4144 | pd = p.phys_offset; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4145 | |
Avi Kivity | 1d393fa | 2012-01-01 21:15:42 +0200 | [diff] [blame] | 4146 | if (!is_ram_rom_romd(pd)) { |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4147 | /* I/O case */ |
Avi Kivity | 11c7ef0 | 2012-01-02 17:21:07 +0200 | [diff] [blame] | 4148 | io_index = pd & (IO_MEM_NB_ENTRIES - 1); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4149 | addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset; |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4150 | |
| 4151 | /* XXX This is broken when device endian != cpu endian. |
| 4152 | Fix and add "endian" variable check */ |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4153 | #ifdef TARGET_WORDS_BIGENDIAN |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 4154 | val = io_mem_read(io_index, addr, 4) << 32; |
| 4155 | val |= io_mem_read(io_index, addr + 4, 4); |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4156 | #else |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 4157 | val = io_mem_read(io_index, addr, 4); |
| 4158 | val |= io_mem_read(io_index, addr + 4, 4) << 32; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4159 | #endif |
| 4160 | } else { |
| 4161 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4162 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4163 | (addr & ~TARGET_PAGE_MASK); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4164 | switch (endian) { |
| 4165 | case DEVICE_LITTLE_ENDIAN: |
| 4166 | val = ldq_le_p(ptr); |
| 4167 | break; |
| 4168 | case DEVICE_BIG_ENDIAN: |
| 4169 | val = ldq_be_p(ptr); |
| 4170 | break; |
| 4171 | default: |
| 4172 | val = ldq_p(ptr); |
| 4173 | break; |
| 4174 | } |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4175 | } |
| 4176 | return val; |
| 4177 | } |
| 4178 | |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4179 | uint64_t ldq_phys(target_phys_addr_t addr) |
| 4180 | { |
| 4181 | return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN); |
| 4182 | } |
| 4183 | |
| 4184 | uint64_t ldq_le_phys(target_phys_addr_t addr) |
| 4185 | { |
| 4186 | return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN); |
| 4187 | } |
| 4188 | |
| 4189 | uint64_t ldq_be_phys(target_phys_addr_t addr) |
| 4190 | { |
| 4191 | return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN); |
| 4192 | } |
| 4193 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4194 | /* XXX: optimize */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4195 | uint32_t ldub_phys(target_phys_addr_t addr) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4196 | { |
| 4197 | uint8_t val; |
| 4198 | cpu_physical_memory_read(addr, &val, 1); |
| 4199 | return val; |
| 4200 | } |
| 4201 | |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4202 | /* warning: addr must be aligned */ |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4203 | static inline uint32_t lduw_phys_internal(target_phys_addr_t addr, |
| 4204 | enum device_endian endian) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4205 | { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4206 | int io_index; |
| 4207 | uint8_t *ptr; |
| 4208 | uint64_t val; |
| 4209 | unsigned long pd; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4210 | PhysPageDesc p; |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4211 | |
| 4212 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4213 | pd = p.phys_offset; |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4214 | |
Avi Kivity | 1d393fa | 2012-01-01 21:15:42 +0200 | [diff] [blame] | 4215 | if (!is_ram_rom_romd(pd)) { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4216 | /* I/O case */ |
Avi Kivity | 11c7ef0 | 2012-01-02 17:21:07 +0200 | [diff] [blame] | 4217 | io_index = pd & (IO_MEM_NB_ENTRIES - 1); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4218 | addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset; |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 4219 | val = io_mem_read(io_index, addr, 2); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4220 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 4221 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 4222 | val = bswap16(val); |
| 4223 | } |
| 4224 | #else |
| 4225 | if (endian == DEVICE_BIG_ENDIAN) { |
| 4226 | val = bswap16(val); |
| 4227 | } |
| 4228 | #endif |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4229 | } else { |
| 4230 | /* RAM case */ |
| 4231 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
| 4232 | (addr & ~TARGET_PAGE_MASK); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4233 | switch (endian) { |
| 4234 | case DEVICE_LITTLE_ENDIAN: |
| 4235 | val = lduw_le_p(ptr); |
| 4236 | break; |
| 4237 | case DEVICE_BIG_ENDIAN: |
| 4238 | val = lduw_be_p(ptr); |
| 4239 | break; |
| 4240 | default: |
| 4241 | val = lduw_p(ptr); |
| 4242 | break; |
| 4243 | } |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4244 | } |
| 4245 | return val; |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4246 | } |
| 4247 | |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4248 | uint32_t lduw_phys(target_phys_addr_t addr) |
| 4249 | { |
| 4250 | return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN); |
| 4251 | } |
| 4252 | |
| 4253 | uint32_t lduw_le_phys(target_phys_addr_t addr) |
| 4254 | { |
| 4255 | return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN); |
| 4256 | } |
| 4257 | |
| 4258 | uint32_t lduw_be_phys(target_phys_addr_t addr) |
| 4259 | { |
| 4260 | return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN); |
| 4261 | } |
| 4262 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4263 | /* warning: addr must be aligned. The ram page is not masked as dirty |
| 4264 | and the code inside is not invalidated. It is useful if the dirty |
| 4265 | bits are used to track modified PTEs */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4266 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4267 | { |
| 4268 | int io_index; |
| 4269 | uint8_t *ptr; |
| 4270 | unsigned long pd; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4271 | PhysPageDesc p; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4272 | |
| 4273 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4274 | pd = p.phys_offset; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4275 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 4276 | if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) { |
Avi Kivity | 11c7ef0 | 2012-01-02 17:21:07 +0200 | [diff] [blame] | 4277 | io_index = pd & (IO_MEM_NB_ENTRIES - 1); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4278 | addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset; |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 4279 | io_mem_write(io_index, addr, val, 4); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4280 | } else { |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 4281 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4282 | ptr = qemu_get_ram_ptr(addr1); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4283 | stl_p(ptr, val); |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 4284 | |
| 4285 | if (unlikely(in_migration)) { |
| 4286 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 4287 | /* invalidate code */ |
| 4288 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); |
| 4289 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 4290 | cpu_physical_memory_set_dirty_flags( |
| 4291 | addr1, (0xff & ~CODE_DIRTY_FLAG)); |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 4292 | } |
| 4293 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4294 | } |
| 4295 | } |
| 4296 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4297 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4298 | { |
| 4299 | int io_index; |
| 4300 | uint8_t *ptr; |
| 4301 | unsigned long pd; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4302 | PhysPageDesc p; |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4303 | |
| 4304 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4305 | pd = p.phys_offset; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4306 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 4307 | if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) { |
Avi Kivity | 11c7ef0 | 2012-01-02 17:21:07 +0200 | [diff] [blame] | 4308 | io_index = pd & (IO_MEM_NB_ENTRIES - 1); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4309 | addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset; |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4310 | #ifdef TARGET_WORDS_BIGENDIAN |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 4311 | io_mem_write(io_index, addr, val >> 32, 4); |
| 4312 | io_mem_write(io_index, addr + 4, (uint32_t)val, 4); |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4313 | #else |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 4314 | io_mem_write(io_index, addr, (uint32_t)val, 4); |
| 4315 | io_mem_write(io_index, addr + 4, val >> 32, 4); |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4316 | #endif |
| 4317 | } else { |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4318 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4319 | (addr & ~TARGET_PAGE_MASK); |
| 4320 | stq_p(ptr, val); |
| 4321 | } |
| 4322 | } |
| 4323 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4324 | /* warning: addr must be aligned */ |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4325 | static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val, |
| 4326 | enum device_endian endian) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4327 | { |
| 4328 | int io_index; |
| 4329 | uint8_t *ptr; |
| 4330 | unsigned long pd; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4331 | PhysPageDesc p; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4332 | |
| 4333 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4334 | pd = p.phys_offset; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4335 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 4336 | if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) { |
Avi Kivity | 11c7ef0 | 2012-01-02 17:21:07 +0200 | [diff] [blame] | 4337 | io_index = pd & (IO_MEM_NB_ENTRIES - 1); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4338 | addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset; |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4339 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 4340 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 4341 | val = bswap32(val); |
| 4342 | } |
| 4343 | #else |
| 4344 | if (endian == DEVICE_BIG_ENDIAN) { |
| 4345 | val = bswap32(val); |
| 4346 | } |
| 4347 | #endif |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 4348 | io_mem_write(io_index, addr, val, 4); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4349 | } else { |
| 4350 | unsigned long addr1; |
| 4351 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 4352 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4353 | ptr = qemu_get_ram_ptr(addr1); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4354 | switch (endian) { |
| 4355 | case DEVICE_LITTLE_ENDIAN: |
| 4356 | stl_le_p(ptr, val); |
| 4357 | break; |
| 4358 | case DEVICE_BIG_ENDIAN: |
| 4359 | stl_be_p(ptr, val); |
| 4360 | break; |
| 4361 | default: |
| 4362 | stl_p(ptr, val); |
| 4363 | break; |
| 4364 | } |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 4365 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 4366 | /* invalidate code */ |
| 4367 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); |
| 4368 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 4369 | cpu_physical_memory_set_dirty_flags(addr1, |
| 4370 | (0xff & ~CODE_DIRTY_FLAG)); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 4371 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4372 | } |
| 4373 | } |
| 4374 | |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4375 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
| 4376 | { |
| 4377 | stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN); |
| 4378 | } |
| 4379 | |
| 4380 | void stl_le_phys(target_phys_addr_t addr, uint32_t val) |
| 4381 | { |
| 4382 | stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN); |
| 4383 | } |
| 4384 | |
| 4385 | void stl_be_phys(target_phys_addr_t addr, uint32_t val) |
| 4386 | { |
| 4387 | stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN); |
| 4388 | } |
| 4389 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4390 | /* XXX: optimize */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4391 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4392 | { |
| 4393 | uint8_t v = val; |
| 4394 | cpu_physical_memory_write(addr, &v, 1); |
| 4395 | } |
| 4396 | |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4397 | /* warning: addr must be aligned */ |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4398 | static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val, |
| 4399 | enum device_endian endian) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4400 | { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4401 | int io_index; |
| 4402 | uint8_t *ptr; |
| 4403 | unsigned long pd; |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4404 | PhysPageDesc p; |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4405 | |
| 4406 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4407 | pd = p.phys_offset; |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4408 | |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 4409 | if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) { |
Avi Kivity | 11c7ef0 | 2012-01-02 17:21:07 +0200 | [diff] [blame] | 4410 | io_index = pd & (IO_MEM_NB_ENTRIES - 1); |
Avi Kivity | f1f6e3b | 2011-11-20 17:52:22 +0200 | [diff] [blame] | 4411 | addr = (addr & ~TARGET_PAGE_MASK) + p.region_offset; |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4412 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 4413 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 4414 | val = bswap16(val); |
| 4415 | } |
| 4416 | #else |
| 4417 | if (endian == DEVICE_BIG_ENDIAN) { |
| 4418 | val = bswap16(val); |
| 4419 | } |
| 4420 | #endif |
Avi Kivity | acbbec5 | 2011-11-21 12:27:03 +0200 | [diff] [blame] | 4421 | io_mem_write(io_index, addr, val, 2); |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4422 | } else { |
| 4423 | unsigned long addr1; |
| 4424 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 4425 | /* RAM case */ |
| 4426 | ptr = qemu_get_ram_ptr(addr1); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4427 | switch (endian) { |
| 4428 | case DEVICE_LITTLE_ENDIAN: |
| 4429 | stw_le_p(ptr, val); |
| 4430 | break; |
| 4431 | case DEVICE_BIG_ENDIAN: |
| 4432 | stw_be_p(ptr, val); |
| 4433 | break; |
| 4434 | default: |
| 4435 | stw_p(ptr, val); |
| 4436 | break; |
| 4437 | } |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4438 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 4439 | /* invalidate code */ |
| 4440 | tb_invalidate_phys_page_range(addr1, addr1 + 2, 0); |
| 4441 | /* set dirty bit */ |
| 4442 | cpu_physical_memory_set_dirty_flags(addr1, |
| 4443 | (0xff & ~CODE_DIRTY_FLAG)); |
| 4444 | } |
| 4445 | } |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4446 | } |
| 4447 | |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4448 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
| 4449 | { |
| 4450 | stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN); |
| 4451 | } |
| 4452 | |
| 4453 | void stw_le_phys(target_phys_addr_t addr, uint32_t val) |
| 4454 | { |
| 4455 | stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN); |
| 4456 | } |
| 4457 | |
| 4458 | void stw_be_phys(target_phys_addr_t addr, uint32_t val) |
| 4459 | { |
| 4460 | stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN); |
| 4461 | } |
| 4462 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4463 | /* XXX: optimize */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4464 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4465 | { |
| 4466 | val = tswap64(val); |
Stefan Weil | 71d2b72 | 2011-03-26 21:06:56 +0100 | [diff] [blame] | 4467 | cpu_physical_memory_write(addr, &val, 8); |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4468 | } |
| 4469 | |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4470 | void stq_le_phys(target_phys_addr_t addr, uint64_t val) |
| 4471 | { |
| 4472 | val = cpu_to_le64(val); |
| 4473 | cpu_physical_memory_write(addr, &val, 8); |
| 4474 | } |
| 4475 | |
| 4476 | void stq_be_phys(target_phys_addr_t addr, uint64_t val) |
| 4477 | { |
| 4478 | val = cpu_to_be64(val); |
| 4479 | cpu_physical_memory_write(addr, &val, 8); |
| 4480 | } |
| 4481 | |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4482 | /* virtual memory access for debug (includes writing to ROM) */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4483 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 4484 | uint8_t *buf, int len, int is_write) |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4485 | { |
| 4486 | int l; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4487 | target_phys_addr_t phys_addr; |
j_mayer | 9b3c35e | 2007-04-07 11:21:28 +0000 | [diff] [blame] | 4488 | target_ulong page; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4489 | |
| 4490 | while (len > 0) { |
| 4491 | page = addr & TARGET_PAGE_MASK; |
| 4492 | phys_addr = cpu_get_phys_page_debug(env, page); |
| 4493 | /* if no physical page mapped, return an error */ |
| 4494 | if (phys_addr == -1) |
| 4495 | return -1; |
| 4496 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 4497 | if (l > len) |
| 4498 | l = len; |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4499 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4500 | if (is_write) |
| 4501 | cpu_physical_memory_write_rom(phys_addr, buf, l); |
| 4502 | else |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4503 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4504 | len -= l; |
| 4505 | buf += l; |
| 4506 | addr += l; |
| 4507 | } |
| 4508 | return 0; |
| 4509 | } |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 4510 | #endif |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4511 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4512 | /* in deterministic execution mode, instructions doing device I/Os |
| 4513 | must be at the end of the TB */ |
| 4514 | void cpu_io_recompile(CPUState *env, void *retaddr) |
| 4515 | { |
| 4516 | TranslationBlock *tb; |
| 4517 | uint32_t n, cflags; |
| 4518 | target_ulong pc, cs_base; |
| 4519 | uint64_t flags; |
| 4520 | |
| 4521 | tb = tb_find_pc((unsigned long)retaddr); |
| 4522 | if (!tb) { |
| 4523 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", |
| 4524 | retaddr); |
| 4525 | } |
| 4526 | n = env->icount_decr.u16.low + tb->icount; |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 4527 | cpu_restore_state(tb, env, (unsigned long)retaddr); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4528 | /* Calculate how many instructions had been executed before the fault |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 4529 | occurred. */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4530 | n = n - env->icount_decr.u16.low; |
| 4531 | /* Generate a new TB ending on the I/O insn. */ |
| 4532 | n++; |
| 4533 | /* On MIPS and SH, delay slot instructions can only be restarted if |
| 4534 | they were already the first instruction in the TB. If this is not |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 4535 | the first instruction in a TB then re-execute the preceding |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4536 | branch. */ |
| 4537 | #if defined(TARGET_MIPS) |
| 4538 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { |
| 4539 | env->active_tc.PC -= 4; |
| 4540 | env->icount_decr.u16.low++; |
| 4541 | env->hflags &= ~MIPS_HFLAG_BMASK; |
| 4542 | } |
| 4543 | #elif defined(TARGET_SH4) |
| 4544 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 |
| 4545 | && n > 1) { |
| 4546 | env->pc -= 2; |
| 4547 | env->icount_decr.u16.low++; |
| 4548 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
| 4549 | } |
| 4550 | #endif |
| 4551 | /* This should never happen. */ |
| 4552 | if (n > CF_COUNT_MASK) |
| 4553 | cpu_abort(env, "TB too big during recompile"); |
| 4554 | |
| 4555 | cflags = n | CF_LAST_IO; |
| 4556 | pc = tb->pc; |
| 4557 | cs_base = tb->cs_base; |
| 4558 | flags = tb->flags; |
| 4559 | tb_phys_invalidate(tb, -1); |
| 4560 | /* FIXME: In theory this could raise an exception. In practice |
| 4561 | we have already translated the block once so it's probably ok. */ |
| 4562 | tb_gen_code(env, pc, cs_base, flags, cflags); |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 4563 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4564 | the first in the TB) then we end up generating a whole new TB and |
| 4565 | repeating the fault, which is horribly inefficient. |
| 4566 | Better would be to execute just this insn uncached, or generate a |
| 4567 | second new TB. */ |
| 4568 | cpu_resume_from_signal(env, NULL); |
| 4569 | } |
| 4570 | |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 4571 | #if !defined(CONFIG_USER_ONLY) |
| 4572 | |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 4573 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4574 | { |
| 4575 | int i, target_code_size, max_target_code_size; |
| 4576 | int direct_jmp_count, direct_jmp2_count, cross_page; |
| 4577 | TranslationBlock *tb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4578 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4579 | target_code_size = 0; |
| 4580 | max_target_code_size = 0; |
| 4581 | cross_page = 0; |
| 4582 | direct_jmp_count = 0; |
| 4583 | direct_jmp2_count = 0; |
| 4584 | for(i = 0; i < nb_tbs; i++) { |
| 4585 | tb = &tbs[i]; |
| 4586 | target_code_size += tb->size; |
| 4587 | if (tb->size > max_target_code_size) |
| 4588 | max_target_code_size = tb->size; |
| 4589 | if (tb->page_addr[1] != -1) |
| 4590 | cross_page++; |
| 4591 | if (tb->tb_next_offset[0] != 0xffff) { |
| 4592 | direct_jmp_count++; |
| 4593 | if (tb->tb_next_offset[1] != 0xffff) { |
| 4594 | direct_jmp2_count++; |
| 4595 | } |
| 4596 | } |
| 4597 | } |
| 4598 | /* XXX: avoid using doubles ? */ |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 4599 | cpu_fprintf(f, "Translation buffer state:\n"); |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 4600 | cpu_fprintf(f, "gen code size %td/%ld\n", |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 4601 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); |
| 4602 | cpu_fprintf(f, "TB count %d/%d\n", |
| 4603 | nb_tbs, code_gen_max_blocks); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4604 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4605 | nb_tbs ? target_code_size / nb_tbs : 0, |
| 4606 | max_target_code_size); |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 4607 | cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n", |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4608 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
| 4609 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4610 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
| 4611 | cross_page, |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4612 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
| 4613 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4614 | direct_jmp_count, |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4615 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
| 4616 | direct_jmp2_count, |
| 4617 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 4618 | cpu_fprintf(f, "\nStatistics:\n"); |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4619 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
| 4620 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); |
| 4621 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); |
bellard | b67d9a5 | 2008-05-23 09:57:34 +0000 | [diff] [blame] | 4622 | tcg_dump_info(f, cpu_fprintf); |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4623 | } |
| 4624 | |
Avi Kivity | d39e822 | 2012-01-01 23:35:10 +0200 | [diff] [blame] | 4625 | /* NOTE: this function can trigger an exception */ |
| 4626 | /* NOTE2: the returned address is not exactly the physical address: it |
| 4627 | is the offset relative to phys_ram_base */ |
| 4628 | tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr) |
| 4629 | { |
| 4630 | int mmu_idx, page_index, pd; |
| 4631 | void *p; |
| 4632 | |
| 4633 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
| 4634 | mmu_idx = cpu_mmu_index(env1); |
| 4635 | if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code != |
| 4636 | (addr & TARGET_PAGE_MASK))) { |
| 4637 | ldub_code(addr); |
| 4638 | } |
| 4639 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; |
Avi Kivity | 0e0df1e | 2012-01-02 00:32:15 +0200 | [diff] [blame] | 4640 | if (pd != io_mem_ram.ram_addr && pd != io_mem_rom.ram_addr |
Avi Kivity | 75c578d | 2012-01-02 15:40:52 +0200 | [diff] [blame] | 4641 | && !is_romd(pd)) { |
Avi Kivity | d39e822 | 2012-01-01 23:35:10 +0200 | [diff] [blame] | 4642 | #if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC) |
| 4643 | cpu_unassigned_access(env1, addr, 0, 1, 0, 4); |
| 4644 | #else |
| 4645 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
| 4646 | #endif |
| 4647 | } |
| 4648 | p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend); |
| 4649 | return qemu_ram_addr_from_host_nofail(p); |
| 4650 | } |
| 4651 | |
Benjamin Herrenschmidt | 82afa58 | 2012-01-10 01:35:11 +0000 | [diff] [blame] | 4652 | /* |
| 4653 | * A helper function for the _utterly broken_ virtio device model to find out if |
| 4654 | * it's running on a big endian machine. Don't do this at home kids! |
| 4655 | */ |
| 4656 | bool virtio_is_big_endian(void); |
| 4657 | bool virtio_is_big_endian(void) |
| 4658 | { |
| 4659 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 4660 | return true; |
| 4661 | #else |
| 4662 | return false; |
| 4663 | #endif |
| 4664 | } |
| 4665 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 4666 | #define MMUSUFFIX _cmmu |
Blue Swirl | 3917149 | 2011-09-21 18:13:16 +0000 | [diff] [blame] | 4667 | #undef GETPC |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 4668 | #define GETPC() NULL |
| 4669 | #define env cpu_single_env |
bellard | b769d8f | 2004-10-03 15:07:13 +0000 | [diff] [blame] | 4670 | #define SOFTMMU_CODE_ACCESS |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 4671 | |
| 4672 | #define SHIFT 0 |
| 4673 | #include "softmmu_template.h" |
| 4674 | |
| 4675 | #define SHIFT 1 |
| 4676 | #include "softmmu_template.h" |
| 4677 | |
| 4678 | #define SHIFT 2 |
| 4679 | #include "softmmu_template.h" |
| 4680 | |
| 4681 | #define SHIFT 3 |
| 4682 | #include "softmmu_template.h" |
| 4683 | |
| 4684 | #undef env |
| 4685 | |
| 4686 | #endif |