pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * m68k virtual CPU header |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 4 | * Copyright (c) 2005-2007 CodeSourcery |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 5 | * Written by Paul Brook |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 19 | */ |
| 20 | #ifndef CPU_M68K_H |
| 21 | #define CPU_M68K_H |
| 22 | |
| 23 | #define TARGET_LONG_BITS 32 |
| 24 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 25 | #define CPUArchState struct CPUM68KState |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 26 | |
Stefan Weil | 3aef481 | 2012-02-01 20:55:18 +0100 | [diff] [blame] | 27 | #include "config.h" |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 28 | #include "qemu-common.h" |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 29 | #include "exec/cpu-defs.h" |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 30 | |
Paolo Bonzini | 6b4c305 | 2012-10-24 13:12:00 +0200 | [diff] [blame] | 31 | #include "fpu/softfloat.h" |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 32 | |
| 33 | #define MAX_QREGS 32 |
| 34 | |
| 35 | #define TARGET_HAS_ICE 1 |
| 36 | |
ths | 9042c0e | 2006-12-23 14:18:40 +0000 | [diff] [blame] | 37 | #define ELF_MACHINE EM_68K |
| 38 | |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 39 | #define EXCP_ACCESS 2 /* Access (MMU) error. */ |
| 40 | #define EXCP_ADDRESS 3 /* Address error. */ |
| 41 | #define EXCP_ILLEGAL 4 /* Illegal instruction. */ |
| 42 | #define EXCP_DIV0 5 /* Divide by zero */ |
| 43 | #define EXCP_PRIVILEGE 8 /* Privilege violation. */ |
| 44 | #define EXCP_TRACE 9 |
| 45 | #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ |
| 46 | #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ |
| 47 | #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ |
| 48 | #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ |
| 49 | #define EXCP_FORMAT 14 /* RTE format error. */ |
| 50 | #define EXCP_UNINITIALIZED 15 |
| 51 | #define EXCP_TRAP0 32 /* User trap #0. */ |
| 52 | #define EXCP_TRAP15 47 /* User trap #15. */ |
| 53 | #define EXCP_UNSUPPORTED 61 |
| 54 | #define EXCP_ICE 13 |
| 55 | |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 56 | #define EXCP_RTE 0x100 |
pbrook | a87295e | 2007-05-26 15:09:38 +0000 | [diff] [blame] | 57 | #define EXCP_HALT_INSN 0x101 |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 58 | |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 59 | #define NB_MMU_MODES 2 |
| 60 | |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 61 | typedef struct CPUM68KState { |
| 62 | uint32_t dregs[8]; |
| 63 | uint32_t aregs[8]; |
| 64 | uint32_t pc; |
| 65 | uint32_t sr; |
| 66 | |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 67 | /* SSP and USP. The current_sp is stored in aregs[7], the other here. */ |
| 68 | int current_sp; |
| 69 | uint32_t sp[2]; |
| 70 | |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 71 | /* Condition flags. */ |
| 72 | uint32_t cc_op; |
| 73 | uint32_t cc_dest; |
| 74 | uint32_t cc_src; |
| 75 | uint32_t cc_x; |
| 76 | |
| 77 | float64 fregs[8]; |
| 78 | float64 fp_result; |
| 79 | uint32_t fpcr; |
| 80 | uint32_t fpsr; |
| 81 | float_status fp_status; |
| 82 | |
pbrook | acf930a | 2007-05-29 14:57:59 +0000 | [diff] [blame] | 83 | uint64_t mactmp; |
| 84 | /* EMAC Hardware deals with 48-bit values composed of one 32-bit and |
| 85 | two 8-bit parts. We store a single 64-bit value and |
| 86 | rearrange/extend this when changing modes. */ |
| 87 | uint64_t macc[4]; |
| 88 | uint32_t macsr; |
| 89 | uint32_t mac_mask; |
| 90 | |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 91 | /* Temporary storage for DIV helpers. */ |
| 92 | uint32_t div1; |
| 93 | uint32_t div2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 94 | |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 95 | /* MMU status. */ |
| 96 | struct { |
| 97 | uint32_t ar; |
| 98 | } mmu; |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 99 | |
| 100 | /* Control registers. */ |
| 101 | uint32_t vbr; |
| 102 | uint32_t mbar; |
| 103 | uint32_t rambar0; |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 104 | uint32_t cacr; |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 105 | |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 106 | int pending_vector; |
| 107 | int pending_level; |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 108 | |
| 109 | uint32_t qregs[MAX_QREGS]; |
| 110 | |
| 111 | CPU_COMMON |
bellard | aaed909 | 2007-11-10 15:15:54 +0000 | [diff] [blame] | 112 | |
| 113 | uint32_t features; |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 114 | } CPUM68KState; |
| 115 | |
Andreas Färber | b9e7a23 | 2012-04-15 00:35:50 +0200 | [diff] [blame] | 116 | #include "cpu-qom.h" |
| 117 | |
pbrook | e1f3808 | 2008-05-24 22:29:16 +0000 | [diff] [blame] | 118 | void m68k_tcg_init(void); |
Andreas Färber | 6d1bbc6 | 2013-01-05 15:15:30 +0100 | [diff] [blame] | 119 | void m68k_cpu_init_gdb(M68kCPU *cpu); |
Andreas Färber | c7937d9 | 2013-01-18 14:03:58 +0100 | [diff] [blame] | 120 | M68kCPU *cpu_m68k_init(const char *cpu_model); |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 121 | int cpu_m68k_exec(CPUM68KState *s); |
Andreas Färber | 2b3e3cf | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 122 | void do_interrupt_m68k_hardirq(CPUM68KState *env1); |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 123 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
| 124 | signal handlers to inform the virtual CPU of exceptions. non zero |
| 125 | is returned if the signal was handled by the virtual CPU. */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 126 | int cpu_m68k_signal_handler(int host_signum, void *pinfo, |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 127 | void *puc); |
| 128 | void cpu_m68k_flush_flags(CPUM68KState *, int); |
| 129 | |
| 130 | enum { |
| 131 | CC_OP_DYNAMIC, /* Use env->cc_op */ |
| 132 | CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */ |
| 133 | CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */ |
| 134 | CC_OP_ADD, /* CC_DEST = result, CC_SRC = source */ |
| 135 | CC_OP_SUB, /* CC_DEST = result, CC_SRC = source */ |
| 136 | CC_OP_CMPB, /* CC_DEST = result, CC_SRC = source */ |
| 137 | CC_OP_CMPW, /* CC_DEST = result, CC_SRC = source */ |
| 138 | CC_OP_ADDX, /* CC_DEST = result, CC_SRC = source */ |
| 139 | CC_OP_SUBX, /* CC_DEST = result, CC_SRC = source */ |
pbrook | e1f3808 | 2008-05-24 22:29:16 +0000 | [diff] [blame] | 140 | CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */ |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 141 | }; |
| 142 | |
| 143 | #define CCF_C 0x01 |
| 144 | #define CCF_V 0x02 |
| 145 | #define CCF_Z 0x04 |
| 146 | #define CCF_N 0x08 |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 147 | #define CCF_X 0x10 |
| 148 | |
| 149 | #define SR_I_SHIFT 8 |
| 150 | #define SR_I 0x0700 |
| 151 | #define SR_M 0x1000 |
| 152 | #define SR_S 0x2000 |
| 153 | #define SR_T 0x8000 |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 154 | |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 155 | #define M68K_SSP 0 |
| 156 | #define M68K_USP 1 |
| 157 | |
| 158 | /* CACR fields are implementation defined, but some bits are common. */ |
| 159 | #define M68K_CACR_EUSP 0x10 |
| 160 | |
pbrook | acf930a | 2007-05-29 14:57:59 +0000 | [diff] [blame] | 161 | #define MACSR_PAV0 0x100 |
| 162 | #define MACSR_OMC 0x080 |
| 163 | #define MACSR_SU 0x040 |
| 164 | #define MACSR_FI 0x020 |
| 165 | #define MACSR_RT 0x010 |
| 166 | #define MACSR_N 0x008 |
| 167 | #define MACSR_Z 0x004 |
| 168 | #define MACSR_V 0x002 |
| 169 | #define MACSR_EV 0x001 |
| 170 | |
Andreas Färber | cb3fb38 | 2013-01-18 14:20:52 +0100 | [diff] [blame] | 171 | void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); |
pbrook | acf930a | 2007-05-29 14:57:59 +0000 | [diff] [blame] | 172 | void m68k_set_macsr(CPUM68KState *env, uint32_t val); |
pbrook | 20dcee9 | 2007-06-03 11:13:39 +0000 | [diff] [blame] | 173 | void m68k_switch_sp(CPUM68KState *env); |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 174 | |
| 175 | #define M68K_FPCR_PREC (1 << 6) |
| 176 | |
pbrook | a87295e | 2007-05-26 15:09:38 +0000 | [diff] [blame] | 177 | void do_m68k_semihosting(CPUM68KState *env, int nr); |
| 178 | |
pbrook | d315c88 | 2007-06-03 12:35:08 +0000 | [diff] [blame] | 179 | /* There are 4 ColdFire core ISA revisions: A, A+, B and C. |
| 180 | Each feature covers the subset of instructions common to the |
| 181 | ISA revisions mentioned. */ |
| 182 | |
pbrook | 0402f76 | 2007-05-26 16:52:21 +0000 | [diff] [blame] | 183 | enum m68k_features { |
| 184 | M68K_FEATURE_CF_ISA_A, |
pbrook | d315c88 | 2007-06-03 12:35:08 +0000 | [diff] [blame] | 185 | M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ |
| 186 | M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ |
| 187 | M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ |
pbrook | 0402f76 | 2007-05-26 16:52:21 +0000 | [diff] [blame] | 188 | M68K_FEATURE_CF_FPU, |
| 189 | M68K_FEATURE_CF_MAC, |
| 190 | M68K_FEATURE_CF_EMAC, |
pbrook | d315c88 | 2007-06-03 12:35:08 +0000 | [diff] [blame] | 191 | M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ |
| 192 | M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ |
pbrook | e6dbd3b | 2007-05-26 21:16:48 +0000 | [diff] [blame] | 193 | M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ |
| 194 | M68K_FEATURE_WORD_INDEX /* word sized address index registers. */ |
pbrook | 0402f76 | 2007-05-26 16:52:21 +0000 | [diff] [blame] | 195 | }; |
| 196 | |
| 197 | static inline int m68k_feature(CPUM68KState *env, int feature) |
| 198 | { |
| 199 | return (env->features & (1u << feature)) != 0; |
| 200 | } |
| 201 | |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 202 | void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
Laurent Vivier | 009a435 | 2009-05-09 22:21:39 +0200 | [diff] [blame] | 203 | |
pbrook | 0402f76 | 2007-05-26 16:52:21 +0000 | [diff] [blame] | 204 | void register_m68k_insns (CPUM68KState *env); |
| 205 | |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 206 | #ifdef CONFIG_USER_ONLY |
| 207 | /* Linux uses 8k pages. */ |
| 208 | #define TARGET_PAGE_BITS 13 |
| 209 | #else |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 210 | /* Smallest TLB entry size is 1k. */ |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 211 | #define TARGET_PAGE_BITS 10 |
| 212 | #endif |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 213 | |
Richard Henderson | 5270589 | 2010-03-10 14:33:23 -0800 | [diff] [blame] | 214 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
| 215 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
| 216 | |
Andreas Färber | c7937d9 | 2013-01-18 14:03:58 +0100 | [diff] [blame] | 217 | static inline CPUM68KState *cpu_init(const char *cpu_model) |
| 218 | { |
| 219 | M68kCPU *cpu = cpu_m68k_init(cpu_model); |
| 220 | if (cpu == NULL) { |
| 221 | return NULL; |
| 222 | } |
| 223 | return &cpu->env; |
| 224 | } |
| 225 | |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 226 | #define cpu_exec cpu_m68k_exec |
| 227 | #define cpu_gen_code cpu_m68k_gen_code |
| 228 | #define cpu_signal_handler cpu_m68k_signal_handler |
Laurent Vivier | 009a435 | 2009-05-09 22:21:39 +0200 | [diff] [blame] | 229 | #define cpu_list m68k_cpu_list |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 230 | |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 231 | /* MMU modes definitions */ |
| 232 | #define MMU_MODE0_SUFFIX _kernel |
| 233 | #define MMU_MODE1_SUFFIX _user |
| 234 | #define MMU_USER_IDX 1 |
Andreas Färber | 2b3e3cf | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 235 | static inline int cpu_mmu_index (CPUM68KState *env) |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 236 | { |
| 237 | return (env->sr & SR_S) == 0 ? 1 : 0; |
| 238 | } |
| 239 | |
Andreas Färber | 2b3e3cf | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 240 | int cpu_m68k_handle_mmu_fault(CPUM68KState *env, target_ulong address, int rw, |
Blue Swirl | 97b348e | 2011-08-01 16:12:17 +0000 | [diff] [blame] | 241 | int mmu_idx); |
Nathan Froyd | 0b5c1ce | 2009-08-10 13:37:36 -0700 | [diff] [blame] | 242 | #define cpu_handle_mmu_fault cpu_m68k_handle_mmu_fault |
aurel32 | aaedd1f | 2009-03-07 21:48:08 +0000 | [diff] [blame] | 243 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 244 | #include "exec/cpu-all.h" |
aliguori | 622ed36 | 2008-11-18 19:36:03 +0000 | [diff] [blame] | 245 | |
Andreas Färber | 2b3e3cf | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 246 | static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 247 | target_ulong *cs_base, int *flags) |
| 248 | { |
| 249 | *pc = env->pc; |
| 250 | *cs_base = 0; |
| 251 | *flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */ |
| 252 | | (env->sr & SR_S) /* Bit 13 */ |
| 253 | | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ |
| 254 | } |
| 255 | |
Andreas Färber | 3993c6b | 2012-05-03 06:43:49 +0200 | [diff] [blame] | 256 | static inline bool cpu_has_work(CPUState *cpu) |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 257 | { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 258 | return cpu->interrupt_request & CPU_INTERRUPT_HARD; |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 259 | } |
| 260 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 261 | #include "exec/exec-all.h" |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 262 | |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 263 | #endif |