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bellard5a9fdfe2003-06-15 20:02:25 +00001/*
2 * defines common to all virtual CPUs
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard5a9fdfe2003-06-15 20:02:25 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard5a9fdfe2003-06-15 20:02:25 +000018 */
19#ifndef CPU_ALL_H
20#define CPU_ALL_H
21
blueswir17d99a002009-01-14 19:00:36 +000022#include "qemu-common.h"
Paul Brook1ad21342009-05-19 16:17:58 +010023#include "cpu-common.h"
bellard0ac4bd52004-01-04 15:44:17 +000024
ths5fafdf22007-09-16 21:08:06 +000025/* some important defines:
26 *
bellard0ac4bd52004-01-04 15:44:17 +000027 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
28 * memory accesses.
ths5fafdf22007-09-16 21:08:06 +000029 *
Juan Quintelae2542fe2009-07-27 16:13:06 +020030 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
bellard0ac4bd52004-01-04 15:44:17 +000031 * otherwise little endian.
ths5fafdf22007-09-16 21:08:06 +000032 *
bellard0ac4bd52004-01-04 15:44:17 +000033 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
ths5fafdf22007-09-16 21:08:06 +000034 *
bellard0ac4bd52004-01-04 15:44:17 +000035 * TARGET_WORDS_BIGENDIAN : same for target cpu
36 */
37
aurel32939ef592008-05-09 18:45:47 +000038#include "softfloat.h"
bellardf193c792004-03-21 17:06:25 +000039
Juan Quintelae2542fe2009-07-27 16:13:06 +020040#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
bellardf193c792004-03-21 17:06:25 +000041#define BSWAP_NEEDED
42#endif
43
44#ifdef BSWAP_NEEDED
45
46static inline uint16_t tswap16(uint16_t s)
47{
48 return bswap16(s);
49}
50
51static inline uint32_t tswap32(uint32_t s)
52{
53 return bswap32(s);
54}
55
56static inline uint64_t tswap64(uint64_t s)
57{
58 return bswap64(s);
59}
60
61static inline void tswap16s(uint16_t *s)
62{
63 *s = bswap16(*s);
64}
65
66static inline void tswap32s(uint32_t *s)
67{
68 *s = bswap32(*s);
69}
70
71static inline void tswap64s(uint64_t *s)
72{
73 *s = bswap64(*s);
74}
75
76#else
77
78static inline uint16_t tswap16(uint16_t s)
79{
80 return s;
81}
82
83static inline uint32_t tswap32(uint32_t s)
84{
85 return s;
86}
87
88static inline uint64_t tswap64(uint64_t s)
89{
90 return s;
91}
92
93static inline void tswap16s(uint16_t *s)
94{
95}
96
97static inline void tswap32s(uint32_t *s)
98{
99}
100
101static inline void tswap64s(uint64_t *s)
102{
103}
104
105#endif
106
107#if TARGET_LONG_SIZE == 4
108#define tswapl(s) tswap32(s)
109#define tswapls(s) tswap32s((uint32_t *)(s))
bellard0a962c02005-02-10 22:00:27 +0000110#define bswaptls(s) bswap32s(s)
bellardf193c792004-03-21 17:06:25 +0000111#else
112#define tswapl(s) tswap64(s)
113#define tswapls(s) tswap64s((uint64_t *)(s))
bellard0a962c02005-02-10 22:00:27 +0000114#define bswaptls(s) bswap64s(s)
bellardf193c792004-03-21 17:06:25 +0000115#endif
116
aurel320ca9d382008-03-13 19:19:16 +0000117typedef union {
118 float32 f;
119 uint32_t l;
120} CPU_FloatU;
121
bellard832ed0f2005-02-07 12:35:16 +0000122/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
123 endian ! */
bellard0ac4bd52004-01-04 15:44:17 +0000124typedef union {
bellard53cd6632005-03-13 18:50:23 +0000125 float64 d;
Juan Quintelae2542fe2009-07-27 16:13:06 +0200126#if defined(HOST_WORDS_BIGENDIAN) \
bellard9d60cac2005-04-07 19:55:52 +0000127 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
bellard0ac4bd52004-01-04 15:44:17 +0000128 struct {
bellard0ac4bd52004-01-04 15:44:17 +0000129 uint32_t upper;
bellard832ed0f2005-02-07 12:35:16 +0000130 uint32_t lower;
bellard0ac4bd52004-01-04 15:44:17 +0000131 } l;
132#else
133 struct {
bellard0ac4bd52004-01-04 15:44:17 +0000134 uint32_t lower;
bellard832ed0f2005-02-07 12:35:16 +0000135 uint32_t upper;
bellard0ac4bd52004-01-04 15:44:17 +0000136 } l;
137#endif
138 uint64_t ll;
139} CPU_DoubleU;
140
blueswir11f587322007-11-25 18:40:20 +0000141#ifdef TARGET_SPARC
142typedef union {
143 float128 q;
Juan Quintelae2542fe2009-07-27 16:13:06 +0200144#if defined(HOST_WORDS_BIGENDIAN) \
blueswir11f587322007-11-25 18:40:20 +0000145 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
146 struct {
147 uint32_t upmost;
148 uint32_t upper;
149 uint32_t lower;
150 uint32_t lowest;
151 } l;
152 struct {
153 uint64_t upper;
154 uint64_t lower;
155 } ll;
156#else
157 struct {
158 uint32_t lowest;
159 uint32_t lower;
160 uint32_t upper;
161 uint32_t upmost;
162 } l;
163 struct {
164 uint64_t lower;
165 uint64_t upper;
166 } ll;
167#endif
168} CPU_QuadU;
169#endif
170
bellard61382a52003-10-27 21:22:23 +0000171/* CPU memory access without any memory or io remapping */
172
bellard83d73962004-02-22 11:53:50 +0000173/*
174 * the generic syntax for the memory accesses is:
175 *
176 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
177 *
178 * store: st{type}{size}{endian}_{access_type}(ptr, val)
179 *
180 * type is:
181 * (empty): integer access
182 * f : float access
ths5fafdf22007-09-16 21:08:06 +0000183 *
bellard83d73962004-02-22 11:53:50 +0000184 * sign is:
185 * (empty): for floats or 32 bit size
186 * u : unsigned
187 * s : signed
188 *
189 * size is:
190 * b: 8 bits
191 * w: 16 bits
192 * l: 32 bits
193 * q: 64 bits
ths5fafdf22007-09-16 21:08:06 +0000194 *
bellard83d73962004-02-22 11:53:50 +0000195 * endian is:
196 * (empty): target cpu endianness or 8 bit access
197 * r : reversed target cpu endianness (not implemented yet)
198 * be : big endian (not implemented yet)
199 * le : little endian (not implemented yet)
200 *
201 * access_type is:
202 * raw : host memory access
203 * user : user mode access using soft MMU
204 * kernel : kernel mode access using soft MMU
205 */
balrog8bba3ea2008-12-07 23:44:44 +0000206static inline int ldub_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000207{
208 return *(uint8_t *)ptr;
209}
210
balrog8bba3ea2008-12-07 23:44:44 +0000211static inline int ldsb_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000212{
213 return *(int8_t *)ptr;
214}
215
bellardc27004e2005-01-03 23:35:10 +0000216static inline void stb_p(void *ptr, int v)
bellard5a9fdfe2003-06-15 20:02:25 +0000217{
218 *(uint8_t *)ptr = v;
219}
220
221/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
222 kernel handles unaligned load/stores may give better results, but
223 it is a system wide setting : bad */
Juan Quintelae2542fe2009-07-27 16:13:06 +0200224#if defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
bellard5a9fdfe2003-06-15 20:02:25 +0000225
226/* conservative code for little endian unaligned accesses */
balrog8bba3ea2008-12-07 23:44:44 +0000227static inline int lduw_le_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000228{
malce58ffeb2009-01-14 18:39:49 +0000229#ifdef _ARCH_PPC
bellard5a9fdfe2003-06-15 20:02:25 +0000230 int val;
231 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
232 return val;
233#else
malce01fe6d2008-12-11 00:14:30 +0000234 const uint8_t *p = ptr;
bellard5a9fdfe2003-06-15 20:02:25 +0000235 return p[0] | (p[1] << 8);
236#endif
237}
238
balrog8bba3ea2008-12-07 23:44:44 +0000239static inline int ldsw_le_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000240{
malce58ffeb2009-01-14 18:39:49 +0000241#ifdef _ARCH_PPC
bellard5a9fdfe2003-06-15 20:02:25 +0000242 int val;
243 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
244 return (int16_t)val;
245#else
malce01fe6d2008-12-11 00:14:30 +0000246 const uint8_t *p = ptr;
bellard5a9fdfe2003-06-15 20:02:25 +0000247 return (int16_t)(p[0] | (p[1] << 8));
248#endif
249}
250
balrog8bba3ea2008-12-07 23:44:44 +0000251static inline int ldl_le_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000252{
malce58ffeb2009-01-14 18:39:49 +0000253#ifdef _ARCH_PPC
bellard5a9fdfe2003-06-15 20:02:25 +0000254 int val;
255 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
256 return val;
257#else
malce01fe6d2008-12-11 00:14:30 +0000258 const uint8_t *p = ptr;
bellard5a9fdfe2003-06-15 20:02:25 +0000259 return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
260#endif
261}
262
balrog8bba3ea2008-12-07 23:44:44 +0000263static inline uint64_t ldq_le_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000264{
malce01fe6d2008-12-11 00:14:30 +0000265 const uint8_t *p = ptr;
bellard5a9fdfe2003-06-15 20:02:25 +0000266 uint32_t v1, v2;
bellardf0aca822005-11-21 23:22:06 +0000267 v1 = ldl_le_p(p);
268 v2 = ldl_le_p(p + 4);
bellard5a9fdfe2003-06-15 20:02:25 +0000269 return v1 | ((uint64_t)v2 << 32);
270}
271
bellard2df3b952005-11-19 17:47:39 +0000272static inline void stw_le_p(void *ptr, int v)
bellard5a9fdfe2003-06-15 20:02:25 +0000273{
malce58ffeb2009-01-14 18:39:49 +0000274#ifdef _ARCH_PPC
bellard5a9fdfe2003-06-15 20:02:25 +0000275 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
276#else
277 uint8_t *p = ptr;
278 p[0] = v;
279 p[1] = v >> 8;
280#endif
281}
282
bellard2df3b952005-11-19 17:47:39 +0000283static inline void stl_le_p(void *ptr, int v)
bellard5a9fdfe2003-06-15 20:02:25 +0000284{
malce58ffeb2009-01-14 18:39:49 +0000285#ifdef _ARCH_PPC
bellard5a9fdfe2003-06-15 20:02:25 +0000286 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
287#else
288 uint8_t *p = ptr;
289 p[0] = v;
290 p[1] = v >> 8;
291 p[2] = v >> 16;
292 p[3] = v >> 24;
293#endif
294}
295
bellard2df3b952005-11-19 17:47:39 +0000296static inline void stq_le_p(void *ptr, uint64_t v)
bellard5a9fdfe2003-06-15 20:02:25 +0000297{
298 uint8_t *p = ptr;
bellardf0aca822005-11-21 23:22:06 +0000299 stl_le_p(p, (uint32_t)v);
300 stl_le_p(p + 4, v >> 32);
bellard5a9fdfe2003-06-15 20:02:25 +0000301}
302
303/* float access */
304
balrog8bba3ea2008-12-07 23:44:44 +0000305static inline float32 ldfl_le_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000306{
307 union {
bellard53cd6632005-03-13 18:50:23 +0000308 float32 f;
bellard5a9fdfe2003-06-15 20:02:25 +0000309 uint32_t i;
310 } u;
bellard2df3b952005-11-19 17:47:39 +0000311 u.i = ldl_le_p(ptr);
bellard5a9fdfe2003-06-15 20:02:25 +0000312 return u.f;
313}
314
bellard2df3b952005-11-19 17:47:39 +0000315static inline void stfl_le_p(void *ptr, float32 v)
bellard5a9fdfe2003-06-15 20:02:25 +0000316{
317 union {
bellard53cd6632005-03-13 18:50:23 +0000318 float32 f;
bellard5a9fdfe2003-06-15 20:02:25 +0000319 uint32_t i;
320 } u;
321 u.f = v;
bellard2df3b952005-11-19 17:47:39 +0000322 stl_le_p(ptr, u.i);
bellard5a9fdfe2003-06-15 20:02:25 +0000323}
324
balrog8bba3ea2008-12-07 23:44:44 +0000325static inline float64 ldfq_le_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000326{
bellard0ac4bd52004-01-04 15:44:17 +0000327 CPU_DoubleU u;
bellard2df3b952005-11-19 17:47:39 +0000328 u.l.lower = ldl_le_p(ptr);
329 u.l.upper = ldl_le_p(ptr + 4);
bellard5a9fdfe2003-06-15 20:02:25 +0000330 return u.d;
331}
332
bellard2df3b952005-11-19 17:47:39 +0000333static inline void stfq_le_p(void *ptr, float64 v)
bellard5a9fdfe2003-06-15 20:02:25 +0000334{
bellard0ac4bd52004-01-04 15:44:17 +0000335 CPU_DoubleU u;
bellard5a9fdfe2003-06-15 20:02:25 +0000336 u.d = v;
bellard2df3b952005-11-19 17:47:39 +0000337 stl_le_p(ptr, u.l.lower);
338 stl_le_p(ptr + 4, u.l.upper);
bellard5a9fdfe2003-06-15 20:02:25 +0000339}
340
bellard2df3b952005-11-19 17:47:39 +0000341#else
bellard93ac68b2003-09-30 20:57:29 +0000342
balrog8bba3ea2008-12-07 23:44:44 +0000343static inline int lduw_le_p(const void *ptr)
bellard2df3b952005-11-19 17:47:39 +0000344{
345 return *(uint16_t *)ptr;
346}
347
balrog8bba3ea2008-12-07 23:44:44 +0000348static inline int ldsw_le_p(const void *ptr)
bellard2df3b952005-11-19 17:47:39 +0000349{
350 return *(int16_t *)ptr;
351}
352
balrog8bba3ea2008-12-07 23:44:44 +0000353static inline int ldl_le_p(const void *ptr)
bellard2df3b952005-11-19 17:47:39 +0000354{
355 return *(uint32_t *)ptr;
356}
357
balrog8bba3ea2008-12-07 23:44:44 +0000358static inline uint64_t ldq_le_p(const void *ptr)
bellard2df3b952005-11-19 17:47:39 +0000359{
360 return *(uint64_t *)ptr;
361}
362
363static inline void stw_le_p(void *ptr, int v)
364{
365 *(uint16_t *)ptr = v;
366}
367
368static inline void stl_le_p(void *ptr, int v)
369{
370 *(uint32_t *)ptr = v;
371}
372
373static inline void stq_le_p(void *ptr, uint64_t v)
374{
375 *(uint64_t *)ptr = v;
376}
377
378/* float access */
379
balrog8bba3ea2008-12-07 23:44:44 +0000380static inline float32 ldfl_le_p(const void *ptr)
bellard2df3b952005-11-19 17:47:39 +0000381{
382 return *(float32 *)ptr;
383}
384
balrog8bba3ea2008-12-07 23:44:44 +0000385static inline float64 ldfq_le_p(const void *ptr)
bellard2df3b952005-11-19 17:47:39 +0000386{
387 return *(float64 *)ptr;
388}
389
390static inline void stfl_le_p(void *ptr, float32 v)
391{
392 *(float32 *)ptr = v;
393}
394
395static inline void stfq_le_p(void *ptr, float64 v)
396{
397 *(float64 *)ptr = v;
398}
399#endif
400
Juan Quintelae2542fe2009-07-27 16:13:06 +0200401#if !defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
bellard2df3b952005-11-19 17:47:39 +0000402
balrog8bba3ea2008-12-07 23:44:44 +0000403static inline int lduw_be_p(const void *ptr)
bellard93ac68b2003-09-30 20:57:29 +0000404{
bellard83d73962004-02-22 11:53:50 +0000405#if defined(__i386__)
406 int val;
407 asm volatile ("movzwl %1, %0\n"
408 "xchgb %b0, %h0\n"
409 : "=q" (val)
410 : "m" (*(uint16_t *)ptr));
411 return val;
412#else
malce01fe6d2008-12-11 00:14:30 +0000413 const uint8_t *b = ptr;
bellard83d73962004-02-22 11:53:50 +0000414 return ((b[0] << 8) | b[1]);
415#endif
bellard93ac68b2003-09-30 20:57:29 +0000416}
417
balrog8bba3ea2008-12-07 23:44:44 +0000418static inline int ldsw_be_p(const void *ptr)
bellard93ac68b2003-09-30 20:57:29 +0000419{
bellard83d73962004-02-22 11:53:50 +0000420#if defined(__i386__)
421 int val;
422 asm volatile ("movzwl %1, %0\n"
423 "xchgb %b0, %h0\n"
424 : "=q" (val)
425 : "m" (*(uint16_t *)ptr));
426 return (int16_t)val;
427#else
malce01fe6d2008-12-11 00:14:30 +0000428 const uint8_t *b = ptr;
bellard83d73962004-02-22 11:53:50 +0000429 return (int16_t)((b[0] << 8) | b[1]);
430#endif
bellard93ac68b2003-09-30 20:57:29 +0000431}
432
balrog8bba3ea2008-12-07 23:44:44 +0000433static inline int ldl_be_p(const void *ptr)
bellard93ac68b2003-09-30 20:57:29 +0000434{
bellard4f2ac232004-04-26 19:44:02 +0000435#if defined(__i386__) || defined(__x86_64__)
bellard83d73962004-02-22 11:53:50 +0000436 int val;
437 asm volatile ("movl %1, %0\n"
438 "bswap %0\n"
439 : "=r" (val)
440 : "m" (*(uint32_t *)ptr));
441 return val;
442#else
malce01fe6d2008-12-11 00:14:30 +0000443 const uint8_t *b = ptr;
bellard83d73962004-02-22 11:53:50 +0000444 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
445#endif
bellard93ac68b2003-09-30 20:57:29 +0000446}
447
balrog8bba3ea2008-12-07 23:44:44 +0000448static inline uint64_t ldq_be_p(const void *ptr)
bellard93ac68b2003-09-30 20:57:29 +0000449{
450 uint32_t a,b;
bellard2df3b952005-11-19 17:47:39 +0000451 a = ldl_be_p(ptr);
blueswir14d7a0882008-05-10 10:14:22 +0000452 b = ldl_be_p((uint8_t *)ptr + 4);
bellard93ac68b2003-09-30 20:57:29 +0000453 return (((uint64_t)a<<32)|b);
454}
455
bellard2df3b952005-11-19 17:47:39 +0000456static inline void stw_be_p(void *ptr, int v)
bellard93ac68b2003-09-30 20:57:29 +0000457{
bellard83d73962004-02-22 11:53:50 +0000458#if defined(__i386__)
459 asm volatile ("xchgb %b0, %h0\n"
460 "movw %w0, %1\n"
461 : "=q" (v)
462 : "m" (*(uint16_t *)ptr), "0" (v));
463#else
bellard93ac68b2003-09-30 20:57:29 +0000464 uint8_t *d = (uint8_t *) ptr;
465 d[0] = v >> 8;
466 d[1] = v;
bellard83d73962004-02-22 11:53:50 +0000467#endif
bellard93ac68b2003-09-30 20:57:29 +0000468}
469
bellard2df3b952005-11-19 17:47:39 +0000470static inline void stl_be_p(void *ptr, int v)
bellard93ac68b2003-09-30 20:57:29 +0000471{
bellard4f2ac232004-04-26 19:44:02 +0000472#if defined(__i386__) || defined(__x86_64__)
bellard83d73962004-02-22 11:53:50 +0000473 asm volatile ("bswap %0\n"
474 "movl %0, %1\n"
475 : "=r" (v)
476 : "m" (*(uint32_t *)ptr), "0" (v));
477#else
bellard93ac68b2003-09-30 20:57:29 +0000478 uint8_t *d = (uint8_t *) ptr;
479 d[0] = v >> 24;
480 d[1] = v >> 16;
481 d[2] = v >> 8;
482 d[3] = v;
bellard83d73962004-02-22 11:53:50 +0000483#endif
bellard93ac68b2003-09-30 20:57:29 +0000484}
485
bellard2df3b952005-11-19 17:47:39 +0000486static inline void stq_be_p(void *ptr, uint64_t v)
bellard93ac68b2003-09-30 20:57:29 +0000487{
bellard2df3b952005-11-19 17:47:39 +0000488 stl_be_p(ptr, v >> 32);
blueswir14d7a0882008-05-10 10:14:22 +0000489 stl_be_p((uint8_t *)ptr + 4, v);
bellard0ac4bd52004-01-04 15:44:17 +0000490}
491
492/* float access */
493
balrog8bba3ea2008-12-07 23:44:44 +0000494static inline float32 ldfl_be_p(const void *ptr)
bellard0ac4bd52004-01-04 15:44:17 +0000495{
496 union {
bellard53cd6632005-03-13 18:50:23 +0000497 float32 f;
bellard0ac4bd52004-01-04 15:44:17 +0000498 uint32_t i;
499 } u;
bellard2df3b952005-11-19 17:47:39 +0000500 u.i = ldl_be_p(ptr);
bellard0ac4bd52004-01-04 15:44:17 +0000501 return u.f;
502}
503
bellard2df3b952005-11-19 17:47:39 +0000504static inline void stfl_be_p(void *ptr, float32 v)
bellard0ac4bd52004-01-04 15:44:17 +0000505{
506 union {
bellard53cd6632005-03-13 18:50:23 +0000507 float32 f;
bellard0ac4bd52004-01-04 15:44:17 +0000508 uint32_t i;
509 } u;
510 u.f = v;
bellard2df3b952005-11-19 17:47:39 +0000511 stl_be_p(ptr, u.i);
bellard0ac4bd52004-01-04 15:44:17 +0000512}
513
balrog8bba3ea2008-12-07 23:44:44 +0000514static inline float64 ldfq_be_p(const void *ptr)
bellard0ac4bd52004-01-04 15:44:17 +0000515{
516 CPU_DoubleU u;
bellard2df3b952005-11-19 17:47:39 +0000517 u.l.upper = ldl_be_p(ptr);
blueswir14d7a0882008-05-10 10:14:22 +0000518 u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
bellard0ac4bd52004-01-04 15:44:17 +0000519 return u.d;
520}
521
bellard2df3b952005-11-19 17:47:39 +0000522static inline void stfq_be_p(void *ptr, float64 v)
bellard0ac4bd52004-01-04 15:44:17 +0000523{
524 CPU_DoubleU u;
525 u.d = v;
bellard2df3b952005-11-19 17:47:39 +0000526 stl_be_p(ptr, u.l.upper);
blueswir14d7a0882008-05-10 10:14:22 +0000527 stl_be_p((uint8_t *)ptr + 4, u.l.lower);
bellard93ac68b2003-09-30 20:57:29 +0000528}
529
bellard5a9fdfe2003-06-15 20:02:25 +0000530#else
531
balrog8bba3ea2008-12-07 23:44:44 +0000532static inline int lduw_be_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000533{
534 return *(uint16_t *)ptr;
535}
536
balrog8bba3ea2008-12-07 23:44:44 +0000537static inline int ldsw_be_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000538{
539 return *(int16_t *)ptr;
540}
541
balrog8bba3ea2008-12-07 23:44:44 +0000542static inline int ldl_be_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000543{
544 return *(uint32_t *)ptr;
545}
546
balrog8bba3ea2008-12-07 23:44:44 +0000547static inline uint64_t ldq_be_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000548{
549 return *(uint64_t *)ptr;
550}
551
bellard2df3b952005-11-19 17:47:39 +0000552static inline void stw_be_p(void *ptr, int v)
bellard5a9fdfe2003-06-15 20:02:25 +0000553{
554 *(uint16_t *)ptr = v;
555}
556
bellard2df3b952005-11-19 17:47:39 +0000557static inline void stl_be_p(void *ptr, int v)
bellard5a9fdfe2003-06-15 20:02:25 +0000558{
559 *(uint32_t *)ptr = v;
560}
561
bellard2df3b952005-11-19 17:47:39 +0000562static inline void stq_be_p(void *ptr, uint64_t v)
bellard5a9fdfe2003-06-15 20:02:25 +0000563{
564 *(uint64_t *)ptr = v;
565}
566
567/* float access */
568
balrog8bba3ea2008-12-07 23:44:44 +0000569static inline float32 ldfl_be_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000570{
bellard53cd6632005-03-13 18:50:23 +0000571 return *(float32 *)ptr;
bellard5a9fdfe2003-06-15 20:02:25 +0000572}
573
balrog8bba3ea2008-12-07 23:44:44 +0000574static inline float64 ldfq_be_p(const void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000575{
bellard53cd6632005-03-13 18:50:23 +0000576 return *(float64 *)ptr;
bellard5a9fdfe2003-06-15 20:02:25 +0000577}
578
bellard2df3b952005-11-19 17:47:39 +0000579static inline void stfl_be_p(void *ptr, float32 v)
bellard5a9fdfe2003-06-15 20:02:25 +0000580{
bellard53cd6632005-03-13 18:50:23 +0000581 *(float32 *)ptr = v;
bellard5a9fdfe2003-06-15 20:02:25 +0000582}
583
bellard2df3b952005-11-19 17:47:39 +0000584static inline void stfq_be_p(void *ptr, float64 v)
bellard5a9fdfe2003-06-15 20:02:25 +0000585{
bellard53cd6632005-03-13 18:50:23 +0000586 *(float64 *)ptr = v;
bellard5a9fdfe2003-06-15 20:02:25 +0000587}
bellard2df3b952005-11-19 17:47:39 +0000588
589#endif
590
591/* target CPU memory access functions */
592#if defined(TARGET_WORDS_BIGENDIAN)
593#define lduw_p(p) lduw_be_p(p)
594#define ldsw_p(p) ldsw_be_p(p)
595#define ldl_p(p) ldl_be_p(p)
596#define ldq_p(p) ldq_be_p(p)
597#define ldfl_p(p) ldfl_be_p(p)
598#define ldfq_p(p) ldfq_be_p(p)
599#define stw_p(p, v) stw_be_p(p, v)
600#define stl_p(p, v) stl_be_p(p, v)
601#define stq_p(p, v) stq_be_p(p, v)
602#define stfl_p(p, v) stfl_be_p(p, v)
603#define stfq_p(p, v) stfq_be_p(p, v)
604#else
605#define lduw_p(p) lduw_le_p(p)
606#define ldsw_p(p) ldsw_le_p(p)
607#define ldl_p(p) ldl_le_p(p)
608#define ldq_p(p) ldq_le_p(p)
609#define ldfl_p(p) ldfl_le_p(p)
610#define ldfq_p(p) ldfq_le_p(p)
611#define stw_p(p, v) stw_le_p(p, v)
612#define stl_p(p, v) stl_le_p(p, v)
613#define stq_p(p, v) stq_le_p(p, v)
614#define stfl_p(p, v) stfl_le_p(p, v)
615#define stfq_p(p, v) stfq_le_p(p, v)
bellard5a9fdfe2003-06-15 20:02:25 +0000616#endif
617
bellard61382a52003-10-27 21:22:23 +0000618/* MMU memory access macros */
619
pbrook53a59602006-03-25 19:31:22 +0000620#if defined(CONFIG_USER_ONLY)
aurel320e62fd72008-12-08 18:12:11 +0000621#include <assert.h>
622#include "qemu-types.h"
623
pbrook53a59602006-03-25 19:31:22 +0000624/* On some host systems the guest address space is reserved on the host.
625 * This allows the guest address space to be offset to a convenient location.
626 */
Paul Brook379f6692009-07-17 12:48:08 +0100627#if defined(CONFIG_USE_GUEST_BASE)
628extern unsigned long guest_base;
629extern int have_guest_base;
630#define GUEST_BASE guest_base
631#else
632#define GUEST_BASE 0ul
633#endif
pbrook53a59602006-03-25 19:31:22 +0000634
635/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
636#define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
Richard Hendersonb9f83122010-03-10 14:36:58 -0800637
638#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
639#define h2g_valid(x) 1
640#else
641#define h2g_valid(x) ({ \
642 unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
643 __guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS); \
644})
645#endif
646
aurel320e62fd72008-12-08 18:12:11 +0000647#define h2g(x) ({ \
648 unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
649 /* Check if given address fits target address space */ \
Richard Hendersonb9f83122010-03-10 14:36:58 -0800650 assert(h2g_valid(x)); \
aurel320e62fd72008-12-08 18:12:11 +0000651 (abi_ulong)__ret; \
652})
pbrook53a59602006-03-25 19:31:22 +0000653
654#define saddr(x) g2h(x)
655#define laddr(x) g2h(x)
656
657#else /* !CONFIG_USER_ONLY */
bellardc27004e2005-01-03 23:35:10 +0000658/* NOTE: we use double casts if pointers and target_ulong have
659 different sizes */
pbrook53a59602006-03-25 19:31:22 +0000660#define saddr(x) (uint8_t *)(long)(x)
661#define laddr(x) (uint8_t *)(long)(x)
662#endif
663
664#define ldub_raw(p) ldub_p(laddr((p)))
665#define ldsb_raw(p) ldsb_p(laddr((p)))
666#define lduw_raw(p) lduw_p(laddr((p)))
667#define ldsw_raw(p) ldsw_p(laddr((p)))
668#define ldl_raw(p) ldl_p(laddr((p)))
669#define ldq_raw(p) ldq_p(laddr((p)))
670#define ldfl_raw(p) ldfl_p(laddr((p)))
671#define ldfq_raw(p) ldfq_p(laddr((p)))
672#define stb_raw(p, v) stb_p(saddr((p)), v)
673#define stw_raw(p, v) stw_p(saddr((p)), v)
674#define stl_raw(p, v) stl_p(saddr((p)), v)
675#define stq_raw(p, v) stq_p(saddr((p)), v)
676#define stfl_raw(p, v) stfl_p(saddr((p)), v)
677#define stfq_raw(p, v) stfq_p(saddr((p)), v)
bellardc27004e2005-01-03 23:35:10 +0000678
679
ths5fafdf22007-09-16 21:08:06 +0000680#if defined(CONFIG_USER_ONLY)
bellard61382a52003-10-27 21:22:23 +0000681
682/* if user mode, no other memory access functions */
683#define ldub(p) ldub_raw(p)
684#define ldsb(p) ldsb_raw(p)
685#define lduw(p) lduw_raw(p)
686#define ldsw(p) ldsw_raw(p)
687#define ldl(p) ldl_raw(p)
688#define ldq(p) ldq_raw(p)
689#define ldfl(p) ldfl_raw(p)
690#define ldfq(p) ldfq_raw(p)
691#define stb(p, v) stb_raw(p, v)
692#define stw(p, v) stw_raw(p, v)
693#define stl(p, v) stl_raw(p, v)
694#define stq(p, v) stq_raw(p, v)
695#define stfl(p, v) stfl_raw(p, v)
696#define stfq(p, v) stfq_raw(p, v)
697
698#define ldub_code(p) ldub_raw(p)
699#define ldsb_code(p) ldsb_raw(p)
700#define lduw_code(p) lduw_raw(p)
701#define ldsw_code(p) ldsw_raw(p)
702#define ldl_code(p) ldl_raw(p)
j_mayerbc98a7e2007-04-04 07:55:12 +0000703#define ldq_code(p) ldq_raw(p)
bellard61382a52003-10-27 21:22:23 +0000704
705#define ldub_kernel(p) ldub_raw(p)
706#define ldsb_kernel(p) ldsb_raw(p)
707#define lduw_kernel(p) lduw_raw(p)
708#define ldsw_kernel(p) ldsw_raw(p)
709#define ldl_kernel(p) ldl_raw(p)
j_mayerbc98a7e2007-04-04 07:55:12 +0000710#define ldq_kernel(p) ldq_raw(p)
bellard0ac4bd52004-01-04 15:44:17 +0000711#define ldfl_kernel(p) ldfl_raw(p)
712#define ldfq_kernel(p) ldfq_raw(p)
bellard61382a52003-10-27 21:22:23 +0000713#define stb_kernel(p, v) stb_raw(p, v)
714#define stw_kernel(p, v) stw_raw(p, v)
715#define stl_kernel(p, v) stl_raw(p, v)
716#define stq_kernel(p, v) stq_raw(p, v)
bellard0ac4bd52004-01-04 15:44:17 +0000717#define stfl_kernel(p, v) stfl_raw(p, v)
718#define stfq_kernel(p, vt) stfq_raw(p, v)
bellard61382a52003-10-27 21:22:23 +0000719
720#endif /* defined(CONFIG_USER_ONLY) */
721
bellard5a9fdfe2003-06-15 20:02:25 +0000722/* page related stuff */
723
aurel3203875442008-04-22 20:45:18 +0000724#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
bellard5a9fdfe2003-06-15 20:02:25 +0000725#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
726#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
727
pbrook53a59602006-03-25 19:31:22 +0000728/* ??? These should be the larger of unsigned long and target_ulong. */
bellard83fb7ad2004-07-05 21:25:26 +0000729extern unsigned long qemu_real_host_page_size;
730extern unsigned long qemu_host_page_bits;
731extern unsigned long qemu_host_page_size;
732extern unsigned long qemu_host_page_mask;
bellard5a9fdfe2003-06-15 20:02:25 +0000733
bellard83fb7ad2004-07-05 21:25:26 +0000734#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
bellard5a9fdfe2003-06-15 20:02:25 +0000735
736/* same as PROT_xxx */
737#define PAGE_READ 0x0001
738#define PAGE_WRITE 0x0002
739#define PAGE_EXEC 0x0004
740#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
741#define PAGE_VALID 0x0008
742/* original state of the write flag (used when tracking self-modifying
743 code */
ths5fafdf22007-09-16 21:08:06 +0000744#define PAGE_WRITE_ORG 0x0010
balrog50a95692007-12-12 01:16:23 +0000745#define PAGE_RESERVED 0x0020
bellard5a9fdfe2003-06-15 20:02:25 +0000746
Paul Brookb480d9b2010-03-12 23:23:29 +0000747#if defined(CONFIG_USER_ONLY)
bellard5a9fdfe2003-06-15 20:02:25 +0000748void page_dump(FILE *f);
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800749
Paul Brookb480d9b2010-03-12 23:23:29 +0000750typedef int (*walk_memory_regions_fn)(void *, abi_ulong,
751 abi_ulong, unsigned long);
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800752int walk_memory_regions(void *, walk_memory_regions_fn);
753
pbrook53a59602006-03-25 19:31:22 +0000754int page_get_flags(target_ulong address);
755void page_set_flags(target_ulong start, target_ulong end, int flags);
ths3d97b402007-11-02 19:02:07 +0000756int page_check_range(target_ulong start, target_ulong len, int flags);
Paul Brookb480d9b2010-03-12 23:23:29 +0000757#endif
bellard5a9fdfe2003-06-15 20:02:25 +0000758
bellard26a5f132008-05-28 12:30:31 +0000759void cpu_exec_init_all(unsigned long tb_size);
thsc5be9f02007-02-28 20:20:53 +0000760CPUState *cpu_copy(CPUState *env);
Glauber Costa950f1472009-06-09 12:15:18 -0400761CPUState *qemu_get_cpu(int cpu);
thsc5be9f02007-02-28 20:20:53 +0000762
ths5fafdf22007-09-16 21:08:06 +0000763void cpu_dump_state(CPUState *env, FILE *f,
bellard7fe48482004-10-09 18:08:01 +0000764 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
765 int flags);
j_mayer76a66252007-03-07 08:32:30 +0000766void cpu_dump_statistics (CPUState *env, FILE *f,
767 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
768 int flags);
bellard7fe48482004-10-09 18:08:01 +0000769
malca5e50b22009-02-01 22:19:27 +0000770void QEMU_NORETURN cpu_abort(CPUState *env, const char *fmt, ...)
blueswir17d99a002009-01-14 19:00:36 +0000771 __attribute__ ((__format__ (__printf__, 2, 3)));
bellardf0aca822005-11-21 23:22:06 +0000772extern CPUState *first_cpu;
bellarde2f22892003-06-25 16:09:48 +0000773extern CPUState *cpu_single_env;
Paolo Bonzinidb1a4972010-03-10 11:38:55 +0100774
775int64_t qemu_icount_round(int64_t count);
pbrook2e70f6e2008-06-29 01:03:05 +0000776extern int64_t qemu_icount;
777extern int use_icount;
bellard5a9fdfe2003-06-15 20:02:25 +0000778
bellard9acbed02004-02-16 21:57:02 +0000779#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
780#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
bellardef792f92004-05-17 20:19:32 +0000781#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
bellard98699962005-11-26 10:29:22 +0000782#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
bellardba3c64f2005-12-05 20:31:52 +0000783#define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
bellard3b21e032006-09-24 18:41:56 +0000784#define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
pbrook6658ffb2007-03-16 23:58:11 +0000785#define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */
ths0573fbf2007-09-23 15:28:04 +0000786#define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */
aurel32474ea842008-04-13 16:08:15 +0000787#define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300788#define CPU_INTERRUPT_INIT 0x400 /* INIT pending. */
789#define CPU_INTERRUPT_SIPI 0x800 /* SIPI pending. */
Huang Ying79c4f6b2009-06-23 10:05:14 +0800790#define CPU_INTERRUPT_MCE 0x1000 /* (x86 only) MCE pending. */
bellard98699962005-11-26 10:29:22 +0000791
bellard46907642003-07-07 12:17:46 +0000792void cpu_interrupt(CPUState *s, int mask);
bellardb54ad042004-05-20 13:42:52 +0000793void cpu_reset_interrupt(CPUState *env, int mask);
bellard68a79312003-06-30 13:12:32 +0000794
aurel323098dba2009-03-07 21:28:24 +0000795void cpu_exit(CPUState *s);
796
aliguori6a4955a2009-04-24 18:03:20 +0000797int qemu_cpu_has_work(CPUState *env);
798
aliguoria1d1bb32008-11-18 20:07:32 +0000799/* Breakpoint/watchpoint flags */
800#define BP_MEM_READ 0x01
801#define BP_MEM_WRITE 0x02
802#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
aliguori06d55cc2008-11-18 20:24:06 +0000803#define BP_STOP_BEFORE_ACCESS 0x04
aliguori6e140f22008-11-18 20:37:55 +0000804#define BP_WATCHPOINT_HIT 0x08
aliguoria1d1bb32008-11-18 20:07:32 +0000805#define BP_GDB 0x10
aliguori2dc9f412008-11-18 20:56:59 +0000806#define BP_CPU 0x20
aliguoria1d1bb32008-11-18 20:07:32 +0000807
808int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
809 CPUBreakpoint **breakpoint);
810int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags);
811void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint);
812void cpu_breakpoint_remove_all(CPUState *env, int mask);
813int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
814 int flags, CPUWatchpoint **watchpoint);
815int cpu_watchpoint_remove(CPUState *env, target_ulong addr,
816 target_ulong len, int flags);
817void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint);
818void cpu_watchpoint_remove_all(CPUState *env, int mask);
edgar_igl60897d32008-05-09 08:25:14 +0000819
820#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
821#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
822#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
823
bellardc33a3462003-07-29 20:50:33 +0000824void cpu_single_step(CPUState *env, int enabled);
bellardd95dc322004-06-20 12:35:26 +0000825void cpu_reset(CPUState *s);
bellard4c3a88a2003-07-26 12:06:08 +0000826
ths5fafdf22007-09-16 21:08:06 +0000827#define CPU_LOG_TB_OUT_ASM (1 << 0)
bellard9fddaa02004-05-21 12:59:32 +0000828#define CPU_LOG_TB_IN_ASM (1 << 1)
bellardf193c792004-03-21 17:06:25 +0000829#define CPU_LOG_TB_OP (1 << 2)
830#define CPU_LOG_TB_OP_OPT (1 << 3)
831#define CPU_LOG_INT (1 << 4)
832#define CPU_LOG_EXEC (1 << 5)
833#define CPU_LOG_PCALL (1 << 6)
bellardfd872592004-05-12 19:11:15 +0000834#define CPU_LOG_IOPORT (1 << 7)
bellard9fddaa02004-05-21 12:59:32 +0000835#define CPU_LOG_TB_CPU (1 << 8)
aliguorieca1bdf2009-01-26 19:54:31 +0000836#define CPU_LOG_RESET (1 << 9)
bellardf193c792004-03-21 17:06:25 +0000837
838/* define log items */
839typedef struct CPULogItem {
840 int mask;
841 const char *name;
842 const char *help;
843} CPULogItem;
844
blueswir1c7cd6a32008-10-02 18:27:46 +0000845extern const CPULogItem cpu_log_items[];
bellardf193c792004-03-21 17:06:25 +0000846
bellard34865132003-10-05 14:28:56 +0000847void cpu_set_log(int log_flags);
848void cpu_set_log_filename(const char *filename);
bellardf193c792004-03-21 17:06:25 +0000849int cpu_str_to_log_mask(const char *str);
bellard34865132003-10-05 14:28:56 +0000850
Paul Brookb3755a92010-03-12 16:54:58 +0000851#if !defined(CONFIG_USER_ONLY)
852
Paul Brook4fcc5622010-03-01 03:46:18 +0000853/* Return the physical page corresponding to a virtual one. Use it
854 only for debugging because no protection checks are done. Return -1
855 if no page found. */
856target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
857
bellard33417e72003-08-10 21:47:01 +0000858/* memory API */
859
bellardedf75d52004-01-04 17:43:30 +0000860extern int phys_ram_fd;
bellard1ccde1c2004-02-06 19:46:14 +0000861extern uint8_t *phys_ram_dirty;
Anthony Liguoric227f092009-10-01 16:12:16 -0500862extern ram_addr_t ram_size;
863extern ram_addr_t last_ram_offset;
bellardedf75d52004-01-04 17:43:30 +0000864
Marcelo Tosattic9027602010-03-01 20:25:08 -0300865extern const char *mem_path;
866extern int mem_prealloc;
867
bellardedf75d52004-01-04 17:43:30 +0000868/* physical memory access */
pbrook0f459d12008-06-09 00:20:13 +0000869
870/* MMIO pages are identified by a combination of an IO device index and
871 3 flags. The ROMD code stores the page ram offset in iotlb entry,
872 so only a limited number of ids are avaiable. */
873
bellard98699962005-11-26 10:29:22 +0000874#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
bellardedf75d52004-01-04 17:43:30 +0000875
pbrook0f459d12008-06-09 00:20:13 +0000876/* Flags stored in the low bits of the TLB virtual address. These are
877 defined so that fast path ram access is all zeros. */
878/* Zero if TLB entry is valid. */
879#define TLB_INVALID_MASK (1 << 3)
880/* Set if TLB entry references a clean RAM page. The iotlb entry will
881 contain the page physical address. */
882#define TLB_NOTDIRTY (1 << 4)
883/* Set if TLB entry is an IO callback. */
884#define TLB_MMIO (1 << 5)
885
aliguori74576192008-10-06 14:02:03 +0000886#define VGA_DIRTY_FLAG 0x01
887#define CODE_DIRTY_FLAG 0x02
aliguori74576192008-10-06 14:02:03 +0000888#define MIGRATION_DIRTY_FLAG 0x08
bellard0a962c02005-02-10 22:00:27 +0000889
bellard1ccde1c2004-02-06 19:46:14 +0000890/* read dirty bit (return 0 or 1) */
Anthony Liguoric227f092009-10-01 16:12:16 -0500891static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
bellard1ccde1c2004-02-06 19:46:14 +0000892{
bellard0a962c02005-02-10 22:00:27 +0000893 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
894}
895
Anthony Liguoric227f092009-10-01 16:12:16 -0500896static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
bellard0a962c02005-02-10 22:00:27 +0000897 int dirty_flags)
898{
899 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
bellard1ccde1c2004-02-06 19:46:14 +0000900}
901
Anthony Liguoric227f092009-10-01 16:12:16 -0500902static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
bellard1ccde1c2004-02-06 19:46:14 +0000903{
bellard0a962c02005-02-10 22:00:27 +0000904 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
bellard1ccde1c2004-02-06 19:46:14 +0000905}
906
Anthony Liguoric227f092009-10-01 16:12:16 -0500907void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
bellard0a962c02005-02-10 22:00:27 +0000908 int dirty_flags);
bellard04c504c2005-08-21 09:24:50 +0000909void cpu_tlb_update_dirty(CPUState *env);
bellard1ccde1c2004-02-06 19:46:14 +0000910
aliguori74576192008-10-06 14:02:03 +0000911int cpu_physical_memory_set_dirty_tracking(int enable);
912
913int cpu_physical_memory_get_dirty_tracking(void);
914
Anthony Liguoric227f092009-10-01 16:12:16 -0500915int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
916 target_phys_addr_t end_addr);
aliguori2bec46d2008-11-24 20:21:41 +0000917
bellarde3db7222005-01-26 22:00:47 +0000918void dump_exec_info(FILE *f,
919 int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
920
aliguorif65ed4c2008-12-09 20:09:57 +0000921/* Coalesced MMIO regions are areas where write operations can be reordered.
922 * This usually implies that write operations are side-effect free. This allows
923 * batching which can make a major impact on performance when using
924 * virtualization.
925 */
Anthony Liguoric227f092009-10-01 16:12:16 -0500926void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
aliguorif65ed4c2008-12-09 20:09:57 +0000927
Anthony Liguoric227f092009-10-01 16:12:16 -0500928void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
aliguorif65ed4c2008-12-09 20:09:57 +0000929
Sheng Yang62a27442010-01-26 19:21:16 +0800930void qemu_flush_coalesced_mmio_buffer(void);
931
Paul Brookb3755a92010-03-12 16:54:58 +0000932#endif /* !CONFIG_USER_ONLY */
933
934int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
935 uint8_t *buf, int len, int is_write);
936
bellardeffedbc2006-07-13 23:00:40 +0000937/*******************************************/
938/* host CPU ticks (if available) */
939
malce58ffeb2009-01-14 18:39:49 +0000940#if defined(_ARCH_PPC)
bellardeffedbc2006-07-13 23:00:40 +0000941
bellardeffedbc2006-07-13 23:00:40 +0000942static inline int64_t cpu_get_real_ticks(void)
943{
malc5e10fc92009-01-25 10:56:48 +0000944 int64_t retval;
945#ifdef _ARCH_PPC64
946 /* This reads timebase in one 64bit go and includes Cell workaround from:
947 http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027052.html
948 */
949 __asm__ __volatile__ (
950 "mftb %0\n\t"
951 "cmpwi %0,0\n\t"
952 "beq- $-8"
953 : "=r" (retval));
954#else
955 /* http://ozlabs.org/pipermail/linuxppc-dev/1999-October/003889.html */
956 unsigned long junk;
957 __asm__ __volatile__ (
958 "mftbu %1\n\t"
959 "mftb %L0\n\t"
960 "mftbu %0\n\t"
961 "cmpw %0,%1\n\t"
962 "bne $-16"
963 : "=r" (retval), "=r" (junk));
964#endif
965 return retval;
bellardeffedbc2006-07-13 23:00:40 +0000966}
967
968#elif defined(__i386__)
969
970static inline int64_t cpu_get_real_ticks(void)
bellard5f1ce942006-02-08 22:40:15 +0000971{
972 int64_t val;
973 asm volatile ("rdtsc" : "=A" (val));
974 return val;
975}
976
bellardeffedbc2006-07-13 23:00:40 +0000977#elif defined(__x86_64__)
978
979static inline int64_t cpu_get_real_ticks(void)
980{
981 uint32_t low,high;
982 int64_t val;
983 asm volatile("rdtsc" : "=a" (low), "=d" (high));
984 val = high;
985 val <<= 32;
986 val |= low;
987 return val;
988}
989
aurel32f54b3f92008-04-12 20:14:54 +0000990#elif defined(__hppa__)
991
992static inline int64_t cpu_get_real_ticks(void)
993{
994 int val;
995 asm volatile ("mfctl %%cr16, %0" : "=r"(val));
996 return val;
997}
998
bellardeffedbc2006-07-13 23:00:40 +0000999#elif defined(__ia64)
1000
1001static inline int64_t cpu_get_real_ticks(void)
1002{
1003 int64_t val;
1004 asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
1005 return val;
1006}
1007
1008#elif defined(__s390__)
1009
1010static inline int64_t cpu_get_real_ticks(void)
1011{
1012 int64_t val;
1013 asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
1014 return val;
1015}
1016
blueswir131422552007-04-16 18:27:06 +00001017#elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
bellardeffedbc2006-07-13 23:00:40 +00001018
1019static inline int64_t cpu_get_real_ticks (void)
1020{
1021#if defined(_LP64)
1022 uint64_t rval;
1023 asm volatile("rd %%tick,%0" : "=r"(rval));
1024 return rval;
1025#else
1026 union {
1027 uint64_t i64;
1028 struct {
1029 uint32_t high;
1030 uint32_t low;
1031 } i32;
1032 } rval;
1033 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1034 : "=r"(rval.i32.high), "=r"(rval.i32.low));
1035 return rval.i64;
1036#endif
1037}
thsc4b89d12007-05-05 19:23:11 +00001038
Aurelien Jarno9706c062009-12-20 21:18:57 +01001039#elif defined(__mips__) && \
1040 ((defined(__mips_isa_rev) && __mips_isa_rev >= 2) || defined(__linux__))
Arnaud Patardfea0ac22009-04-11 16:02:46 +02001041/*
1042 * binutils wants to use rdhwr only on mips32r2
1043 * but as linux kernel emulate it, it's fine
1044 * to use it.
1045 *
1046 */
1047#define MIPS_RDHWR(rd, value) { \
1048 __asm__ __volatile__ ( \
1049 ".set push\n\t" \
1050 ".set mips32r2\n\t" \
1051 "rdhwr %0, "rd"\n\t" \
1052 ".set pop" \
1053 : "=r" (value)); \
1054}
thsc4b89d12007-05-05 19:23:11 +00001055
1056static inline int64_t cpu_get_real_ticks(void)
1057{
Arnaud Patardfea0ac22009-04-11 16:02:46 +02001058/* On kernels >= 2.6.25 rdhwr <reg>, $2 and $3 are emulated */
thsc4b89d12007-05-05 19:23:11 +00001059 uint32_t count;
1060 static uint32_t cyc_per_count = 0;
1061
1062 if (!cyc_per_count)
Arnaud Patardfea0ac22009-04-11 16:02:46 +02001063 MIPS_RDHWR("$3", cyc_per_count);
thsc4b89d12007-05-05 19:23:11 +00001064
Arnaud Patardfea0ac22009-04-11 16:02:46 +02001065 MIPS_RDHWR("$2", count);
thsc4b89d12007-05-05 19:23:11 +00001066 return (int64_t)(count * cyc_per_count);
thsc4b89d12007-05-05 19:23:11 +00001067}
1068
pbrook46152182006-07-30 19:16:29 +00001069#else
1070/* The host CPU doesn't have an easily accessible cycle counter.
ths85028e42007-05-08 22:51:41 +00001071 Just return a monotonically increasing value. This will be
1072 totally wrong, but hopefully better than nothing. */
pbrook46152182006-07-30 19:16:29 +00001073static inline int64_t cpu_get_real_ticks (void)
1074{
1075 static int64_t ticks = 0;
1076 return ticks++;
1077}
bellardeffedbc2006-07-13 23:00:40 +00001078#endif
1079
1080/* profiling */
1081#ifdef CONFIG_PROFILER
1082static inline int64_t profile_getclock(void)
1083{
1084 return cpu_get_real_ticks();
1085}
1086
bellard5f1ce942006-02-08 22:40:15 +00001087extern int64_t qemu_time, qemu_time_start;
1088extern int64_t tlb_flush_time;
bellard5f1ce942006-02-08 22:40:15 +00001089extern int64_t dev_time;
bellard5f1ce942006-02-08 22:40:15 +00001090#endif
1091
Huang Ying79c4f6b2009-06-23 10:05:14 +08001092void cpu_inject_x86_mce(CPUState *cenv, int bank, uint64_t status,
1093 uint64_t mcg_status, uint64_t addr, uint64_t misc);
1094
bellard5a9fdfe2003-06-15 20:02:25 +00001095#endif /* CPU_ALL_H */