bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 1 | /* |
| 2 | * defines common to all virtual CPUs |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 18 | */ |
| 19 | #ifndef CPU_ALL_H |
| 20 | #define CPU_ALL_H |
| 21 | |
blueswir1 | 7d99a00 | 2009-01-14 19:00:36 +0000 | [diff] [blame] | 22 | #include "qemu-common.h" |
Paul Brook | 1ad2134 | 2009-05-19 16:17:58 +0100 | [diff] [blame] | 23 | #include "cpu-common.h" |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 24 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 25 | /* some important defines: |
| 26 | * |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 27 | * WORDS_ALIGNED : if defined, the host cpu can only make word aligned |
| 28 | * memory accesses. |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 29 | * |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 30 | * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 31 | * otherwise little endian. |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 32 | * |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 33 | * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet)) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 34 | * |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 35 | * TARGET_WORDS_BIGENDIAN : same for target cpu |
| 36 | */ |
| 37 | |
aurel32 | 939ef59 | 2008-05-09 18:45:47 +0000 | [diff] [blame] | 38 | #include "softfloat.h" |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 39 | |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 40 | #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 41 | #define BSWAP_NEEDED |
| 42 | #endif |
| 43 | |
| 44 | #ifdef BSWAP_NEEDED |
| 45 | |
| 46 | static inline uint16_t tswap16(uint16_t s) |
| 47 | { |
| 48 | return bswap16(s); |
| 49 | } |
| 50 | |
| 51 | static inline uint32_t tswap32(uint32_t s) |
| 52 | { |
| 53 | return bswap32(s); |
| 54 | } |
| 55 | |
| 56 | static inline uint64_t tswap64(uint64_t s) |
| 57 | { |
| 58 | return bswap64(s); |
| 59 | } |
| 60 | |
| 61 | static inline void tswap16s(uint16_t *s) |
| 62 | { |
| 63 | *s = bswap16(*s); |
| 64 | } |
| 65 | |
| 66 | static inline void tswap32s(uint32_t *s) |
| 67 | { |
| 68 | *s = bswap32(*s); |
| 69 | } |
| 70 | |
| 71 | static inline void tswap64s(uint64_t *s) |
| 72 | { |
| 73 | *s = bswap64(*s); |
| 74 | } |
| 75 | |
| 76 | #else |
| 77 | |
| 78 | static inline uint16_t tswap16(uint16_t s) |
| 79 | { |
| 80 | return s; |
| 81 | } |
| 82 | |
| 83 | static inline uint32_t tswap32(uint32_t s) |
| 84 | { |
| 85 | return s; |
| 86 | } |
| 87 | |
| 88 | static inline uint64_t tswap64(uint64_t s) |
| 89 | { |
| 90 | return s; |
| 91 | } |
| 92 | |
| 93 | static inline void tswap16s(uint16_t *s) |
| 94 | { |
| 95 | } |
| 96 | |
| 97 | static inline void tswap32s(uint32_t *s) |
| 98 | { |
| 99 | } |
| 100 | |
| 101 | static inline void tswap64s(uint64_t *s) |
| 102 | { |
| 103 | } |
| 104 | |
| 105 | #endif |
| 106 | |
| 107 | #if TARGET_LONG_SIZE == 4 |
| 108 | #define tswapl(s) tswap32(s) |
| 109 | #define tswapls(s) tswap32s((uint32_t *)(s)) |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 110 | #define bswaptls(s) bswap32s(s) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 111 | #else |
| 112 | #define tswapl(s) tswap64(s) |
| 113 | #define tswapls(s) tswap64s((uint64_t *)(s)) |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 114 | #define bswaptls(s) bswap64s(s) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 115 | #endif |
| 116 | |
aurel32 | 0ca9d38 | 2008-03-13 19:19:16 +0000 | [diff] [blame] | 117 | typedef union { |
| 118 | float32 f; |
| 119 | uint32_t l; |
| 120 | } CPU_FloatU; |
| 121 | |
bellard | 832ed0f | 2005-02-07 12:35:16 +0000 | [diff] [blame] | 122 | /* NOTE: arm FPA is horrible as double 32 bit words are stored in big |
| 123 | endian ! */ |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 124 | typedef union { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 125 | float64 d; |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 126 | #if defined(HOST_WORDS_BIGENDIAN) \ |
bellard | 9d60cac | 2005-04-07 19:55:52 +0000 | [diff] [blame] | 127 | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 128 | struct { |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 129 | uint32_t upper; |
bellard | 832ed0f | 2005-02-07 12:35:16 +0000 | [diff] [blame] | 130 | uint32_t lower; |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 131 | } l; |
| 132 | #else |
| 133 | struct { |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 134 | uint32_t lower; |
bellard | 832ed0f | 2005-02-07 12:35:16 +0000 | [diff] [blame] | 135 | uint32_t upper; |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 136 | } l; |
| 137 | #endif |
| 138 | uint64_t ll; |
| 139 | } CPU_DoubleU; |
| 140 | |
blueswir1 | 1f58732 | 2007-11-25 18:40:20 +0000 | [diff] [blame] | 141 | #ifdef TARGET_SPARC |
| 142 | typedef union { |
| 143 | float128 q; |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 144 | #if defined(HOST_WORDS_BIGENDIAN) \ |
blueswir1 | 1f58732 | 2007-11-25 18:40:20 +0000 | [diff] [blame] | 145 | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) |
| 146 | struct { |
| 147 | uint32_t upmost; |
| 148 | uint32_t upper; |
| 149 | uint32_t lower; |
| 150 | uint32_t lowest; |
| 151 | } l; |
| 152 | struct { |
| 153 | uint64_t upper; |
| 154 | uint64_t lower; |
| 155 | } ll; |
| 156 | #else |
| 157 | struct { |
| 158 | uint32_t lowest; |
| 159 | uint32_t lower; |
| 160 | uint32_t upper; |
| 161 | uint32_t upmost; |
| 162 | } l; |
| 163 | struct { |
| 164 | uint64_t lower; |
| 165 | uint64_t upper; |
| 166 | } ll; |
| 167 | #endif |
| 168 | } CPU_QuadU; |
| 169 | #endif |
| 170 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 171 | /* CPU memory access without any memory or io remapping */ |
| 172 | |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 173 | /* |
| 174 | * the generic syntax for the memory accesses is: |
| 175 | * |
| 176 | * load: ld{type}{sign}{size}{endian}_{access_type}(ptr) |
| 177 | * |
| 178 | * store: st{type}{size}{endian}_{access_type}(ptr, val) |
| 179 | * |
| 180 | * type is: |
| 181 | * (empty): integer access |
| 182 | * f : float access |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 183 | * |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 184 | * sign is: |
| 185 | * (empty): for floats or 32 bit size |
| 186 | * u : unsigned |
| 187 | * s : signed |
| 188 | * |
| 189 | * size is: |
| 190 | * b: 8 bits |
| 191 | * w: 16 bits |
| 192 | * l: 32 bits |
| 193 | * q: 64 bits |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 194 | * |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 195 | * endian is: |
| 196 | * (empty): target cpu endianness or 8 bit access |
| 197 | * r : reversed target cpu endianness (not implemented yet) |
| 198 | * be : big endian (not implemented yet) |
| 199 | * le : little endian (not implemented yet) |
| 200 | * |
| 201 | * access_type is: |
| 202 | * raw : host memory access |
| 203 | * user : user mode access using soft MMU |
| 204 | * kernel : kernel mode access using soft MMU |
| 205 | */ |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 206 | static inline int ldub_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 207 | { |
| 208 | return *(uint8_t *)ptr; |
| 209 | } |
| 210 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 211 | static inline int ldsb_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 212 | { |
| 213 | return *(int8_t *)ptr; |
| 214 | } |
| 215 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 216 | static inline void stb_p(void *ptr, int v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 217 | { |
| 218 | *(uint8_t *)ptr = v; |
| 219 | } |
| 220 | |
| 221 | /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the |
| 222 | kernel handles unaligned load/stores may give better results, but |
| 223 | it is a system wide setting : bad */ |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 224 | #if defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 225 | |
| 226 | /* conservative code for little endian unaligned accesses */ |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 227 | static inline int lduw_le_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 228 | { |
malc | e58ffeb | 2009-01-14 18:39:49 +0000 | [diff] [blame] | 229 | #ifdef _ARCH_PPC |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 230 | int val; |
| 231 | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
| 232 | return val; |
| 233 | #else |
malc | e01fe6d | 2008-12-11 00:14:30 +0000 | [diff] [blame] | 234 | const uint8_t *p = ptr; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 235 | return p[0] | (p[1] << 8); |
| 236 | #endif |
| 237 | } |
| 238 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 239 | static inline int ldsw_le_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 240 | { |
malc | e58ffeb | 2009-01-14 18:39:49 +0000 | [diff] [blame] | 241 | #ifdef _ARCH_PPC |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 242 | int val; |
| 243 | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
| 244 | return (int16_t)val; |
| 245 | #else |
malc | e01fe6d | 2008-12-11 00:14:30 +0000 | [diff] [blame] | 246 | const uint8_t *p = ptr; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 247 | return (int16_t)(p[0] | (p[1] << 8)); |
| 248 | #endif |
| 249 | } |
| 250 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 251 | static inline int ldl_le_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 252 | { |
malc | e58ffeb | 2009-01-14 18:39:49 +0000 | [diff] [blame] | 253 | #ifdef _ARCH_PPC |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 254 | int val; |
| 255 | __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
| 256 | return val; |
| 257 | #else |
malc | e01fe6d | 2008-12-11 00:14:30 +0000 | [diff] [blame] | 258 | const uint8_t *p = ptr; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 259 | return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); |
| 260 | #endif |
| 261 | } |
| 262 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 263 | static inline uint64_t ldq_le_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 264 | { |
malc | e01fe6d | 2008-12-11 00:14:30 +0000 | [diff] [blame] | 265 | const uint8_t *p = ptr; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 266 | uint32_t v1, v2; |
bellard | f0aca82 | 2005-11-21 23:22:06 +0000 | [diff] [blame] | 267 | v1 = ldl_le_p(p); |
| 268 | v2 = ldl_le_p(p + 4); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 269 | return v1 | ((uint64_t)v2 << 32); |
| 270 | } |
| 271 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 272 | static inline void stw_le_p(void *ptr, int v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 273 | { |
malc | e58ffeb | 2009-01-14 18:39:49 +0000 | [diff] [blame] | 274 | #ifdef _ARCH_PPC |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 275 | __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); |
| 276 | #else |
| 277 | uint8_t *p = ptr; |
| 278 | p[0] = v; |
| 279 | p[1] = v >> 8; |
| 280 | #endif |
| 281 | } |
| 282 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 283 | static inline void stl_le_p(void *ptr, int v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 284 | { |
malc | e58ffeb | 2009-01-14 18:39:49 +0000 | [diff] [blame] | 285 | #ifdef _ARCH_PPC |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 286 | __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); |
| 287 | #else |
| 288 | uint8_t *p = ptr; |
| 289 | p[0] = v; |
| 290 | p[1] = v >> 8; |
| 291 | p[2] = v >> 16; |
| 292 | p[3] = v >> 24; |
| 293 | #endif |
| 294 | } |
| 295 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 296 | static inline void stq_le_p(void *ptr, uint64_t v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 297 | { |
| 298 | uint8_t *p = ptr; |
bellard | f0aca82 | 2005-11-21 23:22:06 +0000 | [diff] [blame] | 299 | stl_le_p(p, (uint32_t)v); |
| 300 | stl_le_p(p + 4, v >> 32); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 301 | } |
| 302 | |
| 303 | /* float access */ |
| 304 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 305 | static inline float32 ldfl_le_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 306 | { |
| 307 | union { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 308 | float32 f; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 309 | uint32_t i; |
| 310 | } u; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 311 | u.i = ldl_le_p(ptr); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 312 | return u.f; |
| 313 | } |
| 314 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 315 | static inline void stfl_le_p(void *ptr, float32 v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 316 | { |
| 317 | union { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 318 | float32 f; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 319 | uint32_t i; |
| 320 | } u; |
| 321 | u.f = v; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 322 | stl_le_p(ptr, u.i); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 323 | } |
| 324 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 325 | static inline float64 ldfq_le_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 326 | { |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 327 | CPU_DoubleU u; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 328 | u.l.lower = ldl_le_p(ptr); |
| 329 | u.l.upper = ldl_le_p(ptr + 4); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 330 | return u.d; |
| 331 | } |
| 332 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 333 | static inline void stfq_le_p(void *ptr, float64 v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 334 | { |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 335 | CPU_DoubleU u; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 336 | u.d = v; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 337 | stl_le_p(ptr, u.l.lower); |
| 338 | stl_le_p(ptr + 4, u.l.upper); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 339 | } |
| 340 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 341 | #else |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 342 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 343 | static inline int lduw_le_p(const void *ptr) |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 344 | { |
| 345 | return *(uint16_t *)ptr; |
| 346 | } |
| 347 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 348 | static inline int ldsw_le_p(const void *ptr) |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 349 | { |
| 350 | return *(int16_t *)ptr; |
| 351 | } |
| 352 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 353 | static inline int ldl_le_p(const void *ptr) |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 354 | { |
| 355 | return *(uint32_t *)ptr; |
| 356 | } |
| 357 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 358 | static inline uint64_t ldq_le_p(const void *ptr) |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 359 | { |
| 360 | return *(uint64_t *)ptr; |
| 361 | } |
| 362 | |
| 363 | static inline void stw_le_p(void *ptr, int v) |
| 364 | { |
| 365 | *(uint16_t *)ptr = v; |
| 366 | } |
| 367 | |
| 368 | static inline void stl_le_p(void *ptr, int v) |
| 369 | { |
| 370 | *(uint32_t *)ptr = v; |
| 371 | } |
| 372 | |
| 373 | static inline void stq_le_p(void *ptr, uint64_t v) |
| 374 | { |
| 375 | *(uint64_t *)ptr = v; |
| 376 | } |
| 377 | |
| 378 | /* float access */ |
| 379 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 380 | static inline float32 ldfl_le_p(const void *ptr) |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 381 | { |
| 382 | return *(float32 *)ptr; |
| 383 | } |
| 384 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 385 | static inline float64 ldfq_le_p(const void *ptr) |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 386 | { |
| 387 | return *(float64 *)ptr; |
| 388 | } |
| 389 | |
| 390 | static inline void stfl_le_p(void *ptr, float32 v) |
| 391 | { |
| 392 | *(float32 *)ptr = v; |
| 393 | } |
| 394 | |
| 395 | static inline void stfq_le_p(void *ptr, float64 v) |
| 396 | { |
| 397 | *(float64 *)ptr = v; |
| 398 | } |
| 399 | #endif |
| 400 | |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 401 | #if !defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 402 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 403 | static inline int lduw_be_p(const void *ptr) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 404 | { |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 405 | #if defined(__i386__) |
| 406 | int val; |
| 407 | asm volatile ("movzwl %1, %0\n" |
| 408 | "xchgb %b0, %h0\n" |
| 409 | : "=q" (val) |
| 410 | : "m" (*(uint16_t *)ptr)); |
| 411 | return val; |
| 412 | #else |
malc | e01fe6d | 2008-12-11 00:14:30 +0000 | [diff] [blame] | 413 | const uint8_t *b = ptr; |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 414 | return ((b[0] << 8) | b[1]); |
| 415 | #endif |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 416 | } |
| 417 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 418 | static inline int ldsw_be_p(const void *ptr) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 419 | { |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 420 | #if defined(__i386__) |
| 421 | int val; |
| 422 | asm volatile ("movzwl %1, %0\n" |
| 423 | "xchgb %b0, %h0\n" |
| 424 | : "=q" (val) |
| 425 | : "m" (*(uint16_t *)ptr)); |
| 426 | return (int16_t)val; |
| 427 | #else |
malc | e01fe6d | 2008-12-11 00:14:30 +0000 | [diff] [blame] | 428 | const uint8_t *b = ptr; |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 429 | return (int16_t)((b[0] << 8) | b[1]); |
| 430 | #endif |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 431 | } |
| 432 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 433 | static inline int ldl_be_p(const void *ptr) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 434 | { |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 435 | #if defined(__i386__) || defined(__x86_64__) |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 436 | int val; |
| 437 | asm volatile ("movl %1, %0\n" |
| 438 | "bswap %0\n" |
| 439 | : "=r" (val) |
| 440 | : "m" (*(uint32_t *)ptr)); |
| 441 | return val; |
| 442 | #else |
malc | e01fe6d | 2008-12-11 00:14:30 +0000 | [diff] [blame] | 443 | const uint8_t *b = ptr; |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 444 | return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; |
| 445 | #endif |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 446 | } |
| 447 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 448 | static inline uint64_t ldq_be_p(const void *ptr) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 449 | { |
| 450 | uint32_t a,b; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 451 | a = ldl_be_p(ptr); |
blueswir1 | 4d7a088 | 2008-05-10 10:14:22 +0000 | [diff] [blame] | 452 | b = ldl_be_p((uint8_t *)ptr + 4); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 453 | return (((uint64_t)a<<32)|b); |
| 454 | } |
| 455 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 456 | static inline void stw_be_p(void *ptr, int v) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 457 | { |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 458 | #if defined(__i386__) |
| 459 | asm volatile ("xchgb %b0, %h0\n" |
| 460 | "movw %w0, %1\n" |
| 461 | : "=q" (v) |
| 462 | : "m" (*(uint16_t *)ptr), "0" (v)); |
| 463 | #else |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 464 | uint8_t *d = (uint8_t *) ptr; |
| 465 | d[0] = v >> 8; |
| 466 | d[1] = v; |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 467 | #endif |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 468 | } |
| 469 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 470 | static inline void stl_be_p(void *ptr, int v) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 471 | { |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 472 | #if defined(__i386__) || defined(__x86_64__) |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 473 | asm volatile ("bswap %0\n" |
| 474 | "movl %0, %1\n" |
| 475 | : "=r" (v) |
| 476 | : "m" (*(uint32_t *)ptr), "0" (v)); |
| 477 | #else |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 478 | uint8_t *d = (uint8_t *) ptr; |
| 479 | d[0] = v >> 24; |
| 480 | d[1] = v >> 16; |
| 481 | d[2] = v >> 8; |
| 482 | d[3] = v; |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 483 | #endif |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 484 | } |
| 485 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 486 | static inline void stq_be_p(void *ptr, uint64_t v) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 487 | { |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 488 | stl_be_p(ptr, v >> 32); |
blueswir1 | 4d7a088 | 2008-05-10 10:14:22 +0000 | [diff] [blame] | 489 | stl_be_p((uint8_t *)ptr + 4, v); |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 490 | } |
| 491 | |
| 492 | /* float access */ |
| 493 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 494 | static inline float32 ldfl_be_p(const void *ptr) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 495 | { |
| 496 | union { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 497 | float32 f; |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 498 | uint32_t i; |
| 499 | } u; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 500 | u.i = ldl_be_p(ptr); |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 501 | return u.f; |
| 502 | } |
| 503 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 504 | static inline void stfl_be_p(void *ptr, float32 v) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 505 | { |
| 506 | union { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 507 | float32 f; |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 508 | uint32_t i; |
| 509 | } u; |
| 510 | u.f = v; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 511 | stl_be_p(ptr, u.i); |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 512 | } |
| 513 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 514 | static inline float64 ldfq_be_p(const void *ptr) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 515 | { |
| 516 | CPU_DoubleU u; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 517 | u.l.upper = ldl_be_p(ptr); |
blueswir1 | 4d7a088 | 2008-05-10 10:14:22 +0000 | [diff] [blame] | 518 | u.l.lower = ldl_be_p((uint8_t *)ptr + 4); |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 519 | return u.d; |
| 520 | } |
| 521 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 522 | static inline void stfq_be_p(void *ptr, float64 v) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 523 | { |
| 524 | CPU_DoubleU u; |
| 525 | u.d = v; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 526 | stl_be_p(ptr, u.l.upper); |
blueswir1 | 4d7a088 | 2008-05-10 10:14:22 +0000 | [diff] [blame] | 527 | stl_be_p((uint8_t *)ptr + 4, u.l.lower); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 528 | } |
| 529 | |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 530 | #else |
| 531 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 532 | static inline int lduw_be_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 533 | { |
| 534 | return *(uint16_t *)ptr; |
| 535 | } |
| 536 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 537 | static inline int ldsw_be_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 538 | { |
| 539 | return *(int16_t *)ptr; |
| 540 | } |
| 541 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 542 | static inline int ldl_be_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 543 | { |
| 544 | return *(uint32_t *)ptr; |
| 545 | } |
| 546 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 547 | static inline uint64_t ldq_be_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 548 | { |
| 549 | return *(uint64_t *)ptr; |
| 550 | } |
| 551 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 552 | static inline void stw_be_p(void *ptr, int v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 553 | { |
| 554 | *(uint16_t *)ptr = v; |
| 555 | } |
| 556 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 557 | static inline void stl_be_p(void *ptr, int v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 558 | { |
| 559 | *(uint32_t *)ptr = v; |
| 560 | } |
| 561 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 562 | static inline void stq_be_p(void *ptr, uint64_t v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 563 | { |
| 564 | *(uint64_t *)ptr = v; |
| 565 | } |
| 566 | |
| 567 | /* float access */ |
| 568 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 569 | static inline float32 ldfl_be_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 570 | { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 571 | return *(float32 *)ptr; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 572 | } |
| 573 | |
balrog | 8bba3ea | 2008-12-07 23:44:44 +0000 | [diff] [blame] | 574 | static inline float64 ldfq_be_p(const void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 575 | { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 576 | return *(float64 *)ptr; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 577 | } |
| 578 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 579 | static inline void stfl_be_p(void *ptr, float32 v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 580 | { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 581 | *(float32 *)ptr = v; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 582 | } |
| 583 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 584 | static inline void stfq_be_p(void *ptr, float64 v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 585 | { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 586 | *(float64 *)ptr = v; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 587 | } |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 588 | |
| 589 | #endif |
| 590 | |
| 591 | /* target CPU memory access functions */ |
| 592 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 593 | #define lduw_p(p) lduw_be_p(p) |
| 594 | #define ldsw_p(p) ldsw_be_p(p) |
| 595 | #define ldl_p(p) ldl_be_p(p) |
| 596 | #define ldq_p(p) ldq_be_p(p) |
| 597 | #define ldfl_p(p) ldfl_be_p(p) |
| 598 | #define ldfq_p(p) ldfq_be_p(p) |
| 599 | #define stw_p(p, v) stw_be_p(p, v) |
| 600 | #define stl_p(p, v) stl_be_p(p, v) |
| 601 | #define stq_p(p, v) stq_be_p(p, v) |
| 602 | #define stfl_p(p, v) stfl_be_p(p, v) |
| 603 | #define stfq_p(p, v) stfq_be_p(p, v) |
| 604 | #else |
| 605 | #define lduw_p(p) lduw_le_p(p) |
| 606 | #define ldsw_p(p) ldsw_le_p(p) |
| 607 | #define ldl_p(p) ldl_le_p(p) |
| 608 | #define ldq_p(p) ldq_le_p(p) |
| 609 | #define ldfl_p(p) ldfl_le_p(p) |
| 610 | #define ldfq_p(p) ldfq_le_p(p) |
| 611 | #define stw_p(p, v) stw_le_p(p, v) |
| 612 | #define stl_p(p, v) stl_le_p(p, v) |
| 613 | #define stq_p(p, v) stq_le_p(p, v) |
| 614 | #define stfl_p(p, v) stfl_le_p(p, v) |
| 615 | #define stfq_p(p, v) stfq_le_p(p, v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 616 | #endif |
| 617 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 618 | /* MMU memory access macros */ |
| 619 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 620 | #if defined(CONFIG_USER_ONLY) |
aurel32 | 0e62fd7 | 2008-12-08 18:12:11 +0000 | [diff] [blame] | 621 | #include <assert.h> |
| 622 | #include "qemu-types.h" |
| 623 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 624 | /* On some host systems the guest address space is reserved on the host. |
| 625 | * This allows the guest address space to be offset to a convenient location. |
| 626 | */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 627 | #if defined(CONFIG_USE_GUEST_BASE) |
| 628 | extern unsigned long guest_base; |
| 629 | extern int have_guest_base; |
| 630 | #define GUEST_BASE guest_base |
| 631 | #else |
| 632 | #define GUEST_BASE 0ul |
| 633 | #endif |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 634 | |
| 635 | /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ |
| 636 | #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE)) |
Richard Henderson | b9f8312 | 2010-03-10 14:36:58 -0800 | [diff] [blame] | 637 | |
| 638 | #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS |
| 639 | #define h2g_valid(x) 1 |
| 640 | #else |
| 641 | #define h2g_valid(x) ({ \ |
| 642 | unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \ |
| 643 | __guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS); \ |
| 644 | }) |
| 645 | #endif |
| 646 | |
aurel32 | 0e62fd7 | 2008-12-08 18:12:11 +0000 | [diff] [blame] | 647 | #define h2g(x) ({ \ |
| 648 | unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \ |
| 649 | /* Check if given address fits target address space */ \ |
Richard Henderson | b9f8312 | 2010-03-10 14:36:58 -0800 | [diff] [blame] | 650 | assert(h2g_valid(x)); \ |
aurel32 | 0e62fd7 | 2008-12-08 18:12:11 +0000 | [diff] [blame] | 651 | (abi_ulong)__ret; \ |
| 652 | }) |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 653 | |
| 654 | #define saddr(x) g2h(x) |
| 655 | #define laddr(x) g2h(x) |
| 656 | |
| 657 | #else /* !CONFIG_USER_ONLY */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 658 | /* NOTE: we use double casts if pointers and target_ulong have |
| 659 | different sizes */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 660 | #define saddr(x) (uint8_t *)(long)(x) |
| 661 | #define laddr(x) (uint8_t *)(long)(x) |
| 662 | #endif |
| 663 | |
| 664 | #define ldub_raw(p) ldub_p(laddr((p))) |
| 665 | #define ldsb_raw(p) ldsb_p(laddr((p))) |
| 666 | #define lduw_raw(p) lduw_p(laddr((p))) |
| 667 | #define ldsw_raw(p) ldsw_p(laddr((p))) |
| 668 | #define ldl_raw(p) ldl_p(laddr((p))) |
| 669 | #define ldq_raw(p) ldq_p(laddr((p))) |
| 670 | #define ldfl_raw(p) ldfl_p(laddr((p))) |
| 671 | #define ldfq_raw(p) ldfq_p(laddr((p))) |
| 672 | #define stb_raw(p, v) stb_p(saddr((p)), v) |
| 673 | #define stw_raw(p, v) stw_p(saddr((p)), v) |
| 674 | #define stl_raw(p, v) stl_p(saddr((p)), v) |
| 675 | #define stq_raw(p, v) stq_p(saddr((p)), v) |
| 676 | #define stfl_raw(p, v) stfl_p(saddr((p)), v) |
| 677 | #define stfq_raw(p, v) stfq_p(saddr((p)), v) |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 678 | |
| 679 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 680 | #if defined(CONFIG_USER_ONLY) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 681 | |
| 682 | /* if user mode, no other memory access functions */ |
| 683 | #define ldub(p) ldub_raw(p) |
| 684 | #define ldsb(p) ldsb_raw(p) |
| 685 | #define lduw(p) lduw_raw(p) |
| 686 | #define ldsw(p) ldsw_raw(p) |
| 687 | #define ldl(p) ldl_raw(p) |
| 688 | #define ldq(p) ldq_raw(p) |
| 689 | #define ldfl(p) ldfl_raw(p) |
| 690 | #define ldfq(p) ldfq_raw(p) |
| 691 | #define stb(p, v) stb_raw(p, v) |
| 692 | #define stw(p, v) stw_raw(p, v) |
| 693 | #define stl(p, v) stl_raw(p, v) |
| 694 | #define stq(p, v) stq_raw(p, v) |
| 695 | #define stfl(p, v) stfl_raw(p, v) |
| 696 | #define stfq(p, v) stfq_raw(p, v) |
| 697 | |
| 698 | #define ldub_code(p) ldub_raw(p) |
| 699 | #define ldsb_code(p) ldsb_raw(p) |
| 700 | #define lduw_code(p) lduw_raw(p) |
| 701 | #define ldsw_code(p) ldsw_raw(p) |
| 702 | #define ldl_code(p) ldl_raw(p) |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 703 | #define ldq_code(p) ldq_raw(p) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 704 | |
| 705 | #define ldub_kernel(p) ldub_raw(p) |
| 706 | #define ldsb_kernel(p) ldsb_raw(p) |
| 707 | #define lduw_kernel(p) lduw_raw(p) |
| 708 | #define ldsw_kernel(p) ldsw_raw(p) |
| 709 | #define ldl_kernel(p) ldl_raw(p) |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 710 | #define ldq_kernel(p) ldq_raw(p) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 711 | #define ldfl_kernel(p) ldfl_raw(p) |
| 712 | #define ldfq_kernel(p) ldfq_raw(p) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 713 | #define stb_kernel(p, v) stb_raw(p, v) |
| 714 | #define stw_kernel(p, v) stw_raw(p, v) |
| 715 | #define stl_kernel(p, v) stl_raw(p, v) |
| 716 | #define stq_kernel(p, v) stq_raw(p, v) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 717 | #define stfl_kernel(p, v) stfl_raw(p, v) |
| 718 | #define stfq_kernel(p, vt) stfq_raw(p, v) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 719 | |
| 720 | #endif /* defined(CONFIG_USER_ONLY) */ |
| 721 | |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 722 | /* page related stuff */ |
| 723 | |
aurel32 | 0387544 | 2008-04-22 20:45:18 +0000 | [diff] [blame] | 724 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 725 | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
| 726 | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) |
| 727 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 728 | /* ??? These should be the larger of unsigned long and target_ulong. */ |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 729 | extern unsigned long qemu_real_host_page_size; |
| 730 | extern unsigned long qemu_host_page_bits; |
| 731 | extern unsigned long qemu_host_page_size; |
| 732 | extern unsigned long qemu_host_page_mask; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 733 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 734 | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 735 | |
| 736 | /* same as PROT_xxx */ |
| 737 | #define PAGE_READ 0x0001 |
| 738 | #define PAGE_WRITE 0x0002 |
| 739 | #define PAGE_EXEC 0x0004 |
| 740 | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) |
| 741 | #define PAGE_VALID 0x0008 |
| 742 | /* original state of the write flag (used when tracking self-modifying |
| 743 | code */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 744 | #define PAGE_WRITE_ORG 0x0010 |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 745 | #define PAGE_RESERVED 0x0020 |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 746 | |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 747 | #if defined(CONFIG_USER_ONLY) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 748 | void page_dump(FILE *f); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 749 | |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 750 | typedef int (*walk_memory_regions_fn)(void *, abi_ulong, |
| 751 | abi_ulong, unsigned long); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 752 | int walk_memory_regions(void *, walk_memory_regions_fn); |
| 753 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 754 | int page_get_flags(target_ulong address); |
| 755 | void page_set_flags(target_ulong start, target_ulong end, int flags); |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 756 | int page_check_range(target_ulong start, target_ulong len, int flags); |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 757 | #endif |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 758 | |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 759 | void cpu_exec_init_all(unsigned long tb_size); |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 760 | CPUState *cpu_copy(CPUState *env); |
Glauber Costa | 950f147 | 2009-06-09 12:15:18 -0400 | [diff] [blame] | 761 | CPUState *qemu_get_cpu(int cpu); |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 762 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 763 | void cpu_dump_state(CPUState *env, FILE *f, |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 764 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
| 765 | int flags); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 766 | void cpu_dump_statistics (CPUState *env, FILE *f, |
| 767 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
| 768 | int flags); |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 769 | |
malc | a5e50b2 | 2009-02-01 22:19:27 +0000 | [diff] [blame] | 770 | void QEMU_NORETURN cpu_abort(CPUState *env, const char *fmt, ...) |
blueswir1 | 7d99a00 | 2009-01-14 19:00:36 +0000 | [diff] [blame] | 771 | __attribute__ ((__format__ (__printf__, 2, 3))); |
bellard | f0aca82 | 2005-11-21 23:22:06 +0000 | [diff] [blame] | 772 | extern CPUState *first_cpu; |
bellard | e2f2289 | 2003-06-25 16:09:48 +0000 | [diff] [blame] | 773 | extern CPUState *cpu_single_env; |
Paolo Bonzini | db1a497 | 2010-03-10 11:38:55 +0100 | [diff] [blame] | 774 | |
| 775 | int64_t qemu_icount_round(int64_t count); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 776 | extern int64_t qemu_icount; |
| 777 | extern int use_icount; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 778 | |
bellard | 9acbed0 | 2004-02-16 21:57:02 +0000 | [diff] [blame] | 779 | #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */ |
| 780 | #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */ |
bellard | ef792f9 | 2004-05-17 20:19:32 +0000 | [diff] [blame] | 781 | #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ |
bellard | 9869996 | 2005-11-26 10:29:22 +0000 | [diff] [blame] | 782 | #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */ |
bellard | ba3c64f | 2005-12-05 20:31:52 +0000 | [diff] [blame] | 783 | #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */ |
bellard | 3b21e03 | 2006-09-24 18:41:56 +0000 | [diff] [blame] | 784 | #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */ |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 785 | #define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */ |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 786 | #define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */ |
aurel32 | 474ea84 | 2008-04-13 16:08:15 +0000 | [diff] [blame] | 787 | #define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */ |
Gleb Natapov | b09ea7d | 2009-06-17 23:26:59 +0300 | [diff] [blame] | 788 | #define CPU_INTERRUPT_INIT 0x400 /* INIT pending. */ |
| 789 | #define CPU_INTERRUPT_SIPI 0x800 /* SIPI pending. */ |
Huang Ying | 79c4f6b | 2009-06-23 10:05:14 +0800 | [diff] [blame] | 790 | #define CPU_INTERRUPT_MCE 0x1000 /* (x86 only) MCE pending. */ |
bellard | 9869996 | 2005-11-26 10:29:22 +0000 | [diff] [blame] | 791 | |
bellard | 4690764 | 2003-07-07 12:17:46 +0000 | [diff] [blame] | 792 | void cpu_interrupt(CPUState *s, int mask); |
bellard | b54ad04 | 2004-05-20 13:42:52 +0000 | [diff] [blame] | 793 | void cpu_reset_interrupt(CPUState *env, int mask); |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 794 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 795 | void cpu_exit(CPUState *s); |
| 796 | |
aliguori | 6a4955a | 2009-04-24 18:03:20 +0000 | [diff] [blame] | 797 | int qemu_cpu_has_work(CPUState *env); |
| 798 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 799 | /* Breakpoint/watchpoint flags */ |
| 800 | #define BP_MEM_READ 0x01 |
| 801 | #define BP_MEM_WRITE 0x02 |
| 802 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 803 | #define BP_STOP_BEFORE_ACCESS 0x04 |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 804 | #define BP_WATCHPOINT_HIT 0x08 |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 805 | #define BP_GDB 0x10 |
aliguori | 2dc9f41 | 2008-11-18 20:56:59 +0000 | [diff] [blame] | 806 | #define BP_CPU 0x20 |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 807 | |
| 808 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, |
| 809 | CPUBreakpoint **breakpoint); |
| 810 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags); |
| 811 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint); |
| 812 | void cpu_breakpoint_remove_all(CPUState *env, int mask); |
| 813 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
| 814 | int flags, CPUWatchpoint **watchpoint); |
| 815 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, |
| 816 | target_ulong len, int flags); |
| 817 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint); |
| 818 | void cpu_watchpoint_remove_all(CPUState *env, int mask); |
edgar_igl | 60897d3 | 2008-05-09 08:25:14 +0000 | [diff] [blame] | 819 | |
| 820 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
| 821 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ |
| 822 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ |
| 823 | |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 824 | void cpu_single_step(CPUState *env, int enabled); |
bellard | d95dc32 | 2004-06-20 12:35:26 +0000 | [diff] [blame] | 825 | void cpu_reset(CPUState *s); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 826 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 827 | #define CPU_LOG_TB_OUT_ASM (1 << 0) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 828 | #define CPU_LOG_TB_IN_ASM (1 << 1) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 829 | #define CPU_LOG_TB_OP (1 << 2) |
| 830 | #define CPU_LOG_TB_OP_OPT (1 << 3) |
| 831 | #define CPU_LOG_INT (1 << 4) |
| 832 | #define CPU_LOG_EXEC (1 << 5) |
| 833 | #define CPU_LOG_PCALL (1 << 6) |
bellard | fd87259 | 2004-05-12 19:11:15 +0000 | [diff] [blame] | 834 | #define CPU_LOG_IOPORT (1 << 7) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 835 | #define CPU_LOG_TB_CPU (1 << 8) |
aliguori | eca1bdf | 2009-01-26 19:54:31 +0000 | [diff] [blame] | 836 | #define CPU_LOG_RESET (1 << 9) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 837 | |
| 838 | /* define log items */ |
| 839 | typedef struct CPULogItem { |
| 840 | int mask; |
| 841 | const char *name; |
| 842 | const char *help; |
| 843 | } CPULogItem; |
| 844 | |
blueswir1 | c7cd6a3 | 2008-10-02 18:27:46 +0000 | [diff] [blame] | 845 | extern const CPULogItem cpu_log_items[]; |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 846 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 847 | void cpu_set_log(int log_flags); |
| 848 | void cpu_set_log_filename(const char *filename); |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 849 | int cpu_str_to_log_mask(const char *str); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 850 | |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 851 | #if !defined(CONFIG_USER_ONLY) |
| 852 | |
Paul Brook | 4fcc562 | 2010-03-01 03:46:18 +0000 | [diff] [blame] | 853 | /* Return the physical page corresponding to a virtual one. Use it |
| 854 | only for debugging because no protection checks are done. Return -1 |
| 855 | if no page found. */ |
| 856 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr); |
| 857 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 858 | /* memory API */ |
| 859 | |
bellard | edf75d5 | 2004-01-04 17:43:30 +0000 | [diff] [blame] | 860 | extern int phys_ram_fd; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 861 | extern uint8_t *phys_ram_dirty; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 862 | extern ram_addr_t ram_size; |
| 863 | extern ram_addr_t last_ram_offset; |
bellard | edf75d5 | 2004-01-04 17:43:30 +0000 | [diff] [blame] | 864 | |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 865 | extern const char *mem_path; |
| 866 | extern int mem_prealloc; |
| 867 | |
bellard | edf75d5 | 2004-01-04 17:43:30 +0000 | [diff] [blame] | 868 | /* physical memory access */ |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 869 | |
| 870 | /* MMIO pages are identified by a combination of an IO device index and |
| 871 | 3 flags. The ROMD code stores the page ram offset in iotlb entry, |
| 872 | so only a limited number of ids are avaiable. */ |
| 873 | |
bellard | 9869996 | 2005-11-26 10:29:22 +0000 | [diff] [blame] | 874 | #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT)) |
bellard | edf75d5 | 2004-01-04 17:43:30 +0000 | [diff] [blame] | 875 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 876 | /* Flags stored in the low bits of the TLB virtual address. These are |
| 877 | defined so that fast path ram access is all zeros. */ |
| 878 | /* Zero if TLB entry is valid. */ |
| 879 | #define TLB_INVALID_MASK (1 << 3) |
| 880 | /* Set if TLB entry references a clean RAM page. The iotlb entry will |
| 881 | contain the page physical address. */ |
| 882 | #define TLB_NOTDIRTY (1 << 4) |
| 883 | /* Set if TLB entry is an IO callback. */ |
| 884 | #define TLB_MMIO (1 << 5) |
| 885 | |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 886 | #define VGA_DIRTY_FLAG 0x01 |
| 887 | #define CODE_DIRTY_FLAG 0x02 |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 888 | #define MIGRATION_DIRTY_FLAG 0x08 |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 889 | |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 890 | /* read dirty bit (return 0 or 1) */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 891 | static inline int cpu_physical_memory_is_dirty(ram_addr_t addr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 892 | { |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 893 | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; |
| 894 | } |
| 895 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 896 | static inline int cpu_physical_memory_get_dirty(ram_addr_t addr, |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 897 | int dirty_flags) |
| 898 | { |
| 899 | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 900 | } |
| 901 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 902 | static inline void cpu_physical_memory_set_dirty(ram_addr_t addr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 903 | { |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 904 | phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 905 | } |
| 906 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 907 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 908 | int dirty_flags); |
bellard | 04c504c | 2005-08-21 09:24:50 +0000 | [diff] [blame] | 909 | void cpu_tlb_update_dirty(CPUState *env); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 910 | |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 911 | int cpu_physical_memory_set_dirty_tracking(int enable); |
| 912 | |
| 913 | int cpu_physical_memory_get_dirty_tracking(void); |
| 914 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 915 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
| 916 | target_phys_addr_t end_addr); |
aliguori | 2bec46d | 2008-11-24 20:21:41 +0000 | [diff] [blame] | 917 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 918 | void dump_exec_info(FILE *f, |
| 919 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
| 920 | |
aliguori | f65ed4c | 2008-12-09 20:09:57 +0000 | [diff] [blame] | 921 | /* Coalesced MMIO regions are areas where write operations can be reordered. |
| 922 | * This usually implies that write operations are side-effect free. This allows |
| 923 | * batching which can make a major impact on performance when using |
| 924 | * virtualization. |
| 925 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 926 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size); |
aliguori | f65ed4c | 2008-12-09 20:09:57 +0000 | [diff] [blame] | 927 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 928 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size); |
aliguori | f65ed4c | 2008-12-09 20:09:57 +0000 | [diff] [blame] | 929 | |
Sheng Yang | 62a2744 | 2010-01-26 19:21:16 +0800 | [diff] [blame] | 930 | void qemu_flush_coalesced_mmio_buffer(void); |
| 931 | |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 932 | #endif /* !CONFIG_USER_ONLY */ |
| 933 | |
| 934 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
| 935 | uint8_t *buf, int len, int is_write); |
| 936 | |
bellard | effedbc | 2006-07-13 23:00:40 +0000 | [diff] [blame] | 937 | /*******************************************/ |
| 938 | /* host CPU ticks (if available) */ |
| 939 | |
malc | e58ffeb | 2009-01-14 18:39:49 +0000 | [diff] [blame] | 940 | #if defined(_ARCH_PPC) |
bellard | effedbc | 2006-07-13 23:00:40 +0000 | [diff] [blame] | 941 | |
bellard | effedbc | 2006-07-13 23:00:40 +0000 | [diff] [blame] | 942 | static inline int64_t cpu_get_real_ticks(void) |
| 943 | { |
malc | 5e10fc9 | 2009-01-25 10:56:48 +0000 | [diff] [blame] | 944 | int64_t retval; |
| 945 | #ifdef _ARCH_PPC64 |
| 946 | /* This reads timebase in one 64bit go and includes Cell workaround from: |
| 947 | http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027052.html |
| 948 | */ |
| 949 | __asm__ __volatile__ ( |
| 950 | "mftb %0\n\t" |
| 951 | "cmpwi %0,0\n\t" |
| 952 | "beq- $-8" |
| 953 | : "=r" (retval)); |
| 954 | #else |
| 955 | /* http://ozlabs.org/pipermail/linuxppc-dev/1999-October/003889.html */ |
| 956 | unsigned long junk; |
| 957 | __asm__ __volatile__ ( |
| 958 | "mftbu %1\n\t" |
| 959 | "mftb %L0\n\t" |
| 960 | "mftbu %0\n\t" |
| 961 | "cmpw %0,%1\n\t" |
| 962 | "bne $-16" |
| 963 | : "=r" (retval), "=r" (junk)); |
| 964 | #endif |
| 965 | return retval; |
bellard | effedbc | 2006-07-13 23:00:40 +0000 | [diff] [blame] | 966 | } |
| 967 | |
| 968 | #elif defined(__i386__) |
| 969 | |
| 970 | static inline int64_t cpu_get_real_ticks(void) |
bellard | 5f1ce94 | 2006-02-08 22:40:15 +0000 | [diff] [blame] | 971 | { |
| 972 | int64_t val; |
| 973 | asm volatile ("rdtsc" : "=A" (val)); |
| 974 | return val; |
| 975 | } |
| 976 | |
bellard | effedbc | 2006-07-13 23:00:40 +0000 | [diff] [blame] | 977 | #elif defined(__x86_64__) |
| 978 | |
| 979 | static inline int64_t cpu_get_real_ticks(void) |
| 980 | { |
| 981 | uint32_t low,high; |
| 982 | int64_t val; |
| 983 | asm volatile("rdtsc" : "=a" (low), "=d" (high)); |
| 984 | val = high; |
| 985 | val <<= 32; |
| 986 | val |= low; |
| 987 | return val; |
| 988 | } |
| 989 | |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 990 | #elif defined(__hppa__) |
| 991 | |
| 992 | static inline int64_t cpu_get_real_ticks(void) |
| 993 | { |
| 994 | int val; |
| 995 | asm volatile ("mfctl %%cr16, %0" : "=r"(val)); |
| 996 | return val; |
| 997 | } |
| 998 | |
bellard | effedbc | 2006-07-13 23:00:40 +0000 | [diff] [blame] | 999 | #elif defined(__ia64) |
| 1000 | |
| 1001 | static inline int64_t cpu_get_real_ticks(void) |
| 1002 | { |
| 1003 | int64_t val; |
| 1004 | asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory"); |
| 1005 | return val; |
| 1006 | } |
| 1007 | |
| 1008 | #elif defined(__s390__) |
| 1009 | |
| 1010 | static inline int64_t cpu_get_real_ticks(void) |
| 1011 | { |
| 1012 | int64_t val; |
| 1013 | asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc"); |
| 1014 | return val; |
| 1015 | } |
| 1016 | |
blueswir1 | 3142255 | 2007-04-16 18:27:06 +0000 | [diff] [blame] | 1017 | #elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__) |
bellard | effedbc | 2006-07-13 23:00:40 +0000 | [diff] [blame] | 1018 | |
| 1019 | static inline int64_t cpu_get_real_ticks (void) |
| 1020 | { |
| 1021 | #if defined(_LP64) |
| 1022 | uint64_t rval; |
| 1023 | asm volatile("rd %%tick,%0" : "=r"(rval)); |
| 1024 | return rval; |
| 1025 | #else |
| 1026 | union { |
| 1027 | uint64_t i64; |
| 1028 | struct { |
| 1029 | uint32_t high; |
| 1030 | uint32_t low; |
| 1031 | } i32; |
| 1032 | } rval; |
| 1033 | asm volatile("rd %%tick,%1; srlx %1,32,%0" |
| 1034 | : "=r"(rval.i32.high), "=r"(rval.i32.low)); |
| 1035 | return rval.i64; |
| 1036 | #endif |
| 1037 | } |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1038 | |
Aurelien Jarno | 9706c06 | 2009-12-20 21:18:57 +0100 | [diff] [blame] | 1039 | #elif defined(__mips__) && \ |
| 1040 | ((defined(__mips_isa_rev) && __mips_isa_rev >= 2) || defined(__linux__)) |
Arnaud Patard | fea0ac2 | 2009-04-11 16:02:46 +0200 | [diff] [blame] | 1041 | /* |
| 1042 | * binutils wants to use rdhwr only on mips32r2 |
| 1043 | * but as linux kernel emulate it, it's fine |
| 1044 | * to use it. |
| 1045 | * |
| 1046 | */ |
| 1047 | #define MIPS_RDHWR(rd, value) { \ |
| 1048 | __asm__ __volatile__ ( \ |
| 1049 | ".set push\n\t" \ |
| 1050 | ".set mips32r2\n\t" \ |
| 1051 | "rdhwr %0, "rd"\n\t" \ |
| 1052 | ".set pop" \ |
| 1053 | : "=r" (value)); \ |
| 1054 | } |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1055 | |
| 1056 | static inline int64_t cpu_get_real_ticks(void) |
| 1057 | { |
Arnaud Patard | fea0ac2 | 2009-04-11 16:02:46 +0200 | [diff] [blame] | 1058 | /* On kernels >= 2.6.25 rdhwr <reg>, $2 and $3 are emulated */ |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1059 | uint32_t count; |
| 1060 | static uint32_t cyc_per_count = 0; |
| 1061 | |
| 1062 | if (!cyc_per_count) |
Arnaud Patard | fea0ac2 | 2009-04-11 16:02:46 +0200 | [diff] [blame] | 1063 | MIPS_RDHWR("$3", cyc_per_count); |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1064 | |
Arnaud Patard | fea0ac2 | 2009-04-11 16:02:46 +0200 | [diff] [blame] | 1065 | MIPS_RDHWR("$2", count); |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1066 | return (int64_t)(count * cyc_per_count); |
ths | c4b89d1 | 2007-05-05 19:23:11 +0000 | [diff] [blame] | 1067 | } |
| 1068 | |
pbrook | 4615218 | 2006-07-30 19:16:29 +0000 | [diff] [blame] | 1069 | #else |
| 1070 | /* The host CPU doesn't have an easily accessible cycle counter. |
ths | 85028e4 | 2007-05-08 22:51:41 +0000 | [diff] [blame] | 1071 | Just return a monotonically increasing value. This will be |
| 1072 | totally wrong, but hopefully better than nothing. */ |
pbrook | 4615218 | 2006-07-30 19:16:29 +0000 | [diff] [blame] | 1073 | static inline int64_t cpu_get_real_ticks (void) |
| 1074 | { |
| 1075 | static int64_t ticks = 0; |
| 1076 | return ticks++; |
| 1077 | } |
bellard | effedbc | 2006-07-13 23:00:40 +0000 | [diff] [blame] | 1078 | #endif |
| 1079 | |
| 1080 | /* profiling */ |
| 1081 | #ifdef CONFIG_PROFILER |
| 1082 | static inline int64_t profile_getclock(void) |
| 1083 | { |
| 1084 | return cpu_get_real_ticks(); |
| 1085 | } |
| 1086 | |
bellard | 5f1ce94 | 2006-02-08 22:40:15 +0000 | [diff] [blame] | 1087 | extern int64_t qemu_time, qemu_time_start; |
| 1088 | extern int64_t tlb_flush_time; |
bellard | 5f1ce94 | 2006-02-08 22:40:15 +0000 | [diff] [blame] | 1089 | extern int64_t dev_time; |
bellard | 5f1ce94 | 2006-02-08 22:40:15 +0000 | [diff] [blame] | 1090 | #endif |
| 1091 | |
Huang Ying | 79c4f6b | 2009-06-23 10:05:14 +0800 | [diff] [blame] | 1092 | void cpu_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, |
| 1093 | uint64_t mcg_status, uint64_t addr, uint64_t misc); |
| 1094 | |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 1095 | #endif /* CPU_ALL_H */ |