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ths94cff602007-10-08 13:11:58 +00001/*
2 * CRIS mmu emulation.
3 *
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
ths94cff602007-10-08 13:11:58 +000019 */
20
21#ifndef CONFIG_USER_ONLY
22
ths94cff602007-10-08 13:11:58 +000023#include "cpu.h"
24#include "mmu.h"
ths94cff602007-10-08 13:11:58 +000025
edgar_igld297f462008-06-30 08:59:49 +000026#ifdef DEBUG
27#define D(x) x
Riccardo Magliocchetti02021c32010-05-19 18:49:29 +020028#define D_LOG(...) qemu_log(__VA_ARGS__)
edgar_igld297f462008-06-30 08:59:49 +000029#else
Blue Swirl3ffd7102010-09-18 07:01:48 +000030#define D(x) do { } while (0)
aliguorid12d51d2009-01-15 21:48:06 +000031#define D_LOG(...) do { } while (0)
edgar_igld297f462008-06-30 08:59:49 +000032#endif
ths94cff602007-10-08 13:11:58 +000033
Andreas Färbera1170bf2012-03-14 01:38:21 +010034void cris_mmu_init(CPUCRISState *env)
edgar_igl44cd42e2008-05-11 14:28:14 +000035{
36 env->mmu_rand_lfsr = 0xcccc;
37}
38
39#define SR_POLYNOM 0x8805
40static inline unsigned int compute_polynom(unsigned int sr)
41{
42 unsigned int i;
43 unsigned int f;
44
45 f = 0;
46 for (i = 0; i < 16; i++)
47 f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
48
49 return f;
50}
51
Andreas Färbera1170bf2012-03-14 01:38:21 +010052static void cris_mmu_update_rand_lfsr(CPUCRISState *env)
Edgar E. Iglesias253248a2010-07-05 10:15:10 +020053{
54 unsigned int f;
55
56 /* Update lfsr at every fault. */
57 f = compute_polynom(env->mmu_rand_lfsr);
58 env->mmu_rand_lfsr >>= 1;
59 env->mmu_rand_lfsr |= (f << 15);
60 env->mmu_rand_lfsr &= 0xffff;
61}
62
edgar_iglef29a702008-05-06 08:04:40 +000063static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
ths94cff602007-10-08 13:11:58 +000064{
65 return (rw_gc_cfg & 12) != 0;
66}
67
edgar_iglef29a702008-05-06 08:04:40 +000068static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
ths94cff602007-10-08 13:11:58 +000069{
70 return (1 << seg) & rw_mm_cfg;
71}
72
Andreas Färbera1170bf2012-03-14 01:38:21 +010073static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
ths94cff602007-10-08 13:11:58 +000074{
75 uint32_t base;
76 int i;
77
78 if (seg < 8)
79 base = env->sregs[SFR_RW_MM_KBASE_LO];
80 else
81 base = env->sregs[SFR_RW_MM_KBASE_HI];
82
83 i = seg & 7;
84 base >>= i * 4;
85 base &= 15;
86
87 base <<= 28;
88 return base;
89}
90/* Used by the tlb decoder. */
91#define EXTRACT_FIELD(src, start, end) \
edgar_igl786c02f2008-03-14 01:08:09 +000092 (((src) >> start) & ((1 << (end - start + 1)) - 1))
93
94static inline void set_field(uint32_t *dst, unsigned int val,
95 unsigned int offset, unsigned int width)
96{
97 uint32_t mask;
98
99 mask = (1 << width) - 1;
100 mask <<= offset;
101 val <<= offset;
102
103 val &= mask;
edgar_igl786c02f2008-03-14 01:08:09 +0000104 *dst &= ~(mask);
105 *dst |= val;
106}
ths94cff602007-10-08 13:11:58 +0000107
edgar_igld297f462008-06-30 08:59:49 +0000108#ifdef DEBUG
Andreas Färbera1170bf2012-03-14 01:38:21 +0100109static void dump_tlb(CPUCRISState *env, int mmu)
edgar_iglb41f7df2008-05-02 22:16:17 +0000110{
111 int set;
112 int idx;
113 uint32_t hi, lo, tlb_vpn, tlb_pfn;
114
115 for (set = 0; set < 4; set++) {
116 for (idx = 0; idx < 16; idx++) {
117 lo = env->tlbsets[mmu][set][idx].lo;
118 hi = env->tlbsets[mmu][set][idx].hi;
119 tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
120 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
121
122 printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
123 set, idx, hi, lo, tlb_vpn, tlb_pfn);
124 }
125 }
126}
edgar_igld297f462008-06-30 08:59:49 +0000127#endif
edgar_iglb41f7df2008-05-02 22:16:17 +0000128
129/* rw 0 = read, 1 = write, 2 = exec. */
Edgar E. Iglesias2fa73ec2009-04-25 15:51:53 +0200130static int cris_mmu_translate_page(struct cris_mmu_result *res,
Andreas Färbera1170bf2012-03-14 01:38:21 +0100131 CPUCRISState *env, uint32_t vaddr,
Edgar E. Iglesias9f5a1fa2010-07-05 11:39:04 +0200132 int rw, int usermode, int debug)
ths94cff602007-10-08 13:11:58 +0000133{
134 unsigned int vpage;
135 unsigned int idx;
edgar_iglb23761f2008-09-03 14:31:11 +0000136 uint32_t pid, lo, hi;
edgar_igl786c02f2008-03-14 01:08:09 +0000137 uint32_t tlb_vpn, tlb_pfn = 0;
138 int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
139 int cfg_v, cfg_k, cfg_w, cfg_x;
edgar_iglb41f7df2008-05-02 22:16:17 +0000140 int set, match = 0;
edgar_igl786c02f2008-03-14 01:08:09 +0000141 uint32_t r_cause;
142 uint32_t r_cfg;
143 int rwcause;
edgar_iglb41f7df2008-05-02 22:16:17 +0000144 int mmu = 1; /* Data mmu is default. */
145 int vect_base;
edgar_igl786c02f2008-03-14 01:08:09 +0000146
147 r_cause = env->sregs[SFR_R_MM_CAUSE];
148 r_cfg = env->sregs[SFR_RW_MM_CFG];
edgar_igl28de16d2008-09-22 20:51:28 +0000149 pid = env->pregs[PR_PID] & 0xff;
edgar_iglb41f7df2008-05-02 22:16:17 +0000150
151 switch (rw) {
152 case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
153 case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
154 default:
155 case 0: rwcause = CRIS_MMU_ERR_READ; break;
156 }
157
158 /* I exception vectors 4 - 7, D 8 - 11. */
159 vect_base = (mmu + 1) * 4;
ths94cff602007-10-08 13:11:58 +0000160
161 vpage = vaddr >> 13;
ths94cff602007-10-08 13:11:58 +0000162
163 /* We know the index which to check on each set.
164 Scan both I and D. */
edgar_igl786c02f2008-03-14 01:08:09 +0000165#if 0
edgar_iglb41f7df2008-05-02 22:16:17 +0000166 for (set = 0; set < 4; set++) {
167 for (idx = 0; idx < 16; idx++) {
168 lo = env->tlbsets[mmu][set][idx].lo;
169 hi = env->tlbsets[mmu][set][idx].hi;
edgar_igl786c02f2008-03-14 01:08:09 +0000170 tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
171 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
172
173 printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
edgar_iglb41f7df2008-05-02 22:16:17 +0000174 set, idx, hi, lo, tlb_vpn, tlb_pfn);
edgar_igl786c02f2008-03-14 01:08:09 +0000175 }
176 }
177#endif
edgar_iglb41f7df2008-05-02 22:16:17 +0000178
179 idx = vpage & 15;
180 for (set = 0; set < 4; set++)
ths94cff602007-10-08 13:11:58 +0000181 {
edgar_iglb41f7df2008-05-02 22:16:17 +0000182 lo = env->tlbsets[mmu][set][idx].lo;
183 hi = env->tlbsets[mmu][set][idx].hi;
ths94cff602007-10-08 13:11:58 +0000184
edgar_iglb23761f2008-09-03 14:31:11 +0000185 tlb_vpn = hi >> 13;
edgar_igl44cd42e2008-05-11 14:28:14 +0000186 tlb_pid = EXTRACT_FIELD(hi, 0, 7);
edgar_igl44cd42e2008-05-11 14:28:14 +0000187 tlb_g = EXTRACT_FIELD(lo, 4, 4);
ths94cff602007-10-08 13:11:58 +0000188
aliguorid12d51d2009-01-15 21:48:06 +0000189 D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
190 mmu, set, idx, tlb_vpn, vpage, lo, hi);
edgar_iglb23761f2008-09-03 14:31:11 +0000191 if ((tlb_g || (tlb_pid == pid))
edgar_igl44cd42e2008-05-11 14:28:14 +0000192 && tlb_vpn == vpage) {
ths94cff602007-10-08 13:11:58 +0000193 match = 1;
194 break;
195 }
196 }
197
edgar_iglb41f7df2008-05-02 22:16:17 +0000198 res->bf_vec = vect_base;
ths94cff602007-10-08 13:11:58 +0000199 if (match) {
edgar_igl786c02f2008-03-14 01:08:09 +0000200 cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
201 cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
202 cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
203 cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
204
edgar_igl786c02f2008-03-14 01:08:09 +0000205 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
edgar_igl786c02f2008-03-14 01:08:09 +0000206 tlb_v = EXTRACT_FIELD(lo, 3, 3);
207 tlb_k = EXTRACT_FIELD(lo, 2, 2);
208 tlb_w = EXTRACT_FIELD(lo, 1, 1);
209 tlb_x = EXTRACT_FIELD(lo, 0, 0);
210
211 /*
212 set_exception_vector(0x04, i_mmu_refill);
213 set_exception_vector(0x05, i_mmu_invalid);
214 set_exception_vector(0x06, i_mmu_access);
215 set_exception_vector(0x07, i_mmu_execute);
216 set_exception_vector(0x08, d_mmu_refill);
217 set_exception_vector(0x09, d_mmu_invalid);
218 set_exception_vector(0x0a, d_mmu_access);
219 set_exception_vector(0x0b, d_mmu_write);
220 */
edgar_igl44cd42e2008-05-11 14:28:14 +0000221 if (cfg_k && tlb_k && usermode) {
edgar_iglef29a702008-05-06 08:04:40 +0000222 D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
223 vaddr, lo, env->pc));
224 match = 0;
225 res->bf_vec = vect_base + 2;
edgar_iglb41f7df2008-05-02 22:16:17 +0000226 } else if (rw == 1 && cfg_w && !tlb_w) {
edgar_iglef29a702008-05-06 08:04:40 +0000227 D(printf ("tlb: write protected %x lo=%x pc=%x\n",
228 vaddr, lo, env->pc));
229 match = 0;
230 /* write accesses never go through the I mmu. */
231 res->bf_vec = vect_base + 3;
232 } else if (rw == 2 && cfg_x && !tlb_x) {
233 D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
234 vaddr, lo, env->pc));
edgar_iglb41f7df2008-05-02 22:16:17 +0000235 match = 0;
236 res->bf_vec = vect_base + 3;
237 } else if (cfg_v && !tlb_v) {
238 D(printf ("tlb: invalid %x\n", vaddr));
edgar_igl786c02f2008-03-14 01:08:09 +0000239 match = 0;
edgar_iglb41f7df2008-05-02 22:16:17 +0000240 res->bf_vec = vect_base + 1;
edgar_igl786c02f2008-03-14 01:08:09 +0000241 }
edgar_igl786c02f2008-03-14 01:08:09 +0000242
edgar_iglb41f7df2008-05-02 22:16:17 +0000243 res->prot = 0;
244 if (match) {
245 res->prot |= PAGE_READ;
246 if (tlb_w)
247 res->prot |= PAGE_WRITE;
Edgar E. Iglesias58aebb92010-09-18 12:34:59 +0200248 if (mmu == 0 && (cfg_x || tlb_x))
edgar_iglb41f7df2008-05-02 22:16:17 +0000249 res->prot |= PAGE_EXEC;
250 }
251 else
252 D(dump_tlb(env, mmu));
edgar_igl44cd42e2008-05-11 14:28:14 +0000253 } else {
254 /* If refill, provide a randomized set. */
255 set = env->mmu_rand_lfsr & 3;
ths94cff602007-10-08 13:11:58 +0000256 }
edgar_igl786c02f2008-03-14 01:08:09 +0000257
Edgar E. Iglesias9f5a1fa2010-07-05 11:39:04 +0200258 if (!match && !debug) {
Edgar E. Iglesias253248a2010-07-05 10:15:10 +0200259 cris_mmu_update_rand_lfsr(env);
edgar_igl44cd42e2008-05-11 14:28:14 +0000260
edgar_igl44cd42e2008-05-11 14:28:14 +0000261 /* Compute index. */
edgar_iglb41f7df2008-05-02 22:16:17 +0000262 idx = vpage & 15;
edgar_iglb41f7df2008-05-02 22:16:17 +0000263
264 /* Update RW_MM_TLB_SEL. */
265 env->sregs[SFR_RW_MM_TLB_SEL] = 0;
266 set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
edgar_igl44cd42e2008-05-11 14:28:14 +0000267 set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
edgar_iglb41f7df2008-05-02 22:16:17 +0000268
269 /* Update RW_MM_CAUSE. */
270 set_field(&r_cause, rwcause, 8, 2);
edgar_igl786c02f2008-03-14 01:08:09 +0000271 set_field(&r_cause, vpage, 13, 19);
edgar_igl28de16d2008-09-22 20:51:28 +0000272 set_field(&r_cause, pid, 0, 8);
edgar_igl786c02f2008-03-14 01:08:09 +0000273 env->sregs[SFR_R_MM_CAUSE] = r_cause;
edgar_iglb41f7df2008-05-02 22:16:17 +0000274 D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
edgar_igl786c02f2008-03-14 01:08:09 +0000275 }
edgar_iglb41f7df2008-05-02 22:16:17 +0000276
edgar_iglb41f7df2008-05-02 22:16:17 +0000277 D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
278 " %x cause=%x sel=%x sp=%x %x %x\n",
279 __func__, rw, match, env->pc,
edgar_igl786c02f2008-03-14 01:08:09 +0000280 vaddr, vpage,
281 tlb_vpn, tlb_pfn, tlb_pid,
edgar_igl28de16d2008-09-22 20:51:28 +0000282 pid,
edgar_igl786c02f2008-03-14 01:08:09 +0000283 r_cause,
284 env->sregs[SFR_RW_MM_TLB_SEL],
edgar_iglb41f7df2008-05-02 22:16:17 +0000285 env->regs[R_SP], env->pregs[PR_USP], env->ksp));
edgar_igl786c02f2008-03-14 01:08:09 +0000286
edgar_iglbf91ada2009-01-04 15:42:04 +0000287 res->phy = tlb_pfn << TARGET_PAGE_BITS;
ths94cff602007-10-08 13:11:58 +0000288 return !match;
289}
290
Andreas Färbera1170bf2012-03-14 01:38:21 +0100291void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
edgar_igl786c02f2008-03-14 01:08:09 +0000292{
edgar_iglcf1d97f2008-05-13 10:59:14 +0000293 target_ulong vaddr;
294 unsigned int idx;
295 uint32_t lo, hi;
296 uint32_t tlb_vpn;
edgar_igl80e1b262009-01-04 15:45:17 +0000297 int tlb_pid, tlb_g, tlb_v;
edgar_iglcf1d97f2008-05-13 10:59:14 +0000298 unsigned int set;
299 unsigned int mmu;
edgar_igl786c02f2008-03-14 01:08:09 +0000300
edgar_iglcf1d97f2008-05-13 10:59:14 +0000301 pid &= 0xff;
302 for (mmu = 0; mmu < 2; mmu++) {
303 for (set = 0; set < 4; set++)
304 {
305 for (idx = 0; idx < 16; idx++) {
306 lo = env->tlbsets[mmu][set][idx].lo;
307 hi = env->tlbsets[mmu][set][idx].hi;
308
309 tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
310 tlb_pid = EXTRACT_FIELD(hi, 0, 7);
311 tlb_g = EXTRACT_FIELD(lo, 4, 4);
312 tlb_v = EXTRACT_FIELD(lo, 3, 3);
edgar_igl786c02f2008-03-14 01:08:09 +0000313
edgar_igl80e1b262009-01-04 15:45:17 +0000314 if (tlb_v && !tlb_g && (tlb_pid == pid)) {
edgar_iglcf1d97f2008-05-13 10:59:14 +0000315 vaddr = tlb_vpn << TARGET_PAGE_BITS;
aliguorid12d51d2009-01-15 21:48:06 +0000316 D_LOG("flush pid=%x vaddr=%x\n",
317 pid, vaddr);
edgar_iglcf1d97f2008-05-13 10:59:14 +0000318 tlb_flush_page(env, vaddr);
319 }
320 }
321 }
322 }
edgar_igl786c02f2008-03-14 01:08:09 +0000323}
324
Edgar E. Iglesias2fa73ec2009-04-25 15:51:53 +0200325int cris_mmu_translate(struct cris_mmu_result *res,
Andreas Färbera1170bf2012-03-14 01:38:21 +0100326 CPUCRISState *env, uint32_t vaddr,
Edgar E. Iglesias9f5a1fa2010-07-05 11:39:04 +0200327 int rw, int mmu_idx, int debug)
ths94cff602007-10-08 13:11:58 +0000328{
ths94cff602007-10-08 13:11:58 +0000329 int seg;
330 int miss = 0;
edgar_igl786c02f2008-03-14 01:08:09 +0000331 int is_user = mmu_idx == MMU_USER_IDX;
edgar_iglb41f7df2008-05-02 22:16:17 +0000332 uint32_t old_srs;
333
334 old_srs= env->pregs[PR_SRS];
335
336 /* rw == 2 means exec, map the access to the insn mmu. */
337 env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
ths94cff602007-10-08 13:11:58 +0000338
339 if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
340 res->phy = vaddr;
edgar_iglb23761f2008-09-03 14:31:11 +0000341 res->prot = PAGE_BITS;
edgar_iglb41f7df2008-05-02 22:16:17 +0000342 goto done;
ths94cff602007-10-08 13:11:58 +0000343 }
344
345 seg = vaddr >> 28;
Edgar E. Iglesias218951e2009-10-10 17:34:27 +0200346 if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
ths94cff602007-10-08 13:11:58 +0000347 {
348 uint32_t base;
349
350 miss = 0;
351 base = cris_mmu_translate_seg(env, seg);
Blue Swirl0d84be52010-04-25 19:46:46 +0000352 res->phy = base | (0x0fffffff & vaddr);
edgar_iglb23761f2008-09-03 14:31:11 +0000353 res->prot = PAGE_BITS;
Edgar E. Iglesias9f5a1fa2010-07-05 11:39:04 +0200354 } else {
355 miss = cris_mmu_translate_page(res, env, vaddr, rw,
356 is_user, debug);
ths94cff602007-10-08 13:11:58 +0000357 }
edgar_iglb41f7df2008-05-02 22:16:17 +0000358 done:
359 env->pregs[PR_SRS] = old_srs;
ths94cff602007-10-08 13:11:58 +0000360 return miss;
361}
362#endif