Google Git
Sign in
qemu / qemu / d2fe226467995c6843bba98da2e51dd5e85cef58 / . / target / mips / helper.h
blob: de32d82e980e2d7c5037d87c4f31e2c5af686349 [file] [log] [blame]
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]1DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int)
2DEF_HELPER_2(raise_exception, noreturn, env, i32)
Pavel Dovgaluk9c708c72015-07-10 12:57:08 +0300[diff] [blame]3DEF_HELPER_1(raise_exception_debug, noreturn, env)
ths7dd9e552008-06-08 07:42:23 +0000[diff] [blame]4
thsc8c22272008-06-20 15:12:14 +0000[diff] [blame]5#ifdef TARGET_MIPS64
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]6DEF_HELPER_4(sdl, void, env, tl, tl, int)
7DEF_HELPER_4(sdr, void, env, tl, tl, int)
thsc8c22272008-06-20 15:12:14 +0000[diff] [blame]8#endif
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]9DEF_HELPER_4(swl, void, env, tl, tl, int)
10DEF_HELPER_4(swr, void, env, tl, tl, int)
thsc8c22272008-06-20 15:12:14 +0000[diff] [blame]11
Aurelien Jarnoe7139c42009-11-30 15:39:54 +0100[diff] [blame]12#ifndef CONFIG_USER_ONLY
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]13DEF_HELPER_3(ll, tl, env, tl, int)
Aurelien Jarnoe7139c42009-11-30 15:39:54 +0100[diff] [blame]14#ifdef TARGET_MIPS64
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]15DEF_HELPER_3(lld, tl, env, tl, int)
Aurelien Jarnoe7139c42009-11-30 15:39:54 +0100[diff] [blame]16#endif
17#endif
18
Yongbok Kim15eacb92014-06-27 08:49:05 +0100[diff] [blame]19DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
20#ifdef TARGET_MIPS64
21DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
22#endif
23
Matthew Fortunee222f502018-08-02 16:16:20 +0200[diff] [blame]24DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
25
Nathan Froyd3c824102010-06-08 13:29:59 -0700[diff] [blame]26/* microMIPS functions */
Richard Hendersonf5daeec2013-09-14 15:38:30 -0700[diff] [blame]27DEF_HELPER_4(lwm, void, env, tl, tl, i32)
28DEF_HELPER_4(swm, void, env, tl, tl, i32)
Nathan Froyd3c824102010-06-08 13:29:59 -0700[diff] [blame]29#ifdef TARGET_MIPS64
Richard Hendersonf5daeec2013-09-14 15:38:30 -0700[diff] [blame]30DEF_HELPER_4(ldm, void, env, tl, tl, i32)
31DEF_HELPER_4(sdm, void, env, tl, tl, i32)
Nathan Froyd3c824102010-06-08 13:29:59 -0700[diff] [blame]32#endif
33
pbrooka7812ae2008-11-17 14:43:54 +0000[diff] [blame]34DEF_HELPER_2(fork, void, tl, tl)
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]35DEF_HELPER_2(yield, tl, env, tl)
thsf1aa6322008-06-09 07:13:38 +0000[diff] [blame]36
37/* CP1 functions */
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]38DEF_HELPER_2(cfc1, tl, env, i32)
Petar Jovanovic736d1202014-01-22 18:35:32 +0100[diff] [blame]39DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
ths5d0fc902008-06-11 15:27:54 +0000[diff] [blame]40
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]41DEF_HELPER_2(float_cvtd_s, i64, env, i32)
42DEF_HELPER_2(float_cvtd_w, i64, env, i32)
43DEF_HELPER_2(float_cvtd_l, i64, env, i64)
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]44DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
45DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
46DEF_HELPER_2(float_cvts_d, i32, env, i64)
47DEF_HELPER_2(float_cvts_w, i32, env, i32)
48DEF_HELPER_2(float_cvts_l, i32, env, i64)
49DEF_HELPER_2(float_cvts_pl, i32, env, i32)
50DEF_HELPER_2(float_cvts_pu, i32, env, i32)
ths5d0fc902008-06-11 15:27:54 +0000[diff] [blame]51
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]52DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
53DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
ths5d0fc902008-06-11 15:27:54 +0000[diff] [blame]54
Aleksandar Markovicaf39bc82016-06-10 11:57:28 +0200[diff] [blame]55DEF_HELPER_FLAGS_2(float_class_s, TCG_CALL_NO_RWG_SE, i32, env, i32)
56DEF_HELPER_FLAGS_2(float_class_d, TCG_CALL_NO_RWG_SE, i64, env, i64)
Leon Alraee7f16ab2014-06-27 08:49:07 +0100[diff] [blame]57
58#define FOP_PROTO(op) \
59DEF_HELPER_4(float_ ## op ## _s, i32, env, i32, i32, i32) \
60DEF_HELPER_4(float_ ## op ## _d, i64, env, i64, i64, i64)
61FOP_PROTO(maddf)
62FOP_PROTO(msubf)
63#undef FOP_PROTO
64
65#define FOP_PROTO(op) \
66DEF_HELPER_3(float_ ## op ## _s, i32, env, i32, i32) \
67DEF_HELPER_3(float_ ## op ## _d, i64, env, i64, i64)
68FOP_PROTO(max)
69FOP_PROTO(maxa)
70FOP_PROTO(min)
71FOP_PROTO(mina)
72#undef FOP_PROTO
73
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]74#define FOP_PROTO(op) \
Aleksandar Markovic87552082016-06-10 11:57:35 +0200[diff] [blame]75DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
76DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
77DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
78DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
79FOP_PROTO(cvt)
thsb6d96be2008-07-09 11:05:10 +0000[diff] [blame]80FOP_PROTO(round)
81FOP_PROTO(trunc)
82FOP_PROTO(ceil)
83FOP_PROTO(floor)
Aleksandar Markovic87552082016-06-10 11:57:35 +0200[diff] [blame]84FOP_PROTO(cvt_2008)
85FOP_PROTO(round_2008)
86FOP_PROTO(trunc_2008)
87FOP_PROTO(ceil_2008)
88FOP_PROTO(floor_2008)
thsb6d96be2008-07-09 11:05:10 +0000[diff] [blame]89#undef FOP_PROTO
90
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]91#define FOP_PROTO(op) \
92DEF_HELPER_2(float_ ## op ## _s, i32, env, i32) \
93DEF_HELPER_2(float_ ## op ## _d, i64, env, i64)
thsa16336e2008-06-19 18:35:02 +0000[diff] [blame]94FOP_PROTO(sqrt)
ths5d0fc902008-06-11 15:27:54 +0000[diff] [blame]95FOP_PROTO(rsqrt)
96FOP_PROTO(recip)
Leon Alraee7f16ab2014-06-27 08:49:07 +0100[diff] [blame]97FOP_PROTO(rint)
ths5d0fc902008-06-11 15:27:54 +0000[diff] [blame]98#undef FOP_PROTO
99
pbrooka7812ae2008-11-17 14:43:54 +0000[diff] [blame]100#define FOP_PROTO(op) \
101DEF_HELPER_1(float_ ## op ## _s, i32, i32) \
102DEF_HELPER_1(float_ ## op ## _d, i64, i64) \
103DEF_HELPER_1(float_ ## op ## _ps, i64, i64)
thsb6d96be2008-07-09 11:05:10 +0000[diff] [blame]104FOP_PROTO(abs)
105FOP_PROTO(chs)
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]106#undef FOP_PROTO
107
108#define FOP_PROTO(op) \
109DEF_HELPER_2(float_ ## op ## _s, i32, env, i32) \
110DEF_HELPER_2(float_ ## op ## _d, i64, env, i64) \
111DEF_HELPER_2(float_ ## op ## _ps, i64, env, i64)
thsb6d96be2008-07-09 11:05:10 +0000[diff] [blame]112FOP_PROTO(recip1)
113FOP_PROTO(rsqrt1)
114#undef FOP_PROTO
115
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]116#define FOP_PROTO(op) \
117DEF_HELPER_3(float_ ## op ## _s, i32, env, i32, i32) \
118DEF_HELPER_3(float_ ## op ## _d, i64, env, i64, i64) \
119DEF_HELPER_3(float_ ## op ## _ps, i64, env, i64, i64)
ths5d0fc902008-06-11 15:27:54 +0000[diff] [blame]120FOP_PROTO(add)
121FOP_PROTO(sub)
122FOP_PROTO(mul)
123FOP_PROTO(div)
thsb6d96be2008-07-09 11:05:10 +0000[diff] [blame]124FOP_PROTO(recip2)
125FOP_PROTO(rsqrt2)
126#undef FOP_PROTO
127
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]128#define FOP_PROTO(op) \
129DEF_HELPER_4(float_ ## op ## _s, i32, env, i32, i32, i32) \
130DEF_HELPER_4(float_ ## op ## _d, i64, env, i64, i64, i64) \
131DEF_HELPER_4(float_ ## op ## _ps, i64, env, i64, i64, i64)
Aurelien Jarnob3d6cd42012-10-09 21:53:20 +0200[diff] [blame]132FOP_PROTO(madd)
133FOP_PROTO(msub)
134FOP_PROTO(nmadd)
135FOP_PROTO(nmsub)
ths5d0fc902008-06-11 15:27:54 +0000[diff] [blame]136#undef FOP_PROTO
137
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]138#define FOP_PROTO(op) \
139DEF_HELPER_4(cmp_d_ ## op, void, env, i64, i64, int) \
140DEF_HELPER_4(cmpabs_d_ ## op, void, env, i64, i64, int) \
141DEF_HELPER_4(cmp_s_ ## op, void, env, i32, i32, int) \
142DEF_HELPER_4(cmpabs_s_ ## op, void, env, i32, i32, int) \
143DEF_HELPER_4(cmp_ps_ ## op, void, env, i64, i64, int) \
144DEF_HELPER_4(cmpabs_ps_ ## op, void, env, i64, i64, int)
ths5d0fc902008-06-11 15:27:54 +0000[diff] [blame]145FOP_PROTO(f)
146FOP_PROTO(un)
147FOP_PROTO(eq)
148FOP_PROTO(ueq)
149FOP_PROTO(olt)
150FOP_PROTO(ult)
151FOP_PROTO(ole)
152FOP_PROTO(ule)
153FOP_PROTO(sf)
154FOP_PROTO(ngle)
155FOP_PROTO(seq)
156FOP_PROTO(ngl)
157FOP_PROTO(lt)
158FOP_PROTO(nge)
159FOP_PROTO(le)
160FOP_PROTO(ngt)
161#undef FOP_PROTO
ths08ba7962008-06-12 03:15:13 +0000[diff] [blame]162
Yongbok Kim3f493882014-06-27 08:49:07 +0100[diff] [blame]163#define FOP_PROTO(op) \
164DEF_HELPER_3(r6_cmp_d_ ## op, i64, env, i64, i64) \
165DEF_HELPER_3(r6_cmp_s_ ## op, i32, env, i32, i32)
166FOP_PROTO(af)
167FOP_PROTO(un)
168FOP_PROTO(eq)
169FOP_PROTO(ueq)
170FOP_PROTO(lt)
171FOP_PROTO(ult)
172FOP_PROTO(le)
173FOP_PROTO(ule)
174FOP_PROTO(saf)
175FOP_PROTO(sun)
176FOP_PROTO(seq)
177FOP_PROTO(sueq)
178FOP_PROTO(slt)
179FOP_PROTO(sult)
180FOP_PROTO(sle)
181FOP_PROTO(sule)
182FOP_PROTO(or)
183FOP_PROTO(une)
184FOP_PROTO(ne)
185FOP_PROTO(sor)
186FOP_PROTO(sune)
187FOP_PROTO(sne)
188#undef FOP_PROTO
189
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]190DEF_HELPER_1(rdhwr_cpunum, tl, env)
191DEF_HELPER_1(rdhwr_synci_step, tl, env)
192DEF_HELPER_1(rdhwr_cc, tl, env)
193DEF_HELPER_1(rdhwr_ccres, tl, env)
Yongbok Kimb00c7212015-10-29 15:18:39 +0000[diff] [blame]194DEF_HELPER_1(rdhwr_performance, tl, env)
195DEF_HELPER_1(rdhwr_xnp, tl, env)
Blue Swirl895c2d02012-09-02 14:52:59 +0000[diff] [blame]196DEF_HELPER_2(pmon, void, env, int)
197DEF_HELPER_1(wait, void, env)
pbrooka7812ae2008-11-17 14:43:54 +0000[diff] [blame]198
Richard Hendersonbd277fa2012-09-18 21:59:44 -0700[diff] [blame]199/* Loongson multimedia functions. */
Aurelien Jarno95bf7872012-10-09 21:53:09 +0200[diff] [blame]200DEF_HELPER_FLAGS_2(paddsh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
201DEF_HELPER_FLAGS_2(paddush, TCG_CALL_NO_RWG_SE, i64, i64, i64)
202DEF_HELPER_FLAGS_2(paddh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
203DEF_HELPER_FLAGS_2(paddw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
204DEF_HELPER_FLAGS_2(paddsb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
205DEF_HELPER_FLAGS_2(paddusb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
206DEF_HELPER_FLAGS_2(paddb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
Richard Hendersonbd277fa2012-09-18 21:59:44 -0700[diff] [blame]207
Aurelien Jarno95bf7872012-10-09 21:53:09 +0200[diff] [blame]208DEF_HELPER_FLAGS_2(psubsh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
209DEF_HELPER_FLAGS_2(psubush, TCG_CALL_NO_RWG_SE, i64, i64, i64)
210DEF_HELPER_FLAGS_2(psubh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
211DEF_HELPER_FLAGS_2(psubw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
212DEF_HELPER_FLAGS_2(psubsb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
213DEF_HELPER_FLAGS_2(psubusb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
214DEF_HELPER_FLAGS_2(psubb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
Richard Hendersonbd277fa2012-09-18 21:59:44 -0700[diff] [blame]215
Aurelien Jarno95bf7872012-10-09 21:53:09 +0200[diff] [blame]216DEF_HELPER_FLAGS_2(pshufh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
217DEF_HELPER_FLAGS_2(packsswh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
218DEF_HELPER_FLAGS_2(packsshb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
219DEF_HELPER_FLAGS_2(packushb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
Richard Hendersonbd277fa2012-09-18 21:59:44 -0700[diff] [blame]220
Aurelien Jarno95bf7872012-10-09 21:53:09 +0200[diff] [blame]221DEF_HELPER_FLAGS_2(punpcklhw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
222DEF_HELPER_FLAGS_2(punpckhhw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
223DEF_HELPER_FLAGS_2(punpcklbh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
224DEF_HELPER_FLAGS_2(punpckhbh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
225DEF_HELPER_FLAGS_2(punpcklwd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
226DEF_HELPER_FLAGS_2(punpckhwd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
Richard Hendersonbd277fa2012-09-18 21:59:44 -0700[diff] [blame]227
Aurelien Jarno95bf7872012-10-09 21:53:09 +0200[diff] [blame]228DEF_HELPER_FLAGS_2(pavgh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
229DEF_HELPER_FLAGS_2(pavgb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
230DEF_HELPER_FLAGS_2(pmaxsh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
231DEF_HELPER_FLAGS_2(pminsh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
232DEF_HELPER_FLAGS_2(pmaxub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
233DEF_HELPER_FLAGS_2(pminub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
Richard Hendersonbd277fa2012-09-18 21:59:44 -0700[diff] [blame]234
Aurelien Jarno95bf7872012-10-09 21:53:09 +0200[diff] [blame]235DEF_HELPER_FLAGS_2(pcmpeqw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
236DEF_HELPER_FLAGS_2(pcmpgtw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
237DEF_HELPER_FLAGS_2(pcmpeqh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
238DEF_HELPER_FLAGS_2(pcmpgth, TCG_CALL_NO_RWG_SE, i64, i64, i64)
239DEF_HELPER_FLAGS_2(pcmpeqb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
240DEF_HELPER_FLAGS_2(pcmpgtb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
Richard Hendersonbd277fa2012-09-18 21:59:44 -0700[diff] [blame]241
Aurelien Jarno95bf7872012-10-09 21:53:09 +0200[diff] [blame]242DEF_HELPER_FLAGS_2(psllw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
243DEF_HELPER_FLAGS_2(psllh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
244DEF_HELPER_FLAGS_2(psrlw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
245DEF_HELPER_FLAGS_2(psrlh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
246DEF_HELPER_FLAGS_2(psraw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
247DEF_HELPER_FLAGS_2(psrah, TCG_CALL_NO_RWG_SE, i64, i64, i64)
Richard Hendersonbd277fa2012-09-18 21:59:44 -0700[diff] [blame]248
Aurelien Jarno95bf7872012-10-09 21:53:09 +0200[diff] [blame]249DEF_HELPER_FLAGS_2(pmullh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
250DEF_HELPER_FLAGS_2(pmulhh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
251DEF_HELPER_FLAGS_2(pmulhuh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
252DEF_HELPER_FLAGS_2(pmaddhw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
Richard Hendersonbd277fa2012-09-18 21:59:44 -0700[diff] [blame]253
Aurelien Jarno95bf7872012-10-09 21:53:09 +0200[diff] [blame]254DEF_HELPER_FLAGS_2(pasubub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
255DEF_HELPER_FLAGS_1(biadd, TCG_CALL_NO_RWG_SE, i64, i64)
256DEF_HELPER_FLAGS_1(pmovmskb, TCG_CALL_NO_RWG_SE, i64, i64)
Richard Hendersonbd277fa2012-09-18 21:59:44 -0700[diff] [blame]257
Jia Liu461c08d2012-10-24 22:17:06 +0800[diff] [blame]258/*** MIPS DSP ***/
259/* DSP Arithmetic Sub-class insns */
260DEF_HELPER_FLAGS_3(addq_ph, 0, tl, tl, tl, env)
261DEF_HELPER_FLAGS_3(addq_s_ph, 0, tl, tl, tl, env)
262#if defined(TARGET_MIPS64)
263DEF_HELPER_FLAGS_3(addq_qh, 0, tl, tl, tl, env)
264DEF_HELPER_FLAGS_3(addq_s_qh, 0, tl, tl, tl, env)
265#endif
266DEF_HELPER_FLAGS_3(addq_s_w, 0, tl, tl, tl, env)
267#if defined(TARGET_MIPS64)
268DEF_HELPER_FLAGS_3(addq_pw, 0, tl, tl, tl, env)
269DEF_HELPER_FLAGS_3(addq_s_pw, 0, tl, tl, tl, env)
270#endif
271DEF_HELPER_FLAGS_3(addu_qb, 0, tl, tl, tl, env)
272DEF_HELPER_FLAGS_3(addu_s_qb, 0, tl, tl, tl, env)
273DEF_HELPER_FLAGS_2(adduh_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
274DEF_HELPER_FLAGS_2(adduh_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
275DEF_HELPER_FLAGS_3(addu_ph, 0, tl, tl, tl, env)
276DEF_HELPER_FLAGS_3(addu_s_ph, 0, tl, tl, tl, env)
277DEF_HELPER_FLAGS_2(addqh_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
278DEF_HELPER_FLAGS_2(addqh_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
279DEF_HELPER_FLAGS_2(addqh_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
280DEF_HELPER_FLAGS_2(addqh_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
281#if defined(TARGET_MIPS64)
282DEF_HELPER_FLAGS_3(addu_ob, 0, tl, tl, tl, env)
283DEF_HELPER_FLAGS_3(addu_s_ob, 0, tl, tl, tl, env)
284DEF_HELPER_FLAGS_2(adduh_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
285DEF_HELPER_FLAGS_2(adduh_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
286DEF_HELPER_FLAGS_3(addu_qh, 0, tl, tl, tl, env)
287DEF_HELPER_FLAGS_3(addu_s_qh, 0, tl, tl, tl, env)
288#endif
289DEF_HELPER_FLAGS_3(subq_ph, 0, tl, tl, tl, env)
290DEF_HELPER_FLAGS_3(subq_s_ph, 0, tl, tl, tl, env)
291#if defined(TARGET_MIPS64)
292DEF_HELPER_FLAGS_3(subq_qh, 0, tl, tl, tl, env)
293DEF_HELPER_FLAGS_3(subq_s_qh, 0, tl, tl, tl, env)
294#endif
295DEF_HELPER_FLAGS_3(subq_s_w, 0, tl, tl, tl, env)
296#if defined(TARGET_MIPS64)
297DEF_HELPER_FLAGS_3(subq_pw, 0, tl, tl, tl, env)
298DEF_HELPER_FLAGS_3(subq_s_pw, 0, tl, tl, tl, env)
299#endif
300DEF_HELPER_FLAGS_3(subu_qb, 0, tl, tl, tl, env)
301DEF_HELPER_FLAGS_3(subu_s_qb, 0, tl, tl, tl, env)
302DEF_HELPER_FLAGS_2(subuh_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
303DEF_HELPER_FLAGS_2(subuh_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
304DEF_HELPER_FLAGS_3(subu_ph, 0, tl, tl, tl, env)
305DEF_HELPER_FLAGS_3(subu_s_ph, 0, tl, tl, tl, env)
306DEF_HELPER_FLAGS_2(subqh_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
307DEF_HELPER_FLAGS_2(subqh_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
308DEF_HELPER_FLAGS_2(subqh_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
309DEF_HELPER_FLAGS_2(subqh_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
310#if defined(TARGET_MIPS64)
311DEF_HELPER_FLAGS_3(subu_ob, 0, tl, tl, tl, env)
312DEF_HELPER_FLAGS_3(subu_s_ob, 0, tl, tl, tl, env)
313DEF_HELPER_FLAGS_2(subuh_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
314DEF_HELPER_FLAGS_2(subuh_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
315DEF_HELPER_FLAGS_3(subu_qh, 0, tl, tl, tl, env)
316DEF_HELPER_FLAGS_3(subu_s_qh, 0, tl, tl, tl, env)
317#endif
318DEF_HELPER_FLAGS_3(addsc, 0, tl, tl, tl, env)
319DEF_HELPER_FLAGS_3(addwc, 0, tl, tl, tl, env)
320DEF_HELPER_FLAGS_2(modsub, TCG_CALL_NO_RWG_SE, tl, tl, tl)
321DEF_HELPER_FLAGS_1(raddu_w_qb, TCG_CALL_NO_RWG_SE, tl, tl)
322#if defined(TARGET_MIPS64)
323DEF_HELPER_FLAGS_1(raddu_l_ob, TCG_CALL_NO_RWG_SE, tl, tl)
324#endif
325DEF_HELPER_FLAGS_2(absq_s_qb, 0, tl, tl, env)
326DEF_HELPER_FLAGS_2(absq_s_ph, 0, tl, tl, env)
327DEF_HELPER_FLAGS_2(absq_s_w, 0, tl, tl, env)
328#if defined(TARGET_MIPS64)
329DEF_HELPER_FLAGS_2(absq_s_ob, 0, tl, tl, env)
330DEF_HELPER_FLAGS_2(absq_s_qh, 0, tl, tl, env)
331DEF_HELPER_FLAGS_2(absq_s_pw, 0, tl, tl, env)
332#endif
333DEF_HELPER_FLAGS_2(precr_qb_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
334DEF_HELPER_FLAGS_2(precrq_qb_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
335DEF_HELPER_FLAGS_3(precr_sra_ph_w, TCG_CALL_NO_RWG_SE,
336 tl, i32, tl, tl)
337DEF_HELPER_FLAGS_3(precr_sra_r_ph_w, TCG_CALL_NO_RWG_SE,
338 tl, i32, tl, tl)
339DEF_HELPER_FLAGS_2(precrq_ph_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
340DEF_HELPER_FLAGS_3(precrq_rs_ph_w, 0, tl, tl, tl, env)
341#if defined(TARGET_MIPS64)
342DEF_HELPER_FLAGS_2(precr_ob_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
343DEF_HELPER_FLAGS_3(precr_sra_qh_pw,
344 TCG_CALL_NO_RWG_SE, tl, tl, tl, i32)
345DEF_HELPER_FLAGS_3(precr_sra_r_qh_pw,
346 TCG_CALL_NO_RWG_SE, tl, tl, tl, i32)
347DEF_HELPER_FLAGS_2(precrq_ob_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
348DEF_HELPER_FLAGS_2(precrq_qh_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
349DEF_HELPER_FLAGS_3(precrq_rs_qh_pw,
350 TCG_CALL_NO_RWG_SE, tl, tl, tl, env)
351DEF_HELPER_FLAGS_2(precrq_pw_l, TCG_CALL_NO_RWG_SE, tl, tl, tl)
352#endif
353DEF_HELPER_FLAGS_3(precrqu_s_qb_ph, 0, tl, tl, tl, env)
354#if defined(TARGET_MIPS64)
355DEF_HELPER_FLAGS_3(precrqu_s_ob_qh,
356 TCG_CALL_NO_RWG_SE, tl, tl, tl, env)
357
358DEF_HELPER_FLAGS_1(preceq_pw_qhl, TCG_CALL_NO_RWG_SE, tl, tl)
359DEF_HELPER_FLAGS_1(preceq_pw_qhr, TCG_CALL_NO_RWG_SE, tl, tl)
360DEF_HELPER_FLAGS_1(preceq_pw_qhla, TCG_CALL_NO_RWG_SE, tl, tl)
361DEF_HELPER_FLAGS_1(preceq_pw_qhra, TCG_CALL_NO_RWG_SE, tl, tl)
362#endif
363DEF_HELPER_FLAGS_1(precequ_ph_qbl, TCG_CALL_NO_RWG_SE, tl, tl)
364DEF_HELPER_FLAGS_1(precequ_ph_qbr, TCG_CALL_NO_RWG_SE, tl, tl)
365DEF_HELPER_FLAGS_1(precequ_ph_qbla, TCG_CALL_NO_RWG_SE, tl, tl)
366DEF_HELPER_FLAGS_1(precequ_ph_qbra, TCG_CALL_NO_RWG_SE, tl, tl)
367#if defined(TARGET_MIPS64)
368DEF_HELPER_FLAGS_1(precequ_qh_obl, TCG_CALL_NO_RWG_SE, tl, tl)
369DEF_HELPER_FLAGS_1(precequ_qh_obr, TCG_CALL_NO_RWG_SE, tl, tl)
370DEF_HELPER_FLAGS_1(precequ_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl)
371DEF_HELPER_FLAGS_1(precequ_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl)
372#endif
373DEF_HELPER_FLAGS_1(preceu_ph_qbl, TCG_CALL_NO_RWG_SE, tl, tl)
374DEF_HELPER_FLAGS_1(preceu_ph_qbr, TCG_CALL_NO_RWG_SE, tl, tl)
375DEF_HELPER_FLAGS_1(preceu_ph_qbla, TCG_CALL_NO_RWG_SE, tl, tl)
376DEF_HELPER_FLAGS_1(preceu_ph_qbra, TCG_CALL_NO_RWG_SE, tl, tl)
377#if defined(TARGET_MIPS64)
378DEF_HELPER_FLAGS_1(preceu_qh_obl, TCG_CALL_NO_RWG_SE, tl, tl)
379DEF_HELPER_FLAGS_1(preceu_qh_obr, TCG_CALL_NO_RWG_SE, tl, tl)
380DEF_HELPER_FLAGS_1(preceu_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl)
381DEF_HELPER_FLAGS_1(preceu_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl)
382#endif
383
Jia Liu77c5fa82012-10-24 22:17:07 +0800[diff] [blame]384/* DSP GPR-Based Shift Sub-class insns */
385DEF_HELPER_FLAGS_3(shll_qb, 0, tl, tl, tl, env)
386#if defined(TARGET_MIPS64)
387DEF_HELPER_FLAGS_3(shll_ob, 0, tl, tl, tl, env)
388#endif
389DEF_HELPER_FLAGS_3(shll_ph, 0, tl, tl, tl, env)
390DEF_HELPER_FLAGS_3(shll_s_ph, 0, tl, tl, tl, env)
391#if defined(TARGET_MIPS64)
392DEF_HELPER_FLAGS_3(shll_qh, 0, tl, tl, tl, env)
393DEF_HELPER_FLAGS_3(shll_s_qh, 0, tl, tl, tl, env)
394#endif
395DEF_HELPER_FLAGS_3(shll_s_w, 0, tl, tl, tl, env)
396#if defined(TARGET_MIPS64)
397DEF_HELPER_FLAGS_3(shll_pw, 0, tl, tl, tl, env)
398DEF_HELPER_FLAGS_3(shll_s_pw, 0, tl, tl, tl, env)
399#endif
400DEF_HELPER_FLAGS_2(shrl_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
401DEF_HELPER_FLAGS_2(shrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
402#if defined(TARGET_MIPS64)
403DEF_HELPER_FLAGS_2(shrl_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
404DEF_HELPER_FLAGS_2(shrl_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
405#endif
406DEF_HELPER_FLAGS_2(shra_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
407DEF_HELPER_FLAGS_2(shra_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
408#if defined(TARGET_MIPS64)
409DEF_HELPER_FLAGS_2(shra_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
410DEF_HELPER_FLAGS_2(shra_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
411#endif
412DEF_HELPER_FLAGS_2(shra_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
413DEF_HELPER_FLAGS_2(shra_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
414DEF_HELPER_FLAGS_2(shra_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
415#if defined(TARGET_MIPS64)
416DEF_HELPER_FLAGS_2(shra_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
417DEF_HELPER_FLAGS_2(shra_r_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
418DEF_HELPER_FLAGS_2(shra_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
419DEF_HELPER_FLAGS_2(shra_r_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
420#endif
421
Jia Liua22260a2012-10-24 22:17:08 +0800[diff] [blame]422/* DSP Multiply Sub-class insns */
423DEF_HELPER_FLAGS_3(muleu_s_ph_qbl, 0, tl, tl, tl, env)
424DEF_HELPER_FLAGS_3(muleu_s_ph_qbr, 0, tl, tl, tl, env)
425#if defined(TARGET_MIPS64)
426DEF_HELPER_FLAGS_3(muleu_s_qh_obl, 0, tl, tl, tl, env)
427DEF_HELPER_FLAGS_3(muleu_s_qh_obr, 0, tl, tl, tl, env)
428#endif
429DEF_HELPER_FLAGS_3(mulq_rs_ph, 0, tl, tl, tl, env)
430#if defined(TARGET_MIPS64)
431DEF_HELPER_FLAGS_3(mulq_rs_qh, 0, tl, tl, tl, env)
432#endif
433DEF_HELPER_FLAGS_3(muleq_s_w_phl, 0, tl, tl, tl, env)
434DEF_HELPER_FLAGS_3(muleq_s_w_phr, 0, tl, tl, tl, env)
435#if defined(TARGET_MIPS64)
436DEF_HELPER_FLAGS_3(muleq_s_pw_qhl, 0, tl, tl, tl, env)
437DEF_HELPER_FLAGS_3(muleq_s_pw_qhr, 0, tl, tl, tl, env)
438#endif
439DEF_HELPER_FLAGS_4(dpau_h_qbl, 0, void, i32, tl, tl, env)
440DEF_HELPER_FLAGS_4(dpau_h_qbr, 0, void, i32, tl, tl, env)
441#if defined(TARGET_MIPS64)
442DEF_HELPER_FLAGS_4(dpau_h_obl, 0, void, tl, tl, i32, env)
443DEF_HELPER_FLAGS_4(dpau_h_obr, 0, void, tl, tl, i32, env)
444#endif
445DEF_HELPER_FLAGS_4(dpsu_h_qbl, 0, void, i32, tl, tl, env)
446DEF_HELPER_FLAGS_4(dpsu_h_qbr, 0, void, i32, tl, tl, env)
447#if defined(TARGET_MIPS64)
448DEF_HELPER_FLAGS_4(dpsu_h_obl, 0, void, tl, tl, i32, env)
449DEF_HELPER_FLAGS_4(dpsu_h_obr, 0, void, tl, tl, i32, env)
450#endif
451DEF_HELPER_FLAGS_4(dpa_w_ph, 0, void, i32, tl, tl, env)
452#if defined(TARGET_MIPS64)
453DEF_HELPER_FLAGS_4(dpa_w_qh, 0, void, tl, tl, i32, env)
454#endif
455DEF_HELPER_FLAGS_4(dpax_w_ph, 0, void, i32, tl, tl, env)
456DEF_HELPER_FLAGS_4(dpaq_s_w_ph, 0, void, i32, tl, tl, env)
457#if defined(TARGET_MIPS64)
458DEF_HELPER_FLAGS_4(dpaq_s_w_qh, 0, void, tl, tl, i32, env)
459#endif
460DEF_HELPER_FLAGS_4(dpaqx_s_w_ph, 0, void, i32, tl, tl, env)
461DEF_HELPER_FLAGS_4(dpaqx_sa_w_ph, 0, void, i32, tl, tl, env)
462DEF_HELPER_FLAGS_4(dps_w_ph, 0, void, i32, tl, tl, env)
463#if defined(TARGET_MIPS64)
464DEF_HELPER_FLAGS_4(dps_w_qh, 0, void, tl, tl, i32, env)
465#endif
466DEF_HELPER_FLAGS_4(dpsx_w_ph, 0, void, i32, tl, tl, env)
467DEF_HELPER_FLAGS_4(dpsq_s_w_ph, 0, void, i32, tl, tl, env)
468#if defined(TARGET_MIPS64)
469DEF_HELPER_FLAGS_4(dpsq_s_w_qh, 0, void, tl, tl, i32, env)
470#endif
471DEF_HELPER_FLAGS_4(dpsqx_s_w_ph, 0, void, i32, tl, tl, env)
472DEF_HELPER_FLAGS_4(dpsqx_sa_w_ph, 0, void, i32, tl, tl, env)
473DEF_HELPER_FLAGS_4(mulsaq_s_w_ph, 0, void, i32, tl, tl, env)
474#if defined(TARGET_MIPS64)
475DEF_HELPER_FLAGS_4(mulsaq_s_w_qh, 0, void, tl, tl, i32, env)
476#endif
477DEF_HELPER_FLAGS_4(dpaq_sa_l_w, 0, void, i32, tl, tl, env)
478#if defined(TARGET_MIPS64)
479DEF_HELPER_FLAGS_4(dpaq_sa_l_pw, 0, void, tl, tl, i32, env)
480#endif
481DEF_HELPER_FLAGS_4(dpsq_sa_l_w, 0, void, i32, tl, tl, env)
482#if defined(TARGET_MIPS64)
483DEF_HELPER_FLAGS_4(dpsq_sa_l_pw, 0, void, tl, tl, i32, env)
484DEF_HELPER_FLAGS_4(mulsaq_s_l_pw, 0, void, tl, tl, i32, env)
485#endif
486DEF_HELPER_FLAGS_4(maq_s_w_phl, 0, void, i32, tl, tl, env)
487DEF_HELPER_FLAGS_4(maq_s_w_phr, 0, void, i32, tl, tl, env)
488DEF_HELPER_FLAGS_4(maq_sa_w_phl, 0, void, i32, tl, tl, env)
489DEF_HELPER_FLAGS_4(maq_sa_w_phr, 0, void, i32, tl, tl, env)
490DEF_HELPER_FLAGS_3(mul_ph, 0, tl, tl, tl, env)
491DEF_HELPER_FLAGS_3(mul_s_ph, 0, tl, tl, tl, env)
492DEF_HELPER_FLAGS_3(mulq_s_ph, 0, tl, tl, tl, env)
493DEF_HELPER_FLAGS_3(mulq_s_w, 0, tl, tl, tl, env)
494DEF_HELPER_FLAGS_3(mulq_rs_w, 0, tl, tl, tl, env)
495DEF_HELPER_FLAGS_4(mulsa_w_ph, 0, void, i32, tl, tl, env)
496#if defined(TARGET_MIPS64)
497DEF_HELPER_FLAGS_4(maq_s_w_qhll, 0, void, tl, tl, i32, env)
498DEF_HELPER_FLAGS_4(maq_s_w_qhlr, 0, void, tl, tl, i32, env)
499DEF_HELPER_FLAGS_4(maq_s_w_qhrl, 0, void, tl, tl, i32, env)
500DEF_HELPER_FLAGS_4(maq_s_w_qhrr, 0, void, tl, tl, i32, env)
501DEF_HELPER_FLAGS_4(maq_sa_w_qhll, 0, void, tl, tl, i32, env)
502DEF_HELPER_FLAGS_4(maq_sa_w_qhlr, 0, void, tl, tl, i32, env)
503DEF_HELPER_FLAGS_4(maq_sa_w_qhrl, 0, void, tl, tl, i32, env)
504DEF_HELPER_FLAGS_4(maq_sa_w_qhrr, 0, void, tl, tl, i32, env)
505DEF_HELPER_FLAGS_4(maq_s_l_pwl, 0, void, tl, tl, i32, env)
506DEF_HELPER_FLAGS_4(maq_s_l_pwr, 0, void, tl, tl, i32, env)
507DEF_HELPER_FLAGS_4(dmadd, 0, void, tl, tl, i32, env)
508DEF_HELPER_FLAGS_4(dmaddu, 0, void, tl, tl, i32, env)
509DEF_HELPER_FLAGS_4(dmsub, 0, void, tl, tl, i32, env)
510DEF_HELPER_FLAGS_4(dmsubu, 0, void, tl, tl, i32, env)
511#endif
512
Jia Liu1cb66862012-10-24 22:17:09 +0800[diff] [blame]513/* DSP Bit/Manipulation Sub-class insns */
514DEF_HELPER_FLAGS_1(bitrev, TCG_CALL_NO_RWG_SE, tl, tl)
515DEF_HELPER_FLAGS_3(insv, 0, tl, env, tl, tl)
516#if defined(TARGET_MIPS64)
Richard Hendersonf5daeec2013-09-14 15:38:30 -0700[diff] [blame]517DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl)
Jia Liu1cb66862012-10-24 22:17:09 +0800[diff] [blame]518#endif
519
Jia Liu26690562012-10-24 22:17:10 +0800[diff] [blame]520/* DSP Compare-Pick Sub-class insns */
521DEF_HELPER_FLAGS_3(cmpu_eq_qb, 0, void, tl, tl, env)
522DEF_HELPER_FLAGS_3(cmpu_lt_qb, 0, void, tl, tl, env)
523DEF_HELPER_FLAGS_3(cmpu_le_qb, 0, void, tl, tl, env)
524DEF_HELPER_FLAGS_2(cmpgu_eq_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
525DEF_HELPER_FLAGS_2(cmpgu_lt_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
526DEF_HELPER_FLAGS_2(cmpgu_le_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
527DEF_HELPER_FLAGS_3(cmp_eq_ph, 0, void, tl, tl, env)
528DEF_HELPER_FLAGS_3(cmp_lt_ph, 0, void, tl, tl, env)
529DEF_HELPER_FLAGS_3(cmp_le_ph, 0, void, tl, tl, env)
530#if defined(TARGET_MIPS64)
531DEF_HELPER_FLAGS_3(cmpu_eq_ob, 0, void, tl, tl, env)
532DEF_HELPER_FLAGS_3(cmpu_lt_ob, 0, void, tl, tl, env)
533DEF_HELPER_FLAGS_3(cmpu_le_ob, 0, void, tl, tl, env)
534DEF_HELPER_FLAGS_3(cmpgdu_eq_ob, 0, tl, tl, tl, env)
535DEF_HELPER_FLAGS_3(cmpgdu_lt_ob, 0, tl, tl, tl, env)
536DEF_HELPER_FLAGS_3(cmpgdu_le_ob, 0, tl, tl, tl, env)
537DEF_HELPER_FLAGS_2(cmpgu_eq_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
538DEF_HELPER_FLAGS_2(cmpgu_lt_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
539DEF_HELPER_FLAGS_2(cmpgu_le_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
540DEF_HELPER_FLAGS_3(cmp_eq_qh, 0, void, tl, tl, env)
541DEF_HELPER_FLAGS_3(cmp_lt_qh, 0, void, tl, tl, env)
542DEF_HELPER_FLAGS_3(cmp_le_qh, 0, void, tl, tl, env)
543DEF_HELPER_FLAGS_3(cmp_eq_pw, 0, void, tl, tl, env)
544DEF_HELPER_FLAGS_3(cmp_lt_pw, 0, void, tl, tl, env)
545DEF_HELPER_FLAGS_3(cmp_le_pw, 0, void, tl, tl, env)
546#endif
547DEF_HELPER_FLAGS_3(pick_qb, 0, tl, tl, tl, env)
548DEF_HELPER_FLAGS_3(pick_ph, 0, tl, tl, tl, env)
549#if defined(TARGET_MIPS64)
550DEF_HELPER_FLAGS_3(pick_ob, 0, tl, tl, tl, env)
551DEF_HELPER_FLAGS_3(pick_qh, 0, tl, tl, tl, env)
552DEF_HELPER_FLAGS_3(pick_pw, 0, tl, tl, tl, env)
553#endif
Jia Liu26690562012-10-24 22:17:10 +0800[diff] [blame]554DEF_HELPER_FLAGS_2(packrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
555#if defined(TARGET_MIPS64)
556DEF_HELPER_FLAGS_2(packrl_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
557#endif
558
Jia Liub53371e2012-10-24 22:17:11 +0800[diff] [blame]559/* DSP Accumulator and DSPControl Access Sub-class insns */
560DEF_HELPER_FLAGS_3(extr_w, 0, tl, tl, tl, env)
561DEF_HELPER_FLAGS_3(extr_r_w, 0, tl, tl, tl, env)
562DEF_HELPER_FLAGS_3(extr_rs_w, 0, tl, tl, tl, env)
563#if defined(TARGET_MIPS64)
564DEF_HELPER_FLAGS_3(dextr_w, 0, tl, tl, tl, env)
565DEF_HELPER_FLAGS_3(dextr_r_w, 0, tl, tl, tl, env)
566DEF_HELPER_FLAGS_3(dextr_rs_w, 0, tl, tl, tl, env)
567DEF_HELPER_FLAGS_3(dextr_l, 0, tl, tl, tl, env)
568DEF_HELPER_FLAGS_3(dextr_r_l, 0, tl, tl, tl, env)
569DEF_HELPER_FLAGS_3(dextr_rs_l, 0, tl, tl, tl, env)
570#endif
571DEF_HELPER_FLAGS_3(extr_s_h, 0, tl, tl, tl, env)
572#if defined(TARGET_MIPS64)
573DEF_HELPER_FLAGS_3(dextr_s_h, 0, tl, tl, tl, env)
574#endif
575DEF_HELPER_FLAGS_3(extp, 0, tl, tl, tl, env)
576DEF_HELPER_FLAGS_3(extpdp, 0, tl, tl, tl, env)
577#if defined(TARGET_MIPS64)
578DEF_HELPER_FLAGS_3(dextp, 0, tl, tl, tl, env)
579DEF_HELPER_FLAGS_3(dextpdp, 0, tl, tl, tl, env)
580#endif
581DEF_HELPER_FLAGS_3(shilo, 0, void, tl, tl, env)
582#if defined(TARGET_MIPS64)
583DEF_HELPER_FLAGS_3(dshilo, 0, void, tl, tl, env)
584#endif
585DEF_HELPER_FLAGS_3(mthlip, 0, void, tl, tl, env)
586#if defined(TARGET_MIPS64)
587DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env)
588#endif
589DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env)
590DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
Yongbok Kim4c789542014-11-01 05:28:43 +0000[diff] [blame]591
Philippe Mathieu-Daudéad520a92021-04-13 11:51:53 +0200[diff] [blame]592#ifndef CONFIG_USER_ONLY
593#include "tcg/sysemu_helper.h.inc"
594#endif /* !CONFIG_USER_ONLY */
595
Philippe Mathieu-Daudéa2b0a272021-04-13 10:47:10 +0200[diff] [blame]596#include "tcg/msa_helper.h.inc"
Philippe Mathieu-Daudé07565cb2020-11-16 16:39:20 +0100[diff] [blame]597
598/* Vendor extensions */
599#include "tcg/vr54xx_helper.h.inc"