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bellard27503322003-11-13 01:46:15 +00001/*
2 * QEMU DMA emulation
bellard85571bc2004-11-07 18:04:02 +00003 *
4 * Copyright (c) 2003-2004 Vassili Karpov (malc)
5 *
bellard27503322003-11-13 01:46:15 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
pbrook87ecb682007-11-17 17:14:51 +000024#include "hw.h"
25#include "isa.h"
bellard27503322003-11-13 01:46:15 +000026
bellard85571bc2004-11-07 18:04:02 +000027/* #define DEBUG_DMA */
bellard7ebb5e42004-06-07 20:51:58 +000028
bellard85571bc2004-11-07 18:04:02 +000029#define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
bellard27503322003-11-13 01:46:15 +000030#ifdef DEBUG_DMA
31#define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__)
32#define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
33#define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
34#else
35#define lwarn(...)
36#define linfo(...)
37#define ldebug(...)
38#endif
39
bellard27503322003-11-13 01:46:15 +000040struct dma_regs {
41 int now[2];
42 uint16_t base[2];
43 uint8_t mode;
44 uint8_t page;
bellardb0bda522004-06-21 16:47:42 +000045 uint8_t pageh;
bellard27503322003-11-13 01:46:15 +000046 uint8_t dack;
47 uint8_t eop;
bellard16f62432004-02-25 23:25:55 +000048 DMA_transfer_handler transfer_handler;
49 void *opaque;
bellard27503322003-11-13 01:46:15 +000050};
51
52#define ADDR 0
53#define COUNT 1
54
55static struct dma_cont {
56 uint8_t status;
57 uint8_t command;
58 uint8_t mask;
59 uint8_t flip_flop;
bellard9eb153f2004-04-06 22:43:01 +000060 int dshift;
bellard27503322003-11-13 01:46:15 +000061 struct dma_regs regs[4];
62} dma_controllers[2];
63
64enum {
bellarde875c402004-11-14 17:30:35 +000065 CMD_MEMORY_TO_MEMORY = 0x01,
66 CMD_FIXED_ADDRESS = 0x02,
67 CMD_BLOCK_CONTROLLER = 0x04,
68 CMD_COMPRESSED_TIME = 0x08,
69 CMD_CYCLIC_PRIORITY = 0x10,
70 CMD_EXTENDED_WRITE = 0x20,
71 CMD_LOW_DREQ = 0x40,
72 CMD_LOW_DACK = 0x80,
73 CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS
74 | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE
75 | CMD_LOW_DREQ | CMD_LOW_DACK
bellard27503322003-11-13 01:46:15 +000076
77};
78
aliguori492c30a2008-10-31 17:25:56 +000079static void DMA_run (void);
80
bellard9eb153f2004-04-06 22:43:01 +000081static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
82
bellard7d977de2004-03-14 21:41:34 +000083static void write_page (void *opaque, uint32_t nport, uint32_t data)
bellard27503322003-11-13 01:46:15 +000084{
bellard9eb153f2004-04-06 22:43:01 +000085 struct dma_cont *d = opaque;
bellard27503322003-11-13 01:46:15 +000086 int ichan;
bellard27503322003-11-13 01:46:15 +000087
bellard9eb153f2004-04-06 22:43:01 +000088 ichan = channels[nport & 7];
bellard27503322003-11-13 01:46:15 +000089 if (-1 == ichan) {
bellard85571bc2004-11-07 18:04:02 +000090 dolog ("invalid channel %#x %#x\n", nport, data);
bellard27503322003-11-13 01:46:15 +000091 return;
92 }
bellard9eb153f2004-04-06 22:43:01 +000093 d->regs[ichan].page = data;
bellard27503322003-11-13 01:46:15 +000094}
95
bellardb0bda522004-06-21 16:47:42 +000096static void write_pageh (void *opaque, uint32_t nport, uint32_t data)
97{
98 struct dma_cont *d = opaque;
99 int ichan;
100
101 ichan = channels[nport & 7];
102 if (-1 == ichan) {
bellard85571bc2004-11-07 18:04:02 +0000103 dolog ("invalid channel %#x %#x\n", nport, data);
bellardb0bda522004-06-21 16:47:42 +0000104 return;
105 }
106 d->regs[ichan].pageh = data;
107}
108
bellard9eb153f2004-04-06 22:43:01 +0000109static uint32_t read_page (void *opaque, uint32_t nport)
110{
111 struct dma_cont *d = opaque;
112 int ichan;
113
114 ichan = channels[nport & 7];
bellard9eb153f2004-04-06 22:43:01 +0000115 if (-1 == ichan) {
bellard85571bc2004-11-07 18:04:02 +0000116 dolog ("invalid channel read %#x\n", nport);
bellard9eb153f2004-04-06 22:43:01 +0000117 return 0;
118 }
119 return d->regs[ichan].page;
120}
121
bellardb0bda522004-06-21 16:47:42 +0000122static uint32_t read_pageh (void *opaque, uint32_t nport)
123{
124 struct dma_cont *d = opaque;
125 int ichan;
126
127 ichan = channels[nport & 7];
128 if (-1 == ichan) {
bellard85571bc2004-11-07 18:04:02 +0000129 dolog ("invalid channel read %#x\n", nport);
bellardb0bda522004-06-21 16:47:42 +0000130 return 0;
131 }
132 return d->regs[ichan].pageh;
133}
134
bellard9eb153f2004-04-06 22:43:01 +0000135static inline void init_chan (struct dma_cont *d, int ichan)
bellard27503322003-11-13 01:46:15 +0000136{
137 struct dma_regs *r;
138
bellard9eb153f2004-04-06 22:43:01 +0000139 r = d->regs + ichan;
bellard85571bc2004-11-07 18:04:02 +0000140 r->now[ADDR] = r->base[ADDR] << d->dshift;
bellard27503322003-11-13 01:46:15 +0000141 r->now[COUNT] = 0;
142}
143
bellard9eb153f2004-04-06 22:43:01 +0000144static inline int getff (struct dma_cont *d)
bellard27503322003-11-13 01:46:15 +0000145{
146 int ff;
147
bellard9eb153f2004-04-06 22:43:01 +0000148 ff = d->flip_flop;
149 d->flip_flop = !ff;
bellard27503322003-11-13 01:46:15 +0000150 return ff;
151}
152
bellard7d977de2004-03-14 21:41:34 +0000153static uint32_t read_chan (void *opaque, uint32_t nport)
bellard27503322003-11-13 01:46:15 +0000154{
bellard9eb153f2004-04-06 22:43:01 +0000155 struct dma_cont *d = opaque;
bellard85571bc2004-11-07 18:04:02 +0000156 int ichan, nreg, iport, ff, val, dir;
bellard27503322003-11-13 01:46:15 +0000157 struct dma_regs *r;
bellard27503322003-11-13 01:46:15 +0000158
bellard9eb153f2004-04-06 22:43:01 +0000159 iport = (nport >> d->dshift) & 0x0f;
160 ichan = iport >> 1;
161 nreg = iport & 1;
162 r = d->regs + ichan;
bellard27503322003-11-13 01:46:15 +0000163
bellard85571bc2004-11-07 18:04:02 +0000164 dir = ((r->mode >> 5) & 1) ? -1 : 1;
bellard9eb153f2004-04-06 22:43:01 +0000165 ff = getff (d);
bellard27503322003-11-13 01:46:15 +0000166 if (nreg)
bellard9eb153f2004-04-06 22:43:01 +0000167 val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
bellard27503322003-11-13 01:46:15 +0000168 else
bellard85571bc2004-11-07 18:04:02 +0000169 val = r->now[ADDR] + r->now[COUNT] * dir;
bellard27503322003-11-13 01:46:15 +0000170
bellard85571bc2004-11-07 18:04:02 +0000171 ldebug ("read_chan %#x -> %d\n", iport, val);
bellard9eb153f2004-04-06 22:43:01 +0000172 return (val >> (d->dshift + (ff << 3))) & 0xff;
bellard27503322003-11-13 01:46:15 +0000173}
174
bellard7d977de2004-03-14 21:41:34 +0000175static void write_chan (void *opaque, uint32_t nport, uint32_t data)
bellard27503322003-11-13 01:46:15 +0000176{
bellard9eb153f2004-04-06 22:43:01 +0000177 struct dma_cont *d = opaque;
178 int iport, ichan, nreg;
bellard27503322003-11-13 01:46:15 +0000179 struct dma_regs *r;
180
bellard9eb153f2004-04-06 22:43:01 +0000181 iport = (nport >> d->dshift) & 0x0f;
182 ichan = iport >> 1;
183 nreg = iport & 1;
184 r = d->regs + ichan;
185 if (getff (d)) {
bellard3504fe12004-01-19 21:11:02 +0000186 r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
bellard9eb153f2004-04-06 22:43:01 +0000187 init_chan (d, ichan);
bellard3504fe12004-01-19 21:11:02 +0000188 } else {
189 r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
bellard27503322003-11-13 01:46:15 +0000190 }
bellard27503322003-11-13 01:46:15 +0000191}
192
bellard7d977de2004-03-14 21:41:34 +0000193static void write_cont (void *opaque, uint32_t nport, uint32_t data)
bellard27503322003-11-13 01:46:15 +0000194{
bellard9eb153f2004-04-06 22:43:01 +0000195 struct dma_cont *d = opaque;
bellard85571bc2004-11-07 18:04:02 +0000196 int iport, ichan = 0;
bellard27503322003-11-13 01:46:15 +0000197
bellard9eb153f2004-04-06 22:43:01 +0000198 iport = (nport >> d->dshift) & 0x0f;
bellard27503322003-11-13 01:46:15 +0000199 switch (iport) {
bellard85571bc2004-11-07 18:04:02 +0000200 case 0x08: /* command */
bellarddf475d12004-04-12 19:07:27 +0000201 if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
bellard85571bc2004-11-07 18:04:02 +0000202 dolog ("command %#x not supported\n", data);
bellarddf475d12004-04-12 19:07:27 +0000203 return;
bellard27503322003-11-13 01:46:15 +0000204 }
205 d->command = data;
206 break;
207
bellard85571bc2004-11-07 18:04:02 +0000208 case 0x09:
bellard27503322003-11-13 01:46:15 +0000209 ichan = data & 3;
210 if (data & 4) {
211 d->status |= 1 << (ichan + 4);
212 }
213 else {
214 d->status &= ~(1 << (ichan + 4));
215 }
216 d->status &= ~(1 << ichan);
aliguori492c30a2008-10-31 17:25:56 +0000217 DMA_run();
bellard27503322003-11-13 01:46:15 +0000218 break;
219
bellard85571bc2004-11-07 18:04:02 +0000220 case 0x0a: /* single mask */
bellard27503322003-11-13 01:46:15 +0000221 if (data & 4)
222 d->mask |= 1 << (data & 3);
223 else
224 d->mask &= ~(1 << (data & 3));
aliguori492c30a2008-10-31 17:25:56 +0000225 DMA_run();
bellard27503322003-11-13 01:46:15 +0000226 break;
227
bellard85571bc2004-11-07 18:04:02 +0000228 case 0x0b: /* mode */
bellard27503322003-11-13 01:46:15 +0000229 {
bellard16d17fd2004-01-05 00:05:50 +0000230 ichan = data & 3;
231#ifdef DEBUG_DMA
bellard85571bc2004-11-07 18:04:02 +0000232 {
233 int op, ai, dir, opmode;
bellarde875c402004-11-14 17:30:35 +0000234 op = (data >> 2) & 3;
235 ai = (data >> 4) & 1;
236 dir = (data >> 5) & 1;
237 opmode = (data >> 6) & 3;
bellard27503322003-11-13 01:46:15 +0000238
bellarde875c402004-11-14 17:30:35 +0000239 linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
240 ichan, op, ai, dir, opmode);
bellard85571bc2004-11-07 18:04:02 +0000241 }
bellard27503322003-11-13 01:46:15 +0000242#endif
bellard27503322003-11-13 01:46:15 +0000243 d->regs[ichan].mode = data;
244 break;
245 }
246
bellard85571bc2004-11-07 18:04:02 +0000247 case 0x0c: /* clear flip flop */
bellard27503322003-11-13 01:46:15 +0000248 d->flip_flop = 0;
249 break;
250
bellard85571bc2004-11-07 18:04:02 +0000251 case 0x0d: /* reset */
bellard27503322003-11-13 01:46:15 +0000252 d->flip_flop = 0;
253 d->mask = ~0;
254 d->status = 0;
255 d->command = 0;
256 break;
257
bellard85571bc2004-11-07 18:04:02 +0000258 case 0x0e: /* clear mask for all channels */
bellard27503322003-11-13 01:46:15 +0000259 d->mask = 0;
aliguori492c30a2008-10-31 17:25:56 +0000260 DMA_run();
bellard27503322003-11-13 01:46:15 +0000261 break;
262
bellard85571bc2004-11-07 18:04:02 +0000263 case 0x0f: /* write mask for all channels */
bellard27503322003-11-13 01:46:15 +0000264 d->mask = data;
aliguori492c30a2008-10-31 17:25:56 +0000265 DMA_run();
bellard27503322003-11-13 01:46:15 +0000266 break;
267
268 default:
bellard85571bc2004-11-07 18:04:02 +0000269 dolog ("unknown iport %#x\n", iport);
bellarddf475d12004-04-12 19:07:27 +0000270 break;
bellard27503322003-11-13 01:46:15 +0000271 }
272
bellard16d17fd2004-01-05 00:05:50 +0000273#ifdef DEBUG_DMA
bellard27503322003-11-13 01:46:15 +0000274 if (0xc != iport) {
bellard85571bc2004-11-07 18:04:02 +0000275 linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
bellard9eb153f2004-04-06 22:43:01 +0000276 nport, ichan, data);
bellard27503322003-11-13 01:46:15 +0000277 }
278#endif
bellard27503322003-11-13 01:46:15 +0000279}
280
bellard9eb153f2004-04-06 22:43:01 +0000281static uint32_t read_cont (void *opaque, uint32_t nport)
282{
283 struct dma_cont *d = opaque;
284 int iport, val;
bellard85571bc2004-11-07 18:04:02 +0000285
bellard9eb153f2004-04-06 22:43:01 +0000286 iport = (nport >> d->dshift) & 0x0f;
287 switch (iport) {
bellard85571bc2004-11-07 18:04:02 +0000288 case 0x08: /* status */
bellard9eb153f2004-04-06 22:43:01 +0000289 val = d->status;
290 d->status &= 0xf0;
291 break;
bellard85571bc2004-11-07 18:04:02 +0000292 case 0x0f: /* mask */
bellard9eb153f2004-04-06 22:43:01 +0000293 val = d->mask;
294 break;
295 default:
296 val = 0;
297 break;
298 }
bellard85571bc2004-11-07 18:04:02 +0000299
300 ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
bellard9eb153f2004-04-06 22:43:01 +0000301 return val;
302}
303
bellard27503322003-11-13 01:46:15 +0000304int DMA_get_channel_mode (int nchan)
305{
306 return dma_controllers[nchan > 3].regs[nchan & 3].mode;
307}
308
309void DMA_hold_DREQ (int nchan)
310{
311 int ncont, ichan;
312
313 ncont = nchan > 3;
314 ichan = nchan & 3;
315 linfo ("held cont=%d chan=%d\n", ncont, ichan);
316 dma_controllers[ncont].status |= 1 << (ichan + 4);
aliguori492c30a2008-10-31 17:25:56 +0000317 DMA_run();
bellard27503322003-11-13 01:46:15 +0000318}
319
320void DMA_release_DREQ (int nchan)
321{
322 int ncont, ichan;
323
324 ncont = nchan > 3;
325 ichan = nchan & 3;
326 linfo ("released cont=%d chan=%d\n", ncont, ichan);
327 dma_controllers[ncont].status &= ~(1 << (ichan + 4));
aliguori492c30a2008-10-31 17:25:56 +0000328 DMA_run();
bellard27503322003-11-13 01:46:15 +0000329}
330
331static void channel_run (int ncont, int ichan)
332{
bellard27503322003-11-13 01:46:15 +0000333 int n;
bellard85571bc2004-11-07 18:04:02 +0000334 struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
335#ifdef DEBUG_DMA
336 int dir, opmode;
337
338 dir = (r->mode >> 5) & 1;
339 opmode = (r->mode >> 6) & 3;
340
341 if (dir) {
342 dolog ("DMA in address decrement mode\n");
343 }
344 if (opmode != 1) {
345 dolog ("DMA not in single mode select %#x\n", opmode);
346 }
347#endif
bellard27503322003-11-13 01:46:15 +0000348
349 r = dma_controllers[ncont].regs + ichan;
bellard85571bc2004-11-07 18:04:02 +0000350 n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
351 r->now[COUNT], (r->base[COUNT] + 1) << ncont);
bellard27503322003-11-13 01:46:15 +0000352 r->now[COUNT] = n;
bellard85571bc2004-11-07 18:04:02 +0000353 ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
bellard27503322003-11-13 01:46:15 +0000354}
355
aliguori492c30a2008-10-31 17:25:56 +0000356static QEMUBH *dma_bh;
357
358static void DMA_run (void)
bellard27503322003-11-13 01:46:15 +0000359{
bellard27503322003-11-13 01:46:15 +0000360 struct dma_cont *d;
361 int icont, ichan;
aliguori492c30a2008-10-31 17:25:56 +0000362 int rearm = 0;
bellard27503322003-11-13 01:46:15 +0000363
bellard27503322003-11-13 01:46:15 +0000364 d = dma_controllers;
365
366 for (icont = 0; icont < 2; icont++, d++) {
367 for (ichan = 0; ichan < 4; ichan++) {
368 int mask;
369
370 mask = 1 << ichan;
371
aliguori492c30a2008-10-31 17:25:56 +0000372 if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {
bellard27503322003-11-13 01:46:15 +0000373 channel_run (icont, ichan);
aliguori492c30a2008-10-31 17:25:56 +0000374 rearm = 1;
375 }
bellard27503322003-11-13 01:46:15 +0000376 }
377 }
aliguori492c30a2008-10-31 17:25:56 +0000378
379 if (rearm)
380 qemu_bh_schedule_idle(dma_bh);
381}
382
383static void DMA_run_bh(void *unused)
384{
385 DMA_run();
bellard27503322003-11-13 01:46:15 +0000386}
387
388void DMA_register_channel (int nchan,
bellard85571bc2004-11-07 18:04:02 +0000389 DMA_transfer_handler transfer_handler,
bellard16f62432004-02-25 23:25:55 +0000390 void *opaque)
bellard27503322003-11-13 01:46:15 +0000391{
392 struct dma_regs *r;
393 int ichan, ncont;
394
395 ncont = nchan > 3;
396 ichan = nchan & 3;
397
398 r = dma_controllers[ncont].regs + ichan;
bellard16f62432004-02-25 23:25:55 +0000399 r->transfer_handler = transfer_handler;
400 r->opaque = opaque;
401}
402
bellard85571bc2004-11-07 18:04:02 +0000403int DMA_read_memory (int nchan, void *buf, int pos, int len)
404{
405 struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
blueswir171db7102007-06-08 16:45:23 +0000406 target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
bellard85571bc2004-11-07 18:04:02 +0000407
408 if (r->mode & 0x20) {
409 int i;
410 uint8_t *p = buf;
411
412 cpu_physical_memory_read (addr - pos - len, buf, len);
413 /* What about 16bit transfers? */
414 for (i = 0; i < len >> 1; i++) {
415 uint8_t b = p[len - i - 1];
416 p[i] = b;
417 }
418 }
419 else
420 cpu_physical_memory_read (addr + pos, buf, len);
421
422 return len;
423}
424
425int DMA_write_memory (int nchan, void *buf, int pos, int len)
426{
427 struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
blueswir171db7102007-06-08 16:45:23 +0000428 target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
bellard85571bc2004-11-07 18:04:02 +0000429
430 if (r->mode & 0x20) {
431 int i;
432 uint8_t *p = buf;
433
434 cpu_physical_memory_write (addr - pos - len, buf, len);
435 /* What about 16bit transfers? */
436 for (i = 0; i < len; i++) {
437 uint8_t b = p[len - i - 1];
438 p[i] = b;
439 }
440 }
441 else
442 cpu_physical_memory_write (addr + pos, buf, len);
443
444 return len;
445}
446
bellard16f62432004-02-25 23:25:55 +0000447/* request the emulator to transfer a new DMA memory block ASAP */
448void DMA_schedule(int nchan)
449{
bellardc68ea702005-11-21 23:33:12 +0000450 CPUState *env = cpu_single_env;
451 if (env)
aurel323098dba2009-03-07 21:28:24 +0000452 cpu_exit(env);
bellard27503322003-11-13 01:46:15 +0000453}
454
bellardd7d02e32004-06-20 12:58:36 +0000455static void dma_reset(void *opaque)
456{
457 struct dma_cont *d = opaque;
458 write_cont (d, (0x0d << d->dshift), 0);
459}
460
balrogca9cc282008-01-14 04:24:29 +0000461static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)
462{
463 dolog ("unregistered DMA channel used nchan=%d dma_pos=%d dma_len=%d\n",
464 nchan, dma_pos, dma_len);
465 return dma_pos;
466}
467
bellard9eb153f2004-04-06 22:43:01 +0000468/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
bellard85571bc2004-11-07 18:04:02 +0000469static void dma_init2(struct dma_cont *d, int base, int dshift,
bellardb0bda522004-06-21 16:47:42 +0000470 int page_base, int pageh_base)
bellard9eb153f2004-04-06 22:43:01 +0000471{
pbrookd70040b2008-07-05 17:03:54 +0000472 static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
bellard9eb153f2004-04-06 22:43:01 +0000473 int i;
474
475 d->dshift = dshift;
476 for (i = 0; i < 8; i++) {
477 register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
478 register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
479 }
malcb1503cd2008-12-22 20:33:55 +0000480 for (i = 0; i < ARRAY_SIZE (page_port_list); i++) {
bellard85571bc2004-11-07 18:04:02 +0000481 register_ioport_write (page_base + page_port_list[i], 1, 1,
bellard9eb153f2004-04-06 22:43:01 +0000482 write_page, d);
bellard85571bc2004-11-07 18:04:02 +0000483 register_ioport_read (page_base + page_port_list[i], 1, 1,
bellard9eb153f2004-04-06 22:43:01 +0000484 read_page, d);
bellardb0bda522004-06-21 16:47:42 +0000485 if (pageh_base >= 0) {
bellard85571bc2004-11-07 18:04:02 +0000486 register_ioport_write (pageh_base + page_port_list[i], 1, 1,
bellardb0bda522004-06-21 16:47:42 +0000487 write_pageh, d);
bellard85571bc2004-11-07 18:04:02 +0000488 register_ioport_read (pageh_base + page_port_list[i], 1, 1,
bellardb0bda522004-06-21 16:47:42 +0000489 read_pageh, d);
490 }
bellard9eb153f2004-04-06 22:43:01 +0000491 }
492 for (i = 0; i < 8; i++) {
bellard85571bc2004-11-07 18:04:02 +0000493 register_ioport_write (base + ((i + 8) << dshift), 1, 1,
bellard9eb153f2004-04-06 22:43:01 +0000494 write_cont, d);
bellard85571bc2004-11-07 18:04:02 +0000495 register_ioport_read (base + ((i + 8) << dshift), 1, 1,
bellard9eb153f2004-04-06 22:43:01 +0000496 read_cont, d);
497 }
bellardd7d02e32004-06-20 12:58:36 +0000498 qemu_register_reset(dma_reset, d);
499 dma_reset(d);
malcb1503cd2008-12-22 20:33:55 +0000500 for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
balrogca9cc282008-01-14 04:24:29 +0000501 d->regs[i].transfer_handler = dma_phony_handler;
502 }
bellard9eb153f2004-04-06 22:43:01 +0000503}
504
bellard85571bc2004-11-07 18:04:02 +0000505static void dma_save (QEMUFile *f, void *opaque)
506{
507 struct dma_cont *d = opaque;
508 int i;
509
510 /* qemu_put_8s (f, &d->status); */
511 qemu_put_8s (f, &d->command);
512 qemu_put_8s (f, &d->mask);
513 qemu_put_8s (f, &d->flip_flop);
thsbee8d682007-12-16 23:41:11 +0000514 qemu_put_be32 (f, d->dshift);
bellard85571bc2004-11-07 18:04:02 +0000515
516 for (i = 0; i < 4; ++i) {
517 struct dma_regs *r = &d->regs[i];
thsbee8d682007-12-16 23:41:11 +0000518 qemu_put_be32 (f, r->now[0]);
519 qemu_put_be32 (f, r->now[1]);
bellard85571bc2004-11-07 18:04:02 +0000520 qemu_put_be16s (f, &r->base[0]);
521 qemu_put_be16s (f, &r->base[1]);
522 qemu_put_8s (f, &r->mode);
523 qemu_put_8s (f, &r->page);
524 qemu_put_8s (f, &r->pageh);
525 qemu_put_8s (f, &r->dack);
526 qemu_put_8s (f, &r->eop);
527 }
528}
529
530static int dma_load (QEMUFile *f, void *opaque, int version_id)
531{
532 struct dma_cont *d = opaque;
533 int i;
534
535 if (version_id != 1)
536 return -EINVAL;
537
538 /* qemu_get_8s (f, &d->status); */
539 qemu_get_8s (f, &d->command);
540 qemu_get_8s (f, &d->mask);
541 qemu_get_8s (f, &d->flip_flop);
thsbee8d682007-12-16 23:41:11 +0000542 d->dshift=qemu_get_be32 (f);
bellard85571bc2004-11-07 18:04:02 +0000543
544 for (i = 0; i < 4; ++i) {
545 struct dma_regs *r = &d->regs[i];
thsbee8d682007-12-16 23:41:11 +0000546 r->now[0]=qemu_get_be32 (f);
547 r->now[1]=qemu_get_be32 (f);
bellard85571bc2004-11-07 18:04:02 +0000548 qemu_get_be16s (f, &r->base[0]);
549 qemu_get_be16s (f, &r->base[1]);
550 qemu_get_8s (f, &r->mode);
551 qemu_get_8s (f, &r->page);
552 qemu_get_8s (f, &r->pageh);
553 qemu_get_8s (f, &r->dack);
554 qemu_get_8s (f, &r->eop);
555 }
aliguori492c30a2008-10-31 17:25:56 +0000556
557 DMA_run();
558
bellard85571bc2004-11-07 18:04:02 +0000559 return 0;
560}
561
bellardb0bda522004-06-21 16:47:42 +0000562void DMA_init (int high_page_enable)
bellard27503322003-11-13 01:46:15 +0000563{
bellard85571bc2004-11-07 18:04:02 +0000564 dma_init2(&dma_controllers[0], 0x00, 0, 0x80,
bellardb0bda522004-06-21 16:47:42 +0000565 high_page_enable ? 0x480 : -1);
566 dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,
567 high_page_enable ? 0x488 : -1);
bellard85571bc2004-11-07 18:04:02 +0000568 register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]);
569 register_savevm ("dma", 1, 1, dma_save, dma_load, &dma_controllers[1]);
aliguori492c30a2008-10-31 17:25:56 +0000570
571 dma_bh = qemu_bh_new(DMA_run_bh, NULL);
bellard27503322003-11-13 01:46:15 +0000572}