Peter Maydell | 0d75590 | 2016-01-26 18:16:58 +0000 | [diff] [blame] | 1 | #include "qemu/osdep.h" |
Markus Armbruster | da34e65 | 2016-03-14 09:01:28 +0100 | [diff] [blame] | 2 | #include "qapi/error.h" |
Vincent Palatin | b394662 | 2017-01-10 11:59:55 +0100 | [diff] [blame] | 3 | #include "sysemu/hw_accel.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 4 | #include "sysemu/sysemu.h" |
Paolo Bonzini | 03dd024 | 2015-12-15 13:16:16 +0100 | [diff] [blame] | 5 | #include "qemu/log.h" |
David Gibson | 9fdf0c2 | 2011-04-01 15:15:20 +1100 | [diff] [blame] | 6 | #include "cpu.h" |
Paolo Bonzini | 63c9155 | 2016-03-15 13:18:37 +0100 | [diff] [blame] | 7 | #include "exec/exec-all.h" |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 8 | #include "helper_regs.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 9 | #include "hw/ppc/spapr.h" |
David Gibson | d5aea6f | 2013-03-12 00:31:18 +0000 | [diff] [blame] | 10 | #include "mmu-hash64.h" |
Alexey Kardashevskiy | 3794d54 | 2014-05-23 12:26:57 +1000 | [diff] [blame] | 11 | #include "cpu-models.h" |
| 12 | #include "trace.h" |
| 13 | #include "kvm_ppc.h" |
Michael Roth | facdb8b | 2016-10-24 23:47:28 -0500 | [diff] [blame] | 14 | #include "hw/ppc/spapr_ovec.h" |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 15 | |
Alexey Kardashevskiy | a46622f | 2014-03-07 15:37:40 +1100 | [diff] [blame] | 16 | struct SPRSyncState { |
Alexey Kardashevskiy | a46622f | 2014-03-07 15:37:40 +1100 | [diff] [blame] | 17 | int spr; |
| 18 | target_ulong value; |
| 19 | target_ulong mask; |
| 20 | }; |
| 21 | |
Paolo Bonzini | 14e6fe1 | 2016-10-31 10:36:08 +0100 | [diff] [blame] | 22 | static void do_spr_sync(CPUState *cs, run_on_cpu_data arg) |
Alexey Kardashevskiy | a46622f | 2014-03-07 15:37:40 +1100 | [diff] [blame] | 23 | { |
Paolo Bonzini | 14e6fe1 | 2016-10-31 10:36:08 +0100 | [diff] [blame] | 24 | struct SPRSyncState *s = arg.host_ptr; |
Alex Bennée | e0eeb4a | 2016-08-02 18:27:33 +0100 | [diff] [blame] | 25 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
Alexey Kardashevskiy | a46622f | 2014-03-07 15:37:40 +1100 | [diff] [blame] | 26 | CPUPPCState *env = &cpu->env; |
| 27 | |
Alex Bennée | e0eeb4a | 2016-08-02 18:27:33 +0100 | [diff] [blame] | 28 | cpu_synchronize_state(cs); |
Alexey Kardashevskiy | a46622f | 2014-03-07 15:37:40 +1100 | [diff] [blame] | 29 | env->spr[s->spr] &= ~s->mask; |
| 30 | env->spr[s->spr] |= s->value; |
| 31 | } |
| 32 | |
| 33 | static void set_spr(CPUState *cs, int spr, target_ulong value, |
| 34 | target_ulong mask) |
| 35 | { |
| 36 | struct SPRSyncState s = { |
Alexey Kardashevskiy | a46622f | 2014-03-07 15:37:40 +1100 | [diff] [blame] | 37 | .spr = spr, |
| 38 | .value = value, |
| 39 | .mask = mask |
| 40 | }; |
Paolo Bonzini | 14e6fe1 | 2016-10-31 10:36:08 +0100 | [diff] [blame] | 41 | run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s)); |
Alexey Kardashevskiy | a46622f | 2014-03-07 15:37:40 +1100 | [diff] [blame] | 42 | } |
| 43 | |
Thomas Huth | af08a58 | 2016-02-11 13:47:19 +0100 | [diff] [blame] | 44 | static bool has_spr(PowerPCCPU *cpu, int spr) |
| 45 | { |
| 46 | /* We can test whether the SPR is defined by checking for a valid name */ |
| 47 | return cpu->env.spr_cb[spr].name != NULL; |
| 48 | } |
| 49 | |
Aneesh Kumar K.V | f3c75d4 | 2014-02-20 18:52:17 +0100 | [diff] [blame] | 50 | static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_index) |
| 51 | { |
| 52 | /* |
| 53 | * hash value/pteg group index is normalized by htab_mask |
| 54 | */ |
| 55 | if (((pte_index & ~7ULL) / HPTES_PER_GROUP) & ~env->htab_mask) { |
| 56 | return false; |
| 57 | } |
| 58 | return true; |
| 59 | } |
| 60 | |
David Gibson | ecbc25f | 2016-01-21 14:48:43 +1100 | [diff] [blame] | 61 | static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) |
| 62 | { |
| 63 | MachineState *machine = MACHINE(spapr); |
| 64 | MemoryHotplugState *hpms = &spapr->hotplug_memory; |
| 65 | |
| 66 | if (addr < machine->ram_size) { |
| 67 | return true; |
| 68 | } |
| 69 | if ((addr >= hpms->base) |
| 70 | && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { |
| 71 | return true; |
| 72 | } |
| 73 | |
| 74 | return false; |
| 75 | } |
| 76 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 77 | static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 78 | target_ulong opcode, target_ulong *args) |
| 79 | { |
Andreas Färber | b13ce26 | 2012-05-03 06:23:01 +0200 | [diff] [blame] | 80 | CPUPPCState *env = &cpu->env; |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 81 | target_ulong flags = args[0]; |
| 82 | target_ulong pte_index = args[1]; |
| 83 | target_ulong pteh = args[2]; |
| 84 | target_ulong ptel = args[3]; |
Cédric Le Goater | 1f0252e | 2016-07-01 09:10:10 +0200 | [diff] [blame] | 85 | unsigned apshift; |
David Gibson | f73a257 | 2011-08-03 21:02:19 +0000 | [diff] [blame] | 86 | target_ulong raddr; |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 87 | target_ulong index; |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 88 | uint64_t token; |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 89 | |
Cédric Le Goater | 1f0252e | 2016-07-01 09:10:10 +0200 | [diff] [blame] | 90 | apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); |
David Gibson | 1114e71 | 2016-01-27 12:01:20 +1100 | [diff] [blame] | 91 | if (!apshift) { |
| 92 | /* Bad page size encoding */ |
| 93 | return H_PARAMETER; |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 94 | } |
| 95 | |
David Gibson | 1114e71 | 2016-01-27 12:01:20 +1100 | [diff] [blame] | 96 | raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 97 | |
David Gibson | ecbc25f | 2016-01-21 14:48:43 +1100 | [diff] [blame] | 98 | if (is_ram_address(spapr, raddr)) { |
David Gibson | f73a257 | 2011-08-03 21:02:19 +0000 | [diff] [blame] | 99 | /* Regular RAM - should have WIMG=0010 */ |
David Gibson | d5aea6f | 2013-03-12 00:31:18 +0000 | [diff] [blame] | 100 | if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { |
David Gibson | f73a257 | 2011-08-03 21:02:19 +0000 | [diff] [blame] | 101 | return H_PARAMETER; |
| 102 | } |
| 103 | } else { |
Aneesh Kumar K.V | c117590 | 2016-06-17 16:07:20 +0530 | [diff] [blame] | 104 | target_ulong wimg_flags; |
David Gibson | f73a257 | 2011-08-03 21:02:19 +0000 | [diff] [blame] | 105 | /* Looks like an IO address */ |
| 106 | /* FIXME: What WIMG combinations could be sensible for IO? |
| 107 | * For now we allow WIMG=010x, but are there others? */ |
| 108 | /* FIXME: Should we check against registered IO addresses? */ |
Aneesh Kumar K.V | c117590 | 2016-06-17 16:07:20 +0530 | [diff] [blame] | 109 | wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); |
| 110 | |
| 111 | if (wimg_flags != HPTE64_R_I && |
| 112 | wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { |
David Gibson | f73a257 | 2011-08-03 21:02:19 +0000 | [diff] [blame] | 113 | return H_PARAMETER; |
| 114 | } |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 115 | } |
David Gibson | f73a257 | 2011-08-03 21:02:19 +0000 | [diff] [blame] | 116 | |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 117 | pteh &= ~0x60ULL; |
| 118 | |
Aneesh Kumar K.V | f3c75d4 | 2014-02-20 18:52:17 +0100 | [diff] [blame] | 119 | if (!valid_pte_index(env, pte_index)) { |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 120 | return H_PARAMETER; |
| 121 | } |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 122 | |
| 123 | index = 0; |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 124 | if (likely((flags & H_EXACT) == 0)) { |
| 125 | pte_index &= ~7ULL; |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 126 | token = ppc_hash64_start_access(cpu, pte_index); |
Aneesh Kumar K.V | 7aaf495 | 2014-03-14 19:21:49 +0530 | [diff] [blame] | 127 | for (; index < 8; index++) { |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 128 | if (!(ppc_hash64_load_hpte0(cpu, token, index) & HPTE64_V_VALID)) { |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 129 | break; |
| 130 | } |
Aneesh Kumar K.V | 7aaf495 | 2014-03-14 19:21:49 +0530 | [diff] [blame] | 131 | } |
David Gibson | c18ad9a | 2016-03-08 11:35:15 +1100 | [diff] [blame] | 132 | ppc_hash64_stop_access(cpu, token); |
Aneesh Kumar K.V | 7aaf495 | 2014-03-14 19:21:49 +0530 | [diff] [blame] | 133 | if (index == 8) { |
| 134 | return H_PTEG_FULL; |
| 135 | } |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 136 | } else { |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 137 | token = ppc_hash64_start_access(cpu, pte_index); |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 138 | if (ppc_hash64_load_hpte0(cpu, token, 0) & HPTE64_V_VALID) { |
David Gibson | c18ad9a | 2016-03-08 11:35:15 +1100 | [diff] [blame] | 139 | ppc_hash64_stop_access(cpu, token); |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 140 | return H_PTEG_FULL; |
| 141 | } |
David Gibson | c18ad9a | 2016-03-08 11:35:15 +1100 | [diff] [blame] | 142 | ppc_hash64_stop_access(cpu, token); |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 143 | } |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 144 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 145 | ppc_hash64_store_hpte(cpu, pte_index + index, |
Aneesh Kumar K.V | 3f94170 | 2014-02-20 18:52:31 +0100 | [diff] [blame] | 146 | pteh | HPTE64_V_HPTE_DIRTY, ptel); |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 147 | |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 148 | args[0] = pte_index + index; |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 149 | return H_SUCCESS; |
| 150 | } |
| 151 | |
Stefan Weil | a380140 | 2013-06-24 19:48:47 +0200 | [diff] [blame] | 152 | typedef enum { |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 153 | REMOVE_SUCCESS = 0, |
| 154 | REMOVE_NOT_FOUND = 1, |
| 155 | REMOVE_PARM = 2, |
| 156 | REMOVE_HW = 3, |
Stefan Weil | a380140 | 2013-06-24 19:48:47 +0200 | [diff] [blame] | 157 | } RemoveResult; |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 158 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 159 | static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 160 | target_ulong avpn, |
| 161 | target_ulong flags, |
| 162 | target_ulong *vp, target_ulong *rp) |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 163 | { |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 164 | CPUPPCState *env = &cpu->env; |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 165 | uint64_t token; |
David Gibson | 61a36c9 | 2016-01-15 16:12:09 +1100 | [diff] [blame] | 166 | target_ulong v, r; |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 167 | |
Aneesh Kumar K.V | f3c75d4 | 2014-02-20 18:52:17 +0100 | [diff] [blame] | 168 | if (!valid_pte_index(env, ptex)) { |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 169 | return REMOVE_PARM; |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 170 | } |
| 171 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 172 | token = ppc_hash64_start_access(cpu, ptex); |
| 173 | v = ppc_hash64_load_hpte0(cpu, token, 0); |
| 174 | r = ppc_hash64_load_hpte1(cpu, token, 0); |
David Gibson | c18ad9a | 2016-03-08 11:35:15 +1100 | [diff] [blame] | 175 | ppc_hash64_stop_access(cpu, token); |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 176 | |
David Gibson | d5aea6f | 2013-03-12 00:31:18 +0000 | [diff] [blame] | 177 | if ((v & HPTE64_V_VALID) == 0 || |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 178 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || |
| 179 | ((flags & H_ANDCOND) && (v & avpn) != 0)) { |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 180 | return REMOVE_NOT_FOUND; |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 181 | } |
David Gibson | 35f9304 | 2012-09-20 17:42:30 +0000 | [diff] [blame] | 182 | *vp = v; |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 183 | *rp = r; |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 184 | ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); |
David Gibson | 61a36c9 | 2016-01-15 16:12:09 +1100 | [diff] [blame] | 185 | ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 186 | return REMOVE_SUCCESS; |
| 187 | } |
| 188 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 189 | static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 190 | target_ulong opcode, target_ulong *args) |
| 191 | { |
Benjamin Herrenschmidt | cd0c6f4 | 2016-05-03 18:03:25 +0200 | [diff] [blame] | 192 | CPUPPCState *env = &cpu->env; |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 193 | target_ulong flags = args[0]; |
| 194 | target_ulong pte_index = args[1]; |
| 195 | target_ulong avpn = args[2]; |
Stefan Weil | a380140 | 2013-06-24 19:48:47 +0200 | [diff] [blame] | 196 | RemoveResult ret; |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 197 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 198 | ret = remove_hpte(cpu, pte_index, avpn, flags, |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 199 | &args[0], &args[1]); |
| 200 | |
| 201 | switch (ret) { |
| 202 | case REMOVE_SUCCESS: |
Nikunj A Dadhania | e3cffe6 | 2016-09-20 22:05:00 +0530 | [diff] [blame] | 203 | check_tlb_flush(env, true); |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 204 | return H_SUCCESS; |
| 205 | |
| 206 | case REMOVE_NOT_FOUND: |
| 207 | return H_NOT_FOUND; |
| 208 | |
| 209 | case REMOVE_PARM: |
| 210 | return H_PARAMETER; |
| 211 | |
| 212 | case REMOVE_HW: |
| 213 | return H_HARDWARE; |
| 214 | } |
| 215 | |
Stefan Weil | 9a39970 | 2013-06-29 15:47:26 +0200 | [diff] [blame] | 216 | g_assert_not_reached(); |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL |
| 220 | #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL |
| 221 | #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL |
| 222 | #define H_BULK_REMOVE_END 0xc000000000000000ULL |
| 223 | #define H_BULK_REMOVE_CODE 0x3000000000000000ULL |
| 224 | #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL |
| 225 | #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL |
| 226 | #define H_BULK_REMOVE_PARM 0x2000000000000000ULL |
| 227 | #define H_BULK_REMOVE_HW 0x3000000000000000ULL |
| 228 | #define H_BULK_REMOVE_RC 0x0c00000000000000ULL |
| 229 | #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL |
| 230 | #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL |
| 231 | #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL |
| 232 | #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL |
| 233 | #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL |
| 234 | |
| 235 | #define H_BULK_REMOVE_MAX_BATCH 4 |
| 236 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 237 | static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 238 | target_ulong opcode, target_ulong *args) |
| 239 | { |
Benjamin Herrenschmidt | cd0c6f4 | 2016-05-03 18:03:25 +0200 | [diff] [blame] | 240 | CPUPPCState *env = &cpu->env; |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 241 | int i; |
Benjamin Herrenschmidt | cd0c6f4 | 2016-05-03 18:03:25 +0200 | [diff] [blame] | 242 | target_ulong rc = H_SUCCESS; |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 243 | |
| 244 | for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { |
| 245 | target_ulong *tsh = &args[i*2]; |
| 246 | target_ulong tsl = args[i*2 + 1]; |
| 247 | target_ulong v, r, ret; |
| 248 | |
| 249 | if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { |
| 250 | break; |
| 251 | } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { |
| 252 | return H_PARAMETER; |
| 253 | } |
| 254 | |
| 255 | *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; |
| 256 | *tsh |= H_BULK_REMOVE_RESPONSE; |
| 257 | |
| 258 | if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { |
| 259 | *tsh |= H_BULK_REMOVE_PARM; |
| 260 | return H_PARAMETER; |
| 261 | } |
| 262 | |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 263 | ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 264 | (*tsh & H_BULK_REMOVE_FLAGS) >> 26, |
| 265 | &v, &r); |
| 266 | |
| 267 | *tsh |= ret << 60; |
| 268 | |
| 269 | switch (ret) { |
| 270 | case REMOVE_SUCCESS: |
David Gibson | d5aea6f | 2013-03-12 00:31:18 +0000 | [diff] [blame] | 271 | *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 272 | break; |
| 273 | |
| 274 | case REMOVE_PARM: |
Benjamin Herrenschmidt | cd0c6f4 | 2016-05-03 18:03:25 +0200 | [diff] [blame] | 275 | rc = H_PARAMETER; |
| 276 | goto exit; |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 277 | |
| 278 | case REMOVE_HW: |
Benjamin Herrenschmidt | cd0c6f4 | 2016-05-03 18:03:25 +0200 | [diff] [blame] | 279 | rc = H_HARDWARE; |
| 280 | goto exit; |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 281 | } |
| 282 | } |
Benjamin Herrenschmidt | cd0c6f4 | 2016-05-03 18:03:25 +0200 | [diff] [blame] | 283 | exit: |
Nikunj A Dadhania | e3cffe6 | 2016-09-20 22:05:00 +0530 | [diff] [blame] | 284 | check_tlb_flush(env, true); |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 285 | |
Benjamin Herrenschmidt | cd0c6f4 | 2016-05-03 18:03:25 +0200 | [diff] [blame] | 286 | return rc; |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 287 | } |
| 288 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 289 | static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 290 | target_ulong opcode, target_ulong *args) |
| 291 | { |
Andreas Färber | b13ce26 | 2012-05-03 06:23:01 +0200 | [diff] [blame] | 292 | CPUPPCState *env = &cpu->env; |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 293 | target_ulong flags = args[0]; |
| 294 | target_ulong pte_index = args[1]; |
| 295 | target_ulong avpn = args[2]; |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 296 | uint64_t token; |
David Gibson | 61a36c9 | 2016-01-15 16:12:09 +1100 | [diff] [blame] | 297 | target_ulong v, r; |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 298 | |
Aneesh Kumar K.V | f3c75d4 | 2014-02-20 18:52:17 +0100 | [diff] [blame] | 299 | if (!valid_pte_index(env, pte_index)) { |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 300 | return H_PARAMETER; |
| 301 | } |
| 302 | |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 303 | token = ppc_hash64_start_access(cpu, pte_index); |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 304 | v = ppc_hash64_load_hpte0(cpu, token, 0); |
| 305 | r = ppc_hash64_load_hpte1(cpu, token, 0); |
David Gibson | c18ad9a | 2016-03-08 11:35:15 +1100 | [diff] [blame] | 306 | ppc_hash64_stop_access(cpu, token); |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 307 | |
David Gibson | d5aea6f | 2013-03-12 00:31:18 +0000 | [diff] [blame] | 308 | if ((v & HPTE64_V_VALID) == 0 || |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 309 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 310 | return H_NOT_FOUND; |
| 311 | } |
| 312 | |
David Gibson | d5aea6f | 2013-03-12 00:31:18 +0000 | [diff] [blame] | 313 | r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | |
| 314 | HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); |
| 315 | r |= (flags << 55) & HPTE64_R_PP0; |
| 316 | r |= (flags << 48) & HPTE64_R_KEY_HI; |
| 317 | r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 318 | ppc_hash64_store_hpte(cpu, pte_index, |
Aneesh Kumar K.V | 3f94170 | 2014-02-20 18:52:31 +0100 | [diff] [blame] | 319 | (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); |
David Gibson | 61a36c9 | 2016-01-15 16:12:09 +1100 | [diff] [blame] | 320 | ppc_hash64_tlb_flush_hpte(cpu, pte_index, v, r); |
Nikunj A Dadhania | d76ab5e | 2016-09-20 22:05:01 +0530 | [diff] [blame] | 321 | /* Flush the tlb */ |
| 322 | check_tlb_flush(env, true); |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 323 | /* Don't need a memory barrier, due to qemu's global lock */ |
David Gibson | 7ef2306 | 2016-01-14 15:33:27 +1100 | [diff] [blame] | 324 | ppc_hash64_store_hpte(cpu, pte_index, v | HPTE64_V_HPTE_DIRTY, r); |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 325 | return H_SUCCESS; |
| 326 | } |
| 327 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 328 | static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
Erlon Cruz | 6bbd5dd | 2013-02-18 05:00:32 +0000 | [diff] [blame] | 329 | target_ulong opcode, target_ulong *args) |
| 330 | { |
| 331 | CPUPPCState *env = &cpu->env; |
| 332 | target_ulong flags = args[0]; |
| 333 | target_ulong pte_index = args[1]; |
| 334 | uint8_t *hpte; |
| 335 | int i, ridx, n_entries = 1; |
| 336 | |
Aneesh Kumar K.V | f3c75d4 | 2014-02-20 18:52:17 +0100 | [diff] [blame] | 337 | if (!valid_pte_index(env, pte_index)) { |
Erlon Cruz | 6bbd5dd | 2013-02-18 05:00:32 +0000 | [diff] [blame] | 338 | return H_PARAMETER; |
| 339 | } |
| 340 | |
| 341 | if (flags & H_READ_4) { |
| 342 | /* Clear the two low order bits */ |
| 343 | pte_index &= ~(3ULL); |
| 344 | n_entries = 4; |
| 345 | } |
| 346 | |
| 347 | hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); |
| 348 | |
| 349 | for (i = 0, ridx = 0; i < n_entries; i++) { |
| 350 | args[ridx++] = ldq_p(hpte); |
| 351 | args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); |
| 352 | hpte += HASH_PTE_SIZE_64; |
| 353 | } |
| 354 | |
| 355 | return H_SUCCESS; |
| 356 | } |
| 357 | |
Thomas Huth | 423576f | 2016-02-11 13:47:18 +0100 | [diff] [blame] | 358 | static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
| 359 | target_ulong opcode, target_ulong *args) |
| 360 | { |
| 361 | cpu_synchronize_state(CPU(cpu)); |
| 362 | cpu->env.spr[SPR_SPRG0] = args[0]; |
| 363 | |
| 364 | return H_SUCCESS; |
| 365 | } |
| 366 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 367 | static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
David Gibson | 821303f | 2011-04-01 15:15:24 +1100 | [diff] [blame] | 368 | target_ulong opcode, target_ulong *args) |
| 369 | { |
Thomas Huth | af08a58 | 2016-02-11 13:47:19 +0100 | [diff] [blame] | 370 | if (!has_spr(cpu, SPR_DABR)) { |
| 371 | return H_HARDWARE; /* DABR register not available */ |
| 372 | } |
| 373 | cpu_synchronize_state(CPU(cpu)); |
| 374 | |
| 375 | if (has_spr(cpu, SPR_DABRX)) { |
| 376 | cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ |
| 377 | } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ |
| 378 | return H_RESERVED_DABR; |
| 379 | } |
| 380 | |
| 381 | cpu->env.spr[SPR_DABR] = args[0]; |
| 382 | return H_SUCCESS; |
David Gibson | 821303f | 2011-04-01 15:15:24 +1100 | [diff] [blame] | 383 | } |
| 384 | |
Thomas Huth | e49ff26 | 2016-02-11 13:47:20 +0100 | [diff] [blame] | 385 | static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
| 386 | target_ulong opcode, target_ulong *args) |
| 387 | { |
| 388 | target_ulong dabrx = args[1]; |
| 389 | |
| 390 | if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { |
| 391 | return H_HARDWARE; |
| 392 | } |
| 393 | |
| 394 | if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 |
| 395 | || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { |
| 396 | return H_PARAMETER; |
| 397 | } |
| 398 | |
| 399 | cpu_synchronize_state(CPU(cpu)); |
| 400 | cpu->env.spr[SPR_DABRX] = dabrx; |
| 401 | cpu->env.spr[SPR_DABR] = args[0]; |
| 402 | |
| 403 | return H_SUCCESS; |
| 404 | } |
| 405 | |
Thomas Huth | 3240dd9 | 2016-02-18 10:15:54 +0100 | [diff] [blame] | 406 | static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
| 407 | target_ulong opcode, target_ulong *args) |
| 408 | { |
| 409 | target_ulong flags = args[0]; |
| 410 | hwaddr dst = args[1]; |
| 411 | hwaddr src = args[2]; |
| 412 | hwaddr len = TARGET_PAGE_SIZE; |
| 413 | uint8_t *pdst, *psrc; |
| 414 | target_long ret = H_SUCCESS; |
| 415 | |
| 416 | if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE |
| 417 | | H_COPY_PAGE | H_ZERO_PAGE)) { |
| 418 | qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", |
| 419 | flags); |
| 420 | return H_PARAMETER; |
| 421 | } |
| 422 | |
| 423 | /* Map-in destination */ |
| 424 | if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { |
| 425 | return H_PARAMETER; |
| 426 | } |
| 427 | pdst = cpu_physical_memory_map(dst, &len, 1); |
| 428 | if (!pdst || len != TARGET_PAGE_SIZE) { |
| 429 | return H_PARAMETER; |
| 430 | } |
| 431 | |
| 432 | if (flags & H_COPY_PAGE) { |
| 433 | /* Map-in source, copy to destination, and unmap source again */ |
| 434 | if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { |
| 435 | ret = H_PARAMETER; |
| 436 | goto unmap_out; |
| 437 | } |
| 438 | psrc = cpu_physical_memory_map(src, &len, 0); |
| 439 | if (!psrc || len != TARGET_PAGE_SIZE) { |
| 440 | ret = H_PARAMETER; |
| 441 | goto unmap_out; |
| 442 | } |
| 443 | memcpy(pdst, psrc, len); |
| 444 | cpu_physical_memory_unmap(psrc, len, 0, len); |
| 445 | } else if (flags & H_ZERO_PAGE) { |
| 446 | memset(pdst, 0, len); /* Just clear the destination page */ |
| 447 | } |
| 448 | |
| 449 | if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { |
| 450 | kvmppc_dcbst_range(cpu, pdst, len); |
| 451 | } |
| 452 | if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { |
| 453 | if (kvm_enabled()) { |
| 454 | kvmppc_icbi_range(cpu, pdst, len); |
| 455 | } else { |
| 456 | tb_flush(CPU(cpu)); |
| 457 | } |
| 458 | } |
| 459 | |
| 460 | unmap_out: |
| 461 | cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); |
| 462 | return ret; |
| 463 | } |
| 464 | |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 465 | #define FLAGS_REGISTER_VPA 0x0000200000000000ULL |
| 466 | #define FLAGS_REGISTER_DTL 0x0000400000000000ULL |
| 467 | #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL |
| 468 | #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL |
| 469 | #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL |
| 470 | #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL |
| 471 | |
| 472 | #define VPA_MIN_SIZE 640 |
| 473 | #define VPA_SIZE_OFFSET 0x4 |
| 474 | #define VPA_SHARED_PROC_OFFSET 0x9 |
| 475 | #define VPA_SHARED_PROC_VAL 0x2 |
| 476 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 477 | static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 478 | { |
Andreas Färber | 33276f1 | 2014-03-09 19:29:41 +0100 | [diff] [blame] | 479 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 480 | uint16_t size; |
| 481 | uint8_t tmp; |
| 482 | |
| 483 | if (vpa == 0) { |
| 484 | hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); |
| 485 | return H_HARDWARE; |
| 486 | } |
| 487 | |
| 488 | if (vpa % env->dcache_line_size) { |
| 489 | return H_PARAMETER; |
| 490 | } |
| 491 | /* FIXME: bounds check the address */ |
| 492 | |
Edgar E. Iglesias | 41701aa | 2013-12-17 14:33:56 +1000 | [diff] [blame] | 493 | size = lduw_be_phys(cs->as, vpa + 0x4); |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 494 | |
| 495 | if (size < VPA_MIN_SIZE) { |
| 496 | return H_PARAMETER; |
| 497 | } |
| 498 | |
| 499 | /* VPA is not allowed to cross a page boundary */ |
| 500 | if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { |
| 501 | return H_PARAMETER; |
| 502 | } |
| 503 | |
David Gibson | 1bfb37d | 2012-10-08 18:17:38 +0000 | [diff] [blame] | 504 | env->vpa_addr = vpa; |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 505 | |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 506 | tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 507 | tmp |= VPA_SHARED_PROC_VAL; |
Edgar E. Iglesias | db3be60 | 2013-12-17 15:29:06 +1000 | [diff] [blame] | 508 | stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 509 | |
| 510 | return H_SUCCESS; |
| 511 | } |
| 512 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 513 | static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 514 | { |
David Gibson | 1bfb37d | 2012-10-08 18:17:38 +0000 | [diff] [blame] | 515 | if (env->slb_shadow_addr) { |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 516 | return H_RESOURCE; |
| 517 | } |
| 518 | |
David Gibson | 1bfb37d | 2012-10-08 18:17:38 +0000 | [diff] [blame] | 519 | if (env->dtl_addr) { |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 520 | return H_RESOURCE; |
| 521 | } |
| 522 | |
David Gibson | 1bfb37d | 2012-10-08 18:17:38 +0000 | [diff] [blame] | 523 | env->vpa_addr = 0; |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 524 | return H_SUCCESS; |
| 525 | } |
| 526 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 527 | static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 528 | { |
Andreas Färber | 33276f1 | 2014-03-09 19:29:41 +0100 | [diff] [blame] | 529 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 530 | uint32_t size; |
| 531 | |
| 532 | if (addr == 0) { |
| 533 | hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); |
| 534 | return H_HARDWARE; |
| 535 | } |
| 536 | |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 537 | size = ldl_be_phys(cs->as, addr + 0x4); |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 538 | if (size < 0x8) { |
| 539 | return H_PARAMETER; |
| 540 | } |
| 541 | |
| 542 | if ((addr / 4096) != ((addr + size - 1) / 4096)) { |
| 543 | return H_PARAMETER; |
| 544 | } |
| 545 | |
David Gibson | 1bfb37d | 2012-10-08 18:17:38 +0000 | [diff] [blame] | 546 | if (!env->vpa_addr) { |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 547 | return H_RESOURCE; |
| 548 | } |
| 549 | |
David Gibson | 1bfb37d | 2012-10-08 18:17:38 +0000 | [diff] [blame] | 550 | env->slb_shadow_addr = addr; |
| 551 | env->slb_shadow_size = size; |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 552 | |
| 553 | return H_SUCCESS; |
| 554 | } |
| 555 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 556 | static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 557 | { |
David Gibson | 1bfb37d | 2012-10-08 18:17:38 +0000 | [diff] [blame] | 558 | env->slb_shadow_addr = 0; |
| 559 | env->slb_shadow_size = 0; |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 560 | return H_SUCCESS; |
| 561 | } |
| 562 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 563 | static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 564 | { |
Andreas Färber | 33276f1 | 2014-03-09 19:29:41 +0100 | [diff] [blame] | 565 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 566 | uint32_t size; |
| 567 | |
| 568 | if (addr == 0) { |
| 569 | hcall_dprintf("Can't cope with DTL at logical 0\n"); |
| 570 | return H_HARDWARE; |
| 571 | } |
| 572 | |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 573 | size = ldl_be_phys(cs->as, addr + 0x4); |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 574 | |
| 575 | if (size < 48) { |
| 576 | return H_PARAMETER; |
| 577 | } |
| 578 | |
David Gibson | 1bfb37d | 2012-10-08 18:17:38 +0000 | [diff] [blame] | 579 | if (!env->vpa_addr) { |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 580 | return H_RESOURCE; |
| 581 | } |
| 582 | |
David Gibson | 1bfb37d | 2012-10-08 18:17:38 +0000 | [diff] [blame] | 583 | env->dtl_addr = addr; |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 584 | env->dtl_size = size; |
| 585 | |
| 586 | return H_SUCCESS; |
| 587 | } |
| 588 | |
Peter Portante | 73f7821 | 2012-04-23 07:27:56 +0000 | [diff] [blame] | 589 | static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 590 | { |
David Gibson | 1bfb37d | 2012-10-08 18:17:38 +0000 | [diff] [blame] | 591 | env->dtl_addr = 0; |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 592 | env->dtl_size = 0; |
| 593 | |
| 594 | return H_SUCCESS; |
| 595 | } |
| 596 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 597 | static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 598 | target_ulong opcode, target_ulong *args) |
| 599 | { |
| 600 | target_ulong flags = args[0]; |
| 601 | target_ulong procno = args[1]; |
| 602 | target_ulong vpa = args[2]; |
| 603 | target_ulong ret = H_PARAMETER; |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 604 | CPUPPCState *tenv; |
Alexey Kardashevskiy | 0f20ba6 | 2014-02-02 01:45:52 +1100 | [diff] [blame] | 605 | PowerPCCPU *tcpu; |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 606 | |
Alexey Kardashevskiy | 0f20ba6 | 2014-02-02 01:45:52 +1100 | [diff] [blame] | 607 | tcpu = ppc_get_vcpu_by_dt_id(procno); |
Andreas Färber | 5353d03 | 2013-02-15 16:43:08 +0100 | [diff] [blame] | 608 | if (!tcpu) { |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 609 | return H_PARAMETER; |
| 610 | } |
Alexey Kardashevskiy | 0f20ba6 | 2014-02-02 01:45:52 +1100 | [diff] [blame] | 611 | tenv = &tcpu->env; |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 612 | |
| 613 | switch (flags) { |
| 614 | case FLAGS_REGISTER_VPA: |
| 615 | ret = register_vpa(tenv, vpa); |
| 616 | break; |
| 617 | |
| 618 | case FLAGS_DEREGISTER_VPA: |
| 619 | ret = deregister_vpa(tenv, vpa); |
| 620 | break; |
| 621 | |
| 622 | case FLAGS_REGISTER_SLBSHADOW: |
| 623 | ret = register_slb_shadow(tenv, vpa); |
| 624 | break; |
| 625 | |
| 626 | case FLAGS_DEREGISTER_SLBSHADOW: |
| 627 | ret = deregister_slb_shadow(tenv, vpa); |
| 628 | break; |
| 629 | |
| 630 | case FLAGS_REGISTER_DTL: |
| 631 | ret = register_dtl(tenv, vpa); |
| 632 | break; |
| 633 | |
| 634 | case FLAGS_DEREGISTER_DTL: |
| 635 | ret = deregister_dtl(tenv, vpa); |
| 636 | break; |
| 637 | } |
| 638 | |
| 639 | return ret; |
| 640 | } |
| 641 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 642 | static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 643 | target_ulong opcode, target_ulong *args) |
| 644 | { |
Andreas Färber | b13ce26 | 2012-05-03 06:23:01 +0200 | [diff] [blame] | 645 | CPUPPCState *env = &cpu->env; |
Andreas Färber | fcd7d00 | 2012-12-17 08:02:44 +0100 | [diff] [blame] | 646 | CPUState *cs = CPU(cpu); |
Andreas Färber | b13ce26 | 2012-05-03 06:23:01 +0200 | [diff] [blame] | 647 | |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 648 | env->msr |= (1ULL << MSR_EE); |
| 649 | hreg_compute_hflags(env); |
Andreas Färber | fcd7d00 | 2012-12-17 08:02:44 +0100 | [diff] [blame] | 650 | if (!cpu_has_work(cs)) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 651 | cs->halted = 1; |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 652 | cs->exception_index = EXCP_HLT; |
Andreas Färber | fcd7d00 | 2012-12-17 08:02:44 +0100 | [diff] [blame] | 653 | cs->exit_request = 1; |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 654 | } |
| 655 | return H_SUCCESS; |
| 656 | } |
| 657 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 658 | static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
David Gibson | 39ac845 | 2011-04-01 15:15:23 +1100 | [diff] [blame] | 659 | target_ulong opcode, target_ulong *args) |
| 660 | { |
| 661 | target_ulong rtas_r3 = args[0]; |
Alexey Kardashevskiy | 4fe822e | 2013-09-27 18:10:18 +1000 | [diff] [blame] | 662 | uint32_t token = rtas_ld(rtas_r3, 0); |
| 663 | uint32_t nargs = rtas_ld(rtas_r3, 1); |
| 664 | uint32_t nret = rtas_ld(rtas_r3, 2); |
David Gibson | 39ac845 | 2011-04-01 15:15:23 +1100 | [diff] [blame] | 665 | |
Anthony Liguori | 210b580 | 2013-06-19 15:40:30 -0500 | [diff] [blame] | 666 | return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, |
David Gibson | 39ac845 | 2011-04-01 15:15:23 +1100 | [diff] [blame] | 667 | nret, rtas_r3 + 12 + 4*nargs); |
| 668 | } |
| 669 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 670 | static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 671 | target_ulong opcode, target_ulong *args) |
| 672 | { |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 673 | CPUState *cs = CPU(cpu); |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 674 | target_ulong size = args[0]; |
| 675 | target_ulong addr = args[1]; |
| 676 | |
| 677 | switch (size) { |
| 678 | case 1: |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 679 | args[0] = ldub_phys(cs->as, addr); |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 680 | return H_SUCCESS; |
| 681 | case 2: |
Edgar E. Iglesias | 41701aa | 2013-12-17 14:33:56 +1000 | [diff] [blame] | 682 | args[0] = lduw_phys(cs->as, addr); |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 683 | return H_SUCCESS; |
| 684 | case 4: |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 685 | args[0] = ldl_phys(cs->as, addr); |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 686 | return H_SUCCESS; |
| 687 | case 8: |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 688 | args[0] = ldq_phys(cs->as, addr); |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 689 | return H_SUCCESS; |
| 690 | } |
| 691 | return H_PARAMETER; |
| 692 | } |
| 693 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 694 | static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 695 | target_ulong opcode, target_ulong *args) |
| 696 | { |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 697 | CPUState *cs = CPU(cpu); |
| 698 | |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 699 | target_ulong size = args[0]; |
| 700 | target_ulong addr = args[1]; |
| 701 | target_ulong val = args[2]; |
| 702 | |
| 703 | switch (size) { |
| 704 | case 1: |
Edgar E. Iglesias | db3be60 | 2013-12-17 15:29:06 +1000 | [diff] [blame] | 705 | stb_phys(cs->as, addr, val); |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 706 | return H_SUCCESS; |
| 707 | case 2: |
Edgar E. Iglesias | 5ce5944 | 2013-12-17 15:22:06 +1000 | [diff] [blame] | 708 | stw_phys(cs->as, addr, val); |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 709 | return H_SUCCESS; |
| 710 | case 4: |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 711 | stl_phys(cs->as, addr, val); |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 712 | return H_SUCCESS; |
| 713 | case 8: |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 714 | stq_phys(cs->as, addr, val); |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 715 | return H_SUCCESS; |
| 716 | } |
| 717 | return H_PARAMETER; |
| 718 | } |
| 719 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 720 | static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
Benjamin Herrenschmidt | c73e377 | 2012-06-18 20:21:37 +0000 | [diff] [blame] | 721 | target_ulong opcode, target_ulong *args) |
| 722 | { |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 723 | CPUState *cs = CPU(cpu); |
| 724 | |
Benjamin Herrenschmidt | c73e377 | 2012-06-18 20:21:37 +0000 | [diff] [blame] | 725 | target_ulong dst = args[0]; /* Destination address */ |
| 726 | target_ulong src = args[1]; /* Source address */ |
| 727 | target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ |
| 728 | target_ulong count = args[3]; /* Element count */ |
| 729 | target_ulong op = args[4]; /* 0 = copy, 1 = invert */ |
| 730 | uint64_t tmp; |
| 731 | unsigned int mask = (1 << esize) - 1; |
| 732 | int step = 1 << esize; |
| 733 | |
| 734 | if (count > 0x80000000) { |
| 735 | return H_PARAMETER; |
| 736 | } |
| 737 | |
| 738 | if ((dst & mask) || (src & mask) || (op > 1)) { |
| 739 | return H_PARAMETER; |
| 740 | } |
| 741 | |
| 742 | if (dst >= src && dst < (src + (count << esize))) { |
| 743 | dst = dst + ((count - 1) << esize); |
| 744 | src = src + ((count - 1) << esize); |
| 745 | step = -step; |
| 746 | } |
| 747 | |
| 748 | while (count--) { |
| 749 | switch (esize) { |
| 750 | case 0: |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 751 | tmp = ldub_phys(cs->as, src); |
Benjamin Herrenschmidt | c73e377 | 2012-06-18 20:21:37 +0000 | [diff] [blame] | 752 | break; |
| 753 | case 1: |
Edgar E. Iglesias | 41701aa | 2013-12-17 14:33:56 +1000 | [diff] [blame] | 754 | tmp = lduw_phys(cs->as, src); |
Benjamin Herrenschmidt | c73e377 | 2012-06-18 20:21:37 +0000 | [diff] [blame] | 755 | break; |
| 756 | case 2: |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 757 | tmp = ldl_phys(cs->as, src); |
Benjamin Herrenschmidt | c73e377 | 2012-06-18 20:21:37 +0000 | [diff] [blame] | 758 | break; |
| 759 | case 3: |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 760 | tmp = ldq_phys(cs->as, src); |
Benjamin Herrenschmidt | c73e377 | 2012-06-18 20:21:37 +0000 | [diff] [blame] | 761 | break; |
| 762 | default: |
| 763 | return H_PARAMETER; |
| 764 | } |
| 765 | if (op == 1) { |
| 766 | tmp = ~tmp; |
| 767 | } |
| 768 | switch (esize) { |
| 769 | case 0: |
Edgar E. Iglesias | db3be60 | 2013-12-17 15:29:06 +1000 | [diff] [blame] | 770 | stb_phys(cs->as, dst, tmp); |
Benjamin Herrenschmidt | c73e377 | 2012-06-18 20:21:37 +0000 | [diff] [blame] | 771 | break; |
| 772 | case 1: |
Edgar E. Iglesias | 5ce5944 | 2013-12-17 15:22:06 +1000 | [diff] [blame] | 773 | stw_phys(cs->as, dst, tmp); |
Benjamin Herrenschmidt | c73e377 | 2012-06-18 20:21:37 +0000 | [diff] [blame] | 774 | break; |
| 775 | case 2: |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 776 | stl_phys(cs->as, dst, tmp); |
Benjamin Herrenschmidt | c73e377 | 2012-06-18 20:21:37 +0000 | [diff] [blame] | 777 | break; |
| 778 | case 3: |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 779 | stq_phys(cs->as, dst, tmp); |
Benjamin Herrenschmidt | c73e377 | 2012-06-18 20:21:37 +0000 | [diff] [blame] | 780 | break; |
| 781 | } |
| 782 | dst = dst + step; |
| 783 | src = src + step; |
| 784 | } |
| 785 | |
| 786 | return H_SUCCESS; |
| 787 | } |
| 788 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 789 | static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 790 | target_ulong opcode, target_ulong *args) |
| 791 | { |
| 792 | /* Nothing to do on emulation, KVM will trap this in the kernel */ |
| 793 | return H_SUCCESS; |
| 794 | } |
| 795 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 796 | static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 797 | target_ulong opcode, target_ulong *args) |
| 798 | { |
| 799 | /* Nothing to do on emulation, KVM will trap this in the kernel */ |
| 800 | return H_SUCCESS; |
| 801 | } |
| 802 | |
Peter Maydell | 7d0cd46 | 2014-07-08 16:02:26 +0100 | [diff] [blame] | 803 | static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, |
| 804 | target_ulong mflags, |
| 805 | target_ulong value1, |
| 806 | target_ulong value2) |
Alexey Kardashevskiy | c4015bb | 2014-06-04 22:51:04 +1000 | [diff] [blame] | 807 | { |
| 808 | CPUState *cs; |
| 809 | |
| 810 | if (value1) { |
| 811 | return H_P3; |
| 812 | } |
| 813 | if (value2) { |
| 814 | return H_P4; |
| 815 | } |
| 816 | |
| 817 | switch (mflags) { |
| 818 | case H_SET_MODE_ENDIAN_BIG: |
| 819 | CPU_FOREACH(cs) { |
| 820 | set_spr(cs, SPR_LPCR, 0, LPCR_ILE); |
| 821 | } |
David Gibson | eefaccc | 2015-02-10 15:36:16 +1100 | [diff] [blame] | 822 | spapr_pci_switch_vga(true); |
Alexey Kardashevskiy | c4015bb | 2014-06-04 22:51:04 +1000 | [diff] [blame] | 823 | return H_SUCCESS; |
| 824 | |
| 825 | case H_SET_MODE_ENDIAN_LITTLE: |
| 826 | CPU_FOREACH(cs) { |
| 827 | set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); |
| 828 | } |
David Gibson | eefaccc | 2015-02-10 15:36:16 +1100 | [diff] [blame] | 829 | spapr_pci_switch_vga(false); |
Alexey Kardashevskiy | c4015bb | 2014-06-04 22:51:04 +1000 | [diff] [blame] | 830 | return H_SUCCESS; |
| 831 | } |
| 832 | |
| 833 | return H_UNSUPPORTED_FLAG; |
| 834 | } |
| 835 | |
Peter Maydell | 7d0cd46 | 2014-07-08 16:02:26 +0100 | [diff] [blame] | 836 | static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, |
| 837 | target_ulong mflags, |
| 838 | target_ulong value1, |
| 839 | target_ulong value2) |
Alexey Kardashevskiy | d5ac4f5 | 2014-06-04 22:51:05 +1000 | [diff] [blame] | 840 | { |
| 841 | CPUState *cs; |
| 842 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
Alexey Kardashevskiy | d5ac4f5 | 2014-06-04 22:51:05 +1000 | [diff] [blame] | 843 | |
| 844 | if (!(pcc->insns_flags2 & PPC2_ISA207S)) { |
| 845 | return H_P2; |
| 846 | } |
| 847 | if (value1) { |
| 848 | return H_P3; |
| 849 | } |
| 850 | if (value2) { |
| 851 | return H_P4; |
| 852 | } |
| 853 | |
Cédric Le Goater | 5c94b2a | 2016-04-03 19:57:50 +0200 | [diff] [blame] | 854 | if (mflags == AIL_RESERVED) { |
Alexey Kardashevskiy | d5ac4f5 | 2014-06-04 22:51:05 +1000 | [diff] [blame] | 855 | return H_UNSUPPORTED_FLAG; |
| 856 | } |
| 857 | |
| 858 | CPU_FOREACH(cs) { |
Alexey Kardashevskiy | d5ac4f5 | 2014-06-04 22:51:05 +1000 | [diff] [blame] | 859 | set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); |
Alexey Kardashevskiy | d5ac4f5 | 2014-06-04 22:51:05 +1000 | [diff] [blame] | 860 | } |
| 861 | |
| 862 | return H_SUCCESS; |
| 863 | } |
| 864 | |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 865 | static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
Anton Blanchard | 42561bf | 2013-08-19 21:04:20 +1000 | [diff] [blame] | 866 | target_ulong opcode, target_ulong *args) |
| 867 | { |
Anton Blanchard | 42561bf | 2013-08-19 21:04:20 +1000 | [diff] [blame] | 868 | target_ulong resource = args[1]; |
Anton Blanchard | 42561bf | 2013-08-19 21:04:20 +1000 | [diff] [blame] | 869 | target_ulong ret = H_P2; |
| 870 | |
Alexey Kardashevskiy | c4015bb | 2014-06-04 22:51:04 +1000 | [diff] [blame] | 871 | switch (resource) { |
| 872 | case H_SET_MODE_RESOURCE_LE: |
Peter Maydell | 7d0cd46 | 2014-07-08 16:02:26 +0100 | [diff] [blame] | 873 | ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); |
Alexey Kardashevskiy | c4015bb | 2014-06-04 22:51:04 +1000 | [diff] [blame] | 874 | break; |
Alexey Kardashevskiy | d5ac4f5 | 2014-06-04 22:51:05 +1000 | [diff] [blame] | 875 | case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: |
Peter Maydell | 7d0cd46 | 2014-07-08 16:02:26 +0100 | [diff] [blame] | 876 | ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], |
| 877 | args[2], args[3]); |
Alexey Kardashevskiy | d5ac4f5 | 2014-06-04 22:51:05 +1000 | [diff] [blame] | 878 | break; |
Anton Blanchard | 42561bf | 2013-08-19 21:04:20 +1000 | [diff] [blame] | 879 | } |
| 880 | |
Anton Blanchard | 42561bf | 2013-08-19 21:04:20 +1000 | [diff] [blame] | 881 | return ret; |
| 882 | } |
| 883 | |
Nicholas Piggin | 1c7ad77 | 2016-12-05 16:50:21 +1100 | [diff] [blame] | 884 | #define H_SIGNAL_SYS_RESET_ALL -1 |
| 885 | #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 |
| 886 | |
| 887 | static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, |
| 888 | sPAPRMachineState *spapr, |
| 889 | target_ulong opcode, target_ulong *args) |
| 890 | { |
| 891 | target_long target = args[0]; |
| 892 | CPUState *cs; |
| 893 | |
| 894 | if (target < 0) { |
| 895 | /* Broadcast */ |
| 896 | if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { |
| 897 | return H_PARAMETER; |
| 898 | } |
| 899 | |
| 900 | CPU_FOREACH(cs) { |
| 901 | PowerPCCPU *c = POWERPC_CPU(cs); |
| 902 | |
| 903 | if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { |
| 904 | if (c == cpu) { |
| 905 | continue; |
| 906 | } |
| 907 | } |
| 908 | run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
| 909 | } |
| 910 | return H_SUCCESS; |
| 911 | |
| 912 | } else { |
| 913 | /* Unicast */ |
| 914 | CPU_FOREACH(cs) { |
| 915 | if (cpu->cpu_dt_id == target) { |
| 916 | run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
| 917 | return H_SUCCESS; |
| 918 | } |
| 919 | } |
| 920 | return H_PARAMETER; |
| 921 | } |
| 922 | } |
| 923 | |
David Gibson | 152ef80 | 2016-11-16 13:54:48 +1100 | [diff] [blame] | 924 | static target_ulong h_client_architecture_support(PowerPCCPU *cpu, |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 925 | sPAPRMachineState *spapr, |
Alexey Kardashevskiy | 2a6593c | 2014-05-23 12:26:54 +1000 | [diff] [blame] | 926 | target_ulong opcode, |
| 927 | target_ulong *args) |
| 928 | { |
David Gibson | 27ac3e0 | 2016-01-19 15:57:59 +1100 | [diff] [blame] | 929 | target_ulong list = ppc64_phys_to_real(args[0]); |
Michael Roth | facdb8b | 2016-10-24 23:47:28 -0500 | [diff] [blame] | 930 | target_ulong ov_table; |
David Gibson | 152ef80 | 2016-11-16 13:54:48 +1100 | [diff] [blame] | 931 | bool explicit_match = false; /* Matched the CPU's real PVR */ |
| 932 | uint32_t max_compat = cpu->max_compat; |
| 933 | uint32_t best_compat = 0; |
| 934 | int i; |
Michael Roth | 6787d27 | 2016-10-24 23:47:29 -0500 | [diff] [blame] | 935 | sPAPROptionVector *ov5_guest, *ov5_cas_old, *ov5_updates; |
Alexey Kardashevskiy | 3794d54 | 2014-05-23 12:26:57 +1000 | [diff] [blame] | 936 | |
David Gibson | 152ef80 | 2016-11-16 13:54:48 +1100 | [diff] [blame] | 937 | /* |
| 938 | * We scan the supplied table of PVRs looking for two things |
| 939 | * 1. Is our real CPU PVR in the list? |
| 940 | * 2. What's the "best" listed logical PVR |
| 941 | */ |
| 942 | for (i = 0; i < 512; ++i) { |
Alexey Kardashevskiy | 3794d54 | 2014-05-23 12:26:57 +1000 | [diff] [blame] | 943 | uint32_t pvr, pvr_mask; |
| 944 | |
David Gibson | 27ac3e0 | 2016-01-19 15:57:59 +1100 | [diff] [blame] | 945 | pvr_mask = ldl_be_phys(&address_space_memory, list); |
David Gibson | 152ef80 | 2016-11-16 13:54:48 +1100 | [diff] [blame] | 946 | pvr = ldl_be_phys(&address_space_memory, list + 4); |
| 947 | list += 8; |
Alexey Kardashevskiy | 3794d54 | 2014-05-23 12:26:57 +1000 | [diff] [blame] | 948 | |
Alexey Kardashevskiy | 3794d54 | 2014-05-23 12:26:57 +1000 | [diff] [blame] | 949 | if (~pvr_mask & pvr) { |
David Gibson | 152ef80 | 2016-11-16 13:54:48 +1100 | [diff] [blame] | 950 | break; /* Terminator record */ |
| 951 | } |
| 952 | |
| 953 | if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { |
| 954 | explicit_match = true; |
| 955 | } else { |
| 956 | if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { |
| 957 | best_compat = pvr; |
| 958 | } |
Alexey Kardashevskiy | 3794d54 | 2014-05-23 12:26:57 +1000 | [diff] [blame] | 959 | } |
| 960 | } |
| 961 | |
David Gibson | 152ef80 | 2016-11-16 13:54:48 +1100 | [diff] [blame] | 962 | if ((best_compat == 0) && (!explicit_match || max_compat)) { |
| 963 | /* We couldn't find a suitable compatibility mode, and either |
| 964 | * the guest doesn't support "raw" mode for this CPU, or raw |
| 965 | * mode is disabled because a maximum compat mode is set */ |
| 966 | return H_HARDWARE; |
| 967 | } |
| 968 | |
Alexey Kardashevskiy | 3794d54 | 2014-05-23 12:26:57 +1000 | [diff] [blame] | 969 | /* Parsing finished */ |
David Gibson | 152ef80 | 2016-11-16 13:54:48 +1100 | [diff] [blame] | 970 | trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); |
Alexey Kardashevskiy | 3794d54 | 2014-05-23 12:26:57 +1000 | [diff] [blame] | 971 | |
| 972 | /* Update CPUs */ |
David Gibson | 152ef80 | 2016-11-16 13:54:48 +1100 | [diff] [blame] | 973 | if (cpu->compat_pvr != best_compat) { |
David Gibson | f6f242c | 2016-11-10 14:37:38 +1100 | [diff] [blame] | 974 | Error *local_err = NULL; |
Alexey Kardashevskiy | 3794d54 | 2014-05-23 12:26:57 +1000 | [diff] [blame] | 975 | |
David Gibson | f6f242c | 2016-11-10 14:37:38 +1100 | [diff] [blame] | 976 | ppc_set_compat_all(best_compat, &local_err); |
| 977 | if (local_err) { |
| 978 | error_report_err(local_err); |
| 979 | return H_HARDWARE; |
Alexey Kardashevskiy | 3794d54 | 2014-05-23 12:26:57 +1000 | [diff] [blame] | 980 | } |
| 981 | } |
| 982 | |
Bharata B Rao | 03d196b | 2015-07-13 10:34:00 +1000 | [diff] [blame] | 983 | /* For the future use: here @ov_table points to the first option vector */ |
| 984 | ov_table = list; |
| 985 | |
Michael Roth | facdb8b | 2016-10-24 23:47:28 -0500 | [diff] [blame] | 986 | ov5_guest = spapr_ovec_parse_vector(ov_table, 5); |
Alexey Kardashevskiy | 2a6593c | 2014-05-23 12:26:54 +1000 | [diff] [blame] | 987 | |
Michael Roth | facdb8b | 2016-10-24 23:47:28 -0500 | [diff] [blame] | 988 | /* NOTE: there are actually a number of ov5 bits where input from the |
| 989 | * guest is always zero, and the platform/QEMU enables them independently |
| 990 | * of guest input. To model these properly we'd want some sort of mask, |
| 991 | * but since they only currently apply to memory migration as defined |
| 992 | * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need |
Michael Roth | 6787d27 | 2016-10-24 23:47:29 -0500 | [diff] [blame] | 993 | * to worry about this for now. |
Michael Roth | facdb8b | 2016-10-24 23:47:28 -0500 | [diff] [blame] | 994 | */ |
Michael Roth | 6787d27 | 2016-10-24 23:47:29 -0500 | [diff] [blame] | 995 | ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); |
| 996 | /* full range of negotiated ov5 capabilities */ |
Michael Roth | facdb8b | 2016-10-24 23:47:28 -0500 | [diff] [blame] | 997 | spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); |
| 998 | spapr_ovec_cleanup(ov5_guest); |
Michael Roth | 6787d27 | 2016-10-24 23:47:29 -0500 | [diff] [blame] | 999 | /* capabilities that have been added since CAS-generated guest reset. |
| 1000 | * if capabilities have since been removed, generate another reset |
| 1001 | */ |
| 1002 | ov5_updates = spapr_ovec_new(); |
| 1003 | spapr->cas_reboot = spapr_ovec_diff(ov5_updates, |
| 1004 | ov5_cas_old, spapr->ov5_cas); |
Bharata B Rao | 03d196b | 2015-07-13 10:34:00 +1000 | [diff] [blame] | 1005 | |
Michael Roth | 6787d27 | 2016-10-24 23:47:29 -0500 | [diff] [blame] | 1006 | if (!spapr->cas_reboot) { |
| 1007 | spapr->cas_reboot = |
David Gibson | 5b12078 | 2016-10-29 00:01:05 +1100 | [diff] [blame] | 1008 | (spapr_h_cas_compose_response(spapr, args[1], args[2], |
Michael Roth | 6787d27 | 2016-10-24 23:47:29 -0500 | [diff] [blame] | 1009 | ov5_updates) != 0); |
| 1010 | } |
| 1011 | spapr_ovec_cleanup(ov5_updates); |
| 1012 | |
| 1013 | if (spapr->cas_reboot) { |
Alexey Kardashevskiy | 2a6593c | 2014-05-23 12:26:54 +1000 | [diff] [blame] | 1014 | qemu_system_reset_request(); |
| 1015 | } |
| 1016 | |
| 1017 | return H_SUCCESS; |
| 1018 | } |
| 1019 | |
David Gibson | 7d7ba3f | 2011-05-10 16:06:21 +1000 | [diff] [blame] | 1020 | static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; |
| 1021 | static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; |
David Gibson | 9fdf0c2 | 2011-04-01 15:15:20 +1100 | [diff] [blame] | 1022 | |
| 1023 | void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) |
| 1024 | { |
David Gibson | 39ac845 | 2011-04-01 15:15:23 +1100 | [diff] [blame] | 1025 | spapr_hcall_fn *slot; |
David Gibson | 9fdf0c2 | 2011-04-01 15:15:20 +1100 | [diff] [blame] | 1026 | |
David Gibson | 39ac845 | 2011-04-01 15:15:23 +1100 | [diff] [blame] | 1027 | if (opcode <= MAX_HCALL_OPCODE) { |
| 1028 | assert((opcode & 0x3) == 0); |
David Gibson | 9fdf0c2 | 2011-04-01 15:15:20 +1100 | [diff] [blame] | 1029 | |
David Gibson | 39ac845 | 2011-04-01 15:15:23 +1100 | [diff] [blame] | 1030 | slot = &papr_hypercall_table[opcode / 4]; |
| 1031 | } else { |
| 1032 | assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); |
David Gibson | 9fdf0c2 | 2011-04-01 15:15:20 +1100 | [diff] [blame] | 1033 | |
David Gibson | 39ac845 | 2011-04-01 15:15:23 +1100 | [diff] [blame] | 1034 | slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
| 1035 | } |
| 1036 | |
David Gibson | c89d529 | 2012-10-08 18:17:36 +0000 | [diff] [blame] | 1037 | assert(!(*slot)); |
David Gibson | 39ac845 | 2011-04-01 15:15:23 +1100 | [diff] [blame] | 1038 | *slot = fn; |
David Gibson | 9fdf0c2 | 2011-04-01 15:15:20 +1100 | [diff] [blame] | 1039 | } |
| 1040 | |
Andreas Färber | aa100fa | 2012-05-03 06:13:14 +0200 | [diff] [blame] | 1041 | target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
David Gibson | 9fdf0c2 | 2011-04-01 15:15:20 +1100 | [diff] [blame] | 1042 | target_ulong *args) |
| 1043 | { |
David Gibson | 28e0204 | 2015-07-02 16:23:04 +1000 | [diff] [blame] | 1044 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
| 1045 | |
David Gibson | 9fdf0c2 | 2011-04-01 15:15:20 +1100 | [diff] [blame] | 1046 | if ((opcode <= MAX_HCALL_OPCODE) |
| 1047 | && ((opcode & 0x3) == 0)) { |
David Gibson | 39ac845 | 2011-04-01 15:15:23 +1100 | [diff] [blame] | 1048 | spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; |
| 1049 | |
| 1050 | if (fn) { |
Andreas Färber | b13ce26 | 2012-05-03 06:23:01 +0200 | [diff] [blame] | 1051 | return fn(cpu, spapr, opcode, args); |
David Gibson | 39ac845 | 2011-04-01 15:15:23 +1100 | [diff] [blame] | 1052 | } |
| 1053 | } else if ((opcode >= KVMPPC_HCALL_BASE) && |
| 1054 | (opcode <= KVMPPC_HCALL_MAX)) { |
| 1055 | spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
David Gibson | 9fdf0c2 | 2011-04-01 15:15:20 +1100 | [diff] [blame] | 1056 | |
| 1057 | if (fn) { |
Andreas Färber | b13ce26 | 2012-05-03 06:23:01 +0200 | [diff] [blame] | 1058 | return fn(cpu, spapr, opcode, args); |
David Gibson | 9fdf0c2 | 2011-04-01 15:15:20 +1100 | [diff] [blame] | 1059 | } |
| 1060 | } |
| 1061 | |
Thomas Huth | aaf87c6 | 2015-09-01 11:29:02 +1000 | [diff] [blame] | 1062 | qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", |
| 1063 | opcode); |
David Gibson | 9fdf0c2 | 2011-04-01 15:15:20 +1100 | [diff] [blame] | 1064 | return H_FUNCTION; |
| 1065 | } |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 1066 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 1067 | static void hypercall_register_types(void) |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 1068 | { |
| 1069 | /* hcall-pft */ |
| 1070 | spapr_register_hypercall(H_ENTER, h_enter); |
| 1071 | spapr_register_hypercall(H_REMOVE, h_remove); |
| 1072 | spapr_register_hypercall(H_PROTECT, h_protect); |
Erlon Cruz | 6bbd5dd | 2013-02-18 05:00:32 +0000 | [diff] [blame] | 1073 | spapr_register_hypercall(H_READ, h_read); |
David Gibson | 39ac845 | 2011-04-01 15:15:23 +1100 | [diff] [blame] | 1074 | |
David Gibson | a3d0aba | 2011-08-31 15:50:50 +0000 | [diff] [blame] | 1075 | /* hcall-bulk */ |
| 1076 | spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); |
| 1077 | |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 1078 | /* hcall-splpar */ |
| 1079 | spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); |
| 1080 | spapr_register_hypercall(H_CEDE, h_cede); |
Nicholas Piggin | 1c7ad77 | 2016-12-05 16:50:21 +1100 | [diff] [blame] | 1081 | spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 1082 | |
Thomas Huth | 423576f | 2016-02-11 13:47:18 +0100 | [diff] [blame] | 1083 | /* processor register resource access h-calls */ |
| 1084 | spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); |
Thomas Huth | af08a58 | 2016-02-11 13:47:19 +0100 | [diff] [blame] | 1085 | spapr_register_hypercall(H_SET_DABR, h_set_dabr); |
Thomas Huth | e49ff26 | 2016-02-11 13:47:20 +0100 | [diff] [blame] | 1086 | spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); |
Thomas Huth | 3240dd9 | 2016-02-18 10:15:54 +0100 | [diff] [blame] | 1087 | spapr_register_hypercall(H_PAGE_INIT, h_page_init); |
Thomas Huth | 423576f | 2016-02-11 13:47:18 +0100 | [diff] [blame] | 1088 | spapr_register_hypercall(H_SET_MODE, h_set_mode); |
| 1089 | |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 1090 | /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate |
| 1091 | * here between the "CI" and the "CACHE" variants, they will use whatever |
| 1092 | * mapping attributes qemu is using. When using KVM, the kernel will |
| 1093 | * enforce the attributes more strongly |
| 1094 | */ |
| 1095 | spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); |
| 1096 | spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); |
| 1097 | spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); |
| 1098 | spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); |
| 1099 | spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); |
| 1100 | spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); |
Benjamin Herrenschmidt | c73e377 | 2012-06-18 20:21:37 +0000 | [diff] [blame] | 1101 | spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); |
David Gibson | 827200a | 2011-08-10 14:44:20 +0000 | [diff] [blame] | 1102 | |
David Gibson | 39ac845 | 2011-04-01 15:15:23 +1100 | [diff] [blame] | 1103 | /* qemu/KVM-PPC specific hcalls */ |
| 1104 | spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); |
Anton Blanchard | 42561bf | 2013-08-19 21:04:20 +1000 | [diff] [blame] | 1105 | |
Alexey Kardashevskiy | 2a6593c | 2014-05-23 12:26:54 +1000 | [diff] [blame] | 1106 | /* ibm,client-architecture-support support */ |
| 1107 | spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 1108 | } |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 1109 | |
| 1110 | type_init(hypercall_register_types) |