blob: 42d20e0b926136264a59eda48b1e37c4777321bb [file] [log] [blame]
Peter Maydell0d755902016-01-26 18:16:58 +00001#include "qemu/osdep.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +01002#include "qapi/error.h"
Vincent Palatinb3946622017-01-10 11:59:55 +01003#include "sysemu/hw_accel.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +01004#include "sysemu/sysemu.h"
Paolo Bonzini03dd0242015-12-15 13:16:16 +01005#include "qemu/log.h"
David Gibson9fdf0c22011-04-01 15:15:20 +11006#include "cpu.h"
Paolo Bonzini63c91552016-03-15 13:18:37 +01007#include "exec/exec-all.h"
David Gibsoned120052011-04-01 15:15:33 +11008#include "helper_regs.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +01009#include "hw/ppc/spapr.h"
David Gibsond5aea6f2013-03-12 00:31:18 +000010#include "mmu-hash64.h"
Alexey Kardashevskiy3794d542014-05-23 12:26:57 +100011#include "cpu-models.h"
12#include "trace.h"
13#include "kvm_ppc.h"
Michael Rothfacdb8b2016-10-24 23:47:28 -050014#include "hw/ppc/spapr_ovec.h"
David Gibsonf43e3522011-04-01 15:15:22 +110015
Alexey Kardashevskiya46622f2014-03-07 15:37:40 +110016struct SPRSyncState {
Alexey Kardashevskiya46622f2014-03-07 15:37:40 +110017 int spr;
18 target_ulong value;
19 target_ulong mask;
20};
21
Paolo Bonzini14e6fe12016-10-31 10:36:08 +010022static void do_spr_sync(CPUState *cs, run_on_cpu_data arg)
Alexey Kardashevskiya46622f2014-03-07 15:37:40 +110023{
Paolo Bonzini14e6fe12016-10-31 10:36:08 +010024 struct SPRSyncState *s = arg.host_ptr;
Alex Bennéee0eeb4a2016-08-02 18:27:33 +010025 PowerPCCPU *cpu = POWERPC_CPU(cs);
Alexey Kardashevskiya46622f2014-03-07 15:37:40 +110026 CPUPPCState *env = &cpu->env;
27
Alex Bennéee0eeb4a2016-08-02 18:27:33 +010028 cpu_synchronize_state(cs);
Alexey Kardashevskiya46622f2014-03-07 15:37:40 +110029 env->spr[s->spr] &= ~s->mask;
30 env->spr[s->spr] |= s->value;
31}
32
33static void set_spr(CPUState *cs, int spr, target_ulong value,
34 target_ulong mask)
35{
36 struct SPRSyncState s = {
Alexey Kardashevskiya46622f2014-03-07 15:37:40 +110037 .spr = spr,
38 .value = value,
39 .mask = mask
40 };
Paolo Bonzini14e6fe12016-10-31 10:36:08 +010041 run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s));
Alexey Kardashevskiya46622f2014-03-07 15:37:40 +110042}
43
Thomas Huthaf08a582016-02-11 13:47:19 +010044static bool has_spr(PowerPCCPU *cpu, int spr)
45{
46 /* We can test whether the SPR is defined by checking for a valid name */
47 return cpu->env.spr_cb[spr].name != NULL;
48}
49
Aneesh Kumar K.Vf3c75d42014-02-20 18:52:17 +010050static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_index)
51{
52 /*
53 * hash value/pteg group index is normalized by htab_mask
54 */
55 if (((pte_index & ~7ULL) / HPTES_PER_GROUP) & ~env->htab_mask) {
56 return false;
57 }
58 return true;
59}
60
David Gibsonecbc25f2016-01-21 14:48:43 +110061static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr)
62{
63 MachineState *machine = MACHINE(spapr);
64 MemoryHotplugState *hpms = &spapr->hotplug_memory;
65
66 if (addr < machine->ram_size) {
67 return true;
68 }
69 if ((addr >= hpms->base)
70 && ((addr - hpms->base) < memory_region_size(&hpms->mr))) {
71 return true;
72 }
73
74 return false;
75}
76
David Gibson28e02042015-07-02 16:23:04 +100077static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
David Gibsonf43e3522011-04-01 15:15:22 +110078 target_ulong opcode, target_ulong *args)
79{
Andreas Färberb13ce262012-05-03 06:23:01 +020080 CPUPPCState *env = &cpu->env;
David Gibsonf43e3522011-04-01 15:15:22 +110081 target_ulong flags = args[0];
82 target_ulong pte_index = args[1];
83 target_ulong pteh = args[2];
84 target_ulong ptel = args[3];
Cédric Le Goater1f0252e2016-07-01 09:10:10 +020085 unsigned apshift;
David Gibsonf73a2572011-08-03 21:02:19 +000086 target_ulong raddr;
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +010087 target_ulong index;
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +010088 uint64_t token;
David Gibsonf43e3522011-04-01 15:15:22 +110089
Cédric Le Goater1f0252e2016-07-01 09:10:10 +020090 apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel);
David Gibson1114e712016-01-27 12:01:20 +110091 if (!apshift) {
92 /* Bad page size encoding */
93 return H_PARAMETER;
David Gibsonf43e3522011-04-01 15:15:22 +110094 }
95
David Gibson1114e712016-01-27 12:01:20 +110096 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
David Gibsonf43e3522011-04-01 15:15:22 +110097
David Gibsonecbc25f2016-01-21 14:48:43 +110098 if (is_ram_address(spapr, raddr)) {
David Gibsonf73a2572011-08-03 21:02:19 +000099 /* Regular RAM - should have WIMG=0010 */
David Gibsond5aea6f2013-03-12 00:31:18 +0000100 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
David Gibsonf73a2572011-08-03 21:02:19 +0000101 return H_PARAMETER;
102 }
103 } else {
Aneesh Kumar K.Vc1175902016-06-17 16:07:20 +0530104 target_ulong wimg_flags;
David Gibsonf73a2572011-08-03 21:02:19 +0000105 /* Looks like an IO address */
106 /* FIXME: What WIMG combinations could be sensible for IO?
107 * For now we allow WIMG=010x, but are there others? */
108 /* FIXME: Should we check against registered IO addresses? */
Aneesh Kumar K.Vc1175902016-06-17 16:07:20 +0530109 wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M));
110
111 if (wimg_flags != HPTE64_R_I &&
112 wimg_flags != (HPTE64_R_I | HPTE64_R_M)) {
David Gibsonf73a2572011-08-03 21:02:19 +0000113 return H_PARAMETER;
114 }
David Gibsonf43e3522011-04-01 15:15:22 +1100115 }
David Gibsonf73a2572011-08-03 21:02:19 +0000116
David Gibsonf43e3522011-04-01 15:15:22 +1100117 pteh &= ~0x60ULL;
118
Aneesh Kumar K.Vf3c75d42014-02-20 18:52:17 +0100119 if (!valid_pte_index(env, pte_index)) {
David Gibsonf43e3522011-04-01 15:15:22 +1100120 return H_PARAMETER;
121 }
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +0100122
123 index = 0;
David Gibsonf43e3522011-04-01 15:15:22 +1100124 if (likely((flags & H_EXACT) == 0)) {
125 pte_index &= ~7ULL;
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +0100126 token = ppc_hash64_start_access(cpu, pte_index);
Aneesh Kumar K.V7aaf4952014-03-14 19:21:49 +0530127 for (; index < 8; index++) {
David Gibson7ef23062016-01-14 15:33:27 +1100128 if (!(ppc_hash64_load_hpte0(cpu, token, index) & HPTE64_V_VALID)) {
David Gibsonf43e3522011-04-01 15:15:22 +1100129 break;
130 }
Aneesh Kumar K.V7aaf4952014-03-14 19:21:49 +0530131 }
David Gibsonc18ad9a2016-03-08 11:35:15 +1100132 ppc_hash64_stop_access(cpu, token);
Aneesh Kumar K.V7aaf4952014-03-14 19:21:49 +0530133 if (index == 8) {
134 return H_PTEG_FULL;
135 }
David Gibsonf43e3522011-04-01 15:15:22 +1100136 } else {
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +0100137 token = ppc_hash64_start_access(cpu, pte_index);
David Gibson7ef23062016-01-14 15:33:27 +1100138 if (ppc_hash64_load_hpte0(cpu, token, 0) & HPTE64_V_VALID) {
David Gibsonc18ad9a2016-03-08 11:35:15 +1100139 ppc_hash64_stop_access(cpu, token);
David Gibsonf43e3522011-04-01 15:15:22 +1100140 return H_PTEG_FULL;
141 }
David Gibsonc18ad9a2016-03-08 11:35:15 +1100142 ppc_hash64_stop_access(cpu, token);
David Gibsonf43e3522011-04-01 15:15:22 +1100143 }
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +0100144
David Gibson7ef23062016-01-14 15:33:27 +1100145 ppc_hash64_store_hpte(cpu, pte_index + index,
Aneesh Kumar K.V3f941702014-02-20 18:52:31 +0100146 pteh | HPTE64_V_HPTE_DIRTY, ptel);
David Gibsonf43e3522011-04-01 15:15:22 +1100147
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +0100148 args[0] = pte_index + index;
David Gibsonf43e3522011-04-01 15:15:22 +1100149 return H_SUCCESS;
150}
151
Stefan Weila3801402013-06-24 19:48:47 +0200152typedef enum {
David Gibsona3d0aba2011-08-31 15:50:50 +0000153 REMOVE_SUCCESS = 0,
154 REMOVE_NOT_FOUND = 1,
155 REMOVE_PARM = 2,
156 REMOVE_HW = 3,
Stefan Weila3801402013-06-24 19:48:47 +0200157} RemoveResult;
David Gibsona3d0aba2011-08-31 15:50:50 +0000158
David Gibson7ef23062016-01-14 15:33:27 +1100159static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex,
David Gibsona3d0aba2011-08-31 15:50:50 +0000160 target_ulong avpn,
161 target_ulong flags,
162 target_ulong *vp, target_ulong *rp)
David Gibsonf43e3522011-04-01 15:15:22 +1100163{
David Gibson7ef23062016-01-14 15:33:27 +1100164 CPUPPCState *env = &cpu->env;
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +0100165 uint64_t token;
David Gibson61a36c92016-01-15 16:12:09 +1100166 target_ulong v, r;
David Gibsonf43e3522011-04-01 15:15:22 +1100167
Aneesh Kumar K.Vf3c75d42014-02-20 18:52:17 +0100168 if (!valid_pte_index(env, ptex)) {
David Gibsona3d0aba2011-08-31 15:50:50 +0000169 return REMOVE_PARM;
David Gibsonf43e3522011-04-01 15:15:22 +1100170 }
171
David Gibson7ef23062016-01-14 15:33:27 +1100172 token = ppc_hash64_start_access(cpu, ptex);
173 v = ppc_hash64_load_hpte0(cpu, token, 0);
174 r = ppc_hash64_load_hpte1(cpu, token, 0);
David Gibsonc18ad9a2016-03-08 11:35:15 +1100175 ppc_hash64_stop_access(cpu, token);
David Gibsonf43e3522011-04-01 15:15:22 +1100176
David Gibsond5aea6f2013-03-12 00:31:18 +0000177 if ((v & HPTE64_V_VALID) == 0 ||
David Gibsonf43e3522011-04-01 15:15:22 +1100178 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
179 ((flags & H_ANDCOND) && (v & avpn) != 0)) {
David Gibsona3d0aba2011-08-31 15:50:50 +0000180 return REMOVE_NOT_FOUND;
David Gibsonf43e3522011-04-01 15:15:22 +1100181 }
David Gibson35f93042012-09-20 17:42:30 +0000182 *vp = v;
David Gibsona3d0aba2011-08-31 15:50:50 +0000183 *rp = r;
David Gibson7ef23062016-01-14 15:33:27 +1100184 ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);
David Gibson61a36c92016-01-15 16:12:09 +1100185 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
David Gibsona3d0aba2011-08-31 15:50:50 +0000186 return REMOVE_SUCCESS;
187}
188
David Gibson28e02042015-07-02 16:23:04 +1000189static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
David Gibsona3d0aba2011-08-31 15:50:50 +0000190 target_ulong opcode, target_ulong *args)
191{
Benjamin Herrenschmidtcd0c6f42016-05-03 18:03:25 +0200192 CPUPPCState *env = &cpu->env;
David Gibsona3d0aba2011-08-31 15:50:50 +0000193 target_ulong flags = args[0];
194 target_ulong pte_index = args[1];
195 target_ulong avpn = args[2];
Stefan Weila3801402013-06-24 19:48:47 +0200196 RemoveResult ret;
David Gibsona3d0aba2011-08-31 15:50:50 +0000197
David Gibson7ef23062016-01-14 15:33:27 +1100198 ret = remove_hpte(cpu, pte_index, avpn, flags,
David Gibsona3d0aba2011-08-31 15:50:50 +0000199 &args[0], &args[1]);
200
201 switch (ret) {
202 case REMOVE_SUCCESS:
Nikunj A Dadhaniae3cffe62016-09-20 22:05:00 +0530203 check_tlb_flush(env, true);
David Gibsona3d0aba2011-08-31 15:50:50 +0000204 return H_SUCCESS;
205
206 case REMOVE_NOT_FOUND:
207 return H_NOT_FOUND;
208
209 case REMOVE_PARM:
210 return H_PARAMETER;
211
212 case REMOVE_HW:
213 return H_HARDWARE;
214 }
215
Stefan Weil9a399702013-06-29 15:47:26 +0200216 g_assert_not_reached();
David Gibsona3d0aba2011-08-31 15:50:50 +0000217}
218
219#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL
220#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL
221#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL
222#define H_BULK_REMOVE_END 0xc000000000000000ULL
223#define H_BULK_REMOVE_CODE 0x3000000000000000ULL
224#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL
225#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL
226#define H_BULK_REMOVE_PARM 0x2000000000000000ULL
227#define H_BULK_REMOVE_HW 0x3000000000000000ULL
228#define H_BULK_REMOVE_RC 0x0c00000000000000ULL
229#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL
230#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL
231#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL
232#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL
233#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL
234
235#define H_BULK_REMOVE_MAX_BATCH 4
236
David Gibson28e02042015-07-02 16:23:04 +1000237static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
David Gibsona3d0aba2011-08-31 15:50:50 +0000238 target_ulong opcode, target_ulong *args)
239{
Benjamin Herrenschmidtcd0c6f42016-05-03 18:03:25 +0200240 CPUPPCState *env = &cpu->env;
David Gibsona3d0aba2011-08-31 15:50:50 +0000241 int i;
Benjamin Herrenschmidtcd0c6f42016-05-03 18:03:25 +0200242 target_ulong rc = H_SUCCESS;
David Gibsona3d0aba2011-08-31 15:50:50 +0000243
244 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
245 target_ulong *tsh = &args[i*2];
246 target_ulong tsl = args[i*2 + 1];
247 target_ulong v, r, ret;
248
249 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
250 break;
251 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {
252 return H_PARAMETER;
253 }
254
255 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS;
256 *tsh |= H_BULK_REMOVE_RESPONSE;
257
258 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
259 *tsh |= H_BULK_REMOVE_PARM;
260 return H_PARAMETER;
261 }
262
David Gibson7ef23062016-01-14 15:33:27 +1100263 ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl,
David Gibsona3d0aba2011-08-31 15:50:50 +0000264 (*tsh & H_BULK_REMOVE_FLAGS) >> 26,
265 &v, &r);
266
267 *tsh |= ret << 60;
268
269 switch (ret) {
270 case REMOVE_SUCCESS:
David Gibsond5aea6f2013-03-12 00:31:18 +0000271 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43;
David Gibsona3d0aba2011-08-31 15:50:50 +0000272 break;
273
274 case REMOVE_PARM:
Benjamin Herrenschmidtcd0c6f42016-05-03 18:03:25 +0200275 rc = H_PARAMETER;
276 goto exit;
David Gibsona3d0aba2011-08-31 15:50:50 +0000277
278 case REMOVE_HW:
Benjamin Herrenschmidtcd0c6f42016-05-03 18:03:25 +0200279 rc = H_HARDWARE;
280 goto exit;
David Gibsona3d0aba2011-08-31 15:50:50 +0000281 }
282 }
Benjamin Herrenschmidtcd0c6f42016-05-03 18:03:25 +0200283 exit:
Nikunj A Dadhaniae3cffe62016-09-20 22:05:00 +0530284 check_tlb_flush(env, true);
David Gibsona3d0aba2011-08-31 15:50:50 +0000285
Benjamin Herrenschmidtcd0c6f42016-05-03 18:03:25 +0200286 return rc;
David Gibsonf43e3522011-04-01 15:15:22 +1100287}
288
David Gibson28e02042015-07-02 16:23:04 +1000289static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr,
David Gibsonf43e3522011-04-01 15:15:22 +1100290 target_ulong opcode, target_ulong *args)
291{
Andreas Färberb13ce262012-05-03 06:23:01 +0200292 CPUPPCState *env = &cpu->env;
David Gibsonf43e3522011-04-01 15:15:22 +1100293 target_ulong flags = args[0];
294 target_ulong pte_index = args[1];
295 target_ulong avpn = args[2];
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +0100296 uint64_t token;
David Gibson61a36c92016-01-15 16:12:09 +1100297 target_ulong v, r;
David Gibsonf43e3522011-04-01 15:15:22 +1100298
Aneesh Kumar K.Vf3c75d42014-02-20 18:52:17 +0100299 if (!valid_pte_index(env, pte_index)) {
David Gibsonf43e3522011-04-01 15:15:22 +1100300 return H_PARAMETER;
301 }
302
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +0100303 token = ppc_hash64_start_access(cpu, pte_index);
David Gibson7ef23062016-01-14 15:33:27 +1100304 v = ppc_hash64_load_hpte0(cpu, token, 0);
305 r = ppc_hash64_load_hpte1(cpu, token, 0);
David Gibsonc18ad9a2016-03-08 11:35:15 +1100306 ppc_hash64_stop_access(cpu, token);
David Gibsonf43e3522011-04-01 15:15:22 +1100307
David Gibsond5aea6f2013-03-12 00:31:18 +0000308 if ((v & HPTE64_V_VALID) == 0 ||
David Gibsonf43e3522011-04-01 15:15:22 +1100309 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
David Gibsonf43e3522011-04-01 15:15:22 +1100310 return H_NOT_FOUND;
311 }
312
David Gibsond5aea6f2013-03-12 00:31:18 +0000313 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N |
314 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO);
315 r |= (flags << 55) & HPTE64_R_PP0;
316 r |= (flags << 48) & HPTE64_R_KEY_HI;
317 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
David Gibson7ef23062016-01-14 15:33:27 +1100318 ppc_hash64_store_hpte(cpu, pte_index,
Aneesh Kumar K.V3f941702014-02-20 18:52:31 +0100319 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
David Gibson61a36c92016-01-15 16:12:09 +1100320 ppc_hash64_tlb_flush_hpte(cpu, pte_index, v, r);
Nikunj A Dadhaniad76ab5e2016-09-20 22:05:01 +0530321 /* Flush the tlb */
322 check_tlb_flush(env, true);
David Gibsonf43e3522011-04-01 15:15:22 +1100323 /* Don't need a memory barrier, due to qemu's global lock */
David Gibson7ef23062016-01-14 15:33:27 +1100324 ppc_hash64_store_hpte(cpu, pte_index, v | HPTE64_V_HPTE_DIRTY, r);
David Gibsonf43e3522011-04-01 15:15:22 +1100325 return H_SUCCESS;
326}
327
David Gibson28e02042015-07-02 16:23:04 +1000328static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr,
Erlon Cruz6bbd5dd2013-02-18 05:00:32 +0000329 target_ulong opcode, target_ulong *args)
330{
331 CPUPPCState *env = &cpu->env;
332 target_ulong flags = args[0];
333 target_ulong pte_index = args[1];
334 uint8_t *hpte;
335 int i, ridx, n_entries = 1;
336
Aneesh Kumar K.Vf3c75d42014-02-20 18:52:17 +0100337 if (!valid_pte_index(env, pte_index)) {
Erlon Cruz6bbd5dd2013-02-18 05:00:32 +0000338 return H_PARAMETER;
339 }
340
341 if (flags & H_READ_4) {
342 /* Clear the two low order bits */
343 pte_index &= ~(3ULL);
344 n_entries = 4;
345 }
346
347 hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
348
349 for (i = 0, ridx = 0; i < n_entries; i++) {
350 args[ridx++] = ldq_p(hpte);
351 args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
352 hpte += HASH_PTE_SIZE_64;
353 }
354
355 return H_SUCCESS;
356}
357
Thomas Huth423576f2016-02-11 13:47:18 +0100358static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr,
359 target_ulong opcode, target_ulong *args)
360{
361 cpu_synchronize_state(CPU(cpu));
362 cpu->env.spr[SPR_SPRG0] = args[0];
363
364 return H_SUCCESS;
365}
366
David Gibson28e02042015-07-02 16:23:04 +1000367static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
David Gibson821303f2011-04-01 15:15:24 +1100368 target_ulong opcode, target_ulong *args)
369{
Thomas Huthaf08a582016-02-11 13:47:19 +0100370 if (!has_spr(cpu, SPR_DABR)) {
371 return H_HARDWARE; /* DABR register not available */
372 }
373 cpu_synchronize_state(CPU(cpu));
374
375 if (has_spr(cpu, SPR_DABRX)) {
376 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */
377 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */
378 return H_RESERVED_DABR;
379 }
380
381 cpu->env.spr[SPR_DABR] = args[0];
382 return H_SUCCESS;
David Gibson821303f2011-04-01 15:15:24 +1100383}
384
Thomas Huthe49ff262016-02-11 13:47:20 +0100385static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
386 target_ulong opcode, target_ulong *args)
387{
388 target_ulong dabrx = args[1];
389
390 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) {
391 return H_HARDWARE;
392 }
393
394 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0
395 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) {
396 return H_PARAMETER;
397 }
398
399 cpu_synchronize_state(CPU(cpu));
400 cpu->env.spr[SPR_DABRX] = dabrx;
401 cpu->env.spr[SPR_DABR] = args[0];
402
403 return H_SUCCESS;
404}
405
Thomas Huth3240dd92016-02-18 10:15:54 +0100406static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr,
407 target_ulong opcode, target_ulong *args)
408{
409 target_ulong flags = args[0];
410 hwaddr dst = args[1];
411 hwaddr src = args[2];
412 hwaddr len = TARGET_PAGE_SIZE;
413 uint8_t *pdst, *psrc;
414 target_long ret = H_SUCCESS;
415
416 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE
417 | H_COPY_PAGE | H_ZERO_PAGE)) {
418 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n",
419 flags);
420 return H_PARAMETER;
421 }
422
423 /* Map-in destination */
424 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) {
425 return H_PARAMETER;
426 }
427 pdst = cpu_physical_memory_map(dst, &len, 1);
428 if (!pdst || len != TARGET_PAGE_SIZE) {
429 return H_PARAMETER;
430 }
431
432 if (flags & H_COPY_PAGE) {
433 /* Map-in source, copy to destination, and unmap source again */
434 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) {
435 ret = H_PARAMETER;
436 goto unmap_out;
437 }
438 psrc = cpu_physical_memory_map(src, &len, 0);
439 if (!psrc || len != TARGET_PAGE_SIZE) {
440 ret = H_PARAMETER;
441 goto unmap_out;
442 }
443 memcpy(pdst, psrc, len);
444 cpu_physical_memory_unmap(psrc, len, 0, len);
445 } else if (flags & H_ZERO_PAGE) {
446 memset(pdst, 0, len); /* Just clear the destination page */
447 }
448
449 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) {
450 kvmppc_dcbst_range(cpu, pdst, len);
451 }
452 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) {
453 if (kvm_enabled()) {
454 kvmppc_icbi_range(cpu, pdst, len);
455 } else {
456 tb_flush(CPU(cpu));
457 }
458 }
459
460unmap_out:
461 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len);
462 return ret;
463}
464
David Gibsoned120052011-04-01 15:15:33 +1100465#define FLAGS_REGISTER_VPA 0x0000200000000000ULL
466#define FLAGS_REGISTER_DTL 0x0000400000000000ULL
467#define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL
468#define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL
469#define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL
470#define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL
471
472#define VPA_MIN_SIZE 640
473#define VPA_SIZE_OFFSET 0x4
474#define VPA_SHARED_PROC_OFFSET 0x9
475#define VPA_SHARED_PROC_VAL 0x2
476
Andreas Färbere2684c02012-03-14 01:38:23 +0100477static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
David Gibsoned120052011-04-01 15:15:33 +1100478{
Andreas Färber33276f12014-03-09 19:29:41 +0100479 CPUState *cs = CPU(ppc_env_get_cpu(env));
David Gibsoned120052011-04-01 15:15:33 +1100480 uint16_t size;
481 uint8_t tmp;
482
483 if (vpa == 0) {
484 hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
485 return H_HARDWARE;
486 }
487
488 if (vpa % env->dcache_line_size) {
489 return H_PARAMETER;
490 }
491 /* FIXME: bounds check the address */
492
Edgar E. Iglesias41701aa2013-12-17 14:33:56 +1000493 size = lduw_be_phys(cs->as, vpa + 0x4);
David Gibsoned120052011-04-01 15:15:33 +1100494
495 if (size < VPA_MIN_SIZE) {
496 return H_PARAMETER;
497 }
498
499 /* VPA is not allowed to cross a page boundary */
500 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) {
501 return H_PARAMETER;
502 }
503
David Gibson1bfb37d2012-10-08 18:17:38 +0000504 env->vpa_addr = vpa;
David Gibsoned120052011-04-01 15:15:33 +1100505
Edgar E. Iglesias2c174492013-12-17 14:05:40 +1000506 tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET);
David Gibsoned120052011-04-01 15:15:33 +1100507 tmp |= VPA_SHARED_PROC_VAL;
Edgar E. Iglesiasdb3be602013-12-17 15:29:06 +1000508 stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
David Gibsoned120052011-04-01 15:15:33 +1100509
510 return H_SUCCESS;
511}
512
Andreas Färbere2684c02012-03-14 01:38:23 +0100513static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
David Gibsoned120052011-04-01 15:15:33 +1100514{
David Gibson1bfb37d2012-10-08 18:17:38 +0000515 if (env->slb_shadow_addr) {
David Gibsoned120052011-04-01 15:15:33 +1100516 return H_RESOURCE;
517 }
518
David Gibson1bfb37d2012-10-08 18:17:38 +0000519 if (env->dtl_addr) {
David Gibsoned120052011-04-01 15:15:33 +1100520 return H_RESOURCE;
521 }
522
David Gibson1bfb37d2012-10-08 18:17:38 +0000523 env->vpa_addr = 0;
David Gibsoned120052011-04-01 15:15:33 +1100524 return H_SUCCESS;
525}
526
Andreas Färbere2684c02012-03-14 01:38:23 +0100527static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
David Gibsoned120052011-04-01 15:15:33 +1100528{
Andreas Färber33276f12014-03-09 19:29:41 +0100529 CPUState *cs = CPU(ppc_env_get_cpu(env));
David Gibsoned120052011-04-01 15:15:33 +1100530 uint32_t size;
531
532 if (addr == 0) {
533 hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
534 return H_HARDWARE;
535 }
536
Edgar E. Iglesiasfdfba1a2013-11-15 14:46:38 +0100537 size = ldl_be_phys(cs->as, addr + 0x4);
David Gibsoned120052011-04-01 15:15:33 +1100538 if (size < 0x8) {
539 return H_PARAMETER;
540 }
541
542 if ((addr / 4096) != ((addr + size - 1) / 4096)) {
543 return H_PARAMETER;
544 }
545
David Gibson1bfb37d2012-10-08 18:17:38 +0000546 if (!env->vpa_addr) {
David Gibsoned120052011-04-01 15:15:33 +1100547 return H_RESOURCE;
548 }
549
David Gibson1bfb37d2012-10-08 18:17:38 +0000550 env->slb_shadow_addr = addr;
551 env->slb_shadow_size = size;
David Gibsoned120052011-04-01 15:15:33 +1100552
553 return H_SUCCESS;
554}
555
Andreas Färbere2684c02012-03-14 01:38:23 +0100556static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
David Gibsoned120052011-04-01 15:15:33 +1100557{
David Gibson1bfb37d2012-10-08 18:17:38 +0000558 env->slb_shadow_addr = 0;
559 env->slb_shadow_size = 0;
David Gibsoned120052011-04-01 15:15:33 +1100560 return H_SUCCESS;
561}
562
Andreas Färbere2684c02012-03-14 01:38:23 +0100563static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
David Gibsoned120052011-04-01 15:15:33 +1100564{
Andreas Färber33276f12014-03-09 19:29:41 +0100565 CPUState *cs = CPU(ppc_env_get_cpu(env));
David Gibsoned120052011-04-01 15:15:33 +1100566 uint32_t size;
567
568 if (addr == 0) {
569 hcall_dprintf("Can't cope with DTL at logical 0\n");
570 return H_HARDWARE;
571 }
572
Edgar E. Iglesiasfdfba1a2013-11-15 14:46:38 +0100573 size = ldl_be_phys(cs->as, addr + 0x4);
David Gibsoned120052011-04-01 15:15:33 +1100574
575 if (size < 48) {
576 return H_PARAMETER;
577 }
578
David Gibson1bfb37d2012-10-08 18:17:38 +0000579 if (!env->vpa_addr) {
David Gibsoned120052011-04-01 15:15:33 +1100580 return H_RESOURCE;
581 }
582
David Gibson1bfb37d2012-10-08 18:17:38 +0000583 env->dtl_addr = addr;
David Gibsoned120052011-04-01 15:15:33 +1100584 env->dtl_size = size;
585
586 return H_SUCCESS;
587}
588
Peter Portante73f78212012-04-23 07:27:56 +0000589static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr)
David Gibsoned120052011-04-01 15:15:33 +1100590{
David Gibson1bfb37d2012-10-08 18:17:38 +0000591 env->dtl_addr = 0;
David Gibsoned120052011-04-01 15:15:33 +1100592 env->dtl_size = 0;
593
594 return H_SUCCESS;
595}
596
David Gibson28e02042015-07-02 16:23:04 +1000597static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr,
David Gibsoned120052011-04-01 15:15:33 +1100598 target_ulong opcode, target_ulong *args)
599{
600 target_ulong flags = args[0];
601 target_ulong procno = args[1];
602 target_ulong vpa = args[2];
603 target_ulong ret = H_PARAMETER;
Andreas Färbere2684c02012-03-14 01:38:23 +0100604 CPUPPCState *tenv;
Alexey Kardashevskiy0f20ba62014-02-02 01:45:52 +1100605 PowerPCCPU *tcpu;
David Gibsoned120052011-04-01 15:15:33 +1100606
Alexey Kardashevskiy0f20ba62014-02-02 01:45:52 +1100607 tcpu = ppc_get_vcpu_by_dt_id(procno);
Andreas Färber5353d032013-02-15 16:43:08 +0100608 if (!tcpu) {
David Gibsoned120052011-04-01 15:15:33 +1100609 return H_PARAMETER;
610 }
Alexey Kardashevskiy0f20ba62014-02-02 01:45:52 +1100611 tenv = &tcpu->env;
David Gibsoned120052011-04-01 15:15:33 +1100612
613 switch (flags) {
614 case FLAGS_REGISTER_VPA:
615 ret = register_vpa(tenv, vpa);
616 break;
617
618 case FLAGS_DEREGISTER_VPA:
619 ret = deregister_vpa(tenv, vpa);
620 break;
621
622 case FLAGS_REGISTER_SLBSHADOW:
623 ret = register_slb_shadow(tenv, vpa);
624 break;
625
626 case FLAGS_DEREGISTER_SLBSHADOW:
627 ret = deregister_slb_shadow(tenv, vpa);
628 break;
629
630 case FLAGS_REGISTER_DTL:
631 ret = register_dtl(tenv, vpa);
632 break;
633
634 case FLAGS_DEREGISTER_DTL:
635 ret = deregister_dtl(tenv, vpa);
636 break;
637 }
638
639 return ret;
640}
641
David Gibson28e02042015-07-02 16:23:04 +1000642static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr,
David Gibsoned120052011-04-01 15:15:33 +1100643 target_ulong opcode, target_ulong *args)
644{
Andreas Färberb13ce262012-05-03 06:23:01 +0200645 CPUPPCState *env = &cpu->env;
Andreas Färberfcd7d002012-12-17 08:02:44 +0100646 CPUState *cs = CPU(cpu);
Andreas Färberb13ce262012-05-03 06:23:01 +0200647
David Gibsoned120052011-04-01 15:15:33 +1100648 env->msr |= (1ULL << MSR_EE);
649 hreg_compute_hflags(env);
Andreas Färberfcd7d002012-12-17 08:02:44 +0100650 if (!cpu_has_work(cs)) {
Andreas Färber259186a2013-01-17 18:51:17 +0100651 cs->halted = 1;
Andreas Färber27103422013-08-26 08:31:06 +0200652 cs->exception_index = EXCP_HLT;
Andreas Färberfcd7d002012-12-17 08:02:44 +0100653 cs->exit_request = 1;
David Gibsoned120052011-04-01 15:15:33 +1100654 }
655 return H_SUCCESS;
656}
657
David Gibson28e02042015-07-02 16:23:04 +1000658static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr,
David Gibson39ac8452011-04-01 15:15:23 +1100659 target_ulong opcode, target_ulong *args)
660{
661 target_ulong rtas_r3 = args[0];
Alexey Kardashevskiy4fe822e2013-09-27 18:10:18 +1000662 uint32_t token = rtas_ld(rtas_r3, 0);
663 uint32_t nargs = rtas_ld(rtas_r3, 1);
664 uint32_t nret = rtas_ld(rtas_r3, 2);
David Gibson39ac8452011-04-01 15:15:23 +1100665
Anthony Liguori210b5802013-06-19 15:40:30 -0500666 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12,
David Gibson39ac8452011-04-01 15:15:23 +1100667 nret, rtas_r3 + 12 + 4*nargs);
668}
669
David Gibson28e02042015-07-02 16:23:04 +1000670static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr,
David Gibson827200a2011-08-10 14:44:20 +0000671 target_ulong opcode, target_ulong *args)
672{
Edgar E. Iglesiasfdfba1a2013-11-15 14:46:38 +0100673 CPUState *cs = CPU(cpu);
David Gibson827200a2011-08-10 14:44:20 +0000674 target_ulong size = args[0];
675 target_ulong addr = args[1];
676
677 switch (size) {
678 case 1:
Edgar E. Iglesias2c174492013-12-17 14:05:40 +1000679 args[0] = ldub_phys(cs->as, addr);
David Gibson827200a2011-08-10 14:44:20 +0000680 return H_SUCCESS;
681 case 2:
Edgar E. Iglesias41701aa2013-12-17 14:33:56 +1000682 args[0] = lduw_phys(cs->as, addr);
David Gibson827200a2011-08-10 14:44:20 +0000683 return H_SUCCESS;
684 case 4:
Edgar E. Iglesiasfdfba1a2013-11-15 14:46:38 +0100685 args[0] = ldl_phys(cs->as, addr);
David Gibson827200a2011-08-10 14:44:20 +0000686 return H_SUCCESS;
687 case 8:
Edgar E. Iglesias2c174492013-12-17 14:05:40 +1000688 args[0] = ldq_phys(cs->as, addr);
David Gibson827200a2011-08-10 14:44:20 +0000689 return H_SUCCESS;
690 }
691 return H_PARAMETER;
692}
693
David Gibson28e02042015-07-02 16:23:04 +1000694static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr,
David Gibson827200a2011-08-10 14:44:20 +0000695 target_ulong opcode, target_ulong *args)
696{
Edgar E. Iglesiasf6066042013-11-28 00:11:44 +0100697 CPUState *cs = CPU(cpu);
698
David Gibson827200a2011-08-10 14:44:20 +0000699 target_ulong size = args[0];
700 target_ulong addr = args[1];
701 target_ulong val = args[2];
702
703 switch (size) {
704 case 1:
Edgar E. Iglesiasdb3be602013-12-17 15:29:06 +1000705 stb_phys(cs->as, addr, val);
David Gibson827200a2011-08-10 14:44:20 +0000706 return H_SUCCESS;
707 case 2:
Edgar E. Iglesias5ce59442013-12-17 15:22:06 +1000708 stw_phys(cs->as, addr, val);
David Gibson827200a2011-08-10 14:44:20 +0000709 return H_SUCCESS;
710 case 4:
Edgar E. Iglesiasab1da852013-12-17 15:07:29 +1000711 stl_phys(cs->as, addr, val);
David Gibson827200a2011-08-10 14:44:20 +0000712 return H_SUCCESS;
713 case 8:
Edgar E. Iglesiasf6066042013-11-28 00:11:44 +0100714 stq_phys(cs->as, addr, val);
David Gibson827200a2011-08-10 14:44:20 +0000715 return H_SUCCESS;
716 }
717 return H_PARAMETER;
718}
719
David Gibson28e02042015-07-02 16:23:04 +1000720static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr,
Benjamin Herrenschmidtc73e3772012-06-18 20:21:37 +0000721 target_ulong opcode, target_ulong *args)
722{
Edgar E. Iglesiasfdfba1a2013-11-15 14:46:38 +0100723 CPUState *cs = CPU(cpu);
724
Benjamin Herrenschmidtc73e3772012-06-18 20:21:37 +0000725 target_ulong dst = args[0]; /* Destination address */
726 target_ulong src = args[1]; /* Source address */
727 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */
728 target_ulong count = args[3]; /* Element count */
729 target_ulong op = args[4]; /* 0 = copy, 1 = invert */
730 uint64_t tmp;
731 unsigned int mask = (1 << esize) - 1;
732 int step = 1 << esize;
733
734 if (count > 0x80000000) {
735 return H_PARAMETER;
736 }
737
738 if ((dst & mask) || (src & mask) || (op > 1)) {
739 return H_PARAMETER;
740 }
741
742 if (dst >= src && dst < (src + (count << esize))) {
743 dst = dst + ((count - 1) << esize);
744 src = src + ((count - 1) << esize);
745 step = -step;
746 }
747
748 while (count--) {
749 switch (esize) {
750 case 0:
Edgar E. Iglesias2c174492013-12-17 14:05:40 +1000751 tmp = ldub_phys(cs->as, src);
Benjamin Herrenschmidtc73e3772012-06-18 20:21:37 +0000752 break;
753 case 1:
Edgar E. Iglesias41701aa2013-12-17 14:33:56 +1000754 tmp = lduw_phys(cs->as, src);
Benjamin Herrenschmidtc73e3772012-06-18 20:21:37 +0000755 break;
756 case 2:
Edgar E. Iglesiasfdfba1a2013-11-15 14:46:38 +0100757 tmp = ldl_phys(cs->as, src);
Benjamin Herrenschmidtc73e3772012-06-18 20:21:37 +0000758 break;
759 case 3:
Edgar E. Iglesias2c174492013-12-17 14:05:40 +1000760 tmp = ldq_phys(cs->as, src);
Benjamin Herrenschmidtc73e3772012-06-18 20:21:37 +0000761 break;
762 default:
763 return H_PARAMETER;
764 }
765 if (op == 1) {
766 tmp = ~tmp;
767 }
768 switch (esize) {
769 case 0:
Edgar E. Iglesiasdb3be602013-12-17 15:29:06 +1000770 stb_phys(cs->as, dst, tmp);
Benjamin Herrenschmidtc73e3772012-06-18 20:21:37 +0000771 break;
772 case 1:
Edgar E. Iglesias5ce59442013-12-17 15:22:06 +1000773 stw_phys(cs->as, dst, tmp);
Benjamin Herrenschmidtc73e3772012-06-18 20:21:37 +0000774 break;
775 case 2:
Edgar E. Iglesiasab1da852013-12-17 15:07:29 +1000776 stl_phys(cs->as, dst, tmp);
Benjamin Herrenschmidtc73e3772012-06-18 20:21:37 +0000777 break;
778 case 3:
Edgar E. Iglesiasf6066042013-11-28 00:11:44 +0100779 stq_phys(cs->as, dst, tmp);
Benjamin Herrenschmidtc73e3772012-06-18 20:21:37 +0000780 break;
781 }
782 dst = dst + step;
783 src = src + step;
784 }
785
786 return H_SUCCESS;
787}
788
David Gibson28e02042015-07-02 16:23:04 +1000789static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
David Gibson827200a2011-08-10 14:44:20 +0000790 target_ulong opcode, target_ulong *args)
791{
792 /* Nothing to do on emulation, KVM will trap this in the kernel */
793 return H_SUCCESS;
794}
795
David Gibson28e02042015-07-02 16:23:04 +1000796static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr,
David Gibson827200a2011-08-10 14:44:20 +0000797 target_ulong opcode, target_ulong *args)
798{
799 /* Nothing to do on emulation, KVM will trap this in the kernel */
800 return H_SUCCESS;
801}
802
Peter Maydell7d0cd462014-07-08 16:02:26 +0100803static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu,
804 target_ulong mflags,
805 target_ulong value1,
806 target_ulong value2)
Alexey Kardashevskiyc4015bb2014-06-04 22:51:04 +1000807{
808 CPUState *cs;
809
810 if (value1) {
811 return H_P3;
812 }
813 if (value2) {
814 return H_P4;
815 }
816
817 switch (mflags) {
818 case H_SET_MODE_ENDIAN_BIG:
819 CPU_FOREACH(cs) {
820 set_spr(cs, SPR_LPCR, 0, LPCR_ILE);
821 }
David Gibsoneefaccc2015-02-10 15:36:16 +1100822 spapr_pci_switch_vga(true);
Alexey Kardashevskiyc4015bb2014-06-04 22:51:04 +1000823 return H_SUCCESS;
824
825 case H_SET_MODE_ENDIAN_LITTLE:
826 CPU_FOREACH(cs) {
827 set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE);
828 }
David Gibsoneefaccc2015-02-10 15:36:16 +1100829 spapr_pci_switch_vga(false);
Alexey Kardashevskiyc4015bb2014-06-04 22:51:04 +1000830 return H_SUCCESS;
831 }
832
833 return H_UNSUPPORTED_FLAG;
834}
835
Peter Maydell7d0cd462014-07-08 16:02:26 +0100836static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu,
837 target_ulong mflags,
838 target_ulong value1,
839 target_ulong value2)
Alexey Kardashevskiyd5ac4f52014-06-04 22:51:05 +1000840{
841 CPUState *cs;
842 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
Alexey Kardashevskiyd5ac4f52014-06-04 22:51:05 +1000843
844 if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
845 return H_P2;
846 }
847 if (value1) {
848 return H_P3;
849 }
850 if (value2) {
851 return H_P4;
852 }
853
Cédric Le Goater5c94b2a2016-04-03 19:57:50 +0200854 if (mflags == AIL_RESERVED) {
Alexey Kardashevskiyd5ac4f52014-06-04 22:51:05 +1000855 return H_UNSUPPORTED_FLAG;
856 }
857
858 CPU_FOREACH(cs) {
Alexey Kardashevskiyd5ac4f52014-06-04 22:51:05 +1000859 set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL);
Alexey Kardashevskiyd5ac4f52014-06-04 22:51:05 +1000860 }
861
862 return H_SUCCESS;
863}
864
David Gibson28e02042015-07-02 16:23:04 +1000865static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr,
Anton Blanchard42561bf2013-08-19 21:04:20 +1000866 target_ulong opcode, target_ulong *args)
867{
Anton Blanchard42561bf2013-08-19 21:04:20 +1000868 target_ulong resource = args[1];
Anton Blanchard42561bf2013-08-19 21:04:20 +1000869 target_ulong ret = H_P2;
870
Alexey Kardashevskiyc4015bb2014-06-04 22:51:04 +1000871 switch (resource) {
872 case H_SET_MODE_RESOURCE_LE:
Peter Maydell7d0cd462014-07-08 16:02:26 +0100873 ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]);
Alexey Kardashevskiyc4015bb2014-06-04 22:51:04 +1000874 break;
Alexey Kardashevskiyd5ac4f52014-06-04 22:51:05 +1000875 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
Peter Maydell7d0cd462014-07-08 16:02:26 +0100876 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0],
877 args[2], args[3]);
Alexey Kardashevskiyd5ac4f52014-06-04 22:51:05 +1000878 break;
Anton Blanchard42561bf2013-08-19 21:04:20 +1000879 }
880
Anton Blanchard42561bf2013-08-19 21:04:20 +1000881 return ret;
882}
883
Nicholas Piggin1c7ad772016-12-05 16:50:21 +1100884#define H_SIGNAL_SYS_RESET_ALL -1
885#define H_SIGNAL_SYS_RESET_ALLBUTSELF -2
886
887static target_ulong h_signal_sys_reset(PowerPCCPU *cpu,
888 sPAPRMachineState *spapr,
889 target_ulong opcode, target_ulong *args)
890{
891 target_long target = args[0];
892 CPUState *cs;
893
894 if (target < 0) {
895 /* Broadcast */
896 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) {
897 return H_PARAMETER;
898 }
899
900 CPU_FOREACH(cs) {
901 PowerPCCPU *c = POWERPC_CPU(cs);
902
903 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) {
904 if (c == cpu) {
905 continue;
906 }
907 }
908 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
909 }
910 return H_SUCCESS;
911
912 } else {
913 /* Unicast */
914 CPU_FOREACH(cs) {
915 if (cpu->cpu_dt_id == target) {
916 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
917 return H_SUCCESS;
918 }
919 }
920 return H_PARAMETER;
921 }
922}
923
David Gibson152ef802016-11-16 13:54:48 +1100924static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
David Gibson28e02042015-07-02 16:23:04 +1000925 sPAPRMachineState *spapr,
Alexey Kardashevskiy2a6593c2014-05-23 12:26:54 +1000926 target_ulong opcode,
927 target_ulong *args)
928{
David Gibson27ac3e02016-01-19 15:57:59 +1100929 target_ulong list = ppc64_phys_to_real(args[0]);
Michael Rothfacdb8b2016-10-24 23:47:28 -0500930 target_ulong ov_table;
David Gibson152ef802016-11-16 13:54:48 +1100931 bool explicit_match = false; /* Matched the CPU's real PVR */
932 uint32_t max_compat = cpu->max_compat;
933 uint32_t best_compat = 0;
934 int i;
Michael Roth6787d272016-10-24 23:47:29 -0500935 sPAPROptionVector *ov5_guest, *ov5_cas_old, *ov5_updates;
Alexey Kardashevskiy3794d542014-05-23 12:26:57 +1000936
David Gibson152ef802016-11-16 13:54:48 +1100937 /*
938 * We scan the supplied table of PVRs looking for two things
939 * 1. Is our real CPU PVR in the list?
940 * 2. What's the "best" listed logical PVR
941 */
942 for (i = 0; i < 512; ++i) {
Alexey Kardashevskiy3794d542014-05-23 12:26:57 +1000943 uint32_t pvr, pvr_mask;
944
David Gibson27ac3e02016-01-19 15:57:59 +1100945 pvr_mask = ldl_be_phys(&address_space_memory, list);
David Gibson152ef802016-11-16 13:54:48 +1100946 pvr = ldl_be_phys(&address_space_memory, list + 4);
947 list += 8;
Alexey Kardashevskiy3794d542014-05-23 12:26:57 +1000948
Alexey Kardashevskiy3794d542014-05-23 12:26:57 +1000949 if (~pvr_mask & pvr) {
David Gibson152ef802016-11-16 13:54:48 +1100950 break; /* Terminator record */
951 }
952
953 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) {
954 explicit_match = true;
955 } else {
956 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) {
957 best_compat = pvr;
958 }
Alexey Kardashevskiy3794d542014-05-23 12:26:57 +1000959 }
960 }
961
David Gibson152ef802016-11-16 13:54:48 +1100962 if ((best_compat == 0) && (!explicit_match || max_compat)) {
963 /* We couldn't find a suitable compatibility mode, and either
964 * the guest doesn't support "raw" mode for this CPU, or raw
965 * mode is disabled because a maximum compat mode is set */
966 return H_HARDWARE;
967 }
968
Alexey Kardashevskiy3794d542014-05-23 12:26:57 +1000969 /* Parsing finished */
David Gibson152ef802016-11-16 13:54:48 +1100970 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat);
Alexey Kardashevskiy3794d542014-05-23 12:26:57 +1000971
972 /* Update CPUs */
David Gibson152ef802016-11-16 13:54:48 +1100973 if (cpu->compat_pvr != best_compat) {
David Gibsonf6f242c2016-11-10 14:37:38 +1100974 Error *local_err = NULL;
Alexey Kardashevskiy3794d542014-05-23 12:26:57 +1000975
David Gibsonf6f242c2016-11-10 14:37:38 +1100976 ppc_set_compat_all(best_compat, &local_err);
977 if (local_err) {
978 error_report_err(local_err);
979 return H_HARDWARE;
Alexey Kardashevskiy3794d542014-05-23 12:26:57 +1000980 }
981 }
982
Bharata B Rao03d196b2015-07-13 10:34:00 +1000983 /* For the future use: here @ov_table points to the first option vector */
984 ov_table = list;
985
Michael Rothfacdb8b2016-10-24 23:47:28 -0500986 ov5_guest = spapr_ovec_parse_vector(ov_table, 5);
Alexey Kardashevskiy2a6593c2014-05-23 12:26:54 +1000987
Michael Rothfacdb8b2016-10-24 23:47:28 -0500988 /* NOTE: there are actually a number of ov5 bits where input from the
989 * guest is always zero, and the platform/QEMU enables them independently
990 * of guest input. To model these properly we'd want some sort of mask,
991 * but since they only currently apply to memory migration as defined
992 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need
Michael Roth6787d272016-10-24 23:47:29 -0500993 * to worry about this for now.
Michael Rothfacdb8b2016-10-24 23:47:28 -0500994 */
Michael Roth6787d272016-10-24 23:47:29 -0500995 ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas);
996 /* full range of negotiated ov5 capabilities */
Michael Rothfacdb8b2016-10-24 23:47:28 -0500997 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest);
998 spapr_ovec_cleanup(ov5_guest);
Michael Roth6787d272016-10-24 23:47:29 -0500999 /* capabilities that have been added since CAS-generated guest reset.
1000 * if capabilities have since been removed, generate another reset
1001 */
1002 ov5_updates = spapr_ovec_new();
1003 spapr->cas_reboot = spapr_ovec_diff(ov5_updates,
1004 ov5_cas_old, spapr->ov5_cas);
Bharata B Rao03d196b2015-07-13 10:34:00 +10001005
Michael Roth6787d272016-10-24 23:47:29 -05001006 if (!spapr->cas_reboot) {
1007 spapr->cas_reboot =
David Gibson5b120782016-10-29 00:01:05 +11001008 (spapr_h_cas_compose_response(spapr, args[1], args[2],
Michael Roth6787d272016-10-24 23:47:29 -05001009 ov5_updates) != 0);
1010 }
1011 spapr_ovec_cleanup(ov5_updates);
1012
1013 if (spapr->cas_reboot) {
Alexey Kardashevskiy2a6593c2014-05-23 12:26:54 +10001014 qemu_system_reset_request();
1015 }
1016
1017 return H_SUCCESS;
1018}
1019
David Gibson7d7ba3f2011-05-10 16:06:21 +10001020static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
1021static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1];
David Gibson9fdf0c22011-04-01 15:15:20 +11001022
1023void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
1024{
David Gibson39ac8452011-04-01 15:15:23 +11001025 spapr_hcall_fn *slot;
David Gibson9fdf0c22011-04-01 15:15:20 +11001026
David Gibson39ac8452011-04-01 15:15:23 +11001027 if (opcode <= MAX_HCALL_OPCODE) {
1028 assert((opcode & 0x3) == 0);
David Gibson9fdf0c22011-04-01 15:15:20 +11001029
David Gibson39ac8452011-04-01 15:15:23 +11001030 slot = &papr_hypercall_table[opcode / 4];
1031 } else {
1032 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
David Gibson9fdf0c22011-04-01 15:15:20 +11001033
David Gibson39ac8452011-04-01 15:15:23 +11001034 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
1035 }
1036
David Gibsonc89d5292012-10-08 18:17:36 +00001037 assert(!(*slot));
David Gibson39ac8452011-04-01 15:15:23 +11001038 *slot = fn;
David Gibson9fdf0c22011-04-01 15:15:20 +11001039}
1040
Andreas Färberaa100fa2012-05-03 06:13:14 +02001041target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
David Gibson9fdf0c22011-04-01 15:15:20 +11001042 target_ulong *args)
1043{
David Gibson28e02042015-07-02 16:23:04 +10001044 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1045
David Gibson9fdf0c22011-04-01 15:15:20 +11001046 if ((opcode <= MAX_HCALL_OPCODE)
1047 && ((opcode & 0x3) == 0)) {
David Gibson39ac8452011-04-01 15:15:23 +11001048 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
1049
1050 if (fn) {
Andreas Färberb13ce262012-05-03 06:23:01 +02001051 return fn(cpu, spapr, opcode, args);
David Gibson39ac8452011-04-01 15:15:23 +11001052 }
1053 } else if ((opcode >= KVMPPC_HCALL_BASE) &&
1054 (opcode <= KVMPPC_HCALL_MAX)) {
1055 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
David Gibson9fdf0c22011-04-01 15:15:20 +11001056
1057 if (fn) {
Andreas Färberb13ce262012-05-03 06:23:01 +02001058 return fn(cpu, spapr, opcode, args);
David Gibson9fdf0c22011-04-01 15:15:20 +11001059 }
1060 }
1061
Thomas Huthaaf87c62015-09-01 11:29:02 +10001062 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n",
1063 opcode);
David Gibson9fdf0c22011-04-01 15:15:20 +11001064 return H_FUNCTION;
1065}
David Gibsonf43e3522011-04-01 15:15:22 +11001066
Andreas Färber83f7d432012-02-09 15:20:55 +01001067static void hypercall_register_types(void)
David Gibsonf43e3522011-04-01 15:15:22 +11001068{
1069 /* hcall-pft */
1070 spapr_register_hypercall(H_ENTER, h_enter);
1071 spapr_register_hypercall(H_REMOVE, h_remove);
1072 spapr_register_hypercall(H_PROTECT, h_protect);
Erlon Cruz6bbd5dd2013-02-18 05:00:32 +00001073 spapr_register_hypercall(H_READ, h_read);
David Gibson39ac8452011-04-01 15:15:23 +11001074
David Gibsona3d0aba2011-08-31 15:50:50 +00001075 /* hcall-bulk */
1076 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);
1077
David Gibsoned120052011-04-01 15:15:33 +11001078 /* hcall-splpar */
1079 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa);
1080 spapr_register_hypercall(H_CEDE, h_cede);
Nicholas Piggin1c7ad772016-12-05 16:50:21 +11001081 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset);
David Gibsoned120052011-04-01 15:15:33 +11001082
Thomas Huth423576f2016-02-11 13:47:18 +01001083 /* processor register resource access h-calls */
1084 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0);
Thomas Huthaf08a582016-02-11 13:47:19 +01001085 spapr_register_hypercall(H_SET_DABR, h_set_dabr);
Thomas Huthe49ff262016-02-11 13:47:20 +01001086 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr);
Thomas Huth3240dd92016-02-18 10:15:54 +01001087 spapr_register_hypercall(H_PAGE_INIT, h_page_init);
Thomas Huth423576f2016-02-11 13:47:18 +01001088 spapr_register_hypercall(H_SET_MODE, h_set_mode);
1089
David Gibson827200a2011-08-10 14:44:20 +00001090 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
1091 * here between the "CI" and the "CACHE" variants, they will use whatever
1092 * mapping attributes qemu is using. When using KVM, the kernel will
1093 * enforce the attributes more strongly
1094 */
1095 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load);
1096 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store);
1097 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load);
1098 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store);
1099 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi);
1100 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf);
Benjamin Herrenschmidtc73e3772012-06-18 20:21:37 +00001101 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop);
David Gibson827200a2011-08-10 14:44:20 +00001102
David Gibson39ac8452011-04-01 15:15:23 +11001103 /* qemu/KVM-PPC specific hcalls */
1104 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
Anton Blanchard42561bf2013-08-19 21:04:20 +10001105
Alexey Kardashevskiy2a6593c2014-05-23 12:26:54 +10001106 /* ibm,client-architecture-support support */
1107 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support);
David Gibsonf43e3522011-04-01 15:15:22 +11001108}
Andreas Färber83f7d432012-02-09 15:20:55 +01001109
1110type_init(hypercall_register_types)