blob: c1e56be74e5cb8cef695f79d0088616ca06068c1 [file] [log] [blame]
ths5fafdf22007-09-16 21:08:06 +00001/*
pbrookcdbdb642006-04-09 01:32:52 +00002 * ARM PrimeCell Timer modules.
3 *
4 * Copyright (c) 2005-2006 CodeSourcery.
5 * Written by Paul Brook
6 *
Matthew Fernandez8e31bf32011-06-26 12:21:35 +10007 * This code is licensed under the GPL.
pbrookcdbdb642006-04-09 01:32:52 +00008 */
9
Paul Brook6a824ec2009-05-14 22:35:07 +010010#include "sysbus.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010011#include "qemu/timer.h"
Mark Langsdorf104a26a2011-12-29 06:19:51 +000012#include "qemu-common.h"
13#include "qdev.h"
Paolo Bonzini49d4d9b62012-01-13 17:07:19 +010014#include "ptimer.h"
pbrookcdbdb642006-04-09 01:32:52 +000015
16/* Common timer implementation. */
17
18#define TIMER_CTRL_ONESHOT (1 << 0)
19#define TIMER_CTRL_32BIT (1 << 1)
20#define TIMER_CTRL_DIV1 (0 << 2)
21#define TIMER_CTRL_DIV16 (1 << 2)
22#define TIMER_CTRL_DIV256 (2 << 2)
23#define TIMER_CTRL_IE (1 << 5)
24#define TIMER_CTRL_PERIODIC (1 << 6)
25#define TIMER_CTRL_ENABLE (1 << 7)
26
27typedef struct {
pbrook423f0742007-05-23 00:06:54 +000028 ptimer_state *timer;
pbrookcdbdb642006-04-09 01:32:52 +000029 uint32_t control;
pbrookcdbdb642006-04-09 01:32:52 +000030 uint32_t limit;
pbrookcdbdb642006-04-09 01:32:52 +000031 int freq;
32 int int_level;
pbrookd537cf62007-04-07 18:14:41 +000033 qemu_irq irq;
pbrookcdbdb642006-04-09 01:32:52 +000034} arm_timer_state;
35
pbrookcdbdb642006-04-09 01:32:52 +000036/* Check all active timers, and schedule the next timer interrupt. */
37
pbrook423f0742007-05-23 00:06:54 +000038static void arm_timer_update(arm_timer_state *s)
pbrookcdbdb642006-04-09 01:32:52 +000039{
pbrookcdbdb642006-04-09 01:32:52 +000040 /* Update interrupts. */
41 if (s->int_level && (s->control & TIMER_CTRL_IE)) {
pbrookd537cf62007-04-07 18:14:41 +000042 qemu_irq_raise(s->irq);
pbrookcdbdb642006-04-09 01:32:52 +000043 } else {
pbrookd537cf62007-04-07 18:14:41 +000044 qemu_irq_lower(s->irq);
pbrookcdbdb642006-04-09 01:32:52 +000045 }
pbrookcdbdb642006-04-09 01:32:52 +000046}
47
Avi Kivitya8170e52012-10-23 12:30:10 +020048static uint32_t arm_timer_read(void *opaque, hwaddr offset)
pbrookcdbdb642006-04-09 01:32:52 +000049{
50 arm_timer_state *s = (arm_timer_state *)opaque;
51
52 switch (offset >> 2) {
53 case 0: /* TimerLoad */
54 case 6: /* TimerBGLoad */
55 return s->limit;
56 case 1: /* TimerValue */
pbrook423f0742007-05-23 00:06:54 +000057 return ptimer_get_count(s->timer);
pbrookcdbdb642006-04-09 01:32:52 +000058 case 2: /* TimerControl */
59 return s->control;
60 case 4: /* TimerRIS */
61 return s->int_level;
62 case 5: /* TimerMIS */
63 if ((s->control & TIMER_CTRL_IE) == 0)
64 return 0;
65 return s->int_level;
66 default:
Peter Maydelledb94a42012-10-30 07:45:10 +000067 qemu_log_mask(LOG_GUEST_ERROR,
68 "%s: Bad offset %x\n", __func__, (int)offset);
pbrookcdbdb642006-04-09 01:32:52 +000069 return 0;
70 }
71}
72
pbrook423f0742007-05-23 00:06:54 +000073/* Reset the timer limit after settings have changed. */
74static void arm_timer_recalibrate(arm_timer_state *s, int reload)
75{
76 uint32_t limit;
77
Rabin Vincenta9cf98d2010-05-02 15:20:52 +053078 if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
pbrook423f0742007-05-23 00:06:54 +000079 /* Free running. */
80 if (s->control & TIMER_CTRL_32BIT)
81 limit = 0xffffffff;
82 else
83 limit = 0xffff;
84 } else {
85 /* Periodic. */
86 limit = s->limit;
87 }
88 ptimer_set_limit(s->timer, limit, reload);
89}
90
Avi Kivitya8170e52012-10-23 12:30:10 +020091static void arm_timer_write(void *opaque, hwaddr offset,
pbrookcdbdb642006-04-09 01:32:52 +000092 uint32_t value)
93{
94 arm_timer_state *s = (arm_timer_state *)opaque;
pbrook423f0742007-05-23 00:06:54 +000095 int freq;
pbrookcdbdb642006-04-09 01:32:52 +000096
pbrookcdbdb642006-04-09 01:32:52 +000097 switch (offset >> 2) {
98 case 0: /* TimerLoad */
99 s->limit = value;
pbrook423f0742007-05-23 00:06:54 +0000100 arm_timer_recalibrate(s, 1);
pbrookcdbdb642006-04-09 01:32:52 +0000101 break;
102 case 1: /* TimerValue */
103 /* ??? Linux seems to want to write to this readonly register.
104 Ignore it. */
105 break;
106 case 2: /* TimerControl */
107 if (s->control & TIMER_CTRL_ENABLE) {
108 /* Pause the timer if it is running. This may cause some
109 inaccuracy dure to rounding, but avoids a whole lot of other
110 messyness. */
pbrook423f0742007-05-23 00:06:54 +0000111 ptimer_stop(s->timer);
pbrookcdbdb642006-04-09 01:32:52 +0000112 }
113 s->control = value;
pbrook423f0742007-05-23 00:06:54 +0000114 freq = s->freq;
pbrookcdbdb642006-04-09 01:32:52 +0000115 /* ??? Need to recalculate expiry time after changing divisor. */
116 switch ((value >> 2) & 3) {
pbrook423f0742007-05-23 00:06:54 +0000117 case 1: freq >>= 4; break;
118 case 2: freq >>= 8; break;
pbrookcdbdb642006-04-09 01:32:52 +0000119 }
Rabin Vincentd6759902010-05-02 15:20:51 +0530120 arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
pbrook423f0742007-05-23 00:06:54 +0000121 ptimer_set_freq(s->timer, freq);
pbrookcdbdb642006-04-09 01:32:52 +0000122 if (s->control & TIMER_CTRL_ENABLE) {
123 /* Restart the timer if still enabled. */
pbrook423f0742007-05-23 00:06:54 +0000124 ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
pbrookcdbdb642006-04-09 01:32:52 +0000125 }
126 break;
127 case 3: /* TimerIntClr */
128 s->int_level = 0;
129 break;
130 case 6: /* TimerBGLoad */
131 s->limit = value;
pbrook423f0742007-05-23 00:06:54 +0000132 arm_timer_recalibrate(s, 0);
pbrookcdbdb642006-04-09 01:32:52 +0000133 break;
134 default:
Peter Maydelledb94a42012-10-30 07:45:10 +0000135 qemu_log_mask(LOG_GUEST_ERROR,
136 "%s: Bad offset %x\n", __func__, (int)offset);
pbrookcdbdb642006-04-09 01:32:52 +0000137 }
pbrook423f0742007-05-23 00:06:54 +0000138 arm_timer_update(s);
pbrookcdbdb642006-04-09 01:32:52 +0000139}
140
141static void arm_timer_tick(void *opaque)
142{
pbrook423f0742007-05-23 00:06:54 +0000143 arm_timer_state *s = (arm_timer_state *)opaque;
144 s->int_level = 1;
145 arm_timer_update(s);
pbrookcdbdb642006-04-09 01:32:52 +0000146}
147
Juan Quintelaeecd33a2010-12-01 23:15:41 +0100148static const VMStateDescription vmstate_arm_timer = {
149 .name = "arm_timer",
150 .version_id = 1,
151 .minimum_version_id = 1,
152 .minimum_version_id_old = 1,
153 .fields = (VMStateField[]) {
154 VMSTATE_UINT32(control, arm_timer_state),
155 VMSTATE_UINT32(limit, arm_timer_state),
156 VMSTATE_INT32(int_level, arm_timer_state),
157 VMSTATE_PTIMER(timer, arm_timer_state),
158 VMSTATE_END_OF_LIST()
159 }
160};
pbrook23e39292008-07-02 16:48:32 +0000161
Paul Brook6a824ec2009-05-14 22:35:07 +0100162static arm_timer_state *arm_timer_init(uint32_t freq)
pbrookcdbdb642006-04-09 01:32:52 +0000163{
164 arm_timer_state *s;
pbrook423f0742007-05-23 00:06:54 +0000165 QEMUBH *bh;
pbrookcdbdb642006-04-09 01:32:52 +0000166
Anthony Liguori7267c092011-08-20 22:09:37 -0500167 s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
pbrook423f0742007-05-23 00:06:54 +0000168 s->freq = freq;
pbrookcdbdb642006-04-09 01:32:52 +0000169 s->control = TIMER_CTRL_IE;
pbrookcdbdb642006-04-09 01:32:52 +0000170
pbrook423f0742007-05-23 00:06:54 +0000171 bh = qemu_bh_new(arm_timer_tick, s);
172 s->timer = ptimer_init(bh);
Juan Quintelaeecd33a2010-12-01 23:15:41 +0100173 vmstate_register(NULL, -1, &vmstate_arm_timer, s);
pbrookcdbdb642006-04-09 01:32:52 +0000174 return s;
175}
176
177/* ARM PrimeCell SP804 dual timer module.
Peter Chubb7b4252e2011-12-12 10:25:42 +0000178 * Docs at
179 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
180*/
pbrookcdbdb642006-04-09 01:32:52 +0000181
182typedef struct {
Paul Brook6a824ec2009-05-14 22:35:07 +0100183 SysBusDevice busdev;
Avi Kivitye219dea2011-08-15 17:17:19 +0300184 MemoryRegion iomem;
Paul Brook6a824ec2009-05-14 22:35:07 +0100185 arm_timer_state *timer[2];
Mark Langsdorf104a26a2011-12-29 06:19:51 +0000186 uint32_t freq0, freq1;
pbrookcdbdb642006-04-09 01:32:52 +0000187 int level[2];
pbrookd537cf62007-04-07 18:14:41 +0000188 qemu_irq irq;
pbrookcdbdb642006-04-09 01:32:52 +0000189} sp804_state;
190
Peter Chubb7b4252e2011-12-12 10:25:42 +0000191static const uint8_t sp804_ids[] = {
192 /* Timer ID */
193 0x04, 0x18, 0x14, 0,
194 /* PrimeCell ID */
195 0xd, 0xf0, 0x05, 0xb1
196};
197
pbrookd537cf62007-04-07 18:14:41 +0000198/* Merge the IRQs from the two component devices. */
pbrookcdbdb642006-04-09 01:32:52 +0000199static void sp804_set_irq(void *opaque, int irq, int level)
200{
201 sp804_state *s = (sp804_state *)opaque;
202
203 s->level[irq] = level;
pbrookd537cf62007-04-07 18:14:41 +0000204 qemu_set_irq(s->irq, s->level[0] || s->level[1]);
pbrookcdbdb642006-04-09 01:32:52 +0000205}
206
Avi Kivitya8170e52012-10-23 12:30:10 +0200207static uint64_t sp804_read(void *opaque, hwaddr offset,
Avi Kivitye219dea2011-08-15 17:17:19 +0300208 unsigned size)
pbrookcdbdb642006-04-09 01:32:52 +0000209{
210 sp804_state *s = (sp804_state *)opaque;
211
pbrookcdbdb642006-04-09 01:32:52 +0000212 if (offset < 0x20) {
213 return arm_timer_read(s->timer[0], offset);
Peter Chubb7b4252e2011-12-12 10:25:42 +0000214 }
215 if (offset < 0x40) {
pbrookcdbdb642006-04-09 01:32:52 +0000216 return arm_timer_read(s->timer[1], offset - 0x20);
217 }
Peter Chubb7b4252e2011-12-12 10:25:42 +0000218
219 /* TimerPeriphID */
220 if (offset >= 0xfe0 && offset <= 0xffc) {
221 return sp804_ids[(offset - 0xfe0) >> 2];
222 }
223
224 switch (offset) {
225 /* Integration Test control registers, which we won't support */
226 case 0xf00: /* TimerITCR */
227 case 0xf04: /* TimerITOP (strictly write only but..) */
Peter Maydelledb94a42012-10-30 07:45:10 +0000228 qemu_log_mask(LOG_UNIMP,
229 "%s: integration test registers unimplemented\n",
230 __func__);
Peter Chubb7b4252e2011-12-12 10:25:42 +0000231 return 0;
232 }
233
Peter Maydelledb94a42012-10-30 07:45:10 +0000234 qemu_log_mask(LOG_GUEST_ERROR,
235 "%s: Bad offset %x\n", __func__, (int)offset);
Peter Chubb7b4252e2011-12-12 10:25:42 +0000236 return 0;
pbrookcdbdb642006-04-09 01:32:52 +0000237}
238
Avi Kivitya8170e52012-10-23 12:30:10 +0200239static void sp804_write(void *opaque, hwaddr offset,
Avi Kivitye219dea2011-08-15 17:17:19 +0300240 uint64_t value, unsigned size)
pbrookcdbdb642006-04-09 01:32:52 +0000241{
242 sp804_state *s = (sp804_state *)opaque;
243
pbrookcdbdb642006-04-09 01:32:52 +0000244 if (offset < 0x20) {
245 arm_timer_write(s->timer[0], offset, value);
Peter Chubb7b4252e2011-12-12 10:25:42 +0000246 return;
pbrookcdbdb642006-04-09 01:32:52 +0000247 }
Peter Chubb7b4252e2011-12-12 10:25:42 +0000248
249 if (offset < 0x40) {
250 arm_timer_write(s->timer[1], offset - 0x20, value);
251 return;
252 }
253
254 /* Technically we could be writing to the Test Registers, but not likely */
Peter Maydelledb94a42012-10-30 07:45:10 +0000255 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n",
256 __func__, (int)offset);
pbrookcdbdb642006-04-09 01:32:52 +0000257}
258
Avi Kivitye219dea2011-08-15 17:17:19 +0300259static const MemoryRegionOps sp804_ops = {
260 .read = sp804_read,
261 .write = sp804_write,
262 .endianness = DEVICE_NATIVE_ENDIAN,
pbrookcdbdb642006-04-09 01:32:52 +0000263};
264
Juan Quintela81986ac2010-12-01 23:12:32 +0100265static const VMStateDescription vmstate_sp804 = {
266 .name = "sp804",
267 .version_id = 1,
268 .minimum_version_id = 1,
269 .minimum_version_id_old = 1,
270 .fields = (VMStateField[]) {
271 VMSTATE_INT32_ARRAY(level, sp804_state, 2),
272 VMSTATE_END_OF_LIST()
273 }
274};
pbrook23e39292008-07-02 16:48:32 +0000275
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200276static int sp804_init(SysBusDevice *dev)
pbrookcdbdb642006-04-09 01:32:52 +0000277{
Paul Brook6a824ec2009-05-14 22:35:07 +0100278 sp804_state *s = FROM_SYSBUS(sp804_state, dev);
pbrookd537cf62007-04-07 18:14:41 +0000279 qemu_irq *qi;
pbrookcdbdb642006-04-09 01:32:52 +0000280
pbrookd537cf62007-04-07 18:14:41 +0000281 qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
Paul Brook6a824ec2009-05-14 22:35:07 +0100282 sysbus_init_irq(dev, &s->irq);
Mark Langsdorf104a26a2011-12-29 06:19:51 +0000283 s->timer[0] = arm_timer_init(s->freq0);
284 s->timer[1] = arm_timer_init(s->freq1);
Paul Brook6a824ec2009-05-14 22:35:07 +0100285 s->timer[0]->irq = qi[0];
286 s->timer[1]->irq = qi[1];
Avi Kivitye219dea2011-08-15 17:17:19 +0300287 memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
Avi Kivity750ecd42011-11-27 11:38:10 +0200288 sysbus_init_mmio(dev, &s->iomem);
Juan Quintela81986ac2010-12-01 23:12:32 +0100289 vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200290 return 0;
pbrookcdbdb642006-04-09 01:32:52 +0000291}
292
pbrookcdbdb642006-04-09 01:32:52 +0000293/* Integrator/CP timer module. */
294
295typedef struct {
Paul Brook6a824ec2009-05-14 22:35:07 +0100296 SysBusDevice busdev;
Avi Kivitye219dea2011-08-15 17:17:19 +0300297 MemoryRegion iomem;
Paul Brook6a824ec2009-05-14 22:35:07 +0100298 arm_timer_state *timer[3];
pbrookcdbdb642006-04-09 01:32:52 +0000299} icp_pit_state;
300
Avi Kivitya8170e52012-10-23 12:30:10 +0200301static uint64_t icp_pit_read(void *opaque, hwaddr offset,
Avi Kivitye219dea2011-08-15 17:17:19 +0300302 unsigned size)
pbrookcdbdb642006-04-09 01:32:52 +0000303{
304 icp_pit_state *s = (icp_pit_state *)opaque;
305 int n;
306
307 /* ??? Don't know the PrimeCell ID for this device. */
pbrookcdbdb642006-04-09 01:32:52 +0000308 n = offset >> 8;
Peter Maydellee71c982011-11-11 13:30:15 +0000309 if (n > 2) {
Peter Maydelledb94a42012-10-30 07:45:10 +0000310 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
Paul Brook2ac71172009-05-08 02:35:15 +0100311 }
pbrookcdbdb642006-04-09 01:32:52 +0000312
313 return arm_timer_read(s->timer[n], offset & 0xff);
314}
315
Avi Kivitya8170e52012-10-23 12:30:10 +0200316static void icp_pit_write(void *opaque, hwaddr offset,
Avi Kivitye219dea2011-08-15 17:17:19 +0300317 uint64_t value, unsigned size)
pbrookcdbdb642006-04-09 01:32:52 +0000318{
319 icp_pit_state *s = (icp_pit_state *)opaque;
320 int n;
321
pbrookcdbdb642006-04-09 01:32:52 +0000322 n = offset >> 8;
Peter Maydellee71c982011-11-11 13:30:15 +0000323 if (n > 2) {
Peter Maydelledb94a42012-10-30 07:45:10 +0000324 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
Paul Brook2ac71172009-05-08 02:35:15 +0100325 }
pbrookcdbdb642006-04-09 01:32:52 +0000326
327 arm_timer_write(s->timer[n], offset & 0xff, value);
328}
329
Avi Kivitye219dea2011-08-15 17:17:19 +0300330static const MemoryRegionOps icp_pit_ops = {
331 .read = icp_pit_read,
332 .write = icp_pit_write,
333 .endianness = DEVICE_NATIVE_ENDIAN,
pbrookcdbdb642006-04-09 01:32:52 +0000334};
335
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200336static int icp_pit_init(SysBusDevice *dev)
pbrookcdbdb642006-04-09 01:32:52 +0000337{
Paul Brook6a824ec2009-05-14 22:35:07 +0100338 icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
pbrookcdbdb642006-04-09 01:32:52 +0000339
pbrookcdbdb642006-04-09 01:32:52 +0000340 /* Timer 0 runs at the system clock speed (40MHz). */
Paul Brook6a824ec2009-05-14 22:35:07 +0100341 s->timer[0] = arm_timer_init(40000000);
pbrookcdbdb642006-04-09 01:32:52 +0000342 /* The other two timers run at 1MHz. */
Paul Brook6a824ec2009-05-14 22:35:07 +0100343 s->timer[1] = arm_timer_init(1000000);
344 s->timer[2] = arm_timer_init(1000000);
345
346 sysbus_init_irq(dev, &s->timer[0]->irq);
347 sysbus_init_irq(dev, &s->timer[1]->irq);
348 sysbus_init_irq(dev, &s->timer[2]->irq);
pbrookcdbdb642006-04-09 01:32:52 +0000349
Avi Kivitye219dea2011-08-15 17:17:19 +0300350 memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000);
Avi Kivity750ecd42011-11-27 11:38:10 +0200351 sysbus_init_mmio(dev, &s->iomem);
pbrook23e39292008-07-02 16:48:32 +0000352 /* This device has no state to save/restore. The component timers will
353 save themselves. */
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200354 return 0;
pbrookcdbdb642006-04-09 01:32:52 +0000355}
Paul Brook6a824ec2009-05-14 22:35:07 +0100356
Anthony Liguori999e12b2012-01-24 13:12:29 -0600357static void icp_pit_class_init(ObjectClass *klass, void *data)
358{
359 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
360
361 sdc->init = icp_pit_init;
362}
363
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100364static const TypeInfo icp_pit_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600365 .name = "integrator_pit",
366 .parent = TYPE_SYS_BUS_DEVICE,
367 .instance_size = sizeof(icp_pit_state),
368 .class_init = icp_pit_class_init,
369};
370
371static Property sp804_properties[] = {
372 DEFINE_PROP_UINT32("freq0", sp804_state, freq0, 1000000),
373 DEFINE_PROP_UINT32("freq1", sp804_state, freq1, 1000000),
374 DEFINE_PROP_END_OF_LIST(),
Anthony Liguori999e12b2012-01-24 13:12:29 -0600375};
376
377static void sp804_class_init(ObjectClass *klass, void *data)
378{
379 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
Anthony Liguori39bffca2011-12-07 21:34:16 -0600380 DeviceClass *k = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600381
382 sdc->init = sp804_init;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600383 k->props = sp804_properties;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600384}
385
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100386static const TypeInfo sp804_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600387 .name = "sp804",
388 .parent = TYPE_SYS_BUS_DEVICE,
389 .instance_size = sizeof(sp804_state),
390 .class_init = sp804_class_init,
Anthony Liguori999e12b2012-01-24 13:12:29 -0600391};
392
Andreas Färber83f7d432012-02-09 15:20:55 +0100393static void arm_timer_register_types(void)
Paul Brook6a824ec2009-05-14 22:35:07 +0100394{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600395 type_register_static(&icp_pit_info);
396 type_register_static(&sp804_info);
Paul Brook6a824ec2009-05-14 22:35:07 +0100397}
398
Andreas Färber83f7d432012-02-09 15:20:55 +0100399type_init(arm_timer_register_types)