ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1 | /* |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 2 | * ARM PrimeCell Timer modules. |
| 3 | * |
| 4 | * Copyright (c) 2005-2006 CodeSourcery. |
| 5 | * Written by Paul Brook |
| 6 | * |
Matthew Fernandez | 8e31bf3 | 2011-06-26 12:21:35 +1000 | [diff] [blame] | 7 | * This code is licensed under the GPL. |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 10 | #include "sysbus.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 11 | #include "qemu/timer.h" |
Mark Langsdorf | 104a26a | 2011-12-29 06:19:51 +0000 | [diff] [blame] | 12 | #include "qemu-common.h" |
| 13 | #include "qdev.h" |
Paolo Bonzini | 49d4d9b6 | 2012-01-13 17:07:19 +0100 | [diff] [blame] | 14 | #include "ptimer.h" |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 15 | |
| 16 | /* Common timer implementation. */ |
| 17 | |
| 18 | #define TIMER_CTRL_ONESHOT (1 << 0) |
| 19 | #define TIMER_CTRL_32BIT (1 << 1) |
| 20 | #define TIMER_CTRL_DIV1 (0 << 2) |
| 21 | #define TIMER_CTRL_DIV16 (1 << 2) |
| 22 | #define TIMER_CTRL_DIV256 (2 << 2) |
| 23 | #define TIMER_CTRL_IE (1 << 5) |
| 24 | #define TIMER_CTRL_PERIODIC (1 << 6) |
| 25 | #define TIMER_CTRL_ENABLE (1 << 7) |
| 26 | |
| 27 | typedef struct { |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 28 | ptimer_state *timer; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 29 | uint32_t control; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 30 | uint32_t limit; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 31 | int freq; |
| 32 | int int_level; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 33 | qemu_irq irq; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 34 | } arm_timer_state; |
| 35 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 36 | /* Check all active timers, and schedule the next timer interrupt. */ |
| 37 | |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 38 | static void arm_timer_update(arm_timer_state *s) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 39 | { |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 40 | /* Update interrupts. */ |
| 41 | if (s->int_level && (s->control & TIMER_CTRL_IE)) { |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 42 | qemu_irq_raise(s->irq); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 43 | } else { |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 44 | qemu_irq_lower(s->irq); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 45 | } |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 46 | } |
| 47 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 48 | static uint32_t arm_timer_read(void *opaque, hwaddr offset) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 49 | { |
| 50 | arm_timer_state *s = (arm_timer_state *)opaque; |
| 51 | |
| 52 | switch (offset >> 2) { |
| 53 | case 0: /* TimerLoad */ |
| 54 | case 6: /* TimerBGLoad */ |
| 55 | return s->limit; |
| 56 | case 1: /* TimerValue */ |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 57 | return ptimer_get_count(s->timer); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 58 | case 2: /* TimerControl */ |
| 59 | return s->control; |
| 60 | case 4: /* TimerRIS */ |
| 61 | return s->int_level; |
| 62 | case 5: /* TimerMIS */ |
| 63 | if ((s->control & TIMER_CTRL_IE) == 0) |
| 64 | return 0; |
| 65 | return s->int_level; |
| 66 | default: |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 67 | qemu_log_mask(LOG_GUEST_ERROR, |
| 68 | "%s: Bad offset %x\n", __func__, (int)offset); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 69 | return 0; |
| 70 | } |
| 71 | } |
| 72 | |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 73 | /* Reset the timer limit after settings have changed. */ |
| 74 | static void arm_timer_recalibrate(arm_timer_state *s, int reload) |
| 75 | { |
| 76 | uint32_t limit; |
| 77 | |
Rabin Vincent | a9cf98d | 2010-05-02 15:20:52 +0530 | [diff] [blame] | 78 | if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) { |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 79 | /* Free running. */ |
| 80 | if (s->control & TIMER_CTRL_32BIT) |
| 81 | limit = 0xffffffff; |
| 82 | else |
| 83 | limit = 0xffff; |
| 84 | } else { |
| 85 | /* Periodic. */ |
| 86 | limit = s->limit; |
| 87 | } |
| 88 | ptimer_set_limit(s->timer, limit, reload); |
| 89 | } |
| 90 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 91 | static void arm_timer_write(void *opaque, hwaddr offset, |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 92 | uint32_t value) |
| 93 | { |
| 94 | arm_timer_state *s = (arm_timer_state *)opaque; |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 95 | int freq; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 96 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 97 | switch (offset >> 2) { |
| 98 | case 0: /* TimerLoad */ |
| 99 | s->limit = value; |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 100 | arm_timer_recalibrate(s, 1); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 101 | break; |
| 102 | case 1: /* TimerValue */ |
| 103 | /* ??? Linux seems to want to write to this readonly register. |
| 104 | Ignore it. */ |
| 105 | break; |
| 106 | case 2: /* TimerControl */ |
| 107 | if (s->control & TIMER_CTRL_ENABLE) { |
| 108 | /* Pause the timer if it is running. This may cause some |
| 109 | inaccuracy dure to rounding, but avoids a whole lot of other |
| 110 | messyness. */ |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 111 | ptimer_stop(s->timer); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 112 | } |
| 113 | s->control = value; |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 114 | freq = s->freq; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 115 | /* ??? Need to recalculate expiry time after changing divisor. */ |
| 116 | switch ((value >> 2) & 3) { |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 117 | case 1: freq >>= 4; break; |
| 118 | case 2: freq >>= 8; break; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 119 | } |
Rabin Vincent | d675990 | 2010-05-02 15:20:51 +0530 | [diff] [blame] | 120 | arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 121 | ptimer_set_freq(s->timer, freq); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 122 | if (s->control & TIMER_CTRL_ENABLE) { |
| 123 | /* Restart the timer if still enabled. */ |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 124 | ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 125 | } |
| 126 | break; |
| 127 | case 3: /* TimerIntClr */ |
| 128 | s->int_level = 0; |
| 129 | break; |
| 130 | case 6: /* TimerBGLoad */ |
| 131 | s->limit = value; |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 132 | arm_timer_recalibrate(s, 0); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 133 | break; |
| 134 | default: |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 135 | qemu_log_mask(LOG_GUEST_ERROR, |
| 136 | "%s: Bad offset %x\n", __func__, (int)offset); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 137 | } |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 138 | arm_timer_update(s); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | static void arm_timer_tick(void *opaque) |
| 142 | { |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 143 | arm_timer_state *s = (arm_timer_state *)opaque; |
| 144 | s->int_level = 1; |
| 145 | arm_timer_update(s); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 146 | } |
| 147 | |
Juan Quintela | eecd33a | 2010-12-01 23:15:41 +0100 | [diff] [blame] | 148 | static const VMStateDescription vmstate_arm_timer = { |
| 149 | .name = "arm_timer", |
| 150 | .version_id = 1, |
| 151 | .minimum_version_id = 1, |
| 152 | .minimum_version_id_old = 1, |
| 153 | .fields = (VMStateField[]) { |
| 154 | VMSTATE_UINT32(control, arm_timer_state), |
| 155 | VMSTATE_UINT32(limit, arm_timer_state), |
| 156 | VMSTATE_INT32(int_level, arm_timer_state), |
| 157 | VMSTATE_PTIMER(timer, arm_timer_state), |
| 158 | VMSTATE_END_OF_LIST() |
| 159 | } |
| 160 | }; |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 161 | |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 162 | static arm_timer_state *arm_timer_init(uint32_t freq) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 163 | { |
| 164 | arm_timer_state *s; |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 165 | QEMUBH *bh; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 166 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 167 | s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state)); |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 168 | s->freq = freq; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 169 | s->control = TIMER_CTRL_IE; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 170 | |
pbrook | 423f074 | 2007-05-23 00:06:54 +0000 | [diff] [blame] | 171 | bh = qemu_bh_new(arm_timer_tick, s); |
| 172 | s->timer = ptimer_init(bh); |
Juan Quintela | eecd33a | 2010-12-01 23:15:41 +0100 | [diff] [blame] | 173 | vmstate_register(NULL, -1, &vmstate_arm_timer, s); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 174 | return s; |
| 175 | } |
| 176 | |
| 177 | /* ARM PrimeCell SP804 dual timer module. |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 178 | * Docs at |
| 179 | * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html |
| 180 | */ |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 181 | |
| 182 | typedef struct { |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 183 | SysBusDevice busdev; |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 184 | MemoryRegion iomem; |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 185 | arm_timer_state *timer[2]; |
Mark Langsdorf | 104a26a | 2011-12-29 06:19:51 +0000 | [diff] [blame] | 186 | uint32_t freq0, freq1; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 187 | int level[2]; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 188 | qemu_irq irq; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 189 | } sp804_state; |
| 190 | |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 191 | static const uint8_t sp804_ids[] = { |
| 192 | /* Timer ID */ |
| 193 | 0x04, 0x18, 0x14, 0, |
| 194 | /* PrimeCell ID */ |
| 195 | 0xd, 0xf0, 0x05, 0xb1 |
| 196 | }; |
| 197 | |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 198 | /* Merge the IRQs from the two component devices. */ |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 199 | static void sp804_set_irq(void *opaque, int irq, int level) |
| 200 | { |
| 201 | sp804_state *s = (sp804_state *)opaque; |
| 202 | |
| 203 | s->level[irq] = level; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 204 | qemu_set_irq(s->irq, s->level[0] || s->level[1]); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 205 | } |
| 206 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 207 | static uint64_t sp804_read(void *opaque, hwaddr offset, |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 208 | unsigned size) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 209 | { |
| 210 | sp804_state *s = (sp804_state *)opaque; |
| 211 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 212 | if (offset < 0x20) { |
| 213 | return arm_timer_read(s->timer[0], offset); |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 214 | } |
| 215 | if (offset < 0x40) { |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 216 | return arm_timer_read(s->timer[1], offset - 0x20); |
| 217 | } |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 218 | |
| 219 | /* TimerPeriphID */ |
| 220 | if (offset >= 0xfe0 && offset <= 0xffc) { |
| 221 | return sp804_ids[(offset - 0xfe0) >> 2]; |
| 222 | } |
| 223 | |
| 224 | switch (offset) { |
| 225 | /* Integration Test control registers, which we won't support */ |
| 226 | case 0xf00: /* TimerITCR */ |
| 227 | case 0xf04: /* TimerITOP (strictly write only but..) */ |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 228 | qemu_log_mask(LOG_UNIMP, |
| 229 | "%s: integration test registers unimplemented\n", |
| 230 | __func__); |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 231 | return 0; |
| 232 | } |
| 233 | |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 234 | qemu_log_mask(LOG_GUEST_ERROR, |
| 235 | "%s: Bad offset %x\n", __func__, (int)offset); |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 236 | return 0; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 237 | } |
| 238 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 239 | static void sp804_write(void *opaque, hwaddr offset, |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 240 | uint64_t value, unsigned size) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 241 | { |
| 242 | sp804_state *s = (sp804_state *)opaque; |
| 243 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 244 | if (offset < 0x20) { |
| 245 | arm_timer_write(s->timer[0], offset, value); |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 246 | return; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 247 | } |
Peter Chubb | 7b4252e | 2011-12-12 10:25:42 +0000 | [diff] [blame] | 248 | |
| 249 | if (offset < 0x40) { |
| 250 | arm_timer_write(s->timer[1], offset - 0x20, value); |
| 251 | return; |
| 252 | } |
| 253 | |
| 254 | /* Technically we could be writing to the Test Registers, but not likely */ |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 255 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", |
| 256 | __func__, (int)offset); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 257 | } |
| 258 | |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 259 | static const MemoryRegionOps sp804_ops = { |
| 260 | .read = sp804_read, |
| 261 | .write = sp804_write, |
| 262 | .endianness = DEVICE_NATIVE_ENDIAN, |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 263 | }; |
| 264 | |
Juan Quintela | 81986ac | 2010-12-01 23:12:32 +0100 | [diff] [blame] | 265 | static const VMStateDescription vmstate_sp804 = { |
| 266 | .name = "sp804", |
| 267 | .version_id = 1, |
| 268 | .minimum_version_id = 1, |
| 269 | .minimum_version_id_old = 1, |
| 270 | .fields = (VMStateField[]) { |
| 271 | VMSTATE_INT32_ARRAY(level, sp804_state, 2), |
| 272 | VMSTATE_END_OF_LIST() |
| 273 | } |
| 274 | }; |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 275 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 276 | static int sp804_init(SysBusDevice *dev) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 277 | { |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 278 | sp804_state *s = FROM_SYSBUS(sp804_state, dev); |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 279 | qemu_irq *qi; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 280 | |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 281 | qi = qemu_allocate_irqs(sp804_set_irq, s, 2); |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 282 | sysbus_init_irq(dev, &s->irq); |
Mark Langsdorf | 104a26a | 2011-12-29 06:19:51 +0000 | [diff] [blame] | 283 | s->timer[0] = arm_timer_init(s->freq0); |
| 284 | s->timer[1] = arm_timer_init(s->freq1); |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 285 | s->timer[0]->irq = qi[0]; |
| 286 | s->timer[1]->irq = qi[1]; |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 287 | memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000); |
Avi Kivity | 750ecd4 | 2011-11-27 11:38:10 +0200 | [diff] [blame] | 288 | sysbus_init_mmio(dev, &s->iomem); |
Juan Quintela | 81986ac | 2010-12-01 23:12:32 +0100 | [diff] [blame] | 289 | vmstate_register(&dev->qdev, -1, &vmstate_sp804, s); |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 290 | return 0; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 291 | } |
| 292 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 293 | /* Integrator/CP timer module. */ |
| 294 | |
| 295 | typedef struct { |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 296 | SysBusDevice busdev; |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 297 | MemoryRegion iomem; |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 298 | arm_timer_state *timer[3]; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 299 | } icp_pit_state; |
| 300 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 301 | static uint64_t icp_pit_read(void *opaque, hwaddr offset, |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 302 | unsigned size) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 303 | { |
| 304 | icp_pit_state *s = (icp_pit_state *)opaque; |
| 305 | int n; |
| 306 | |
| 307 | /* ??? Don't know the PrimeCell ID for this device. */ |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 308 | n = offset >> 8; |
Peter Maydell | ee71c98 | 2011-11-11 13:30:15 +0000 | [diff] [blame] | 309 | if (n > 2) { |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 310 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 311 | } |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 312 | |
| 313 | return arm_timer_read(s->timer[n], offset & 0xff); |
| 314 | } |
| 315 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 316 | static void icp_pit_write(void *opaque, hwaddr offset, |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 317 | uint64_t value, unsigned size) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 318 | { |
| 319 | icp_pit_state *s = (icp_pit_state *)opaque; |
| 320 | int n; |
| 321 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 322 | n = offset >> 8; |
Peter Maydell | ee71c98 | 2011-11-11 13:30:15 +0000 | [diff] [blame] | 323 | if (n > 2) { |
Peter Maydell | edb94a4 | 2012-10-30 07:45:10 +0000 | [diff] [blame] | 324 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 325 | } |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 326 | |
| 327 | arm_timer_write(s->timer[n], offset & 0xff, value); |
| 328 | } |
| 329 | |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 330 | static const MemoryRegionOps icp_pit_ops = { |
| 331 | .read = icp_pit_read, |
| 332 | .write = icp_pit_write, |
| 333 | .endianness = DEVICE_NATIVE_ENDIAN, |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 334 | }; |
| 335 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 336 | static int icp_pit_init(SysBusDevice *dev) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 337 | { |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 338 | icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 339 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 340 | /* Timer 0 runs at the system clock speed (40MHz). */ |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 341 | s->timer[0] = arm_timer_init(40000000); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 342 | /* The other two timers run at 1MHz. */ |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 343 | s->timer[1] = arm_timer_init(1000000); |
| 344 | s->timer[2] = arm_timer_init(1000000); |
| 345 | |
| 346 | sysbus_init_irq(dev, &s->timer[0]->irq); |
| 347 | sysbus_init_irq(dev, &s->timer[1]->irq); |
| 348 | sysbus_init_irq(dev, &s->timer[2]->irq); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 349 | |
Avi Kivity | e219dea | 2011-08-15 17:17:19 +0300 | [diff] [blame] | 350 | memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000); |
Avi Kivity | 750ecd4 | 2011-11-27 11:38:10 +0200 | [diff] [blame] | 351 | sysbus_init_mmio(dev, &s->iomem); |
pbrook | 23e3929 | 2008-07-02 16:48:32 +0000 | [diff] [blame] | 352 | /* This device has no state to save/restore. The component timers will |
| 353 | save themselves. */ |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 354 | return 0; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 355 | } |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 356 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 357 | static void icp_pit_class_init(ObjectClass *klass, void *data) |
| 358 | { |
| 359 | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
| 360 | |
| 361 | sdc->init = icp_pit_init; |
| 362 | } |
| 363 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 364 | static const TypeInfo icp_pit_info = { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 365 | .name = "integrator_pit", |
| 366 | .parent = TYPE_SYS_BUS_DEVICE, |
| 367 | .instance_size = sizeof(icp_pit_state), |
| 368 | .class_init = icp_pit_class_init, |
| 369 | }; |
| 370 | |
| 371 | static Property sp804_properties[] = { |
| 372 | DEFINE_PROP_UINT32("freq0", sp804_state, freq0, 1000000), |
| 373 | DEFINE_PROP_UINT32("freq1", sp804_state, freq1, 1000000), |
| 374 | DEFINE_PROP_END_OF_LIST(), |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 375 | }; |
| 376 | |
| 377 | static void sp804_class_init(ObjectClass *klass, void *data) |
| 378 | { |
| 379 | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 380 | DeviceClass *k = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 381 | |
| 382 | sdc->init = sp804_init; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 383 | k->props = sp804_properties; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 384 | } |
| 385 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 386 | static const TypeInfo sp804_info = { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 387 | .name = "sp804", |
| 388 | .parent = TYPE_SYS_BUS_DEVICE, |
| 389 | .instance_size = sizeof(sp804_state), |
| 390 | .class_init = sp804_class_init, |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 391 | }; |
| 392 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 393 | static void arm_timer_register_types(void) |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 394 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 395 | type_register_static(&icp_pit_info); |
| 396 | type_register_static(&sp804_info); |
Paul Brook | 6a824ec | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 397 | } |
| 398 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 399 | type_init(arm_timer_register_types) |