blob: 87337b6385509c9cffe46f1e060a07f06e272a56 [file] [log] [blame]
Peter Maydelld14d42f2013-09-03 20:12:07 +01001/*
2 * QEMU AArch64 CPU
3 *
4 * Copyright (c) 2013 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
Peter Maydell74c21bd2015-12-07 16:23:44 +000021#include "qemu/osdep.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +010022#include "qapi/error.h"
Peter Maydelld14d42f2013-09-03 20:12:07 +010023#include "cpu.h"
24#include "qemu-common.h"
25#if !defined(CONFIG_USER_ONLY)
26#include "hw/loader.h"
27#endif
28#include "hw/arm/arm.h"
29#include "sysemu/sysemu.h"
30#include "sysemu/kvm.h"
Peter Maydellbab52d42018-03-09 17:09:44 +000031#include "kvm_arm.h"
Richard Hendersonadf92ea2018-08-16 14:05:28 +010032#include "qapi/visitor.h"
Peter Maydelld14d42f2013-09-03 20:12:07 +010033
34static inline void set_feature(CPUARMState *env, int feature)
35{
36 env->features |= 1ULL << feature;
37}
38
Greg Bellowsfb8d6c22015-02-13 05:46:08 +000039static inline void unset_feature(CPUARMState *env, int feature)
40{
41 env->features &= ~(1ULL << feature);
42}
43
Peter Maydell377a44e2014-04-15 19:18:48 +010044#ifndef CONFIG_USER_ONLY
Peter Crosthwaiteee804262015-05-14 19:22:52 -070045static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
Peter Maydell377a44e2014-04-15 19:18:48 +010046{
Alistair Francisf9a69712018-03-09 17:09:43 +000047 ARMCPU *cpu = arm_env_get_cpu(env);
48
49 /* Number of cores is in [25:24]; otherwise we RAZ */
50 return (cpu->core_count - 1) << 24;
Peter Maydell377a44e2014-04-15 19:18:48 +010051}
52#endif
53
Edgar E. Iglesiasf11b4522018-10-11 04:19:29 +020054static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
Peter Maydell377a44e2014-04-15 19:18:48 +010055#ifndef CONFIG_USER_ONLY
56 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
57 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
Peter Crosthwaiteee804262015-05-14 19:22:52 -070058 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
Peter Maydell377a44e2014-04-15 19:18:48 +010059 .writefn = arm_cp_write_ignore },
60 { .name = "L2CTLR",
61 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
Peter Crosthwaiteee804262015-05-14 19:22:52 -070062 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
Peter Maydell377a44e2014-04-15 19:18:48 +010063 .writefn = arm_cp_write_ignore },
64#endif
65 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
66 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
67 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
68 { .name = "L2ECTLR",
69 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
70 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
71 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
72 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
73 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
74 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
75 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
76 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
77 { .name = "CPUACTLR",
78 .cp = 15, .opc1 = 0, .crm = 15,
79 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
80 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
81 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
82 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
83 { .name = "CPUECTLR",
84 .cp = 15, .opc1 = 1, .crm = 15,
85 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
86 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
87 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
88 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
89 { .name = "CPUMERRSR",
90 .cp = 15, .opc1 = 2, .crm = 15,
91 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
92 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
93 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
94 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
95 { .name = "L2MERRSR",
96 .cp = 15, .opc1 = 3, .crm = 15,
97 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
98 REGINFO_SENTINEL
99};
100
Peter Maydellcb1fa942014-04-15 19:18:44 +0100101static void aarch64_a57_initfn(Object *obj)
102{
103 ARMCPU *cpu = ARM_CPU(obj);
104
Ryota Ozaki0458b7b2015-03-11 13:21:06 +0000105 cpu->dtb_compatible = "arm,cortex-a57";
Peter Maydellcb1fa942014-04-15 19:18:44 +0100106 set_feature(&cpu->env, ARM_FEATURE_V8);
107 set_feature(&cpu->env, ARM_FEATURE_VFP4);
Peter Maydellcb1fa942014-04-15 19:18:44 +0100108 set_feature(&cpu->env, ARM_FEATURE_NEON);
109 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
110 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
Peter Maydellf318cec2014-04-15 19:18:49 +0100111 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
Peter Maydellc25bd182017-01-20 11:15:10 +0000112 set_feature(&cpu->env, ARM_FEATURE_EL2);
Peter Maydell3ad901b2016-02-11 11:17:31 +0000113 set_feature(&cpu->env, ARM_FEATURE_EL3);
Wei Huang929e7542016-10-28 14:12:31 +0100114 set_feature(&cpu->env, ARM_FEATURE_PMU);
Peter Maydellcb1fa942014-04-15 19:18:44 +0100115 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
116 cpu->midr = 0x411fd070;
Sergey Fedorov13b72b22015-06-15 18:06:08 +0100117 cpu->revidr = 0x00000000;
Peter Maydellcb1fa942014-04-15 19:18:44 +0100118 cpu->reset_fpsid = 0x41034070;
Richard Henderson47576b92018-10-24 07:50:16 +0100119 cpu->isar.mvfr0 = 0x10110222;
120 cpu->isar.mvfr1 = 0x12111111;
121 cpu->isar.mvfr2 = 0x00000043;
Peter Maydellcb1fa942014-04-15 19:18:44 +0100122 cpu->ctr = 0x8444c004;
123 cpu->reset_sctlr = 0x00c50838;
124 cpu->id_pfr0 = 0x00000131;
125 cpu->id_pfr1 = 0x00011011;
126 cpu->id_dfr0 = 0x03010066;
127 cpu->id_afr0 = 0x00000000;
128 cpu->id_mmfr0 = 0x10101105;
129 cpu->id_mmfr1 = 0x40000000;
130 cpu->id_mmfr2 = 0x01260000;
131 cpu->id_mmfr3 = 0x02102211;
Richard Henderson47576b92018-10-24 07:50:16 +0100132 cpu->isar.id_isar0 = 0x02101110;
133 cpu->isar.id_isar1 = 0x13112111;
134 cpu->isar.id_isar2 = 0x21232042;
135 cpu->isar.id_isar3 = 0x01112131;
136 cpu->isar.id_isar4 = 0x00011142;
137 cpu->isar.id_isar5 = 0x00011121;
138 cpu->isar.id_isar6 = 0;
139 cpu->isar.id_aa64pfr0 = 0x00002222;
Peter Maydellcb1fa942014-04-15 19:18:44 +0100140 cpu->id_aa64dfr0 = 0x10305106;
Richard Henderson47576b92018-10-24 07:50:16 +0100141 cpu->isar.id_aa64isar0 = 0x00011120;
Peter Maydell3dc91dd2018-12-13 14:40:56 +0000142 cpu->isar.id_aa64mmfr0 = 0x00001124;
Peter Maydell48eb3ae2014-08-19 18:56:25 +0100143 cpu->dbgdidr = 0x3516d000;
Peter Maydellcb1fa942014-04-15 19:18:44 +0100144 cpu->clidr = 0x0a200023;
145 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
146 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
147 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
148 cpu->dcz_blocksize = 4; /* 64 bytes */
Peter Maydelle45868a2017-01-20 11:15:09 +0000149 cpu->gic_num_lrs = 4;
150 cpu->gic_vpribits = 5;
151 cpu->gic_vprebits = 5;
Edgar E. Iglesiasf11b4522018-10-11 04:19:29 +0200152 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
Peter Maydellcb1fa942014-04-15 19:18:44 +0100153}
154
Peter Crosthwaitee3531022015-05-14 19:22:55 -0700155static void aarch64_a53_initfn(Object *obj)
156{
157 ARMCPU *cpu = ARM_CPU(obj);
158
159 cpu->dtb_compatible = "arm,cortex-a53";
160 set_feature(&cpu->env, ARM_FEATURE_V8);
161 set_feature(&cpu->env, ARM_FEATURE_VFP4);
162 set_feature(&cpu->env, ARM_FEATURE_NEON);
163 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
164 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
165 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
Peter Maydellc25bd182017-01-20 11:15:10 +0000166 set_feature(&cpu->env, ARM_FEATURE_EL2);
Peter Maydell3ad901b2016-02-11 11:17:31 +0000167 set_feature(&cpu->env, ARM_FEATURE_EL3);
Wei Huang929e7542016-10-28 14:12:31 +0100168 set_feature(&cpu->env, ARM_FEATURE_PMU);
Shannon Zhao75254652015-06-15 18:06:08 +0100169 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
Peter Crosthwaitee3531022015-05-14 19:22:55 -0700170 cpu->midr = 0x410fd034;
Sergey Fedorov13b72b22015-06-15 18:06:08 +0100171 cpu->revidr = 0x00000000;
Peter Crosthwaitee3531022015-05-14 19:22:55 -0700172 cpu->reset_fpsid = 0x41034070;
Richard Henderson47576b92018-10-24 07:50:16 +0100173 cpu->isar.mvfr0 = 0x10110222;
174 cpu->isar.mvfr1 = 0x12111111;
175 cpu->isar.mvfr2 = 0x00000043;
Peter Crosthwaitee3531022015-05-14 19:22:55 -0700176 cpu->ctr = 0x84448004; /* L1Ip = VIPT */
177 cpu->reset_sctlr = 0x00c50838;
178 cpu->id_pfr0 = 0x00000131;
179 cpu->id_pfr1 = 0x00011011;
180 cpu->id_dfr0 = 0x03010066;
181 cpu->id_afr0 = 0x00000000;
182 cpu->id_mmfr0 = 0x10101105;
183 cpu->id_mmfr1 = 0x40000000;
184 cpu->id_mmfr2 = 0x01260000;
185 cpu->id_mmfr3 = 0x02102211;
Richard Henderson47576b92018-10-24 07:50:16 +0100186 cpu->isar.id_isar0 = 0x02101110;
187 cpu->isar.id_isar1 = 0x13112111;
188 cpu->isar.id_isar2 = 0x21232042;
189 cpu->isar.id_isar3 = 0x01112131;
190 cpu->isar.id_isar4 = 0x00011142;
191 cpu->isar.id_isar5 = 0x00011121;
192 cpu->isar.id_isar6 = 0;
193 cpu->isar.id_aa64pfr0 = 0x00002222;
Peter Crosthwaitee3531022015-05-14 19:22:55 -0700194 cpu->id_aa64dfr0 = 0x10305106;
Richard Henderson47576b92018-10-24 07:50:16 +0100195 cpu->isar.id_aa64isar0 = 0x00011120;
Peter Maydell3dc91dd2018-12-13 14:40:56 +0000196 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
Peter Crosthwaitee3531022015-05-14 19:22:55 -0700197 cpu->dbgdidr = 0x3516d000;
198 cpu->clidr = 0x0a200023;
199 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
200 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
201 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
202 cpu->dcz_blocksize = 4; /* 64 bytes */
Peter Maydelle45868a2017-01-20 11:15:09 +0000203 cpu->gic_num_lrs = 4;
204 cpu->gic_vpribits = 5;
205 cpu->gic_vprebits = 5;
Edgar E. Iglesiasf11b4522018-10-11 04:19:29 +0200206 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
207}
208
209static void aarch64_a72_initfn(Object *obj)
210{
211 ARMCPU *cpu = ARM_CPU(obj);
212
213 cpu->dtb_compatible = "arm,cortex-a72";
214 set_feature(&cpu->env, ARM_FEATURE_V8);
215 set_feature(&cpu->env, ARM_FEATURE_VFP4);
216 set_feature(&cpu->env, ARM_FEATURE_NEON);
217 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
218 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
219 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
Edgar E. Iglesiasf11b4522018-10-11 04:19:29 +0200220 set_feature(&cpu->env, ARM_FEATURE_EL2);
221 set_feature(&cpu->env, ARM_FEATURE_EL3);
222 set_feature(&cpu->env, ARM_FEATURE_PMU);
223 cpu->midr = 0x410fd083;
224 cpu->revidr = 0x00000000;
225 cpu->reset_fpsid = 0x41034080;
Richard Henderson47576b92018-10-24 07:50:16 +0100226 cpu->isar.mvfr0 = 0x10110222;
227 cpu->isar.mvfr1 = 0x12111111;
228 cpu->isar.mvfr2 = 0x00000043;
Edgar E. Iglesiasf11b4522018-10-11 04:19:29 +0200229 cpu->ctr = 0x8444c004;
230 cpu->reset_sctlr = 0x00c50838;
231 cpu->id_pfr0 = 0x00000131;
232 cpu->id_pfr1 = 0x00011011;
233 cpu->id_dfr0 = 0x03010066;
234 cpu->id_afr0 = 0x00000000;
235 cpu->id_mmfr0 = 0x10201105;
236 cpu->id_mmfr1 = 0x40000000;
237 cpu->id_mmfr2 = 0x01260000;
238 cpu->id_mmfr3 = 0x02102211;
Richard Henderson47576b92018-10-24 07:50:16 +0100239 cpu->isar.id_isar0 = 0x02101110;
240 cpu->isar.id_isar1 = 0x13112111;
241 cpu->isar.id_isar2 = 0x21232042;
242 cpu->isar.id_isar3 = 0x01112131;
243 cpu->isar.id_isar4 = 0x00011142;
244 cpu->isar.id_isar5 = 0x00011121;
245 cpu->isar.id_aa64pfr0 = 0x00002222;
Edgar E. Iglesiasf11b4522018-10-11 04:19:29 +0200246 cpu->id_aa64dfr0 = 0x10305106;
Richard Henderson47576b92018-10-24 07:50:16 +0100247 cpu->isar.id_aa64isar0 = 0x00011120;
Peter Maydell3dc91dd2018-12-13 14:40:56 +0000248 cpu->isar.id_aa64mmfr0 = 0x00001124;
Edgar E. Iglesiasf11b4522018-10-11 04:19:29 +0200249 cpu->dbgdidr = 0x3516d000;
250 cpu->clidr = 0x0a200023;
251 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
252 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
253 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
254 cpu->dcz_blocksize = 4; /* 64 bytes */
255 cpu->gic_num_lrs = 4;
256 cpu->gic_vpribits = 5;
257 cpu->gic_vprebits = 5;
258 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
Peter Crosthwaitee3531022015-05-14 19:22:55 -0700259}
260
Richard Hendersonadf92ea2018-08-16 14:05:28 +0100261static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
262 void *opaque, Error **errp)
263{
264 ARMCPU *cpu = ARM_CPU(obj);
265 visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
266}
267
268static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
269 void *opaque, Error **errp)
270{
271 ARMCPU *cpu = ARM_CPU(obj);
272 Error *err = NULL;
273
274 visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
275
276 if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
277 error_setg(&err, "unsupported SVE vector length");
278 error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
279 ARM_MAX_VQ);
280 }
281 error_propagate(errp, err);
282}
283
Peter Maydellbab52d42018-03-09 17:09:44 +0000284/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
285 * otherwise, a CPU with as many features enabled as our emulation supports.
286 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
287 * this only needs to handle 64 bits.
288 */
289static void aarch64_max_initfn(Object *obj)
290{
291 ARMCPU *cpu = ARM_CPU(obj);
292
293 if (kvm_enabled()) {
294 kvm_arm_set_cpu_features_from_host(cpu);
295 } else {
Richard Henderson962fcbf2018-10-24 07:50:16 +0100296 uint64_t t;
297 uint32_t u;
Peter Maydellbab52d42018-03-09 17:09:44 +0000298 aarch64_a57_initfn(obj);
Richard Henderson962fcbf2018-10-24 07:50:16 +0100299
300 t = cpu->isar.id_aa64isar0;
301 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
302 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
303 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
304 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
305 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
306 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
307 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
308 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
309 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
310 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
Richard Henderson991c0592019-02-28 10:55:17 +0000311 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
Richard Henderson962fcbf2018-10-24 07:50:16 +0100312 cpu->isar.id_aa64isar0 = t;
313
314 t = cpu->isar.id_aa64isar1;
Richard Henderson6c1f6f22019-02-21 18:17:46 +0000315 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
Richard Henderson962fcbf2018-10-24 07:50:16 +0100316 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
Richard Henderson1ce32e42019-01-21 10:23:13 +0000317 t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
318 t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
319 t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
320 t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
Richard Henderson9888bd12019-03-01 12:04:53 -0800321 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
Richard Hendersoncb570bd2019-03-01 12:04:54 -0800322 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
Richard Henderson962fcbf2018-10-24 07:50:16 +0100323 cpu->isar.id_aa64isar1 = t;
324
Richard Hendersoncd208a12018-10-24 07:50:17 +0100325 t = cpu->isar.id_aa64pfr0;
326 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
Richard Henderson57631902018-10-24 07:50:17 +0100327 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
328 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
Richard Hendersoncd208a12018-10-24 07:50:17 +0100329 cpu->isar.id_aa64pfr0 = t;
330
Richard Hendersona15daaf2019-02-05 16:52:38 +0000331 t = cpu->isar.id_aa64pfr1;
332 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
333 cpu->isar.id_aa64pfr1 = t;
334
Richard Henderson037c13c2018-12-13 13:48:06 +0000335 t = cpu->isar.id_aa64mmfr1;
336 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
Richard Henderson2d7137c2018-12-13 13:48:08 +0000337 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
Richard Henderson037c13c2018-12-13 13:48:06 +0000338 cpu->isar.id_aa64mmfr1 = t;
339
Richard Henderson962fcbf2018-10-24 07:50:16 +0100340 /* Replicate the same data to the 32-bit id registers. */
341 u = cpu->isar.id_isar5;
342 u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
343 u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
344 u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
345 u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
346 u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
347 u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
348 cpu->isar.id_isar5 = u;
349
350 u = cpu->isar.id_isar6;
Richard Henderson6c1f6f22019-02-21 18:17:46 +0000351 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
Richard Henderson962fcbf2018-10-24 07:50:16 +0100352 u = FIELD_DP32(u, ID_ISAR6, DP, 1);
Richard Henderson991c0592019-02-28 10:55:17 +0000353 u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
Richard Henderson9888bd12019-03-01 12:04:53 -0800354 u = FIELD_DP32(u, ID_ISAR6, SB, 1);
Richard Hendersoncb570bd2019-03-01 12:04:54 -0800355 u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
Richard Henderson962fcbf2018-10-24 07:50:16 +0100356 cpu->isar.id_isar6 = u;
357
Richard Henderson57631902018-10-24 07:50:17 +0100358 /*
359 * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
360 * so do not set MVFR1.FPHP. Strictly speaking this is not legal,
361 * but it is also not legal to enable SVE without support for FP16,
362 * and enabling SVE in system mode is more useful in the short term.
Peter Maydellbab52d42018-03-09 17:09:44 +0000363 */
Richard Henderson57631902018-10-24 07:50:17 +0100364
365#ifdef CONFIG_USER_ONLY
Peter Maydella0032cc2018-03-09 17:09:44 +0000366 /* For usermode -cpu max we can use a larger and more efficient DCZ
367 * blocksize since we don't have to follow what the hardware does.
368 */
369 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
370 cpu->dcz_blocksize = 7; /* 512 bytes */
371#endif
Richard Hendersonadf92ea2018-08-16 14:05:28 +0100372
373 cpu->sve_max_vq = ARM_MAX_VQ;
374 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
375 cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
Peter Maydellbab52d42018-03-09 17:09:44 +0000376 }
377}
378
Marc-André Lureau51e5ef42018-11-27 12:55:59 +0400379struct ARMCPUInfo {
Peter Maydelld14d42f2013-09-03 20:12:07 +0100380 const char *name;
381 void (*initfn)(Object *obj);
382 void (*class_init)(ObjectClass *oc, void *data);
Marc-André Lureau51e5ef42018-11-27 12:55:59 +0400383};
Peter Maydelld14d42f2013-09-03 20:12:07 +0100384
385static const ARMCPUInfo aarch64_cpus[] = {
Peter Maydellcb1fa942014-04-15 19:18:44 +0100386 { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
Peter Crosthwaitee3531022015-05-14 19:22:55 -0700387 { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
Edgar E. Iglesiasf11b4522018-10-11 04:19:29 +0200388 { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
Peter Maydellbab52d42018-03-09 17:09:44 +0000389 { .name = "max", .initfn = aarch64_max_initfn },
Peter Maydell83e68132014-01-13 10:26:16 +0000390 { .name = NULL }
Peter Maydelld14d42f2013-09-03 20:12:07 +0100391};
392
Greg Bellowsfb8d6c22015-02-13 05:46:08 +0000393static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
394{
395 ARMCPU *cpu = ARM_CPU(obj);
396
397 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
398}
399
400static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
401{
402 ARMCPU *cpu = ARM_CPU(obj);
403
404 /* At this time, this property is only allowed if KVM is enabled. This
405 * restriction allows us to avoid fixing up functionality that assumes a
406 * uniform execution state like do_interrupt.
407 */
408 if (!kvm_enabled()) {
409 error_setg(errp, "'aarch64' feature cannot be disabled "
410 "unless KVM is enabled");
411 return;
412 }
413
414 if (value == false) {
415 unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
416 } else {
417 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
418 }
419}
420
Peter Maydelld14d42f2013-09-03 20:12:07 +0100421static void aarch64_cpu_initfn(Object *obj)
422{
Greg Bellowsfb8d6c22015-02-13 05:46:08 +0000423 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
424 aarch64_cpu_set_aarch64, NULL);
425 object_property_set_description(obj, "aarch64",
426 "Set on/off to enable/disable aarch64 "
427 "execution state ",
428 NULL);
Peter Maydelld14d42f2013-09-03 20:12:07 +0100429}
430
431static void aarch64_cpu_finalizefn(Object *obj)
432{
433}
434
David Hildenbrandb3820e62015-12-03 13:14:41 +0100435static gchar *aarch64_gdb_arch_name(CPUState *cs)
436{
437 return g_strdup("aarch64");
438}
439
Peter Maydelld14d42f2013-09-03 20:12:07 +0100440static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
441{
Alexander Graf14ade102013-09-03 20:12:10 +0100442 CPUClass *cc = CPU_CLASS(oc);
443
Richard Hendersone8925712014-09-13 09:45:25 -0700444 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
Alexander Graf96c04212013-09-03 20:12:11 +0100445 cc->gdb_read_register = aarch64_cpu_gdb_read_register;
446 cc->gdb_write_register = aarch64_cpu_gdb_write_register;
447 cc->gdb_num_core_regs = 34;
448 cc->gdb_core_xml_file = "aarch64-core.xml";
David Hildenbrandb3820e62015-12-03 13:14:41 +0100449 cc->gdb_arch_name = aarch64_gdb_arch_name;
Peter Maydelld14d42f2013-09-03 20:12:07 +0100450}
451
Marc-André Lureau51e5ef42018-11-27 12:55:59 +0400452static void aarch64_cpu_instance_init(Object *obj)
453{
454 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
455
456 acc->info->initfn(obj);
457 arm_cpu_post_init(obj);
458}
459
460static void cpu_register_class_init(ObjectClass *oc, void *data)
461{
462 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
463
464 acc->info = data;
465}
466
Peter Maydelld14d42f2013-09-03 20:12:07 +0100467static void aarch64_cpu_register(const ARMCPUInfo *info)
468{
469 TypeInfo type_info = {
470 .parent = TYPE_AARCH64_CPU,
471 .instance_size = sizeof(ARMCPU),
Marc-André Lureau51e5ef42018-11-27 12:55:59 +0400472 .instance_init = aarch64_cpu_instance_init,
Peter Maydelld14d42f2013-09-03 20:12:07 +0100473 .class_size = sizeof(ARMCPUClass),
Marc-André Lureau51e5ef42018-11-27 12:55:59 +0400474 .class_init = info->class_init ?: cpu_register_class_init,
475 .class_data = (void *)info,
Peter Maydelld14d42f2013-09-03 20:12:07 +0100476 };
477
Peter Maydelld14d42f2013-09-03 20:12:07 +0100478 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
479 type_register(&type_info);
480 g_free((void *)type_info.name);
481}
482
483static const TypeInfo aarch64_cpu_type_info = {
484 .name = TYPE_AARCH64_CPU,
485 .parent = TYPE_ARM_CPU,
486 .instance_size = sizeof(ARMCPU),
487 .instance_init = aarch64_cpu_initfn,
488 .instance_finalize = aarch64_cpu_finalizefn,
489 .abstract = true,
490 .class_size = sizeof(AArch64CPUClass),
491 .class_init = aarch64_cpu_class_init,
492};
493
494static void aarch64_cpu_register_types(void)
495{
Peter Maydell83e68132014-01-13 10:26:16 +0000496 const ARMCPUInfo *info = aarch64_cpus;
Peter Maydelld14d42f2013-09-03 20:12:07 +0100497
498 type_register_static(&aarch64_cpu_type_info);
Peter Maydell83e68132014-01-13 10:26:16 +0000499
500 while (info->name) {
501 aarch64_cpu_register(info);
502 info++;
Peter Maydelld14d42f2013-09-03 20:12:07 +0100503 }
504}
505
506type_init(aarch64_cpu_register_types)