blob: 55cf156a0b49be6b3d2e68e408845c27d9e44021 [file] [log] [blame]
David Gibson9d7c3f42013-03-12 00:31:07 +00001/*
2 * PowerPC MMU, TLB and BAT emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2013 David Gibson, IBM Corporation
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
Peter Maydell0d755902016-01-26 18:16:58 +000021#include "qemu/osdep.h"
David Gibson9d7c3f42013-03-12 00:31:07 +000022#include "cpu.h"
Paolo Bonzini63c91552016-03-15 13:18:37 +010023#include "exec/exec-all.h"
Richard Henderson2ef61752014-04-07 22:31:41 -070024#include "exec/helper-proto.h"
David Gibson9d7c3f42013-03-12 00:31:07 +000025#include "sysemu/kvm.h"
26#include "kvm_ppc.h"
27#include "mmu-hash32.h"
Paolo Bonzini508127e2016-01-07 16:55:28 +030028#include "exec/log.h"
David Gibson9d7c3f42013-03-12 00:31:07 +000029
David Gibson596e3ca2019-03-21 22:29:06 +110030/* #define DEBUG_BAT */
David Gibson9d7c3f42013-03-12 00:31:07 +000031
David Gibson98132792013-03-12 00:31:16 +000032#ifdef DEBUG_BATS
Paolo Bonzini48880da2015-11-13 13:34:23 +010033# define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
David Gibson98132792013-03-12 00:31:16 +000034#else
35# define LOG_BATS(...) do { } while (0)
36#endif
37
David Gibson5dc68eb2013-03-12 00:31:17 +000038struct mmu_ctx_hash32 {
39 hwaddr raddr; /* Real address */
David Gibson5dc68eb2013-03-12 00:31:17 +000040 int prot; /* Protection bits */
David Gibson5dc68eb2013-03-12 00:31:17 +000041 int key; /* Access key */
David Gibson5dc68eb2013-03-12 00:31:17 +000042};
43
David Gibsone01b4442013-03-12 00:31:40 +000044static int ppc_hash32_pp_prot(int key, int pp, int nx)
David Gibson496272a2013-03-12 00:31:14 +000045{
David Gibsone01b4442013-03-12 00:31:40 +000046 int prot;
David Gibson496272a2013-03-12 00:31:14 +000047
David Gibson496272a2013-03-12 00:31:14 +000048 if (key == 0) {
49 switch (pp) {
50 case 0x0:
51 case 0x1:
52 case 0x2:
David Gibsone01b4442013-03-12 00:31:40 +000053 prot = PAGE_READ | PAGE_WRITE;
David Gibson496272a2013-03-12 00:31:14 +000054 break;
David Gibsone01b4442013-03-12 00:31:40 +000055
56 case 0x3:
57 prot = PAGE_READ;
58 break;
59
60 default:
61 abort();
David Gibson496272a2013-03-12 00:31:14 +000062 }
63 } else {
64 switch (pp) {
65 case 0x0:
David Gibsone01b4442013-03-12 00:31:40 +000066 prot = 0;
David Gibson496272a2013-03-12 00:31:14 +000067 break;
David Gibsone01b4442013-03-12 00:31:40 +000068
David Gibson496272a2013-03-12 00:31:14 +000069 case 0x1:
70 case 0x3:
David Gibsone01b4442013-03-12 00:31:40 +000071 prot = PAGE_READ;
David Gibson496272a2013-03-12 00:31:14 +000072 break;
David Gibsone01b4442013-03-12 00:31:40 +000073
David Gibson496272a2013-03-12 00:31:14 +000074 case 0x2:
David Gibsone01b4442013-03-12 00:31:40 +000075 prot = PAGE_READ | PAGE_WRITE;
David Gibson496272a2013-03-12 00:31:14 +000076 break;
David Gibsone01b4442013-03-12 00:31:40 +000077
78 default:
79 abort();
David Gibson496272a2013-03-12 00:31:14 +000080 }
81 }
82 if (nx == 0) {
David Gibsone01b4442013-03-12 00:31:40 +000083 prot |= PAGE_EXEC;
David Gibson496272a2013-03-12 00:31:14 +000084 }
85
David Gibsone01b4442013-03-12 00:31:40 +000086 return prot;
David Gibson496272a2013-03-12 00:31:14 +000087}
88
David Gibson7ef23062016-01-14 15:33:27 +110089static int ppc_hash32_pte_prot(PowerPCCPU *cpu,
David Gibsone01b4442013-03-12 00:31:40 +000090 target_ulong sr, ppc_hash_pte32_t pte)
David Gibson496272a2013-03-12 00:31:14 +000091{
David Gibson7ef23062016-01-14 15:33:27 +110092 CPUPPCState *env = &cpu->env;
David Gibsone01b4442013-03-12 00:31:40 +000093 unsigned pp, key;
David Gibson496272a2013-03-12 00:31:14 +000094
David Gibsone01b4442013-03-12 00:31:40 +000095 key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
96 pp = pte.pte1 & HPTE32_R_PP;
David Gibson496272a2013-03-12 00:31:14 +000097
David Gibsone01b4442013-03-12 00:31:40 +000098 return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
David Gibson496272a2013-03-12 00:31:14 +000099}
100
David Gibson7ef23062016-01-14 15:33:27 +1100101static target_ulong hash32_bat_size(PowerPCCPU *cpu,
David Gibson6fc76aa2013-03-12 00:31:35 +0000102 target_ulong batu, target_ulong batl)
David Gibson98132792013-03-12 00:31:16 +0000103{
David Gibson7ef23062016-01-14 15:33:27 +1100104 CPUPPCState *env = &cpu->env;
105
David Gibson6fc76aa2013-03-12 00:31:35 +0000106 if ((msr_pr && !(batu & BATU32_VP))
107 || (!msr_pr && !(batu & BATU32_VS))) {
108 return 0;
David Gibson98132792013-03-12 00:31:16 +0000109 }
David Gibson6fc76aa2013-03-12 00:31:35 +0000110
111 return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
David Gibson98132792013-03-12 00:31:16 +0000112}
113
David Gibson7ef23062016-01-14 15:33:27 +1100114static int hash32_bat_prot(PowerPCCPU *cpu,
David Gibsone1d49512013-03-12 00:31:34 +0000115 target_ulong batu, target_ulong batl)
116{
117 int pp, prot;
118
119 prot = 0;
120 pp = batl & BATL32_PP;
121 if (pp != 0) {
122 prot = PAGE_READ | PAGE_EXEC;
123 if (pp == 0x2) {
124 prot |= PAGE_WRITE;
125 }
126 }
127 return prot;
128}
129
David Gibson7ef23062016-01-14 15:33:27 +1100130static target_ulong hash32_bat_601_size(PowerPCCPU *cpu,
David Gibsone1d49512013-03-12 00:31:34 +0000131 target_ulong batu, target_ulong batl)
David Gibson98132792013-03-12 00:31:16 +0000132{
David Gibson6fc76aa2013-03-12 00:31:35 +0000133 if (!(batl & BATL32_601_V)) {
134 return 0;
135 }
David Gibson98132792013-03-12 00:31:16 +0000136
David Gibson6fc76aa2013-03-12 00:31:35 +0000137 return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
David Gibsone1d49512013-03-12 00:31:34 +0000138}
139
David Gibson7ef23062016-01-14 15:33:27 +1100140static int hash32_bat_601_prot(PowerPCCPU *cpu,
David Gibsone1d49512013-03-12 00:31:34 +0000141 target_ulong batu, target_ulong batl)
142{
David Gibson7ef23062016-01-14 15:33:27 +1100143 CPUPPCState *env = &cpu->env;
David Gibsone1d49512013-03-12 00:31:34 +0000144 int key, pp;
145
146 pp = batu & BATU32_601_PP;
147 if (msr_pr == 0) {
148 key = !!(batu & BATU32_601_KS);
149 } else {
150 key = !!(batu & BATU32_601_KP);
151 }
David Gibsone01b4442013-03-12 00:31:40 +0000152 return ppc_hash32_pp_prot(key, pp, 0);
David Gibson98132792013-03-12 00:31:16 +0000153}
154
David Gibson7ef23062016-01-14 15:33:27 +1100155static hwaddr ppc_hash32_bat_lookup(PowerPCCPU *cpu, target_ulong ea, int rwx,
David Gibson145e52f2013-03-12 00:31:36 +0000156 int *prot)
David Gibson98132792013-03-12 00:31:16 +0000157{
David Gibson7ef23062016-01-14 15:33:27 +1100158 CPUPPCState *env = &cpu->env;
David Gibson9986ed12013-03-12 00:31:33 +0000159 target_ulong *BATlt, *BATut;
David Gibson145e52f2013-03-12 00:31:36 +0000160 int i;
David Gibson98132792013-03-12 00:31:16 +0000161
162 LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
David Gibson145e52f2013-03-12 00:31:36 +0000163 rwx == 2 ? 'I' : 'D', ea);
David Gibson91cda452013-03-12 00:31:20 +0000164 if (rwx == 2) {
David Gibson98132792013-03-12 00:31:16 +0000165 BATlt = env->IBAT[1];
166 BATut = env->IBAT[0];
David Gibson91cda452013-03-12 00:31:20 +0000167 } else {
David Gibson98132792013-03-12 00:31:16 +0000168 BATlt = env->DBAT[1];
169 BATut = env->DBAT[0];
David Gibson98132792013-03-12 00:31:16 +0000170 }
171 for (i = 0; i < env->nb_BATs; i++) {
David Gibson9986ed12013-03-12 00:31:33 +0000172 target_ulong batu = BATut[i];
173 target_ulong batl = BATlt[i];
David Gibson6fc76aa2013-03-12 00:31:35 +0000174 target_ulong mask;
David Gibson9986ed12013-03-12 00:31:33 +0000175
David Gibson98132792013-03-12 00:31:16 +0000176 if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
David Gibson7ef23062016-01-14 15:33:27 +1100177 mask = hash32_bat_601_size(cpu, batu, batl);
David Gibson98132792013-03-12 00:31:16 +0000178 } else {
David Gibson7ef23062016-01-14 15:33:27 +1100179 mask = hash32_bat_size(cpu, batu, batl);
David Gibson98132792013-03-12 00:31:16 +0000180 }
181 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
182 " BATl " TARGET_FMT_lx "\n", __func__,
David Gibson145e52f2013-03-12 00:31:36 +0000183 type == ACCESS_CODE ? 'I' : 'D', i, ea, batu, batl);
David Gibson6fc76aa2013-03-12 00:31:35 +0000184
David Gibson145e52f2013-03-12 00:31:36 +0000185 if (mask && ((ea & mask) == (batu & BATU32_BEPI))) {
186 hwaddr raddr = (batl & mask) | (ea & ~mask);
187
188 if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
David Gibson7ef23062016-01-14 15:33:27 +1100189 *prot = hash32_bat_601_prot(cpu, batu, batl);
David Gibson145e52f2013-03-12 00:31:36 +0000190 } else {
David Gibson7ef23062016-01-14 15:33:27 +1100191 *prot = hash32_bat_prot(cpu, batu, batl);
David Gibson98132792013-03-12 00:31:16 +0000192 }
David Gibson145e52f2013-03-12 00:31:36 +0000193
194 return raddr & TARGET_PAGE_MASK;
David Gibson98132792013-03-12 00:31:16 +0000195 }
196 }
David Gibson145e52f2013-03-12 00:31:36 +0000197
David Gibson98132792013-03-12 00:31:16 +0000198 /* No hit */
David Gibson145e52f2013-03-12 00:31:36 +0000199#if defined(DEBUG_BATS)
200 if (qemu_log_enabled()) {
201 LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", ea);
202 for (i = 0; i < 4; i++) {
203 BATu = &BATut[i];
204 BATl = &BATlt[i];
205 BEPIu = *BATu & BATU32_BEPIU;
206 BEPIl = *BATu & BATU32_BEPIL;
207 bl = (*BATu & 0x00001FFC) << 15;
208 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
209 " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
210 TARGET_FMT_lx " " TARGET_FMT_lx "\n",
211 __func__, type == ACCESS_CODE ? 'I' : 'D', i, ea,
212 *BATu, *BATl, BEPIu, BEPIl, bl);
213 }
214 }
215#endif
216
217 return -1;
David Gibson98132792013-03-12 00:31:16 +0000218}
219
David Gibson7ef23062016-01-14 15:33:27 +1100220static int ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr,
David Gibson723ed732013-03-12 00:31:25 +0000221 target_ulong eaddr, int rwx,
222 hwaddr *raddr, int *prot)
223{
David Gibson7ef23062016-01-14 15:33:27 +1100224 CPUState *cs = CPU(cpu);
225 CPUPPCState *env = &cpu->env;
David Gibson723ed732013-03-12 00:31:25 +0000226 int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
227
Antony Pavlov339aaf52014-12-13 19:48:18 +0300228 qemu_log_mask(CPU_LOG_MMU, "direct store...\n");
David Gibson723ed732013-03-12 00:31:25 +0000229
230 if ((sr & 0x1FF00000) >> 20 == 0x07f) {
David Gibson596e3ca2019-03-21 22:29:06 +1100231 /*
232 * Memory-forced I/O controller interface access
233 *
234 * If T=1 and BUID=x'07F', the 601 performs a memory access
David Gibson723ed732013-03-12 00:31:25 +0000235 * to SR[28-31] LA[4-31], bypassing all protection mechanisms.
236 */
237 *raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
238 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
239 return 0;
240 }
241
242 if (rwx == 2) {
243 /* No code fetch is allowed in direct-store areas */
Andreas Färber27103422013-08-26 08:31:06 +0200244 cs->exception_index = POWERPC_EXCP_ISI;
David Gibsoncaa597b2013-03-12 00:31:46 +0000245 env->error_code = 0x10000000;
246 return 1;
David Gibson723ed732013-03-12 00:31:25 +0000247 }
248
249 switch (env->access_type) {
250 case ACCESS_INT:
251 /* Integer load/store : only access allowed */
252 break;
253 case ACCESS_FLOAT:
254 /* Floating point load/store */
Andreas Färber27103422013-08-26 08:31:06 +0200255 cs->exception_index = POWERPC_EXCP_ALIGN;
David Gibsoncaa597b2013-03-12 00:31:46 +0000256 env->error_code = POWERPC_EXCP_ALIGN_FP;
257 env->spr[SPR_DAR] = eaddr;
258 return 1;
David Gibson723ed732013-03-12 00:31:25 +0000259 case ACCESS_RES:
260 /* lwarx, ldarx or srwcx. */
David Gibsoncaa597b2013-03-12 00:31:46 +0000261 env->error_code = 0;
262 env->spr[SPR_DAR] = eaddr;
263 if (rwx == 1) {
264 env->spr[SPR_DSISR] = 0x06000000;
265 } else {
266 env->spr[SPR_DSISR] = 0x04000000;
267 }
268 return 1;
David Gibson723ed732013-03-12 00:31:25 +0000269 case ACCESS_CACHE:
David Gibson596e3ca2019-03-21 22:29:06 +1100270 /*
271 * dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi
272 *
273 * Should make the instruction do no-op. As it already do
274 * no-op, it's quite easy :-)
David Gibson723ed732013-03-12 00:31:25 +0000275 */
276 *raddr = eaddr;
277 return 0;
278 case ACCESS_EXT:
279 /* eciwx or ecowx */
Andreas Färber27103422013-08-26 08:31:06 +0200280 cs->exception_index = POWERPC_EXCP_DSI;
David Gibsoncaa597b2013-03-12 00:31:46 +0000281 env->error_code = 0;
282 env->spr[SPR_DAR] = eaddr;
283 if (rwx == 1) {
284 env->spr[SPR_DSISR] = 0x06100000;
285 } else {
286 env->spr[SPR_DSISR] = 0x04100000;
287 }
288 return 1;
David Gibson723ed732013-03-12 00:31:25 +0000289 default:
Paolo Bonzini48880da2015-11-13 13:34:23 +0100290 cpu_abort(cs, "ERROR: instruction should not need "
David Gibson723ed732013-03-12 00:31:25 +0000291 "address translation\n");
David Gibson723ed732013-03-12 00:31:25 +0000292 }
293 if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) {
294 *raddr = eaddr;
David Gibsoncaa597b2013-03-12 00:31:46 +0000295 return 0;
David Gibson723ed732013-03-12 00:31:25 +0000296 } else {
Andreas Färber27103422013-08-26 08:31:06 +0200297 cs->exception_index = POWERPC_EXCP_DSI;
David Gibsoncaa597b2013-03-12 00:31:46 +0000298 env->error_code = 0;
299 env->spr[SPR_DAR] = eaddr;
300 if (rwx == 1) {
301 env->spr[SPR_DSISR] = 0x0a000000;
302 } else {
303 env->spr[SPR_DSISR] = 0x08000000;
304 }
305 return 1;
David Gibson723ed732013-03-12 00:31:25 +0000306 }
307}
308
David Gibson7ef23062016-01-14 15:33:27 +1100309hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash)
David Gibson59191722013-03-12 00:31:15 +0000310{
David Gibson36778662017-02-24 16:36:44 +1100311 target_ulong mask = ppc_hash32_hpt_mask(cpu);
David Gibson7ef23062016-01-14 15:33:27 +1100312
David Gibson36778662017-02-24 16:36:44 +1100313 return (hash * HASH_PTEG_SIZE_32) & mask;
David Gibson59191722013-03-12 00:31:15 +0000314}
315
David Gibson7ef23062016-01-14 15:33:27 +1100316static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, hwaddr pteg_off,
David Gibsonaea390e2013-03-12 00:31:28 +0000317 bool secondary, target_ulong ptem,
318 ppc_hash_pte32_t *pte)
319{
320 hwaddr pte_offset = pteg_off;
321 target_ulong pte0, pte1;
322 int i;
323
324 for (i = 0; i < HPTES_PER_GROUP; i++) {
David Gibson7ef23062016-01-14 15:33:27 +1100325 pte0 = ppc_hash32_load_hpte0(cpu, pte_offset);
Benjamin Herrenschmidt3054b0c2019-02-15 18:00:23 +0100326 /*
327 * pte0 contains the valid bit and must be read before pte1,
328 * otherwise we might see an old pte1 with a new valid bit and
329 * thus an inconsistent hpte value
330 */
331 smp_rmb();
David Gibson7ef23062016-01-14 15:33:27 +1100332 pte1 = ppc_hash32_load_hpte1(cpu, pte_offset);
David Gibsonaea390e2013-03-12 00:31:28 +0000333
334 if ((pte0 & HPTE32_V_VALID)
335 && (secondary == !!(pte0 & HPTE32_V_SECONDARY))
336 && HPTE32_V_COMPARE(pte0, ptem)) {
337 pte->pte0 = pte0;
338 pte->pte1 = pte1;
339 return pte_offset;
340 }
341
342 pte_offset += HASH_PTE_SIZE_32;
343 }
344
345 return -1;
346}
347
Benjamin Herrenschmidt6e8a65a2019-04-11 10:00:02 +0200348static void ppc_hash32_set_r(PowerPCCPU *cpu, hwaddr pte_offset, uint32_t pte1)
349{
350 target_ulong base = ppc_hash32_hpt_base(cpu);
351 hwaddr offset = pte_offset + 6;
352
353 /* The HW performs a non-atomic byte update */
354 stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01);
355}
356
357static void ppc_hash32_set_c(PowerPCCPU *cpu, hwaddr pte_offset, uint64_t pte1)
358{
359 target_ulong base = ppc_hash32_hpt_base(cpu);
360 hwaddr offset = pte_offset + 7;
361
362 /* The HW performs a non-atomic byte update */
363 stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
364}
365
David Gibson7ef23062016-01-14 15:33:27 +1100366static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu,
David Gibson7f3bdc22013-03-12 00:31:30 +0000367 target_ulong sr, target_ulong eaddr,
368 ppc_hash_pte32_t *pte)
David Gibsonc69b6152013-03-12 00:31:08 +0000369{
David Gibsonaea390e2013-03-12 00:31:28 +0000370 hwaddr pteg_off, pte_offset;
David Gibsona1ff7512013-03-12 00:31:29 +0000371 hwaddr hash;
372 uint32_t vsid, pgidx, ptem;
David Gibsonc69b6152013-03-12 00:31:08 +0000373
David Gibsona1ff7512013-03-12 00:31:29 +0000374 vsid = sr & SR32_VSID;
David Gibsona1ff7512013-03-12 00:31:29 +0000375 pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
376 hash = vsid ^ pgidx;
377 ptem = (vsid << 7) | (pgidx >> 10);
378
379 /* Page address translation */
Antony Pavlov339aaf52014-12-13 19:48:18 +0300380 qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
381 " htab_mask " TARGET_FMT_plx
David Gibsona1ff7512013-03-12 00:31:29 +0000382 " hash " TARGET_FMT_plx "\n",
David Gibson36778662017-02-24 16:36:44 +1100383 ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash);
David Gibsona1ff7512013-03-12 00:31:29 +0000384
385 /* Primary PTEG lookup */
Antony Pavlov339aaf52014-12-13 19:48:18 +0300386 qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
David Gibsona1ff7512013-03-12 00:31:29 +0000387 " vsid=%" PRIx32 " ptem=%" PRIx32
388 " hash=" TARGET_FMT_plx "\n",
David Gibson36778662017-02-24 16:36:44 +1100389 ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu),
390 vsid, ptem, hash);
David Gibson7ef23062016-01-14 15:33:27 +1100391 pteg_off = get_pteg_offset32(cpu, hash);
392 pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte);
David Gibsona1ff7512013-03-12 00:31:29 +0000393 if (pte_offset == -1) {
394 /* Secondary PTEG lookup */
Antony Pavlov339aaf52014-12-13 19:48:18 +0300395 qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
David Gibsona1ff7512013-03-12 00:31:29 +0000396 " vsid=%" PRIx32 " api=%" PRIx32
David Gibson36778662017-02-24 16:36:44 +1100397 " hash=" TARGET_FMT_plx "\n", ppc_hash32_hpt_base(cpu),
398 ppc_hash32_hpt_mask(cpu), vsid, ptem, ~hash);
David Gibson7ef23062016-01-14 15:33:27 +1100399 pteg_off = get_pteg_offset32(cpu, ~hash);
400 pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte);
David Gibsona1ff7512013-03-12 00:31:29 +0000401 }
402
David Gibson7f3bdc22013-03-12 00:31:30 +0000403 return pte_offset;
David Gibsonc69b6152013-03-12 00:31:08 +0000404}
David Gibson04808842013-03-12 00:31:09 +0000405
David Gibson6d11d992013-03-12 00:31:43 +0000406static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
407 target_ulong eaddr)
408{
David Gibson75d5ec82013-03-12 00:31:44 +0000409 hwaddr rpn = pte.pte1 & HPTE32_R_RPN;
David Gibson6d11d992013-03-12 00:31:43 +0000410 hwaddr mask = ~TARGET_PAGE_MASK;
411
412 return (rpn & ~mask) | (eaddr & mask);
413}
414
Paolo Bonzinib2305602016-03-15 15:12:16 +0100415int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
David Gibsoncaa597b2013-03-12 00:31:46 +0000416 int mmu_idx)
David Gibson04808842013-03-12 00:31:09 +0000417{
Andreas Färberd0e39c52013-09-02 14:14:24 +0200418 CPUState *cs = CPU(cpu);
419 CPUPPCState *env = &cpu->env;
David Gibsona1ff7512013-03-12 00:31:29 +0000420 target_ulong sr;
David Gibson7f3bdc22013-03-12 00:31:30 +0000421 hwaddr pte_offset;
422 ppc_hash_pte32_t pte;
David Gibsoncaa597b2013-03-12 00:31:46 +0000423 int prot;
David Gibsone01b4442013-03-12 00:31:40 +0000424 const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
David Gibsoncaa597b2013-03-12 00:31:46 +0000425 hwaddr raddr;
David Gibson04808842013-03-12 00:31:09 +0000426
David Gibson6a980112013-03-12 00:31:32 +0000427 assert((rwx == 0) || (rwx == 1) || (rwx == 2));
428
David Gibson65d61642013-03-12 00:31:23 +0000429 /* 1. Handle real mode accesses */
430 if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
431 /* Translation is off */
David Gibsoncaa597b2013-03-12 00:31:46 +0000432 raddr = eaddr;
Andreas Färber0c591eb2013-09-03 13:59:37 +0200433 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
David Gibsoncaa597b2013-03-12 00:31:46 +0000434 PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
435 TARGET_PAGE_SIZE);
David Gibson65d61642013-03-12 00:31:23 +0000436 return 0;
437 }
438
439 /* 2. Check Block Address Translation entries (BATs) */
440 if (env->nb_BATs != 0) {
David Gibson7ef23062016-01-14 15:33:27 +1100441 raddr = ppc_hash32_bat_lookup(cpu, eaddr, rwx, &prot);
David Gibsoncaa597b2013-03-12 00:31:46 +0000442 if (raddr != -1) {
443 if (need_prot[rwx] & ~prot) {
444 if (rwx == 2) {
Andreas Färber27103422013-08-26 08:31:06 +0200445 cs->exception_index = POWERPC_EXCP_ISI;
David Gibsoncaa597b2013-03-12 00:31:46 +0000446 env->error_code = 0x08000000;
447 } else {
Andreas Färber27103422013-08-26 08:31:06 +0200448 cs->exception_index = POWERPC_EXCP_DSI;
David Gibsoncaa597b2013-03-12 00:31:46 +0000449 env->error_code = 0;
450 env->spr[SPR_DAR] = eaddr;
451 if (rwx == 1) {
452 env->spr[SPR_DSISR] = 0x0a000000;
453 } else {
454 env->spr[SPR_DSISR] = 0x08000000;
455 }
456 }
457 return 1;
David Gibsone01b4442013-03-12 00:31:40 +0000458 }
David Gibsoncaa597b2013-03-12 00:31:46 +0000459
Andreas Färber0c591eb2013-09-03 13:59:37 +0200460 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
David Gibsoncaa597b2013-03-12 00:31:46 +0000461 raddr & TARGET_PAGE_MASK, prot, mmu_idx,
462 TARGET_PAGE_SIZE);
David Gibsone01b4442013-03-12 00:31:40 +0000463 return 0;
David Gibson65d61642013-03-12 00:31:23 +0000464 }
465 }
466
David Gibson4b9605a2013-03-12 00:31:24 +0000467 /* 3. Look up the Segment Register */
David Gibson04808842013-03-12 00:31:09 +0000468 sr = env->sr[eaddr >> 28];
David Gibson4b9605a2013-03-12 00:31:24 +0000469
David Gibson723ed732013-03-12 00:31:25 +0000470 /* 4. Handle direct store segments */
471 if (sr & SR32_T) {
David Gibson7ef23062016-01-14 15:33:27 +1100472 if (ppc_hash32_direct_store(cpu, sr, eaddr, rwx,
David Gibsoncaa597b2013-03-12 00:31:46 +0000473 &raddr, &prot) == 0) {
Andreas Färber0c591eb2013-09-03 13:59:37 +0200474 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
David Gibsoncaa597b2013-03-12 00:31:46 +0000475 raddr & TARGET_PAGE_MASK, prot, mmu_idx,
476 TARGET_PAGE_SIZE);
477 return 0;
478 } else {
479 return 1;
480 }
David Gibson723ed732013-03-12 00:31:25 +0000481 }
482
David Gibsonbb218042013-03-12 00:31:26 +0000483 /* 5. Check for segment level no-execute violation */
David Gibsone01b4442013-03-12 00:31:40 +0000484 if ((rwx == 2) && (sr & SR32_NX)) {
Andreas Färber27103422013-08-26 08:31:06 +0200485 cs->exception_index = POWERPC_EXCP_ISI;
David Gibsoncaa597b2013-03-12 00:31:46 +0000486 env->error_code = 0x10000000;
487 return 1;
David Gibsonbb218042013-03-12 00:31:26 +0000488 }
David Gibson7f3bdc22013-03-12 00:31:30 +0000489
490 /* 6. Locate the PTE in the hash table */
David Gibson7ef23062016-01-14 15:33:27 +1100491 pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte);
David Gibson7f3bdc22013-03-12 00:31:30 +0000492 if (pte_offset == -1) {
David Gibsoncaa597b2013-03-12 00:31:46 +0000493 if (rwx == 2) {
Andreas Färber27103422013-08-26 08:31:06 +0200494 cs->exception_index = POWERPC_EXCP_ISI;
David Gibsoncaa597b2013-03-12 00:31:46 +0000495 env->error_code = 0x40000000;
496 } else {
Andreas Färber27103422013-08-26 08:31:06 +0200497 cs->exception_index = POWERPC_EXCP_DSI;
David Gibsoncaa597b2013-03-12 00:31:46 +0000498 env->error_code = 0;
499 env->spr[SPR_DAR] = eaddr;
500 if (rwx == 1) {
501 env->spr[SPR_DSISR] = 0x42000000;
502 } else {
503 env->spr[SPR_DSISR] = 0x40000000;
504 }
505 }
506
507 return 1;
David Gibson7f3bdc22013-03-12 00:31:30 +0000508 }
Antony Pavlov339aaf52014-12-13 19:48:18 +0300509 qemu_log_mask(CPU_LOG_MMU,
510 "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
David Gibson7f3bdc22013-03-12 00:31:30 +0000511
512 /* 7. Check access permissions */
David Gibson6a980112013-03-12 00:31:32 +0000513
David Gibson7ef23062016-01-14 15:33:27 +1100514 prot = ppc_hash32_pte_prot(cpu, sr, pte);
David Gibson6a980112013-03-12 00:31:32 +0000515
David Gibsoncaa597b2013-03-12 00:31:46 +0000516 if (need_prot[rwx] & ~prot) {
David Gibson6a980112013-03-12 00:31:32 +0000517 /* Access right violation */
Antony Pavlov339aaf52014-12-13 19:48:18 +0300518 qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
David Gibsoncaa597b2013-03-12 00:31:46 +0000519 if (rwx == 2) {
Andreas Färber27103422013-08-26 08:31:06 +0200520 cs->exception_index = POWERPC_EXCP_ISI;
David Gibsoncaa597b2013-03-12 00:31:46 +0000521 env->error_code = 0x08000000;
522 } else {
Andreas Färber27103422013-08-26 08:31:06 +0200523 cs->exception_index = POWERPC_EXCP_DSI;
David Gibsoncaa597b2013-03-12 00:31:46 +0000524 env->error_code = 0;
525 env->spr[SPR_DAR] = eaddr;
526 if (rwx == 1) {
527 env->spr[SPR_DSISR] = 0x0a000000;
528 } else {
529 env->spr[SPR_DSISR] = 0x08000000;
530 }
531 }
532 return 1;
David Gibson6a980112013-03-12 00:31:32 +0000533 }
534
Antony Pavlov339aaf52014-12-13 19:48:18 +0300535 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
David Gibson87dc3fd2013-03-12 00:31:38 +0000536
537 /* 8. Update PTE referenced and changed bits if necessary */
538
Benjamin Herrenschmidt6e8a65a2019-04-11 10:00:02 +0200539 if (!(pte.pte1 & HPTE32_R_R)) {
540 ppc_hash32_set_r(cpu, pte_offset, pte.pte1);
David Gibsonb3440742013-03-12 00:31:42 +0000541 }
Benjamin Herrenschmidt6e8a65a2019-04-11 10:00:02 +0200542 if (!(pte.pte1 & HPTE32_R_C)) {
543 if (rwx == 1) {
544 ppc_hash32_set_c(cpu, pte_offset, pte.pte1);
545 } else {
546 /*
547 * Treat the page as read-only for now, so that a later write
548 * will pass through this function again to set the C bit
549 */
550 prot &= ~PAGE_WRITE;
551 }
552 }
David Gibson4b9605a2013-03-12 00:31:24 +0000553
David Gibson6d11d992013-03-12 00:31:43 +0000554 /* 9. Determine the real address from the PTE */
555
David Gibsoncaa597b2013-03-12 00:31:46 +0000556 raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
557
Andreas Färber0c591eb2013-09-03 13:59:37 +0200558 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
David Gibsoncaa597b2013-03-12 00:31:46 +0000559 prot, mmu_idx, TARGET_PAGE_SIZE);
David Gibsone01b4442013-03-12 00:31:40 +0000560
561 return 0;
David Gibson04808842013-03-12 00:31:09 +0000562}
David Gibson629bd512013-03-12 00:31:11 +0000563
David Gibson7ef23062016-01-14 15:33:27 +1100564hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
David Gibsonf2ad6be2013-03-12 00:31:13 +0000565{
David Gibson7ef23062016-01-14 15:33:27 +1100566 CPUPPCState *env = &cpu->env;
David Gibson5883d8b2013-03-12 00:31:45 +0000567 target_ulong sr;
568 hwaddr pte_offset;
569 ppc_hash_pte32_t pte;
570 int prot;
David Gibsonf2ad6be2013-03-12 00:31:13 +0000571
David Gibson5883d8b2013-03-12 00:31:45 +0000572 if (msr_dr == 0) {
573 /* Translation is off */
574 return eaddr;
575 }
576
577 if (env->nb_BATs != 0) {
David Gibson7ef23062016-01-14 15:33:27 +1100578 hwaddr raddr = ppc_hash32_bat_lookup(cpu, eaddr, 0, &prot);
David Gibson5883d8b2013-03-12 00:31:45 +0000579 if (raddr != -1) {
580 return raddr;
581 }
582 }
583
584 sr = env->sr[eaddr >> 28];
585
586 if (sr & SR32_T) {
587 /* FIXME: Add suitable debug support for Direct Store segments */
David Gibsonf2ad6be2013-03-12 00:31:13 +0000588 return -1;
589 }
590
David Gibson7ef23062016-01-14 15:33:27 +1100591 pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte);
David Gibson5883d8b2013-03-12 00:31:45 +0000592 if (pte_offset == -1) {
593 return -1;
594 }
595
596 return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;
David Gibsonf2ad6be2013-03-12 00:31:13 +0000597}