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thsf0fc6f82007-10-17 13:39:42 +00001/*
2 * QEMU/mipssim emulation
3 *
4 * Emulates a very simple machine model similiar to the one use by the
5 * proprietary MIPS emulator.
thsa79ee212007-10-31 17:14:08 +00006 *
7 * Copyright (c) 2007 Thiemo Seufer
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
thsf0fc6f82007-10-17 13:39:42 +000026 */
pbrook87ecb682007-11-17 17:14:51 +000027#include "hw.h"
28#include "mips.h"
Blue Swirlb970ea82010-03-27 07:26:16 +000029#include "mips_cpudevs.h"
pbrook87ecb682007-11-17 17:14:51 +000030#include "pc.h"
31#include "isa.h"
32#include "net.h"
33#include "sysemu.h"
34#include "boards.h"
Paul Brookbba831e2009-05-19 14:52:42 +010035#include "mips-bios.h"
Blue Swirlca20cf32009-09-20 14:58:02 +000036#include "loader.h"
37#include "elf.h"
thsf0fc6f82007-10-17 13:39:42 +000038
ths7df526e2007-11-09 17:52:11 +000039static struct _loaderparams {
40 int ram_size;
41 const char *kernel_filename;
42 const char *kernel_cmdline;
43 const char *initrd_filename;
44} loaderparams;
45
Aurelien Jarnoe16ad5b2009-11-14 01:04:29 +010046typedef struct ResetData {
47 CPUState *env;
48 uint64_t vector;
49} ResetData;
50
51static int64_t load_kernel(void)
thsf0fc6f82007-10-17 13:39:42 +000052{
Aurelien Jarno409dbce2010-03-14 21:20:59 +010053 int64_t entry, kernel_high;
thsf0fc6f82007-10-17 13:39:42 +000054 long kernel_size;
55 long initrd_size;
Anthony Liguoric227f092009-10-01 16:12:16 -050056 ram_addr_t initrd_offset;
Blue Swirlca20cf32009-09-20 14:58:02 +000057 int big_endian;
58
59#ifdef TARGET_WORDS_BIGENDIAN
60 big_endian = 1;
61#else
62 big_endian = 0;
63#endif
thsf0fc6f82007-10-17 13:39:42 +000064
Aurelien Jarno409dbce2010-03-14 21:20:59 +010065 kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys,
66 NULL, (uint64_t *)&entry, NULL,
67 (uint64_t *)&kernel_high, big_endian,
68 ELF_MACHINE, 1);
thsf0fc6f82007-10-17 13:39:42 +000069 if (kernel_size >= 0) {
70 if ((entry & ~0x7fffffffULL) == 0x80000000)
71 entry = (int32_t)entry;
thsf0fc6f82007-10-17 13:39:42 +000072 } else {
73 fprintf(stderr, "qemu: could not load kernel '%s'\n",
ths7df526e2007-11-09 17:52:11 +000074 loaderparams.kernel_filename);
thsf0fc6f82007-10-17 13:39:42 +000075 exit(1);
76 }
77
78 /* load initrd */
79 initrd_size = 0;
80 initrd_offset = 0;
ths7df526e2007-11-09 17:52:11 +000081 if (loaderparams.initrd_filename) {
82 initrd_size = get_image_size (loaderparams.initrd_filename);
thsf0fc6f82007-10-17 13:39:42 +000083 if (initrd_size > 0) {
84 initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
ths7df526e2007-11-09 17:52:11 +000085 if (initrd_offset + initrd_size > loaderparams.ram_size) {
thsf0fc6f82007-10-17 13:39:42 +000086 fprintf(stderr,
87 "qemu: memory too small for initial ram disk '%s'\n",
ths7df526e2007-11-09 17:52:11 +000088 loaderparams.initrd_filename);
thsf0fc6f82007-10-17 13:39:42 +000089 exit(1);
90 }
pbrookdcac9672009-04-09 20:05:49 +000091 initrd_size = load_image_targphys(loaderparams.initrd_filename,
92 initrd_offset, loaderparams.ram_size - initrd_offset);
thsf0fc6f82007-10-17 13:39:42 +000093 }
94 if (initrd_size == (target_ulong) -1) {
95 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
ths7df526e2007-11-09 17:52:11 +000096 loaderparams.initrd_filename);
thsf0fc6f82007-10-17 13:39:42 +000097 exit(1);
98 }
99 }
Aurelien Jarnoe16ad5b2009-11-14 01:04:29 +0100100 return entry;
thsf0fc6f82007-10-17 13:39:42 +0000101}
102
103static void main_cpu_reset(void *opaque)
104{
Aurelien Jarnoe16ad5b2009-11-14 01:04:29 +0100105 ResetData *s = (ResetData *)opaque;
106 CPUState *env = s->env;
thsf0fc6f82007-10-17 13:39:42 +0000107
Aurelien Jarnoe16ad5b2009-11-14 01:04:29 +0100108 cpu_reset(env);
Nathan Froydaecf1372010-06-08 13:30:03 -0700109 env->active_tc.PC = s->vector & ~(target_ulong)1;
110 if (s->vector & 1) {
111 env->hflags |= MIPS_HFLAG_M16;
112 }
thsf0fc6f82007-10-17 13:39:42 +0000113}
114
115static void
Anthony Liguoric227f092009-10-01 16:12:16 -0500116mips_mipssim_init (ram_addr_t ram_size,
aliguori3023f332009-01-16 19:04:14 +0000117 const char *boot_device,
thsf0fc6f82007-10-17 13:39:42 +0000118 const char *kernel_filename, const char *kernel_cmdline,
119 const char *initrd_filename, const char *cpu_model)
120{
Paul Brook5cea8592009-05-30 00:52:44 +0100121 char *filename;
Anthony Liguoric227f092009-10-01 16:12:16 -0500122 ram_addr_t ram_offset;
123 ram_addr_t bios_offset;
thsf0fc6f82007-10-17 13:39:42 +0000124 CPUState *env;
Aurelien Jarnoe16ad5b2009-11-14 01:04:29 +0100125 ResetData *reset_info;
thsb5334152007-10-18 15:05:11 +0000126 int bios_size;
thsf0fc6f82007-10-17 13:39:42 +0000127
128 /* Init CPUs. */
129 if (cpu_model == NULL) {
130#ifdef TARGET_MIPS64
131 cpu_model = "5Kf";
132#else
133 cpu_model = "24Kf";
134#endif
135 }
bellardaaed9092007-11-10 15:15:54 +0000136 env = cpu_init(cpu_model);
137 if (!env) {
138 fprintf(stderr, "Unable to find CPU definition\n");
139 exit(1);
140 }
Aurelien Jarnoe16ad5b2009-11-14 01:04:29 +0100141 reset_info = qemu_mallocz(sizeof(ResetData));
142 reset_info->env = env;
143 reset_info->vector = env->active_tc.PC;
144 qemu_register_reset(main_cpu_reset, reset_info);
thsf0fc6f82007-10-17 13:39:42 +0000145
146 /* Allocate RAM. */
pbrookdcac9672009-04-09 20:05:49 +0000147 ram_offset = qemu_ram_alloc(ram_size);
148 bios_offset = qemu_ram_alloc(BIOS_SIZE);
thsf0fc6f82007-10-17 13:39:42 +0000149
pbrookdcac9672009-04-09 20:05:49 +0000150 cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
151
152 /* Map the BIOS / boot exception handler. */
153 cpu_register_physical_memory(0x1fc00000LL,
154 BIOS_SIZE, bios_offset | IO_MEM_ROM);
thsf0fc6f82007-10-17 13:39:42 +0000155 /* Load a BIOS / boot exception handler image. */
156 if (bios_name == NULL)
157 bios_name = BIOS_FILENAME;
Paul Brook5cea8592009-05-30 00:52:44 +0100158 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
159 if (filename) {
160 bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
161 qemu_free(filename);
162 } else {
163 bios_size = -1;
164 }
thsb5334152007-10-18 15:05:11 +0000165 if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {
thsf0fc6f82007-10-17 13:39:42 +0000166 /* Bail out if we have neither a kernel image nor boot vector code. */
167 fprintf(stderr,
168 "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
Paul Brook5cea8592009-05-30 00:52:44 +0100169 filename);
thsf0fc6f82007-10-17 13:39:42 +0000170 exit(1);
171 } else {
thsb5334152007-10-18 15:05:11 +0000172 /* We have a boot vector start address. */
thsb5dc7732008-06-27 10:02:35 +0000173 env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
thsf0fc6f82007-10-17 13:39:42 +0000174 }
175
176 if (kernel_filename) {
ths7df526e2007-11-09 17:52:11 +0000177 loaderparams.ram_size = ram_size;
178 loaderparams.kernel_filename = kernel_filename;
179 loaderparams.kernel_cmdline = kernel_cmdline;
180 loaderparams.initrd_filename = initrd_filename;
Aurelien Jarnoe16ad5b2009-11-14 01:04:29 +0100181 reset_info->vector = load_kernel();
thsf0fc6f82007-10-17 13:39:42 +0000182 }
183
184 /* Init CPU internal devices. */
185 cpu_mips_irq_init_cpu(env);
186 cpu_mips_clock_init(env);
thsf0fc6f82007-10-17 13:39:42 +0000187
188 /* Register 64 KB of ISA IO space at 0x1fd00000. */
Blue Swirl84108e12010-03-21 19:47:09 +0000189#ifdef TARGET_WORDS_BIGENDIAN
190 isa_mmio_init(0x1fd00000, 0x00010000, 1);
191#else
192 isa_mmio_init(0x1fd00000, 0x00010000, 0);
193#endif
thsf0fc6f82007-10-17 13:39:42 +0000194
195 /* A single 16450 sits at offset 0x3f8. It is attached to
196 MIPS CPU INT2, which is interrupt 4. */
197 if (serial_hds[0])
aurel32b6cd0ea2008-05-04 21:42:11 +0000198 serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]);
thsf0fc6f82007-10-17 13:39:42 +0000199
aliguori0ae18ce2009-01-13 19:39:36 +0000200 if (nd_table[0].vlan)
201 /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
202 mipsnet_init(0x4200, env->irq[2], &nd_table[0]);
thsf0fc6f82007-10-17 13:39:42 +0000203}
204
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500205static QEMUMachine mips_mipssim_machine = {
thseec27432008-08-13 13:01:28 +0000206 .name = "mipssim",
207 .desc = "MIPS MIPSsim platform",
208 .init = mips_mipssim_init,
thsf0fc6f82007-10-17 13:39:42 +0000209};
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500210
211static void mips_mipssim_machine_init(void)
212{
213 qemu_register_machine(&mips_mipssim_machine);
214}
215
216machine_init(mips_mipssim_machine_init);