ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 1 | /* |
edgar_igl | e62b5b1 | 2008-03-14 01:04:24 +0000 | [diff] [blame] | 2 | * QEMU ETRAX Timers |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 24 | |
Peter Maydell | 282bc81 | 2016-01-26 18:17:18 +0000 | [diff] [blame] | 25 | #include "qemu/osdep.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 26 | #include "hw/sysbus.h" |
Markus Armbruster | 71e8a91 | 2019-08-12 07:23:38 +0200 | [diff] [blame] | 27 | #include "sysemu/reset.h" |
Markus Armbruster | 54d3123 | 2019-08-12 07:23:59 +0200 | [diff] [blame] | 28 | #include "sysemu/runstate.h" |
Philippe Mathieu-Daudé | 6446a79 | 2021-11-06 11:56:23 +0100 | [diff] [blame] | 29 | #include "migration/vmstate.h" |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 30 | #include "qemu/module.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 31 | #include "qemu/timer.h" |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 32 | #include "hw/irq.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 33 | #include "hw/ptimer.h" |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 34 | #include "qom/object.h" |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 35 | |
edgar_igl | bbaf29c | 2008-03-01 17:25:33 +0000 | [diff] [blame] | 36 | #define D(x) |
| 37 | |
edgar_igl | ca87d03 | 2008-03-14 01:50:49 +0000 | [diff] [blame] | 38 | #define RW_TMR0_DIV 0x00 |
| 39 | #define R_TMR0_DATA 0x04 |
| 40 | #define RW_TMR0_CTRL 0x08 |
| 41 | #define RW_TMR1_DIV 0x10 |
| 42 | #define R_TMR1_DATA 0x14 |
| 43 | #define RW_TMR1_CTRL 0x18 |
| 44 | #define R_TIME 0x38 |
| 45 | #define RW_WD_CTRL 0x40 |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 46 | #define R_WD_STAT 0x44 |
edgar_igl | ca87d03 | 2008-03-14 01:50:49 +0000 | [diff] [blame] | 47 | #define RW_INTR_MASK 0x48 |
| 48 | #define RW_ACK_INTR 0x4c |
| 49 | #define R_INTR 0x50 |
| 50 | #define R_MASKED_INTR 0x54 |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 51 | |
Markus Armbruster | e178113 | 2021-03-04 15:02:28 +0100 | [diff] [blame] | 52 | #define TYPE_ETRAX_FS_TIMER "etraxfs-timer" |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 53 | typedef struct ETRAXTimerState ETRAXTimerState; |
Eduardo Habkost | 8110fa1 | 2020-08-31 17:07:33 -0400 | [diff] [blame] | 54 | DECLARE_INSTANCE_CHECKER(ETRAXTimerState, ETRAX_TIMER, |
| 55 | TYPE_ETRAX_FS_TIMER) |
Andreas Färber | 5880ce5 | 2013-07-27 14:34:22 +0200 | [diff] [blame] | 56 | |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 57 | struct ETRAXTimerState { |
Andreas Färber | 5880ce5 | 2013-07-27 14:34:22 +0200 | [diff] [blame] | 58 | SysBusDevice parent_obj; |
| 59 | |
Edgar E. Iglesias | b8e5da2 | 2011-08-11 13:47:46 +0200 | [diff] [blame] | 60 | MemoryRegion mmio; |
Edgar E. Iglesias | 3b1fd90 | 2009-05-16 02:08:16 +0200 | [diff] [blame] | 61 | qemu_irq irq; |
| 62 | qemu_irq nmi; |
edgar_igl | ca87d03 | 2008-03-14 01:50:49 +0000 | [diff] [blame] | 63 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 64 | ptimer_state *ptimer_t0; |
| 65 | ptimer_state *ptimer_t1; |
| 66 | ptimer_state *ptimer_wd; |
edgar_igl | e62b5b1 | 2008-03-14 01:04:24 +0000 | [diff] [blame] | 67 | |
Philippe Mathieu-Daudé | 6446a79 | 2021-11-06 11:56:23 +0100 | [diff] [blame] | 68 | uint32_t wd_hits; |
edgar_igl | 5ef98b4 | 2008-06-09 23:33:30 +0000 | [diff] [blame] | 69 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 70 | /* Control registers. */ |
| 71 | uint32_t rw_tmr0_div; |
| 72 | uint32_t r_tmr0_data; |
| 73 | uint32_t rw_tmr0_ctrl; |
edgar_igl | 6023722 | 2008-05-02 22:32:02 +0000 | [diff] [blame] | 74 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 75 | uint32_t rw_tmr1_div; |
| 76 | uint32_t r_tmr1_data; |
| 77 | uint32_t rw_tmr1_ctrl; |
edgar_igl | 6023722 | 2008-05-02 22:32:02 +0000 | [diff] [blame] | 78 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 79 | uint32_t rw_wd_ctrl; |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 80 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 81 | uint32_t rw_intr_mask; |
| 82 | uint32_t rw_ack_intr; |
| 83 | uint32_t r_intr; |
| 84 | uint32_t r_masked_intr; |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 85 | }; |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 86 | |
Philippe Mathieu-Daudé | 6446a79 | 2021-11-06 11:56:23 +0100 | [diff] [blame] | 87 | static const VMStateDescription vmstate_etraxfs = { |
| 88 | .name = "etraxfs", |
| 89 | .version_id = 0, |
| 90 | .minimum_version_id = 0, |
Richard Henderson | ba324b3 | 2023-12-21 14:16:37 +1100 | [diff] [blame] | 91 | .fields = (const VMStateField[]) { |
Philippe Mathieu-Daudé | 6446a79 | 2021-11-06 11:56:23 +0100 | [diff] [blame] | 92 | VMSTATE_PTIMER(ptimer_t0, ETRAXTimerState), |
| 93 | VMSTATE_PTIMER(ptimer_t1, ETRAXTimerState), |
| 94 | VMSTATE_PTIMER(ptimer_wd, ETRAXTimerState), |
| 95 | |
| 96 | VMSTATE_UINT32(wd_hits, ETRAXTimerState), |
| 97 | |
| 98 | VMSTATE_UINT32(rw_tmr0_div, ETRAXTimerState), |
| 99 | VMSTATE_UINT32(r_tmr0_data, ETRAXTimerState), |
| 100 | VMSTATE_UINT32(rw_tmr0_ctrl, ETRAXTimerState), |
| 101 | |
| 102 | VMSTATE_UINT32(rw_tmr1_div, ETRAXTimerState), |
| 103 | VMSTATE_UINT32(r_tmr1_data, ETRAXTimerState), |
| 104 | VMSTATE_UINT32(rw_tmr1_ctrl, ETRAXTimerState), |
| 105 | |
| 106 | VMSTATE_UINT32(rw_wd_ctrl, ETRAXTimerState), |
| 107 | |
| 108 | VMSTATE_UINT32(rw_intr_mask, ETRAXTimerState), |
| 109 | VMSTATE_UINT32(rw_ack_intr, ETRAXTimerState), |
| 110 | VMSTATE_UINT32(r_intr, ETRAXTimerState), |
| 111 | VMSTATE_UINT32(r_masked_intr, ETRAXTimerState), |
| 112 | |
| 113 | VMSTATE_END_OF_LIST() |
| 114 | } |
| 115 | }; |
| 116 | |
Edgar E. Iglesias | b8e5da2 | 2011-08-11 13:47:46 +0200 | [diff] [blame] | 117 | static uint64_t |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 118 | timer_read(void *opaque, hwaddr addr, unsigned int size) |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 119 | { |
Andreas Färber | 3c9a8a8 | 2013-07-27 14:30:31 +0200 | [diff] [blame] | 120 | ETRAXTimerState *t = opaque; |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 121 | uint32_t r = 0; |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 122 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 123 | switch (addr) { |
| 124 | case R_TMR0_DATA: |
| 125 | r = ptimer_get_count(t->ptimer_t0); |
| 126 | break; |
| 127 | case R_TMR1_DATA: |
| 128 | r = ptimer_get_count(t->ptimer_t1); |
| 129 | break; |
| 130 | case R_TIME: |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 131 | r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10; |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 132 | break; |
| 133 | case RW_INTR_MASK: |
| 134 | r = t->rw_intr_mask; |
| 135 | break; |
| 136 | case R_MASKED_INTR: |
| 137 | r = t->r_intr & t->rw_intr_mask; |
| 138 | break; |
| 139 | default: |
| 140 | D(printf ("%s %x\n", __func__, addr)); |
| 141 | break; |
| 142 | } |
| 143 | return r; |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 144 | } |
| 145 | |
Andreas Färber | 3c9a8a8 | 2013-07-27 14:30:31 +0200 | [diff] [blame] | 146 | static void update_ctrl(ETRAXTimerState *t, int tnum) |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 147 | { |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 148 | unsigned int op; |
| 149 | unsigned int freq; |
| 150 | unsigned int freq_hz; |
| 151 | unsigned int div; |
| 152 | uint32_t ctrl; |
edgar_igl | 5ef98b4 | 2008-06-09 23:33:30 +0000 | [diff] [blame] | 153 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 154 | ptimer_state *timer; |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 155 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 156 | if (tnum == 0) { |
| 157 | ctrl = t->rw_tmr0_ctrl; |
| 158 | div = t->rw_tmr0_div; |
| 159 | timer = t->ptimer_t0; |
| 160 | } else { |
| 161 | ctrl = t->rw_tmr1_ctrl; |
| 162 | div = t->rw_tmr1_div; |
| 163 | timer = t->ptimer_t1; |
| 164 | } |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 165 | |
| 166 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 167 | op = ctrl & 3; |
| 168 | freq = ctrl >> 2; |
| 169 | freq_hz = 32000000; |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 170 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 171 | switch (freq) |
| 172 | { |
| 173 | case 0: |
| 174 | case 1: |
| 175 | D(printf ("extern or disabled timer clock?\n")); |
| 176 | break; |
| 177 | case 4: freq_hz = 29493000; break; |
| 178 | case 5: freq_hz = 32000000; break; |
| 179 | case 6: freq_hz = 32768000; break; |
| 180 | case 7: freq_hz = 100000000; break; |
| 181 | default: |
| 182 | abort(); |
| 183 | break; |
| 184 | } |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 185 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 186 | D(printf ("freq_hz=%d div=%d\n", freq_hz, div)); |
Peter Maydell | 2cb42c9 | 2019-10-22 16:50:36 +0100 | [diff] [blame] | 187 | ptimer_transaction_begin(timer); |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 188 | ptimer_set_freq(timer, freq_hz); |
| 189 | ptimer_set_limit(timer, div, 0); |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 190 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 191 | switch (op) |
| 192 | { |
| 193 | case 0: |
| 194 | /* Load. */ |
| 195 | ptimer_set_limit(timer, div, 1); |
| 196 | break; |
| 197 | case 1: |
| 198 | /* Hold. */ |
| 199 | ptimer_stop(timer); |
| 200 | break; |
| 201 | case 2: |
| 202 | /* Run. */ |
| 203 | ptimer_run(timer, 0); |
| 204 | break; |
| 205 | default: |
| 206 | abort(); |
| 207 | break; |
| 208 | } |
Peter Maydell | 2cb42c9 | 2019-10-22 16:50:36 +0100 | [diff] [blame] | 209 | ptimer_transaction_commit(timer); |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 210 | } |
| 211 | |
Andreas Färber | 3c9a8a8 | 2013-07-27 14:30:31 +0200 | [diff] [blame] | 212 | static void timer_update_irq(ETRAXTimerState *t) |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 213 | { |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 214 | t->r_intr &= ~(t->rw_ack_intr); |
| 215 | t->r_masked_intr = t->r_intr & t->rw_intr_mask; |
edgar_igl | 6023722 | 2008-05-02 22:32:02 +0000 | [diff] [blame] | 216 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 217 | D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr)); |
Edgar E. Iglesias | 3b1fd90 | 2009-05-16 02:08:16 +0200 | [diff] [blame] | 218 | qemu_set_irq(t->irq, !!t->r_masked_intr); |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 219 | } |
| 220 | |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 221 | static void timer0_hit(void *opaque) |
edgar_igl | 6023722 | 2008-05-02 22:32:02 +0000 | [diff] [blame] | 222 | { |
Andreas Färber | 3c9a8a8 | 2013-07-27 14:30:31 +0200 | [diff] [blame] | 223 | ETRAXTimerState *t = opaque; |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 224 | t->r_intr |= 1; |
| 225 | timer_update_irq(t); |
edgar_igl | 6023722 | 2008-05-02 22:32:02 +0000 | [diff] [blame] | 226 | } |
| 227 | |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 228 | static void timer1_hit(void *opaque) |
| 229 | { |
Andreas Färber | 3c9a8a8 | 2013-07-27 14:30:31 +0200 | [diff] [blame] | 230 | ETRAXTimerState *t = opaque; |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 231 | t->r_intr |= 2; |
| 232 | timer_update_irq(t); |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 233 | } |
| 234 | |
| 235 | static void watchdog_hit(void *opaque) |
| 236 | { |
Andreas Färber | 3c9a8a8 | 2013-07-27 14:30:31 +0200 | [diff] [blame] | 237 | ETRAXTimerState *t = opaque; |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 238 | if (t->wd_hits == 0) { |
Michael Tokarev | 9b4b4e5 | 2023-07-14 14:32:24 +0300 | [diff] [blame] | 239 | /* real hw gives a single tick before resetting but we are |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 240 | a bit friendlier to compensate for our slower execution. */ |
| 241 | ptimer_set_count(t->ptimer_wd, 10); |
| 242 | ptimer_run(t->ptimer_wd, 1); |
Edgar E. Iglesias | 3b1fd90 | 2009-05-16 02:08:16 +0200 | [diff] [blame] | 243 | qemu_irq_raise(t->nmi); |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 244 | } |
| 245 | else |
Eric Blake | cf83f14 | 2017-05-15 16:41:13 -0500 | [diff] [blame] | 246 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
edgar_igl | 5ef98b4 | 2008-06-09 23:33:30 +0000 | [diff] [blame] | 247 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 248 | t->wd_hits++; |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 249 | } |
| 250 | |
Andreas Färber | 3c9a8a8 | 2013-07-27 14:30:31 +0200 | [diff] [blame] | 251 | static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value) |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 252 | { |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 253 | unsigned int wd_en = t->rw_wd_ctrl & (1 << 8); |
| 254 | unsigned int wd_key = t->rw_wd_ctrl >> 9; |
| 255 | unsigned int wd_cnt = t->rw_wd_ctrl & 511; |
| 256 | unsigned int new_key = value >> 9 & ((1 << 7) - 1); |
| 257 | unsigned int new_cmd = (value >> 8) & 1; |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 258 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 259 | /* If the watchdog is enabled, they written key must match the |
| 260 | complement of the previous. */ |
| 261 | wd_key = ~wd_key & ((1 << 7) - 1); |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 262 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 263 | if (wd_en && wd_key != new_key) |
| 264 | return; |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 265 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 266 | D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", |
| 267 | wd_en, new_key, wd_key, new_cmd, wd_cnt)); |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 268 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 269 | if (t->wd_hits) |
Edgar E. Iglesias | 3b1fd90 | 2009-05-16 02:08:16 +0200 | [diff] [blame] | 270 | qemu_irq_lower(t->nmi); |
edgar_igl | 5ef98b4 | 2008-06-09 23:33:30 +0000 | [diff] [blame] | 271 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 272 | t->wd_hits = 0; |
edgar_igl | 5ef98b4 | 2008-06-09 23:33:30 +0000 | [diff] [blame] | 273 | |
Peter Maydell | 2cb42c9 | 2019-10-22 16:50:36 +0100 | [diff] [blame] | 274 | ptimer_transaction_begin(t->ptimer_wd); |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 275 | ptimer_set_freq(t->ptimer_wd, 760); |
| 276 | if (wd_cnt == 0) |
| 277 | wd_cnt = 256; |
| 278 | ptimer_set_count(t->ptimer_wd, wd_cnt); |
| 279 | if (new_cmd) |
| 280 | ptimer_run(t->ptimer_wd, 1); |
| 281 | else |
| 282 | ptimer_stop(t->ptimer_wd); |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 283 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 284 | t->rw_wd_ctrl = value; |
Peter Maydell | 2cb42c9 | 2019-10-22 16:50:36 +0100 | [diff] [blame] | 285 | ptimer_transaction_commit(t->ptimer_wd); |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 286 | } |
| 287 | |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 288 | static void |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 289 | timer_write(void *opaque, hwaddr addr, |
Edgar E. Iglesias | b8e5da2 | 2011-08-11 13:47:46 +0200 | [diff] [blame] | 290 | uint64_t val64, unsigned int size) |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 291 | { |
Andreas Färber | 3c9a8a8 | 2013-07-27 14:30:31 +0200 | [diff] [blame] | 292 | ETRAXTimerState *t = opaque; |
Edgar E. Iglesias | b8e5da2 | 2011-08-11 13:47:46 +0200 | [diff] [blame] | 293 | uint32_t value = val64; |
edgar_igl | bbaf29c | 2008-03-01 17:25:33 +0000 | [diff] [blame] | 294 | |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 295 | switch (addr) |
| 296 | { |
| 297 | case RW_TMR0_DIV: |
| 298 | t->rw_tmr0_div = value; |
| 299 | break; |
| 300 | case RW_TMR0_CTRL: |
| 301 | D(printf ("RW_TMR0_CTRL=%x\n", value)); |
| 302 | t->rw_tmr0_ctrl = value; |
| 303 | update_ctrl(t, 0); |
| 304 | break; |
| 305 | case RW_TMR1_DIV: |
| 306 | t->rw_tmr1_div = value; |
| 307 | break; |
| 308 | case RW_TMR1_CTRL: |
| 309 | D(printf ("RW_TMR1_CTRL=%x\n", value)); |
| 310 | t->rw_tmr1_ctrl = value; |
| 311 | update_ctrl(t, 1); |
| 312 | break; |
| 313 | case RW_INTR_MASK: |
| 314 | D(printf ("RW_INTR_MASK=%x\n", value)); |
| 315 | t->rw_intr_mask = value; |
| 316 | timer_update_irq(t); |
| 317 | break; |
| 318 | case RW_WD_CTRL: |
| 319 | timer_watchdog_update(t, value); |
| 320 | break; |
| 321 | case RW_ACK_INTR: |
| 322 | t->rw_ack_intr = value; |
| 323 | timer_update_irq(t); |
| 324 | t->rw_ack_intr = 0; |
| 325 | break; |
| 326 | default: |
Philippe Mathieu-Daudé | 883f2c5 | 2023-01-10 22:29:47 +0100 | [diff] [blame] | 327 | printf("%s " HWADDR_FMT_plx " %x\n", __func__, addr, value); |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 328 | break; |
| 329 | } |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 330 | } |
| 331 | |
Edgar E. Iglesias | b8e5da2 | 2011-08-11 13:47:46 +0200 | [diff] [blame] | 332 | static const MemoryRegionOps timer_ops = { |
| 333 | .read = timer_read, |
| 334 | .write = timer_write, |
| 335 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 336 | .valid = { |
| 337 | .min_access_size = 4, |
| 338 | .max_access_size = 4 |
| 339 | } |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 340 | }; |
| 341 | |
Philippe Mathieu-Daudé | 72fe474 | 2021-05-02 18:39:30 +0200 | [diff] [blame] | 342 | static void etraxfs_timer_reset_enter(Object *obj, ResetType type) |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 343 | { |
Philippe Mathieu-Daudé | 72fe474 | 2021-05-02 18:39:30 +0200 | [diff] [blame] | 344 | ETRAXTimerState *t = ETRAX_TIMER(obj); |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 345 | |
Peter Maydell | 2cb42c9 | 2019-10-22 16:50:36 +0100 | [diff] [blame] | 346 | ptimer_transaction_begin(t->ptimer_t0); |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 347 | ptimer_stop(t->ptimer_t0); |
Peter Maydell | 2cb42c9 | 2019-10-22 16:50:36 +0100 | [diff] [blame] | 348 | ptimer_transaction_commit(t->ptimer_t0); |
| 349 | ptimer_transaction_begin(t->ptimer_t1); |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 350 | ptimer_stop(t->ptimer_t1); |
Peter Maydell | 2cb42c9 | 2019-10-22 16:50:36 +0100 | [diff] [blame] | 351 | ptimer_transaction_commit(t->ptimer_t1); |
| 352 | ptimer_transaction_begin(t->ptimer_wd); |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 353 | ptimer_stop(t->ptimer_wd); |
Peter Maydell | 2cb42c9 | 2019-10-22 16:50:36 +0100 | [diff] [blame] | 354 | ptimer_transaction_commit(t->ptimer_wd); |
Edgar E. Iglesias | 84ceea5 | 2009-05-16 01:46:26 +0200 | [diff] [blame] | 355 | t->rw_wd_ctrl = 0; |
| 356 | t->r_intr = 0; |
| 357 | t->rw_intr_mask = 0; |
Philippe Mathieu-Daudé | 72fe474 | 2021-05-02 18:39:30 +0200 | [diff] [blame] | 358 | } |
| 359 | |
Peter Maydell | ad80e36 | 2024-04-12 17:08:07 +0100 | [diff] [blame] | 360 | static void etraxfs_timer_reset_hold(Object *obj, ResetType type) |
Philippe Mathieu-Daudé | 72fe474 | 2021-05-02 18:39:30 +0200 | [diff] [blame] | 361 | { |
| 362 | ETRAXTimerState *t = ETRAX_TIMER(obj); |
| 363 | |
Edgar E. Iglesias | 3b1fd90 | 2009-05-16 02:08:16 +0200 | [diff] [blame] | 364 | qemu_irq_lower(t->irq); |
edgar_igl | 5439779 | 2008-05-27 21:04:41 +0000 | [diff] [blame] | 365 | } |
| 366 | |
Mao Zhongyi | 34a598f | 2018-12-13 13:48:00 +0000 | [diff] [blame] | 367 | static void etraxfs_timer_realize(DeviceState *dev, Error **errp) |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 368 | { |
Andreas Färber | 5880ce5 | 2013-07-27 14:34:22 +0200 | [diff] [blame] | 369 | ETRAXTimerState *t = ETRAX_TIMER(dev); |
Mao Zhongyi | 34a598f | 2018-12-13 13:48:00 +0000 | [diff] [blame] | 370 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 371 | |
Peter Maydell | 9598c1b | 2022-05-16 11:30:58 +0100 | [diff] [blame] | 372 | t->ptimer_t0 = ptimer_init(timer0_hit, t, PTIMER_POLICY_LEGACY); |
| 373 | t->ptimer_t1 = ptimer_init(timer1_hit, t, PTIMER_POLICY_LEGACY); |
| 374 | t->ptimer_wd = ptimer_init(watchdog_hit, t, PTIMER_POLICY_LEGACY); |
Edgar E. Iglesias | 3b1fd90 | 2009-05-16 02:08:16 +0200 | [diff] [blame] | 375 | |
Mao Zhongyi | 34a598f | 2018-12-13 13:48:00 +0000 | [diff] [blame] | 376 | sysbus_init_irq(sbd, &t->irq); |
| 377 | sysbus_init_irq(sbd, &t->nmi); |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 378 | |
Paolo Bonzini | 853dca1 | 2013-06-06 21:25:08 -0400 | [diff] [blame] | 379 | memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, |
| 380 | "etraxfs-timer", 0x5c); |
Mao Zhongyi | 34a598f | 2018-12-13 13:48:00 +0000 | [diff] [blame] | 381 | sysbus_init_mmio(sbd, &t->mmio); |
ths | 83fa101 | 2007-10-08 13:26:33 +0000 | [diff] [blame] | 382 | } |
Edgar E. Iglesias | 3b1fd90 | 2009-05-16 02:08:16 +0200 | [diff] [blame] | 383 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 384 | static void etraxfs_timer_class_init(ObjectClass *klass, void *data) |
| 385 | { |
Mao Zhongyi | 34a598f | 2018-12-13 13:48:00 +0000 | [diff] [blame] | 386 | DeviceClass *dc = DEVICE_CLASS(klass); |
Philippe Mathieu-Daudé | 72fe474 | 2021-05-02 18:39:30 +0200 | [diff] [blame] | 387 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 388 | |
Mao Zhongyi | 34a598f | 2018-12-13 13:48:00 +0000 | [diff] [blame] | 389 | dc->realize = etraxfs_timer_realize; |
Philippe Mathieu-Daudé | 6446a79 | 2021-11-06 11:56:23 +0100 | [diff] [blame] | 390 | dc->vmsd = &vmstate_etraxfs; |
Philippe Mathieu-Daudé | 72fe474 | 2021-05-02 18:39:30 +0200 | [diff] [blame] | 391 | rc->phases.enter = etraxfs_timer_reset_enter; |
| 392 | rc->phases.hold = etraxfs_timer_reset_hold; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 393 | } |
| 394 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 395 | static const TypeInfo etraxfs_timer_info = { |
Andreas Färber | 5880ce5 | 2013-07-27 14:34:22 +0200 | [diff] [blame] | 396 | .name = TYPE_ETRAX_FS_TIMER, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 397 | .parent = TYPE_SYS_BUS_DEVICE, |
Andreas Färber | 3c9a8a8 | 2013-07-27 14:30:31 +0200 | [diff] [blame] | 398 | .instance_size = sizeof(ETRAXTimerState), |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 399 | .class_init = etraxfs_timer_class_init, |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 400 | }; |
| 401 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 402 | static void etraxfs_timer_register_types(void) |
Edgar E. Iglesias | 3b1fd90 | 2009-05-16 02:08:16 +0200 | [diff] [blame] | 403 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 404 | type_register_static(&etraxfs_timer_info); |
Edgar E. Iglesias | 3b1fd90 | 2009-05-16 02:08:16 +0200 | [diff] [blame] | 405 | } |
| 406 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 407 | type_init(etraxfs_timer_register_types) |