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ths83fa1012007-10-08 13:26:33 +00001/*
edgar_igle62b5b12008-03-14 01:04:24 +00002 * QEMU ETRAX Timers
ths83fa1012007-10-08 13:26:33 +00003 *
4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Markus Armbruster0b8fa322019-05-23 16:35:07 +020024
Peter Maydell282bc812016-01-26 18:17:18 +000025#include "qemu/osdep.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010026#include "hw/sysbus.h"
Markus Armbruster71e8a912019-08-12 07:23:38 +020027#include "sysemu/reset.h"
Markus Armbruster54d31232019-08-12 07:23:59 +020028#include "sysemu/runstate.h"
Philippe Mathieu-Daudé6446a792021-11-06 11:56:23 +010029#include "migration/vmstate.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020030#include "qemu/module.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010031#include "qemu/timer.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020032#include "hw/irq.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010033#include "hw/ptimer.h"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040034#include "qom/object.h"
ths83fa1012007-10-08 13:26:33 +000035
edgar_iglbbaf29c2008-03-01 17:25:33 +000036#define D(x)
37
edgar_iglca87d032008-03-14 01:50:49 +000038#define RW_TMR0_DIV 0x00
39#define R_TMR0_DATA 0x04
40#define RW_TMR0_CTRL 0x08
41#define RW_TMR1_DIV 0x10
42#define R_TMR1_DATA 0x14
43#define RW_TMR1_CTRL 0x18
44#define R_TIME 0x38
45#define RW_WD_CTRL 0x40
edgar_igl54397792008-05-27 21:04:41 +000046#define R_WD_STAT 0x44
edgar_iglca87d032008-03-14 01:50:49 +000047#define RW_INTR_MASK 0x48
48#define RW_ACK_INTR 0x4c
49#define R_INTR 0x50
50#define R_MASKED_INTR 0x54
ths83fa1012007-10-08 13:26:33 +000051
Markus Armbrustere1781132021-03-04 15:02:28 +010052#define TYPE_ETRAX_FS_TIMER "etraxfs-timer"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040053typedef struct ETRAXTimerState ETRAXTimerState;
Eduardo Habkost8110fa12020-08-31 17:07:33 -040054DECLARE_INSTANCE_CHECKER(ETRAXTimerState, ETRAX_TIMER,
55 TYPE_ETRAX_FS_TIMER)
Andreas Färber5880ce52013-07-27 14:34:22 +020056
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040057struct ETRAXTimerState {
Andreas Färber5880ce52013-07-27 14:34:22 +020058 SysBusDevice parent_obj;
59
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +020060 MemoryRegion mmio;
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +020061 qemu_irq irq;
62 qemu_irq nmi;
edgar_iglca87d032008-03-14 01:50:49 +000063
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020064 ptimer_state *ptimer_t0;
65 ptimer_state *ptimer_t1;
66 ptimer_state *ptimer_wd;
edgar_igle62b5b12008-03-14 01:04:24 +000067
Philippe Mathieu-Daudé6446a792021-11-06 11:56:23 +010068 uint32_t wd_hits;
edgar_igl5ef98b42008-06-09 23:33:30 +000069
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020070 /* Control registers. */
71 uint32_t rw_tmr0_div;
72 uint32_t r_tmr0_data;
73 uint32_t rw_tmr0_ctrl;
edgar_igl60237222008-05-02 22:32:02 +000074
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020075 uint32_t rw_tmr1_div;
76 uint32_t r_tmr1_data;
77 uint32_t rw_tmr1_ctrl;
edgar_igl60237222008-05-02 22:32:02 +000078
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020079 uint32_t rw_wd_ctrl;
edgar_igl54397792008-05-27 21:04:41 +000080
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020081 uint32_t rw_intr_mask;
82 uint32_t rw_ack_intr;
83 uint32_t r_intr;
84 uint32_t r_masked_intr;
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040085};
ths83fa1012007-10-08 13:26:33 +000086
Philippe Mathieu-Daudé6446a792021-11-06 11:56:23 +010087static const VMStateDescription vmstate_etraxfs = {
88 .name = "etraxfs",
89 .version_id = 0,
90 .minimum_version_id = 0,
Richard Hendersonba324b32023-12-21 14:16:37 +110091 .fields = (const VMStateField[]) {
Philippe Mathieu-Daudé6446a792021-11-06 11:56:23 +010092 VMSTATE_PTIMER(ptimer_t0, ETRAXTimerState),
93 VMSTATE_PTIMER(ptimer_t1, ETRAXTimerState),
94 VMSTATE_PTIMER(ptimer_wd, ETRAXTimerState),
95
96 VMSTATE_UINT32(wd_hits, ETRAXTimerState),
97
98 VMSTATE_UINT32(rw_tmr0_div, ETRAXTimerState),
99 VMSTATE_UINT32(r_tmr0_data, ETRAXTimerState),
100 VMSTATE_UINT32(rw_tmr0_ctrl, ETRAXTimerState),
101
102 VMSTATE_UINT32(rw_tmr1_div, ETRAXTimerState),
103 VMSTATE_UINT32(r_tmr1_data, ETRAXTimerState),
104 VMSTATE_UINT32(rw_tmr1_ctrl, ETRAXTimerState),
105
106 VMSTATE_UINT32(rw_wd_ctrl, ETRAXTimerState),
107
108 VMSTATE_UINT32(rw_intr_mask, ETRAXTimerState),
109 VMSTATE_UINT32(rw_ack_intr, ETRAXTimerState),
110 VMSTATE_UINT32(r_intr, ETRAXTimerState),
111 VMSTATE_UINT32(r_masked_intr, ETRAXTimerState),
112
113 VMSTATE_END_OF_LIST()
114 }
115};
116
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +0200117static uint64_t
Avi Kivitya8170e52012-10-23 12:30:10 +0200118timer_read(void *opaque, hwaddr addr, unsigned int size)
ths83fa1012007-10-08 13:26:33 +0000119{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200120 ETRAXTimerState *t = opaque;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200121 uint32_t r = 0;
ths83fa1012007-10-08 13:26:33 +0000122
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200123 switch (addr) {
124 case R_TMR0_DATA:
125 r = ptimer_get_count(t->ptimer_t0);
126 break;
127 case R_TMR1_DATA:
128 r = ptimer_get_count(t->ptimer_t1);
129 break;
130 case R_TIME:
Alex Blighbc72ad62013-08-21 16:03:08 +0100131 r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200132 break;
133 case RW_INTR_MASK:
134 r = t->rw_intr_mask;
135 break;
136 case R_MASKED_INTR:
137 r = t->r_intr & t->rw_intr_mask;
138 break;
139 default:
140 D(printf ("%s %x\n", __func__, addr));
141 break;
142 }
143 return r;
ths83fa1012007-10-08 13:26:33 +0000144}
145
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200146static void update_ctrl(ETRAXTimerState *t, int tnum)
ths83fa1012007-10-08 13:26:33 +0000147{
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200148 unsigned int op;
149 unsigned int freq;
150 unsigned int freq_hz;
151 unsigned int div;
152 uint32_t ctrl;
edgar_igl5ef98b42008-06-09 23:33:30 +0000153
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200154 ptimer_state *timer;
ths83fa1012007-10-08 13:26:33 +0000155
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200156 if (tnum == 0) {
157 ctrl = t->rw_tmr0_ctrl;
158 div = t->rw_tmr0_div;
159 timer = t->ptimer_t0;
160 } else {
161 ctrl = t->rw_tmr1_ctrl;
162 div = t->rw_tmr1_div;
163 timer = t->ptimer_t1;
164 }
edgar_igl54397792008-05-27 21:04:41 +0000165
166
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200167 op = ctrl & 3;
168 freq = ctrl >> 2;
169 freq_hz = 32000000;
ths83fa1012007-10-08 13:26:33 +0000170
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200171 switch (freq)
172 {
173 case 0:
174 case 1:
175 D(printf ("extern or disabled timer clock?\n"));
176 break;
177 case 4: freq_hz = 29493000; break;
178 case 5: freq_hz = 32000000; break;
179 case 6: freq_hz = 32768000; break;
180 case 7: freq_hz = 100000000; break;
181 default:
182 abort();
183 break;
184 }
ths83fa1012007-10-08 13:26:33 +0000185
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200186 D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
Peter Maydell2cb42c92019-10-22 16:50:36 +0100187 ptimer_transaction_begin(timer);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200188 ptimer_set_freq(timer, freq_hz);
189 ptimer_set_limit(timer, div, 0);
ths83fa1012007-10-08 13:26:33 +0000190
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200191 switch (op)
192 {
193 case 0:
194 /* Load. */
195 ptimer_set_limit(timer, div, 1);
196 break;
197 case 1:
198 /* Hold. */
199 ptimer_stop(timer);
200 break;
201 case 2:
202 /* Run. */
203 ptimer_run(timer, 0);
204 break;
205 default:
206 abort();
207 break;
208 }
Peter Maydell2cb42c92019-10-22 16:50:36 +0100209 ptimer_transaction_commit(timer);
ths83fa1012007-10-08 13:26:33 +0000210}
211
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200212static void timer_update_irq(ETRAXTimerState *t)
ths83fa1012007-10-08 13:26:33 +0000213{
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200214 t->r_intr &= ~(t->rw_ack_intr);
215 t->r_masked_intr = t->r_intr & t->rw_intr_mask;
edgar_igl60237222008-05-02 22:32:02 +0000216
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200217 D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200218 qemu_set_irq(t->irq, !!t->r_masked_intr);
ths83fa1012007-10-08 13:26:33 +0000219}
220
edgar_igl54397792008-05-27 21:04:41 +0000221static void timer0_hit(void *opaque)
edgar_igl60237222008-05-02 22:32:02 +0000222{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200223 ETRAXTimerState *t = opaque;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200224 t->r_intr |= 1;
225 timer_update_irq(t);
edgar_igl60237222008-05-02 22:32:02 +0000226}
227
edgar_igl54397792008-05-27 21:04:41 +0000228static void timer1_hit(void *opaque)
229{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200230 ETRAXTimerState *t = opaque;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200231 t->r_intr |= 2;
232 timer_update_irq(t);
edgar_igl54397792008-05-27 21:04:41 +0000233}
234
235static void watchdog_hit(void *opaque)
236{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200237 ETRAXTimerState *t = opaque;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200238 if (t->wd_hits == 0) {
Michael Tokarev9b4b4e52023-07-14 14:32:24 +0300239 /* real hw gives a single tick before resetting but we are
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200240 a bit friendlier to compensate for our slower execution. */
241 ptimer_set_count(t->ptimer_wd, 10);
242 ptimer_run(t->ptimer_wd, 1);
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200243 qemu_irq_raise(t->nmi);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200244 }
245 else
Eric Blakecf83f142017-05-15 16:41:13 -0500246 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
edgar_igl5ef98b42008-06-09 23:33:30 +0000247
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200248 t->wd_hits++;
edgar_igl54397792008-05-27 21:04:41 +0000249}
250
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200251static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
edgar_igl54397792008-05-27 21:04:41 +0000252{
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200253 unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
254 unsigned int wd_key = t->rw_wd_ctrl >> 9;
255 unsigned int wd_cnt = t->rw_wd_ctrl & 511;
256 unsigned int new_key = value >> 9 & ((1 << 7) - 1);
257 unsigned int new_cmd = (value >> 8) & 1;
edgar_igl54397792008-05-27 21:04:41 +0000258
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200259 /* If the watchdog is enabled, they written key must match the
260 complement of the previous. */
261 wd_key = ~wd_key & ((1 << 7) - 1);
edgar_igl54397792008-05-27 21:04:41 +0000262
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200263 if (wd_en && wd_key != new_key)
264 return;
edgar_igl54397792008-05-27 21:04:41 +0000265
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200266 D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
267 wd_en, new_key, wd_key, new_cmd, wd_cnt));
edgar_igl54397792008-05-27 21:04:41 +0000268
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200269 if (t->wd_hits)
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200270 qemu_irq_lower(t->nmi);
edgar_igl5ef98b42008-06-09 23:33:30 +0000271
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200272 t->wd_hits = 0;
edgar_igl5ef98b42008-06-09 23:33:30 +0000273
Peter Maydell2cb42c92019-10-22 16:50:36 +0100274 ptimer_transaction_begin(t->ptimer_wd);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200275 ptimer_set_freq(t->ptimer_wd, 760);
276 if (wd_cnt == 0)
277 wd_cnt = 256;
278 ptimer_set_count(t->ptimer_wd, wd_cnt);
279 if (new_cmd)
280 ptimer_run(t->ptimer_wd, 1);
281 else
282 ptimer_stop(t->ptimer_wd);
edgar_igl54397792008-05-27 21:04:41 +0000283
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200284 t->rw_wd_ctrl = value;
Peter Maydell2cb42c92019-10-22 16:50:36 +0100285 ptimer_transaction_commit(t->ptimer_wd);
edgar_igl54397792008-05-27 21:04:41 +0000286}
287
ths83fa1012007-10-08 13:26:33 +0000288static void
Avi Kivitya8170e52012-10-23 12:30:10 +0200289timer_write(void *opaque, hwaddr addr,
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +0200290 uint64_t val64, unsigned int size)
ths83fa1012007-10-08 13:26:33 +0000291{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200292 ETRAXTimerState *t = opaque;
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +0200293 uint32_t value = val64;
edgar_iglbbaf29c2008-03-01 17:25:33 +0000294
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200295 switch (addr)
296 {
297 case RW_TMR0_DIV:
298 t->rw_tmr0_div = value;
299 break;
300 case RW_TMR0_CTRL:
301 D(printf ("RW_TMR0_CTRL=%x\n", value));
302 t->rw_tmr0_ctrl = value;
303 update_ctrl(t, 0);
304 break;
305 case RW_TMR1_DIV:
306 t->rw_tmr1_div = value;
307 break;
308 case RW_TMR1_CTRL:
309 D(printf ("RW_TMR1_CTRL=%x\n", value));
310 t->rw_tmr1_ctrl = value;
311 update_ctrl(t, 1);
312 break;
313 case RW_INTR_MASK:
314 D(printf ("RW_INTR_MASK=%x\n", value));
315 t->rw_intr_mask = value;
316 timer_update_irq(t);
317 break;
318 case RW_WD_CTRL:
319 timer_watchdog_update(t, value);
320 break;
321 case RW_ACK_INTR:
322 t->rw_ack_intr = value;
323 timer_update_irq(t);
324 t->rw_ack_intr = 0;
325 break;
326 default:
Philippe Mathieu-Daudé883f2c52023-01-10 22:29:47 +0100327 printf("%s " HWADDR_FMT_plx " %x\n", __func__, addr, value);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200328 break;
329 }
ths83fa1012007-10-08 13:26:33 +0000330}
331
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +0200332static const MemoryRegionOps timer_ops = {
333 .read = timer_read,
334 .write = timer_write,
335 .endianness = DEVICE_LITTLE_ENDIAN,
336 .valid = {
337 .min_access_size = 4,
338 .max_access_size = 4
339 }
ths83fa1012007-10-08 13:26:33 +0000340};
341
Philippe Mathieu-Daudé72fe4742021-05-02 18:39:30 +0200342static void etraxfs_timer_reset_enter(Object *obj, ResetType type)
edgar_igl54397792008-05-27 21:04:41 +0000343{
Philippe Mathieu-Daudé72fe4742021-05-02 18:39:30 +0200344 ETRAXTimerState *t = ETRAX_TIMER(obj);
edgar_igl54397792008-05-27 21:04:41 +0000345
Peter Maydell2cb42c92019-10-22 16:50:36 +0100346 ptimer_transaction_begin(t->ptimer_t0);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200347 ptimer_stop(t->ptimer_t0);
Peter Maydell2cb42c92019-10-22 16:50:36 +0100348 ptimer_transaction_commit(t->ptimer_t0);
349 ptimer_transaction_begin(t->ptimer_t1);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200350 ptimer_stop(t->ptimer_t1);
Peter Maydell2cb42c92019-10-22 16:50:36 +0100351 ptimer_transaction_commit(t->ptimer_t1);
352 ptimer_transaction_begin(t->ptimer_wd);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200353 ptimer_stop(t->ptimer_wd);
Peter Maydell2cb42c92019-10-22 16:50:36 +0100354 ptimer_transaction_commit(t->ptimer_wd);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200355 t->rw_wd_ctrl = 0;
356 t->r_intr = 0;
357 t->rw_intr_mask = 0;
Philippe Mathieu-Daudé72fe4742021-05-02 18:39:30 +0200358}
359
Peter Maydellad80e362024-04-12 17:08:07 +0100360static void etraxfs_timer_reset_hold(Object *obj, ResetType type)
Philippe Mathieu-Daudé72fe4742021-05-02 18:39:30 +0200361{
362 ETRAXTimerState *t = ETRAX_TIMER(obj);
363
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200364 qemu_irq_lower(t->irq);
edgar_igl54397792008-05-27 21:04:41 +0000365}
366
Mao Zhongyi34a598f2018-12-13 13:48:00 +0000367static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
ths83fa1012007-10-08 13:26:33 +0000368{
Andreas Färber5880ce52013-07-27 14:34:22 +0200369 ETRAXTimerState *t = ETRAX_TIMER(dev);
Mao Zhongyi34a598f2018-12-13 13:48:00 +0000370 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
ths83fa1012007-10-08 13:26:33 +0000371
Peter Maydell9598c1b2022-05-16 11:30:58 +0100372 t->ptimer_t0 = ptimer_init(timer0_hit, t, PTIMER_POLICY_LEGACY);
373 t->ptimer_t1 = ptimer_init(timer1_hit, t, PTIMER_POLICY_LEGACY);
374 t->ptimer_wd = ptimer_init(watchdog_hit, t, PTIMER_POLICY_LEGACY);
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200375
Mao Zhongyi34a598f2018-12-13 13:48:00 +0000376 sysbus_init_irq(sbd, &t->irq);
377 sysbus_init_irq(sbd, &t->nmi);
ths83fa1012007-10-08 13:26:33 +0000378
Paolo Bonzini853dca12013-06-06 21:25:08 -0400379 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
380 "etraxfs-timer", 0x5c);
Mao Zhongyi34a598f2018-12-13 13:48:00 +0000381 sysbus_init_mmio(sbd, &t->mmio);
ths83fa1012007-10-08 13:26:33 +0000382}
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200383
Anthony Liguori999e12b2012-01-24 13:12:29 -0600384static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
385{
Mao Zhongyi34a598f2018-12-13 13:48:00 +0000386 DeviceClass *dc = DEVICE_CLASS(klass);
Philippe Mathieu-Daudé72fe4742021-05-02 18:39:30 +0200387 ResettableClass *rc = RESETTABLE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600388
Mao Zhongyi34a598f2018-12-13 13:48:00 +0000389 dc->realize = etraxfs_timer_realize;
Philippe Mathieu-Daudé6446a792021-11-06 11:56:23 +0100390 dc->vmsd = &vmstate_etraxfs;
Philippe Mathieu-Daudé72fe4742021-05-02 18:39:30 +0200391 rc->phases.enter = etraxfs_timer_reset_enter;
392 rc->phases.hold = etraxfs_timer_reset_hold;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600393}
394
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100395static const TypeInfo etraxfs_timer_info = {
Andreas Färber5880ce52013-07-27 14:34:22 +0200396 .name = TYPE_ETRAX_FS_TIMER,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600397 .parent = TYPE_SYS_BUS_DEVICE,
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200398 .instance_size = sizeof(ETRAXTimerState),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600399 .class_init = etraxfs_timer_class_init,
Anthony Liguori999e12b2012-01-24 13:12:29 -0600400};
401
Andreas Färber83f7d432012-02-09 15:20:55 +0100402static void etraxfs_timer_register_types(void)
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200403{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600404 type_register_static(&etraxfs_timer_info);
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200405}
406
Andreas Färber83f7d432012-02-09 15:20:55 +0100407type_init(etraxfs_timer_register_types)