Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2010 Red Hat, Inc. |
| 3 | * |
| 4 | * written by Gerd Hoffmann <kraxel@redhat.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 or |
| 9 | * (at your option) version 3 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "hw.h" |
| 21 | #include "pci.h" |
Gerd Hoffmann | 17786d5 | 2010-11-09 11:47:48 +0100 | [diff] [blame] | 22 | #include "msi.h" |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 23 | #include "qemu-timer.h" |
| 24 | #include "audiodev.h" |
| 25 | #include "intel-hda.h" |
| 26 | #include "intel-hda-defs.h" |
| 27 | |
| 28 | /* --------------------------------------------------------------------- */ |
| 29 | /* hda bus */ |
| 30 | |
| 31 | static struct BusInfo hda_codec_bus_info = { |
| 32 | .name = "HDA", |
| 33 | .size = sizeof(HDACodecBus), |
| 34 | .props = (Property[]) { |
| 35 | DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), |
| 36 | DEFINE_PROP_END_OF_LIST() |
| 37 | } |
| 38 | }; |
| 39 | |
| 40 | void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, |
| 41 | hda_codec_response_func response, |
| 42 | hda_codec_xfer_func xfer) |
| 43 | { |
| 44 | qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL); |
| 45 | bus->response = response; |
| 46 | bus->xfer = xfer; |
| 47 | } |
| 48 | |
| 49 | static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo *base) |
| 50 | { |
| 51 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus); |
| 52 | HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
| 53 | HDACodecDeviceInfo *info = DO_UPCAST(HDACodecDeviceInfo, qdev, base); |
| 54 | |
| 55 | dev->info = info; |
| 56 | if (dev->cad == -1) { |
| 57 | dev->cad = bus->next_cad; |
| 58 | } |
Gerd Hoffmann | df0db22 | 2010-11-09 17:28:38 +0100 | [diff] [blame] | 59 | if (dev->cad >= 15) { |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 60 | return -1; |
Gerd Hoffmann | df0db22 | 2010-11-09 17:28:38 +0100 | [diff] [blame] | 61 | } |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 62 | bus->next_cad = dev->cad + 1; |
| 63 | return info->init(dev); |
| 64 | } |
| 65 | |
Gerd Hoffmann | dc4b924 | 2010-11-09 11:47:44 +0100 | [diff] [blame] | 66 | static int hda_codec_dev_exit(DeviceState *qdev) |
| 67 | { |
| 68 | HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
| 69 | |
| 70 | if (dev->info->exit) { |
| 71 | dev->info->exit(dev); |
| 72 | } |
| 73 | return 0; |
| 74 | } |
| 75 | |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 76 | void hda_codec_register(HDACodecDeviceInfo *info) |
| 77 | { |
| 78 | info->qdev.init = hda_codec_dev_init; |
Gerd Hoffmann | dc4b924 | 2010-11-09 11:47:44 +0100 | [diff] [blame] | 79 | info->qdev.exit = hda_codec_dev_exit; |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 80 | info->qdev.bus_info = &hda_codec_bus_info; |
| 81 | qdev_register(&info->qdev); |
| 82 | } |
| 83 | |
| 84 | HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) |
| 85 | { |
| 86 | DeviceState *qdev; |
| 87 | HDACodecDevice *cdev; |
| 88 | |
| 89 | QLIST_FOREACH(qdev, &bus->qbus.children, sibling) { |
| 90 | cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
| 91 | if (cdev->cad == cad) { |
| 92 | return cdev; |
| 93 | } |
| 94 | } |
| 95 | return NULL; |
| 96 | } |
| 97 | |
| 98 | void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) |
| 99 | { |
| 100 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
| 101 | bus->response(dev, solicited, response); |
| 102 | } |
| 103 | |
| 104 | bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, |
| 105 | uint8_t *buf, uint32_t len) |
| 106 | { |
| 107 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
| 108 | return bus->xfer(dev, stnr, output, buf, len); |
| 109 | } |
| 110 | |
| 111 | /* --------------------------------------------------------------------- */ |
| 112 | /* intel hda emulation */ |
| 113 | |
| 114 | typedef struct IntelHDAStream IntelHDAStream; |
| 115 | typedef struct IntelHDAState IntelHDAState; |
| 116 | typedef struct IntelHDAReg IntelHDAReg; |
| 117 | |
| 118 | typedef struct bpl { |
| 119 | uint64_t addr; |
| 120 | uint32_t len; |
| 121 | uint32_t flags; |
| 122 | } bpl; |
| 123 | |
| 124 | struct IntelHDAStream { |
| 125 | /* registers */ |
| 126 | uint32_t ctl; |
| 127 | uint32_t lpib; |
| 128 | uint32_t cbl; |
| 129 | uint32_t lvi; |
| 130 | uint32_t fmt; |
| 131 | uint32_t bdlp_lbase; |
| 132 | uint32_t bdlp_ubase; |
| 133 | |
| 134 | /* state */ |
| 135 | bpl *bpl; |
| 136 | uint32_t bentries; |
| 137 | uint32_t bsize, be, bp; |
| 138 | }; |
| 139 | |
| 140 | struct IntelHDAState { |
| 141 | PCIDevice pci; |
| 142 | const char *name; |
| 143 | HDACodecBus codecs; |
| 144 | |
| 145 | /* registers */ |
| 146 | uint32_t g_ctl; |
| 147 | uint32_t wake_en; |
| 148 | uint32_t state_sts; |
| 149 | uint32_t int_ctl; |
| 150 | uint32_t int_sts; |
| 151 | uint32_t wall_clk; |
| 152 | |
| 153 | uint32_t corb_lbase; |
| 154 | uint32_t corb_ubase; |
| 155 | uint32_t corb_rp; |
| 156 | uint32_t corb_wp; |
| 157 | uint32_t corb_ctl; |
| 158 | uint32_t corb_sts; |
| 159 | uint32_t corb_size; |
| 160 | |
| 161 | uint32_t rirb_lbase; |
| 162 | uint32_t rirb_ubase; |
| 163 | uint32_t rirb_wp; |
| 164 | uint32_t rirb_cnt; |
| 165 | uint32_t rirb_ctl; |
| 166 | uint32_t rirb_sts; |
| 167 | uint32_t rirb_size; |
| 168 | |
| 169 | uint32_t dp_lbase; |
| 170 | uint32_t dp_ubase; |
| 171 | |
| 172 | uint32_t icw; |
| 173 | uint32_t irr; |
| 174 | uint32_t ics; |
| 175 | |
| 176 | /* streams */ |
| 177 | IntelHDAStream st[8]; |
| 178 | |
| 179 | /* state */ |
| 180 | int mmio_addr; |
| 181 | uint32_t rirb_count; |
| 182 | int64_t wall_base_ns; |
| 183 | |
| 184 | /* debug logging */ |
| 185 | const IntelHDAReg *last_reg; |
| 186 | uint32_t last_val; |
| 187 | uint32_t last_write; |
| 188 | uint32_t last_sec; |
| 189 | uint32_t repeat_count; |
| 190 | |
| 191 | /* properties */ |
| 192 | uint32_t debug; |
Gerd Hoffmann | 17786d5 | 2010-11-09 11:47:48 +0100 | [diff] [blame] | 193 | uint32_t msi; |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 194 | }; |
| 195 | |
| 196 | struct IntelHDAReg { |
| 197 | const char *name; /* register name */ |
| 198 | uint32_t size; /* size in bytes */ |
| 199 | uint32_t reset; /* reset value */ |
| 200 | uint32_t wmask; /* write mask */ |
| 201 | uint32_t wclear; /* write 1 to clear bits */ |
| 202 | uint32_t offset; /* location in IntelHDAState */ |
| 203 | uint32_t shift; /* byte access entries for dwords */ |
| 204 | uint32_t stream; |
| 205 | void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); |
| 206 | void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); |
| 207 | }; |
| 208 | |
| 209 | static void intel_hda_reset(DeviceState *dev); |
| 210 | |
| 211 | /* --------------------------------------------------------------------- */ |
| 212 | |
| 213 | static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase) |
| 214 | { |
| 215 | target_phys_addr_t addr; |
| 216 | |
| 217 | #if TARGET_PHYS_ADDR_BITS == 32 |
| 218 | addr = lbase; |
| 219 | #else |
| 220 | addr = ubase; |
| 221 | addr <<= 32; |
| 222 | addr |= lbase; |
| 223 | #endif |
| 224 | return addr; |
| 225 | } |
| 226 | |
| 227 | static void stl_phys_le(target_phys_addr_t addr, uint32_t value) |
| 228 | { |
| 229 | uint32_t value_le = cpu_to_le32(value); |
| 230 | cpu_physical_memory_write(addr, (uint8_t*)(&value_le), sizeof(value_le)); |
| 231 | } |
| 232 | |
| 233 | static uint32_t ldl_phys_le(target_phys_addr_t addr) |
| 234 | { |
| 235 | uint32_t value_le; |
| 236 | cpu_physical_memory_read(addr, (uint8_t*)(&value_le), sizeof(value_le)); |
| 237 | return le32_to_cpu(value_le); |
| 238 | } |
| 239 | |
| 240 | static void intel_hda_update_int_sts(IntelHDAState *d) |
| 241 | { |
| 242 | uint32_t sts = 0; |
| 243 | uint32_t i; |
| 244 | |
| 245 | /* update controller status */ |
| 246 | if (d->rirb_sts & ICH6_RBSTS_IRQ) { |
| 247 | sts |= (1 << 30); |
| 248 | } |
| 249 | if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { |
| 250 | sts |= (1 << 30); |
| 251 | } |
François Revol | af93485 | 2010-11-09 11:47:46 +0100 | [diff] [blame] | 252 | if (d->state_sts & d->wake_en) { |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 253 | sts |= (1 << 30); |
| 254 | } |
| 255 | |
| 256 | /* update stream status */ |
| 257 | for (i = 0; i < 8; i++) { |
| 258 | /* buffer completion interrupt */ |
| 259 | if (d->st[i].ctl & (1 << 26)) { |
| 260 | sts |= (1 << i); |
| 261 | } |
| 262 | } |
| 263 | |
| 264 | /* update global status */ |
| 265 | if (sts & d->int_ctl) { |
| 266 | sts |= (1 << 31); |
| 267 | } |
| 268 | |
| 269 | d->int_sts = sts; |
| 270 | } |
| 271 | |
| 272 | static void intel_hda_update_irq(IntelHDAState *d) |
| 273 | { |
Gerd Hoffmann | 17786d5 | 2010-11-09 11:47:48 +0100 | [diff] [blame] | 274 | int msi = d->msi && msi_enabled(&d->pci); |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 275 | int level; |
| 276 | |
| 277 | intel_hda_update_int_sts(d); |
| 278 | if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) { |
| 279 | level = 1; |
| 280 | } else { |
| 281 | level = 0; |
| 282 | } |
Gerd Hoffmann | 17786d5 | 2010-11-09 11:47:48 +0100 | [diff] [blame] | 283 | dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__, |
| 284 | level, msi ? "msi" : "intx"); |
| 285 | if (msi) { |
| 286 | if (level) { |
| 287 | msi_notify(&d->pci, 0); |
| 288 | } |
| 289 | } else { |
| 290 | qemu_set_irq(d->pci.irq[0], level); |
| 291 | } |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 292 | } |
| 293 | |
| 294 | static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) |
| 295 | { |
| 296 | uint32_t cad, nid, data; |
| 297 | HDACodecDevice *codec; |
| 298 | |
| 299 | cad = (verb >> 28) & 0x0f; |
| 300 | if (verb & (1 << 27)) { |
| 301 | /* indirect node addressing, not specified in HDA 1.0 */ |
| 302 | dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__); |
| 303 | return -1; |
| 304 | } |
| 305 | nid = (verb >> 20) & 0x7f; |
| 306 | data = verb & 0xfffff; |
| 307 | |
| 308 | codec = hda_codec_find(&d->codecs, cad); |
| 309 | if (codec == NULL) { |
| 310 | dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__); |
| 311 | return -1; |
| 312 | } |
| 313 | codec->info->command(codec, nid, data); |
| 314 | return 0; |
| 315 | } |
| 316 | |
| 317 | static void intel_hda_corb_run(IntelHDAState *d) |
| 318 | { |
| 319 | target_phys_addr_t addr; |
| 320 | uint32_t rp, verb; |
| 321 | |
| 322 | if (d->ics & ICH6_IRS_BUSY) { |
| 323 | dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw); |
| 324 | intel_hda_send_command(d, d->icw); |
| 325 | return; |
| 326 | } |
| 327 | |
| 328 | for (;;) { |
| 329 | if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { |
| 330 | dprint(d, 2, "%s: !run\n", __FUNCTION__); |
| 331 | return; |
| 332 | } |
| 333 | if ((d->corb_rp & 0xff) == d->corb_wp) { |
| 334 | dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__); |
| 335 | return; |
| 336 | } |
| 337 | if (d->rirb_count == d->rirb_cnt) { |
| 338 | dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__); |
| 339 | return; |
| 340 | } |
| 341 | |
| 342 | rp = (d->corb_rp + 1) & 0xff; |
| 343 | addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); |
| 344 | verb = ldl_phys_le(addr + 4*rp); |
| 345 | d->corb_rp = rp; |
| 346 | |
| 347 | dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb); |
| 348 | intel_hda_send_command(d, verb); |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) |
| 353 | { |
| 354 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
| 355 | IntelHDAState *d = container_of(bus, IntelHDAState, codecs); |
| 356 | target_phys_addr_t addr; |
| 357 | uint32_t wp, ex; |
| 358 | |
| 359 | if (d->ics & ICH6_IRS_BUSY) { |
| 360 | dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", |
| 361 | __FUNCTION__, response, dev->cad); |
| 362 | d->irr = response; |
| 363 | d->ics &= ~(ICH6_IRS_BUSY | 0xf0); |
| 364 | d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); |
| 365 | return; |
| 366 | } |
| 367 | |
| 368 | if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { |
| 369 | dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__); |
| 370 | return; |
| 371 | } |
| 372 | |
| 373 | ex = (solicited ? 0 : (1 << 4)) | dev->cad; |
| 374 | wp = (d->rirb_wp + 1) & 0xff; |
| 375 | addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); |
| 376 | stl_phys_le(addr + 8*wp, response); |
| 377 | stl_phys_le(addr + 8*wp + 4, ex); |
| 378 | d->rirb_wp = wp; |
| 379 | |
| 380 | dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", |
| 381 | __FUNCTION__, wp, response, ex); |
| 382 | |
| 383 | d->rirb_count++; |
| 384 | if (d->rirb_count == d->rirb_cnt) { |
| 385 | dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count); |
| 386 | if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { |
| 387 | d->rirb_sts |= ICH6_RBSTS_IRQ; |
| 388 | intel_hda_update_irq(d); |
| 389 | } |
| 390 | } else if ((d->corb_rp & 0xff) == d->corb_wp) { |
| 391 | dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__, |
| 392 | d->rirb_count, d->rirb_cnt); |
| 393 | if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { |
| 394 | d->rirb_sts |= ICH6_RBSTS_IRQ; |
| 395 | intel_hda_update_irq(d); |
| 396 | } |
| 397 | } |
| 398 | } |
| 399 | |
| 400 | static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, |
| 401 | uint8_t *buf, uint32_t len) |
| 402 | { |
| 403 | HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
| 404 | IntelHDAState *d = container_of(bus, IntelHDAState, codecs); |
| 405 | IntelHDAStream *st = NULL; |
| 406 | target_phys_addr_t addr; |
| 407 | uint32_t s, copy, left; |
| 408 | bool irq = false; |
| 409 | |
| 410 | for (s = 0; s < ARRAY_SIZE(d->st); s++) { |
| 411 | if (stnr == ((d->st[s].ctl >> 20) & 0x0f)) { |
| 412 | st = d->st + s; |
| 413 | break; |
| 414 | } |
| 415 | } |
| 416 | if (st == NULL) { |
| 417 | return false; |
| 418 | } |
| 419 | if (st->bpl == NULL) { |
| 420 | return false; |
| 421 | } |
| 422 | if (st->ctl & (1 << 26)) { |
| 423 | /* |
| 424 | * Wait with the next DMA xfer until the guest |
| 425 | * has acked the buffer completion interrupt |
| 426 | */ |
| 427 | return false; |
| 428 | } |
| 429 | |
| 430 | left = len; |
| 431 | while (left > 0) { |
| 432 | copy = left; |
| 433 | if (copy > st->bsize - st->lpib) |
| 434 | copy = st->bsize - st->lpib; |
| 435 | if (copy > st->bpl[st->be].len - st->bp) |
| 436 | copy = st->bpl[st->be].len - st->bp; |
| 437 | |
| 438 | dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", |
| 439 | st->be, st->bp, st->bpl[st->be].len, copy); |
| 440 | |
| 441 | cpu_physical_memory_rw(st->bpl[st->be].addr + st->bp, |
| 442 | buf, copy, !output); |
| 443 | st->lpib += copy; |
| 444 | st->bp += copy; |
| 445 | buf += copy; |
| 446 | left -= copy; |
| 447 | |
| 448 | if (st->bpl[st->be].len == st->bp) { |
| 449 | /* bpl entry filled */ |
| 450 | if (st->bpl[st->be].flags & 0x01) { |
| 451 | irq = true; |
| 452 | } |
| 453 | st->bp = 0; |
| 454 | st->be++; |
| 455 | if (st->be == st->bentries) { |
| 456 | /* bpl wrap around */ |
| 457 | st->be = 0; |
| 458 | st->lpib = 0; |
| 459 | } |
| 460 | } |
| 461 | } |
| 462 | if (d->dp_lbase & 0x01) { |
| 463 | addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); |
| 464 | stl_phys_le(addr + 8*s, st->lpib); |
| 465 | } |
| 466 | dprint(d, 3, "dma: --\n"); |
| 467 | |
| 468 | if (irq) { |
| 469 | st->ctl |= (1 << 26); /* buffer completion interrupt */ |
| 470 | intel_hda_update_irq(d); |
| 471 | } |
| 472 | return true; |
| 473 | } |
| 474 | |
| 475 | static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) |
| 476 | { |
| 477 | target_phys_addr_t addr; |
| 478 | uint8_t buf[16]; |
| 479 | uint32_t i; |
| 480 | |
| 481 | addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); |
| 482 | st->bentries = st->lvi +1; |
| 483 | qemu_free(st->bpl); |
| 484 | st->bpl = qemu_malloc(sizeof(bpl) * st->bentries); |
| 485 | for (i = 0; i < st->bentries; i++, addr += 16) { |
| 486 | cpu_physical_memory_read(addr, buf, 16); |
| 487 | st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); |
| 488 | st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); |
| 489 | st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); |
| 490 | dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", |
| 491 | i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); |
| 492 | } |
| 493 | |
| 494 | st->bsize = st->cbl; |
| 495 | st->lpib = 0; |
| 496 | st->be = 0; |
| 497 | st->bp = 0; |
| 498 | } |
| 499 | |
| 500 | static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running) |
| 501 | { |
| 502 | DeviceState *qdev; |
| 503 | HDACodecDevice *cdev; |
| 504 | |
| 505 | QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) { |
| 506 | cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
| 507 | if (cdev->info->stream) { |
| 508 | cdev->info->stream(cdev, stream, running); |
| 509 | } |
| 510 | } |
| 511 | } |
| 512 | |
| 513 | /* --------------------------------------------------------------------- */ |
| 514 | |
| 515 | static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 516 | { |
| 517 | if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { |
| 518 | intel_hda_reset(&d->pci.qdev); |
| 519 | } |
| 520 | } |
| 521 | |
Gerd Hoffmann | 6a0d02f | 2010-11-09 11:47:47 +0100 | [diff] [blame] | 522 | static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 523 | { |
| 524 | intel_hda_update_irq(d); |
| 525 | } |
| 526 | |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 527 | static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 528 | { |
| 529 | intel_hda_update_irq(d); |
| 530 | } |
| 531 | |
| 532 | static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 533 | { |
| 534 | intel_hda_update_irq(d); |
| 535 | } |
| 536 | |
| 537 | static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) |
| 538 | { |
| 539 | int64_t ns; |
| 540 | |
| 541 | ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns; |
| 542 | d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ |
| 543 | } |
| 544 | |
| 545 | static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 546 | { |
| 547 | intel_hda_corb_run(d); |
| 548 | } |
| 549 | |
| 550 | static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 551 | { |
| 552 | intel_hda_corb_run(d); |
| 553 | } |
| 554 | |
| 555 | static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 556 | { |
| 557 | if (d->rirb_wp & ICH6_RIRBWP_RST) { |
| 558 | d->rirb_wp = 0; |
| 559 | } |
| 560 | } |
| 561 | |
| 562 | static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 563 | { |
| 564 | intel_hda_update_irq(d); |
| 565 | |
| 566 | if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { |
| 567 | /* cleared ICH6_RBSTS_IRQ */ |
| 568 | d->rirb_count = 0; |
| 569 | intel_hda_corb_run(d); |
| 570 | } |
| 571 | } |
| 572 | |
| 573 | static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 574 | { |
| 575 | if (d->ics & ICH6_IRS_BUSY) { |
| 576 | intel_hda_corb_run(d); |
| 577 | } |
| 578 | } |
| 579 | |
| 580 | static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 581 | { |
| 582 | IntelHDAStream *st = d->st + reg->stream; |
| 583 | |
| 584 | if (st->ctl & 0x01) { |
| 585 | /* reset */ |
| 586 | dprint(d, 1, "st #%d: reset\n", reg->stream); |
| 587 | st->ctl = 0; |
| 588 | } |
| 589 | if ((st->ctl & 0x02) != (old & 0x02)) { |
| 590 | uint32_t stnr = (st->ctl >> 20) & 0x0f; |
| 591 | /* run bit flipped */ |
| 592 | if (st->ctl & 0x02) { |
| 593 | /* start */ |
| 594 | dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", |
| 595 | reg->stream, stnr, st->cbl); |
| 596 | intel_hda_parse_bdl(d, st); |
| 597 | intel_hda_notify_codecs(d, stnr, true); |
| 598 | } else { |
| 599 | /* stop */ |
| 600 | dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); |
| 601 | intel_hda_notify_codecs(d, stnr, false); |
| 602 | } |
| 603 | } |
| 604 | intel_hda_update_irq(d); |
| 605 | } |
| 606 | |
| 607 | /* --------------------------------------------------------------------- */ |
| 608 | |
| 609 | #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) |
| 610 | |
| 611 | static const struct IntelHDAReg regtab[] = { |
| 612 | /* global */ |
| 613 | [ ICH6_REG_GCAP ] = { |
| 614 | .name = "GCAP", |
| 615 | .size = 2, |
| 616 | .reset = 0x4401, |
| 617 | }, |
| 618 | [ ICH6_REG_VMIN ] = { |
| 619 | .name = "VMIN", |
| 620 | .size = 1, |
| 621 | }, |
| 622 | [ ICH6_REG_VMAJ ] = { |
| 623 | .name = "VMAJ", |
| 624 | .size = 1, |
| 625 | .reset = 1, |
| 626 | }, |
| 627 | [ ICH6_REG_OUTPAY ] = { |
| 628 | .name = "OUTPAY", |
| 629 | .size = 2, |
| 630 | .reset = 0x3c, |
| 631 | }, |
| 632 | [ ICH6_REG_INPAY ] = { |
| 633 | .name = "INPAY", |
| 634 | .size = 2, |
| 635 | .reset = 0x1d, |
| 636 | }, |
| 637 | [ ICH6_REG_GCTL ] = { |
| 638 | .name = "GCTL", |
| 639 | .size = 4, |
| 640 | .wmask = 0x0103, |
| 641 | .offset = offsetof(IntelHDAState, g_ctl), |
| 642 | .whandler = intel_hda_set_g_ctl, |
| 643 | }, |
| 644 | [ ICH6_REG_WAKEEN ] = { |
| 645 | .name = "WAKEEN", |
| 646 | .size = 2, |
Gerd Hoffmann | df0db22 | 2010-11-09 17:28:38 +0100 | [diff] [blame] | 647 | .wmask = 0x7fff, |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 648 | .offset = offsetof(IntelHDAState, wake_en), |
Gerd Hoffmann | 6a0d02f | 2010-11-09 11:47:47 +0100 | [diff] [blame] | 649 | .whandler = intel_hda_set_wake_en, |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 650 | }, |
| 651 | [ ICH6_REG_STATESTS ] = { |
| 652 | .name = "STATESTS", |
| 653 | .size = 2, |
Gerd Hoffmann | df0db22 | 2010-11-09 17:28:38 +0100 | [diff] [blame] | 654 | .wmask = 0x7fff, |
| 655 | .wclear = 0x7fff, |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 656 | .offset = offsetof(IntelHDAState, state_sts), |
| 657 | .whandler = intel_hda_set_state_sts, |
| 658 | }, |
| 659 | |
| 660 | /* interrupts */ |
| 661 | [ ICH6_REG_INTCTL ] = { |
| 662 | .name = "INTCTL", |
| 663 | .size = 4, |
| 664 | .wmask = 0xc00000ff, |
| 665 | .offset = offsetof(IntelHDAState, int_ctl), |
| 666 | .whandler = intel_hda_set_int_ctl, |
| 667 | }, |
| 668 | [ ICH6_REG_INTSTS ] = { |
| 669 | .name = "INTSTS", |
| 670 | .size = 4, |
| 671 | .wmask = 0xc00000ff, |
| 672 | .wclear = 0xc00000ff, |
| 673 | .offset = offsetof(IntelHDAState, int_sts), |
| 674 | }, |
| 675 | |
| 676 | /* misc */ |
| 677 | [ ICH6_REG_WALLCLK ] = { |
| 678 | .name = "WALLCLK", |
| 679 | .size = 4, |
| 680 | .offset = offsetof(IntelHDAState, wall_clk), |
| 681 | .rhandler = intel_hda_get_wall_clk, |
| 682 | }, |
| 683 | [ ICH6_REG_WALLCLK + 0x2000 ] = { |
| 684 | .name = "WALLCLK(alias)", |
| 685 | .size = 4, |
| 686 | .offset = offsetof(IntelHDAState, wall_clk), |
| 687 | .rhandler = intel_hda_get_wall_clk, |
| 688 | }, |
| 689 | |
| 690 | /* dma engine */ |
| 691 | [ ICH6_REG_CORBLBASE ] = { |
| 692 | .name = "CORBLBASE", |
| 693 | .size = 4, |
| 694 | .wmask = 0xffffff80, |
| 695 | .offset = offsetof(IntelHDAState, corb_lbase), |
| 696 | }, |
| 697 | [ ICH6_REG_CORBUBASE ] = { |
| 698 | .name = "CORBUBASE", |
| 699 | .size = 4, |
| 700 | .wmask = 0xffffffff, |
| 701 | .offset = offsetof(IntelHDAState, corb_ubase), |
| 702 | }, |
| 703 | [ ICH6_REG_CORBWP ] = { |
| 704 | .name = "CORBWP", |
| 705 | .size = 2, |
| 706 | .wmask = 0xff, |
| 707 | .offset = offsetof(IntelHDAState, corb_wp), |
| 708 | .whandler = intel_hda_set_corb_wp, |
| 709 | }, |
| 710 | [ ICH6_REG_CORBRP ] = { |
| 711 | .name = "CORBRP", |
| 712 | .size = 2, |
| 713 | .wmask = 0x80ff, |
| 714 | .offset = offsetof(IntelHDAState, corb_rp), |
| 715 | }, |
| 716 | [ ICH6_REG_CORBCTL ] = { |
| 717 | .name = "CORBCTL", |
| 718 | .size = 1, |
| 719 | .wmask = 0x03, |
| 720 | .offset = offsetof(IntelHDAState, corb_ctl), |
| 721 | .whandler = intel_hda_set_corb_ctl, |
| 722 | }, |
| 723 | [ ICH6_REG_CORBSTS ] = { |
| 724 | .name = "CORBSTS", |
| 725 | .size = 1, |
| 726 | .wmask = 0x01, |
| 727 | .wclear = 0x01, |
| 728 | .offset = offsetof(IntelHDAState, corb_sts), |
| 729 | }, |
| 730 | [ ICH6_REG_CORBSIZE ] = { |
| 731 | .name = "CORBSIZE", |
| 732 | .size = 1, |
| 733 | .reset = 0x42, |
| 734 | .offset = offsetof(IntelHDAState, corb_size), |
| 735 | }, |
| 736 | [ ICH6_REG_RIRBLBASE ] = { |
| 737 | .name = "RIRBLBASE", |
| 738 | .size = 4, |
| 739 | .wmask = 0xffffff80, |
| 740 | .offset = offsetof(IntelHDAState, rirb_lbase), |
| 741 | }, |
| 742 | [ ICH6_REG_RIRBUBASE ] = { |
| 743 | .name = "RIRBUBASE", |
| 744 | .size = 4, |
| 745 | .wmask = 0xffffffff, |
| 746 | .offset = offsetof(IntelHDAState, rirb_ubase), |
| 747 | }, |
| 748 | [ ICH6_REG_RIRBWP ] = { |
| 749 | .name = "RIRBWP", |
| 750 | .size = 2, |
| 751 | .wmask = 0x8000, |
| 752 | .offset = offsetof(IntelHDAState, rirb_wp), |
| 753 | .whandler = intel_hda_set_rirb_wp, |
| 754 | }, |
| 755 | [ ICH6_REG_RINTCNT ] = { |
| 756 | .name = "RINTCNT", |
| 757 | .size = 2, |
| 758 | .wmask = 0xff, |
| 759 | .offset = offsetof(IntelHDAState, rirb_cnt), |
| 760 | }, |
| 761 | [ ICH6_REG_RIRBCTL ] = { |
| 762 | .name = "RIRBCTL", |
| 763 | .size = 1, |
| 764 | .wmask = 0x07, |
| 765 | .offset = offsetof(IntelHDAState, rirb_ctl), |
| 766 | }, |
| 767 | [ ICH6_REG_RIRBSTS ] = { |
| 768 | .name = "RIRBSTS", |
| 769 | .size = 1, |
| 770 | .wmask = 0x05, |
| 771 | .wclear = 0x05, |
| 772 | .offset = offsetof(IntelHDAState, rirb_sts), |
| 773 | .whandler = intel_hda_set_rirb_sts, |
| 774 | }, |
| 775 | [ ICH6_REG_RIRBSIZE ] = { |
| 776 | .name = "RIRBSIZE", |
| 777 | .size = 1, |
| 778 | .reset = 0x42, |
| 779 | .offset = offsetof(IntelHDAState, rirb_size), |
| 780 | }, |
| 781 | |
| 782 | [ ICH6_REG_DPLBASE ] = { |
| 783 | .name = "DPLBASE", |
| 784 | .size = 4, |
| 785 | .wmask = 0xffffff81, |
| 786 | .offset = offsetof(IntelHDAState, dp_lbase), |
| 787 | }, |
| 788 | [ ICH6_REG_DPUBASE ] = { |
| 789 | .name = "DPUBASE", |
| 790 | .size = 4, |
| 791 | .wmask = 0xffffffff, |
| 792 | .offset = offsetof(IntelHDAState, dp_ubase), |
| 793 | }, |
| 794 | |
| 795 | [ ICH6_REG_IC ] = { |
| 796 | .name = "ICW", |
| 797 | .size = 4, |
| 798 | .wmask = 0xffffffff, |
| 799 | .offset = offsetof(IntelHDAState, icw), |
| 800 | }, |
| 801 | [ ICH6_REG_IR ] = { |
| 802 | .name = "IRR", |
| 803 | .size = 4, |
| 804 | .offset = offsetof(IntelHDAState, irr), |
| 805 | }, |
| 806 | [ ICH6_REG_IRS ] = { |
| 807 | .name = "ICS", |
| 808 | .size = 2, |
| 809 | .wmask = 0x0003, |
| 810 | .wclear = 0x0002, |
| 811 | .offset = offsetof(IntelHDAState, ics), |
| 812 | .whandler = intel_hda_set_ics, |
| 813 | }, |
| 814 | |
| 815 | #define HDA_STREAM(_t, _i) \ |
| 816 | [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ |
| 817 | .stream = _i, \ |
| 818 | .name = _t stringify(_i) " CTL", \ |
| 819 | .size = 4, \ |
| 820 | .wmask = 0x1cff001f, \ |
| 821 | .offset = offsetof(IntelHDAState, st[_i].ctl), \ |
| 822 | .whandler = intel_hda_set_st_ctl, \ |
| 823 | }, \ |
| 824 | [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \ |
| 825 | .stream = _i, \ |
| 826 | .name = _t stringify(_i) " CTL(stnr)", \ |
| 827 | .size = 1, \ |
| 828 | .shift = 16, \ |
| 829 | .wmask = 0x00ff0000, \ |
| 830 | .offset = offsetof(IntelHDAState, st[_i].ctl), \ |
| 831 | .whandler = intel_hda_set_st_ctl, \ |
| 832 | }, \ |
| 833 | [ ST_REG(_i, ICH6_REG_SD_STS)] = { \ |
| 834 | .stream = _i, \ |
| 835 | .name = _t stringify(_i) " CTL(sts)", \ |
| 836 | .size = 1, \ |
| 837 | .shift = 24, \ |
| 838 | .wmask = 0x1c000000, \ |
| 839 | .wclear = 0x1c000000, \ |
| 840 | .offset = offsetof(IntelHDAState, st[_i].ctl), \ |
| 841 | .whandler = intel_hda_set_st_ctl, \ |
| 842 | }, \ |
| 843 | [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ |
| 844 | .stream = _i, \ |
| 845 | .name = _t stringify(_i) " LPIB", \ |
| 846 | .size = 4, \ |
| 847 | .offset = offsetof(IntelHDAState, st[_i].lpib), \ |
| 848 | }, \ |
| 849 | [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \ |
| 850 | .stream = _i, \ |
| 851 | .name = _t stringify(_i) " LPIB(alias)", \ |
| 852 | .size = 4, \ |
| 853 | .offset = offsetof(IntelHDAState, st[_i].lpib), \ |
| 854 | }, \ |
| 855 | [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ |
| 856 | .stream = _i, \ |
| 857 | .name = _t stringify(_i) " CBL", \ |
| 858 | .size = 4, \ |
| 859 | .wmask = 0xffffffff, \ |
| 860 | .offset = offsetof(IntelHDAState, st[_i].cbl), \ |
| 861 | }, \ |
| 862 | [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ |
| 863 | .stream = _i, \ |
| 864 | .name = _t stringify(_i) " LVI", \ |
| 865 | .size = 2, \ |
| 866 | .wmask = 0x00ff, \ |
| 867 | .offset = offsetof(IntelHDAState, st[_i].lvi), \ |
| 868 | }, \ |
| 869 | [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ |
| 870 | .stream = _i, \ |
| 871 | .name = _t stringify(_i) " FIFOS", \ |
| 872 | .size = 2, \ |
| 873 | .reset = HDA_BUFFER_SIZE, \ |
| 874 | }, \ |
| 875 | [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ |
| 876 | .stream = _i, \ |
| 877 | .name = _t stringify(_i) " FMT", \ |
| 878 | .size = 2, \ |
| 879 | .wmask = 0x7f7f, \ |
| 880 | .offset = offsetof(IntelHDAState, st[_i].fmt), \ |
| 881 | }, \ |
| 882 | [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ |
| 883 | .stream = _i, \ |
| 884 | .name = _t stringify(_i) " BDLPL", \ |
| 885 | .size = 4, \ |
| 886 | .wmask = 0xffffff80, \ |
| 887 | .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ |
| 888 | }, \ |
| 889 | [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ |
| 890 | .stream = _i, \ |
| 891 | .name = _t stringify(_i) " BDLPU", \ |
| 892 | .size = 4, \ |
| 893 | .wmask = 0xffffffff, \ |
| 894 | .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ |
| 895 | }, \ |
| 896 | |
| 897 | HDA_STREAM("IN", 0) |
| 898 | HDA_STREAM("IN", 1) |
| 899 | HDA_STREAM("IN", 2) |
| 900 | HDA_STREAM("IN", 3) |
| 901 | |
| 902 | HDA_STREAM("OUT", 4) |
| 903 | HDA_STREAM("OUT", 5) |
| 904 | HDA_STREAM("OUT", 6) |
| 905 | HDA_STREAM("OUT", 7) |
| 906 | |
| 907 | }; |
| 908 | |
| 909 | static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr) |
| 910 | { |
| 911 | const IntelHDAReg *reg; |
| 912 | |
| 913 | if (addr >= sizeof(regtab)/sizeof(regtab[0])) { |
| 914 | goto noreg; |
| 915 | } |
| 916 | reg = regtab+addr; |
| 917 | if (reg->name == NULL) { |
| 918 | goto noreg; |
| 919 | } |
| 920 | return reg; |
| 921 | |
| 922 | noreg: |
| 923 | dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); |
| 924 | return NULL; |
| 925 | } |
| 926 | |
| 927 | static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) |
| 928 | { |
| 929 | uint8_t *addr = (void*)d; |
| 930 | |
| 931 | addr += reg->offset; |
| 932 | return (uint32_t*)addr; |
| 933 | } |
| 934 | |
| 935 | static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, |
| 936 | uint32_t wmask) |
| 937 | { |
| 938 | uint32_t *addr; |
| 939 | uint32_t old; |
| 940 | |
| 941 | if (!reg) { |
| 942 | return; |
| 943 | } |
| 944 | |
| 945 | if (d->debug) { |
| 946 | time_t now = time(NULL); |
| 947 | if (d->last_write && d->last_reg == reg && d->last_val == val) { |
| 948 | d->repeat_count++; |
| 949 | if (d->last_sec != now) { |
| 950 | dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
| 951 | d->last_sec = now; |
| 952 | d->repeat_count = 0; |
| 953 | } |
| 954 | } else { |
| 955 | if (d->repeat_count) { |
| 956 | dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
| 957 | } |
| 958 | dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); |
| 959 | d->last_write = 1; |
| 960 | d->last_reg = reg; |
| 961 | d->last_val = val; |
| 962 | d->last_sec = now; |
| 963 | d->repeat_count = 0; |
| 964 | } |
| 965 | } |
| 966 | assert(reg->offset != 0); |
| 967 | |
| 968 | addr = intel_hda_reg_addr(d, reg); |
| 969 | old = *addr; |
| 970 | |
| 971 | if (reg->shift) { |
| 972 | val <<= reg->shift; |
| 973 | wmask <<= reg->shift; |
| 974 | } |
| 975 | wmask &= reg->wmask; |
| 976 | *addr &= ~wmask; |
| 977 | *addr |= wmask & val; |
| 978 | *addr &= ~(val & reg->wclear); |
| 979 | |
| 980 | if (reg->whandler) { |
| 981 | reg->whandler(d, reg, old); |
| 982 | } |
| 983 | } |
| 984 | |
| 985 | static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, |
| 986 | uint32_t rmask) |
| 987 | { |
| 988 | uint32_t *addr, ret; |
| 989 | |
| 990 | if (!reg) { |
| 991 | return 0; |
| 992 | } |
| 993 | |
| 994 | if (reg->rhandler) { |
| 995 | reg->rhandler(d, reg); |
| 996 | } |
| 997 | |
| 998 | if (reg->offset == 0) { |
| 999 | /* constant read-only register */ |
| 1000 | ret = reg->reset; |
| 1001 | } else { |
| 1002 | addr = intel_hda_reg_addr(d, reg); |
| 1003 | ret = *addr; |
| 1004 | if (reg->shift) { |
| 1005 | ret >>= reg->shift; |
| 1006 | } |
| 1007 | ret &= rmask; |
| 1008 | } |
| 1009 | if (d->debug) { |
| 1010 | time_t now = time(NULL); |
| 1011 | if (!d->last_write && d->last_reg == reg && d->last_val == ret) { |
| 1012 | d->repeat_count++; |
| 1013 | if (d->last_sec != now) { |
| 1014 | dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
| 1015 | d->last_sec = now; |
| 1016 | d->repeat_count = 0; |
| 1017 | } |
| 1018 | } else { |
| 1019 | if (d->repeat_count) { |
| 1020 | dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
| 1021 | } |
| 1022 | dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); |
| 1023 | d->last_write = 0; |
| 1024 | d->last_reg = reg; |
| 1025 | d->last_val = ret; |
| 1026 | d->last_sec = now; |
| 1027 | d->repeat_count = 0; |
| 1028 | } |
| 1029 | } |
| 1030 | return ret; |
| 1031 | } |
| 1032 | |
| 1033 | static void intel_hda_regs_reset(IntelHDAState *d) |
| 1034 | { |
| 1035 | uint32_t *addr; |
| 1036 | int i; |
| 1037 | |
| 1038 | for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) { |
| 1039 | if (regtab[i].name == NULL) { |
| 1040 | continue; |
| 1041 | } |
| 1042 | if (regtab[i].offset == 0) { |
| 1043 | continue; |
| 1044 | } |
| 1045 | addr = intel_hda_reg_addr(d, regtab + i); |
| 1046 | *addr = regtab[i].reset; |
| 1047 | } |
| 1048 | } |
| 1049 | |
| 1050 | /* --------------------------------------------------------------------- */ |
| 1051 | |
| 1052 | static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1053 | { |
| 1054 | IntelHDAState *d = opaque; |
| 1055 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); |
| 1056 | |
| 1057 | intel_hda_reg_write(d, reg, val, 0xff); |
| 1058 | } |
| 1059 | |
| 1060 | static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1061 | { |
| 1062 | IntelHDAState *d = opaque; |
| 1063 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); |
| 1064 | |
| 1065 | intel_hda_reg_write(d, reg, val, 0xffff); |
| 1066 | } |
| 1067 | |
| 1068 | static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1069 | { |
| 1070 | IntelHDAState *d = opaque; |
| 1071 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); |
| 1072 | |
| 1073 | intel_hda_reg_write(d, reg, val, 0xffffffff); |
| 1074 | } |
| 1075 | |
| 1076 | static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr) |
| 1077 | { |
| 1078 | IntelHDAState *d = opaque; |
| 1079 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); |
| 1080 | |
| 1081 | return intel_hda_reg_read(d, reg, 0xff); |
| 1082 | } |
| 1083 | |
| 1084 | static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr) |
| 1085 | { |
| 1086 | IntelHDAState *d = opaque; |
| 1087 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); |
| 1088 | |
| 1089 | return intel_hda_reg_read(d, reg, 0xffff); |
| 1090 | } |
| 1091 | |
| 1092 | static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr) |
| 1093 | { |
| 1094 | IntelHDAState *d = opaque; |
| 1095 | const IntelHDAReg *reg = intel_hda_reg_find(d, addr); |
| 1096 | |
| 1097 | return intel_hda_reg_read(d, reg, 0xffffffff); |
| 1098 | } |
| 1099 | |
| 1100 | static CPUReadMemoryFunc * const intel_hda_mmio_read[3] = { |
| 1101 | intel_hda_mmio_readb, |
| 1102 | intel_hda_mmio_readw, |
| 1103 | intel_hda_mmio_readl, |
| 1104 | }; |
| 1105 | |
| 1106 | static CPUWriteMemoryFunc * const intel_hda_mmio_write[3] = { |
| 1107 | intel_hda_mmio_writeb, |
| 1108 | intel_hda_mmio_writew, |
| 1109 | intel_hda_mmio_writel, |
| 1110 | }; |
| 1111 | |
| 1112 | static void intel_hda_map(PCIDevice *pci, int region_num, |
| 1113 | pcibus_t addr, pcibus_t size, int type) |
| 1114 | { |
| 1115 | IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
| 1116 | |
| 1117 | cpu_register_physical_memory(addr, 0x4000, d->mmio_addr); |
| 1118 | } |
| 1119 | |
| 1120 | /* --------------------------------------------------------------------- */ |
| 1121 | |
| 1122 | static void intel_hda_reset(DeviceState *dev) |
| 1123 | { |
| 1124 | IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev); |
| 1125 | DeviceState *qdev; |
| 1126 | HDACodecDevice *cdev; |
| 1127 | |
| 1128 | intel_hda_regs_reset(d); |
| 1129 | d->wall_base_ns = qemu_get_clock(vm_clock); |
| 1130 | |
| 1131 | /* reset codecs */ |
| 1132 | QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) { |
| 1133 | cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
| 1134 | if (qdev->info->reset) { |
| 1135 | qdev->info->reset(qdev); |
| 1136 | } |
| 1137 | d->state_sts |= (1 << cdev->cad); |
| 1138 | } |
| 1139 | intel_hda_update_irq(d); |
| 1140 | } |
| 1141 | |
| 1142 | static int intel_hda_init(PCIDevice *pci) |
| 1143 | { |
| 1144 | IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
| 1145 | uint8_t *conf = d->pci.config; |
| 1146 | |
| 1147 | d->name = d->pci.qdev.info->name; |
| 1148 | |
| 1149 | pci_config_set_vendor_id(conf, PCI_VENDOR_ID_INTEL); |
| 1150 | pci_config_set_device_id(conf, 0x2668); |
| 1151 | pci_config_set_revision(conf, 1); |
| 1152 | pci_config_set_class(conf, PCI_CLASS_MULTIMEDIA_HD_AUDIO); |
| 1153 | pci_config_set_interrupt_pin(conf, 1); |
| 1154 | |
| 1155 | /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ |
| 1156 | conf[0x40] = 0x01; |
| 1157 | |
| 1158 | d->mmio_addr = cpu_register_io_memory(intel_hda_mmio_read, |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 1159 | intel_hda_mmio_write, d, |
| 1160 | DEVICE_NATIVE_ENDIAN); |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 1161 | pci_register_bar(&d->pci, 0, 0x4000, PCI_BASE_ADDRESS_SPACE_MEMORY, |
| 1162 | intel_hda_map); |
Gerd Hoffmann | 17786d5 | 2010-11-09 11:47:48 +0100 | [diff] [blame] | 1163 | if (d->msi) { |
| 1164 | msi_init(&d->pci, 0x50, 1, true, false); |
| 1165 | } |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 1166 | |
| 1167 | hda_codec_bus_init(&d->pci.qdev, &d->codecs, |
| 1168 | intel_hda_response, intel_hda_xfer); |
| 1169 | |
| 1170 | return 0; |
| 1171 | } |
| 1172 | |
Gerd Hoffmann | dc4b924 | 2010-11-09 11:47:44 +0100 | [diff] [blame] | 1173 | static int intel_hda_exit(PCIDevice *pci) |
| 1174 | { |
| 1175 | IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
| 1176 | |
Gerd Hoffmann | 17786d5 | 2010-11-09 11:47:48 +0100 | [diff] [blame] | 1177 | if (d->msi) { |
| 1178 | msi_uninit(&d->pci); |
| 1179 | } |
Gerd Hoffmann | dc4b924 | 2010-11-09 11:47:44 +0100 | [diff] [blame] | 1180 | cpu_unregister_io_memory(d->mmio_addr); |
| 1181 | return 0; |
| 1182 | } |
| 1183 | |
Gerd Hoffmann | 17786d5 | 2010-11-09 11:47:48 +0100 | [diff] [blame] | 1184 | static void intel_hda_write_config(PCIDevice *pci, uint32_t addr, |
| 1185 | uint32_t val, int len) |
| 1186 | { |
| 1187 | IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
| 1188 | |
| 1189 | pci_default_write_config(pci, addr, val, len); |
| 1190 | if (d->msi) { |
| 1191 | msi_write_config(pci, addr, val, len); |
| 1192 | } |
| 1193 | } |
| 1194 | |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 1195 | static int intel_hda_post_load(void *opaque, int version) |
| 1196 | { |
| 1197 | IntelHDAState* d = opaque; |
| 1198 | int i; |
| 1199 | |
| 1200 | dprint(d, 1, "%s\n", __FUNCTION__); |
| 1201 | for (i = 0; i < ARRAY_SIZE(d->st); i++) { |
| 1202 | if (d->st[i].ctl & 0x02) { |
| 1203 | intel_hda_parse_bdl(d, &d->st[i]); |
| 1204 | } |
| 1205 | } |
| 1206 | intel_hda_update_irq(d); |
| 1207 | return 0; |
| 1208 | } |
| 1209 | |
| 1210 | static const VMStateDescription vmstate_intel_hda_stream = { |
| 1211 | .name = "intel-hda-stream", |
| 1212 | .version_id = 1, |
| 1213 | .fields = (VMStateField []) { |
| 1214 | VMSTATE_UINT32(ctl, IntelHDAStream), |
| 1215 | VMSTATE_UINT32(lpib, IntelHDAStream), |
| 1216 | VMSTATE_UINT32(cbl, IntelHDAStream), |
| 1217 | VMSTATE_UINT32(lvi, IntelHDAStream), |
| 1218 | VMSTATE_UINT32(fmt, IntelHDAStream), |
| 1219 | VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), |
| 1220 | VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), |
| 1221 | VMSTATE_END_OF_LIST() |
| 1222 | } |
| 1223 | }; |
| 1224 | |
| 1225 | static const VMStateDescription vmstate_intel_hda = { |
| 1226 | .name = "intel-hda", |
| 1227 | .version_id = 1, |
| 1228 | .post_load = intel_hda_post_load, |
| 1229 | .fields = (VMStateField []) { |
| 1230 | VMSTATE_PCI_DEVICE(pci, IntelHDAState), |
| 1231 | |
| 1232 | /* registers */ |
| 1233 | VMSTATE_UINT32(g_ctl, IntelHDAState), |
| 1234 | VMSTATE_UINT32(wake_en, IntelHDAState), |
| 1235 | VMSTATE_UINT32(state_sts, IntelHDAState), |
| 1236 | VMSTATE_UINT32(int_ctl, IntelHDAState), |
| 1237 | VMSTATE_UINT32(int_sts, IntelHDAState), |
| 1238 | VMSTATE_UINT32(wall_clk, IntelHDAState), |
| 1239 | VMSTATE_UINT32(corb_lbase, IntelHDAState), |
| 1240 | VMSTATE_UINT32(corb_ubase, IntelHDAState), |
| 1241 | VMSTATE_UINT32(corb_rp, IntelHDAState), |
| 1242 | VMSTATE_UINT32(corb_wp, IntelHDAState), |
| 1243 | VMSTATE_UINT32(corb_ctl, IntelHDAState), |
| 1244 | VMSTATE_UINT32(corb_sts, IntelHDAState), |
| 1245 | VMSTATE_UINT32(corb_size, IntelHDAState), |
| 1246 | VMSTATE_UINT32(rirb_lbase, IntelHDAState), |
| 1247 | VMSTATE_UINT32(rirb_ubase, IntelHDAState), |
| 1248 | VMSTATE_UINT32(rirb_wp, IntelHDAState), |
| 1249 | VMSTATE_UINT32(rirb_cnt, IntelHDAState), |
| 1250 | VMSTATE_UINT32(rirb_ctl, IntelHDAState), |
| 1251 | VMSTATE_UINT32(rirb_sts, IntelHDAState), |
| 1252 | VMSTATE_UINT32(rirb_size, IntelHDAState), |
| 1253 | VMSTATE_UINT32(dp_lbase, IntelHDAState), |
| 1254 | VMSTATE_UINT32(dp_ubase, IntelHDAState), |
| 1255 | VMSTATE_UINT32(icw, IntelHDAState), |
| 1256 | VMSTATE_UINT32(irr, IntelHDAState), |
| 1257 | VMSTATE_UINT32(ics, IntelHDAState), |
| 1258 | VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, |
| 1259 | vmstate_intel_hda_stream, |
| 1260 | IntelHDAStream), |
| 1261 | |
| 1262 | /* additional state info */ |
| 1263 | VMSTATE_UINT32(rirb_count, IntelHDAState), |
| 1264 | VMSTATE_INT64(wall_base_ns, IntelHDAState), |
| 1265 | |
| 1266 | VMSTATE_END_OF_LIST() |
| 1267 | } |
| 1268 | }; |
| 1269 | |
| 1270 | static PCIDeviceInfo intel_hda_info = { |
| 1271 | .qdev.name = "intel-hda", |
| 1272 | .qdev.desc = "Intel HD Audio Controller", |
| 1273 | .qdev.size = sizeof(IntelHDAState), |
| 1274 | .qdev.vmsd = &vmstate_intel_hda, |
| 1275 | .qdev.reset = intel_hda_reset, |
| 1276 | .init = intel_hda_init, |
Gerd Hoffmann | dc4b924 | 2010-11-09 11:47:44 +0100 | [diff] [blame] | 1277 | .exit = intel_hda_exit, |
Gerd Hoffmann | 17786d5 | 2010-11-09 11:47:48 +0100 | [diff] [blame] | 1278 | .config_write = intel_hda_write_config, |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 1279 | .qdev.props = (Property[]) { |
| 1280 | DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), |
Gerd Hoffmann | 17786d5 | 2010-11-09 11:47:48 +0100 | [diff] [blame] | 1281 | DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1), |
Gerd Hoffmann | d61a4ce | 2010-11-01 13:05:32 +0100 | [diff] [blame] | 1282 | DEFINE_PROP_END_OF_LIST(), |
| 1283 | } |
| 1284 | }; |
| 1285 | |
| 1286 | static void intel_hda_register(void) |
| 1287 | { |
| 1288 | pci_qdev_register(&intel_hda_info); |
| 1289 | } |
| 1290 | device_init(intel_hda_register); |
| 1291 | |
| 1292 | /* |
| 1293 | * create intel hda controller with codec attached to it, |
| 1294 | * so '-soundhw hda' works. |
| 1295 | */ |
| 1296 | int intel_hda_and_codec_init(PCIBus *bus) |
| 1297 | { |
| 1298 | PCIDevice *controller; |
| 1299 | BusState *hdabus; |
| 1300 | DeviceState *codec; |
| 1301 | |
| 1302 | controller = pci_create_simple(bus, -1, "intel-hda"); |
| 1303 | hdabus = QLIST_FIRST(&controller->qdev.child_bus); |
| 1304 | codec = qdev_create(hdabus, "hda-duplex"); |
| 1305 | qdev_init_nofail(codec); |
| 1306 | return 0; |
| 1307 | } |
| 1308 | |