blob: 9c1fbf9b77abbb08862efb96525e2bdf7850792b [file] [log] [blame]
Guan Xuetao6e64da32011-04-12 16:25:59 +08001/*
2 * UniCore32 virtual CPU header
3 *
Guan Xuetaod48813d2012-08-10 14:42:23 +08004 * Copyright (C) 2010-2012 Guan Xuetao
Guan Xuetao6e64da32011-04-12 16:25:59 +08005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
Andreas Färber2b3bc6c2012-03-13 16:48:19 +01008 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
Guan Xuetao6e64da32011-04-12 16:25:59 +080010 */
Guan Xuetaod48813d2012-08-10 14:42:23 +080011#ifndef QEMU_UNICORE32_CPU_H
12#define QEMU_UNICORE32_CPU_H
Guan Xuetao6e64da32011-04-12 16:25:59 +080013
14#define TARGET_LONG_BITS 32
15#define TARGET_PAGE_BITS 12
16
17#define TARGET_PHYS_ADDR_SPACE_BITS 32
18#define TARGET_VIRT_ADDR_SPACE_BITS 32
19
Andreas Färber9349b4f2012-03-14 01:38:32 +010020#define CPUArchState struct CPUUniCore32State
Guan Xuetao6e64da32011-04-12 16:25:59 +080021
Stefan Weil81419052012-02-02 21:47:01 +010022#include "qemu-common.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010023#include "exec/cpu-defs.h"
Paolo Bonzini6b4c3052012-10-24 13:12:00 +020024#include "fpu/softfloat.h"
Guan Xuetao6e64da32011-04-12 16:25:59 +080025
26#define NB_MMU_MODES 2
27
Andreas Färber15ecee72012-02-16 00:12:24 +010028typedef struct CPUUniCore32State {
Guan Xuetao6e64da32011-04-12 16:25:59 +080029 /* Regs for current mode. */
30 uint32_t regs[32];
31 /* Frequently accessed ASR bits are stored separately for efficiently.
32 This contains all the other bits. Use asr_{read,write} to access
33 the whole ASR. */
34 uint32_t uncached_asr;
35 uint32_t bsr;
36
37 /* Banked registers. */
38 uint32_t banked_bsr[6];
39 uint32_t banked_r29[6];
40 uint32_t banked_r30[6];
41
42 /* asr flag cache for faster execution */
43 uint32_t CF; /* 0 or 1 */
44 uint32_t VF; /* V is the bit 31. All other bits are undefined */
45 uint32_t NF; /* N is bit 31. All other bits are undefined. */
46 uint32_t ZF; /* Z set if zero. */
47
48 /* System control coprocessor (cp0) */
49 struct {
50 uint32_t c0_cpuid;
51 uint32_t c0_cachetype;
52 uint32_t c1_sys; /* System control register. */
53 uint32_t c2_base; /* MMU translation table base. */
54 uint32_t c3_faultstatus; /* Fault status registers. */
55 uint32_t c4_faultaddr; /* Fault address registers. */
56 uint32_t c5_cacheop; /* Cache operation registers. */
57 uint32_t c6_tlbop; /* TLB operation registers. */
58 } cp0;
59
60 /* UniCore-F64 coprocessor state. */
61 struct {
62 float64 regs[16];
63 uint32_t xregs[32];
64 float_status fp_status;
65 } ucf64;
66
67 CPU_COMMON
68
69 /* Internal CPU feature flags. */
70 uint32_t features;
71
Andreas Färber15ecee72012-02-16 00:12:24 +010072} CPUUniCore32State;
Guan Xuetao6e64da32011-04-12 16:25:59 +080073
74#define ASR_M (0x1f)
75#define ASR_MODE_USER (0x10)
76#define ASR_MODE_INTR (0x12)
77#define ASR_MODE_PRIV (0x13)
78#define ASR_MODE_TRAP (0x17)
79#define ASR_MODE_EXTN (0x1b)
80#define ASR_MODE_SUSR (0x1f)
81#define ASR_I (1 << 7)
82#define ASR_V (1 << 28)
83#define ASR_C (1 << 29)
84#define ASR_Z (1 << 30)
85#define ASR_N (1 << 31)
86#define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V)
87#define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV))
88
Guan Xuetaod48813d2012-08-10 14:42:23 +080089#define UC32_EXCP_PRIV (1)
90#define UC32_EXCP_ITRAP (2)
91#define UC32_EXCP_DTRAP (3)
92#define UC32_EXCP_INTR (4)
Guan Xuetao6e64da32011-04-12 16:25:59 +080093
94/* Return the current ASR value. */
Andreas Färbereb23b552012-03-14 01:38:23 +010095target_ulong cpu_asr_read(CPUUniCore32State *env1);
Guan Xuetao6e64da32011-04-12 16:25:59 +080096/* Set the ASR. Note that some bits of mask must be all-set or all-clear. */
Andreas Färbereb23b552012-03-14 01:38:23 +010097void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask);
Guan Xuetao6e64da32011-04-12 16:25:59 +080098
99/* UniCore-F64 system registers. */
100#define UC32_UCF64_FPSCR (31)
101#define UCF64_FPSCR_MASK (0x27ffffff)
102#define UCF64_FPSCR_RND_MASK (0x7)
103#define UCF64_FPSCR_RND(r) (((r) >> 0) & UCF64_FPSCR_RND_MASK)
104#define UCF64_FPSCR_TRAPEN_MASK (0x7f)
105#define UCF64_FPSCR_TRAPEN(r) (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK)
106#define UCF64_FPSCR_FLAG_MASK (0x3ff)
107#define UCF64_FPSCR_FLAG(r) (((r) >> 17) & UCF64_FPSCR_FLAG_MASK)
108#define UCF64_FPSCR_FLAG_ZERO (1 << 17)
109#define UCF64_FPSCR_FLAG_INFINITY (1 << 18)
110#define UCF64_FPSCR_FLAG_INVALID (1 << 19)
111#define UCF64_FPSCR_FLAG_UNDERFLOW (1 << 20)
112#define UCF64_FPSCR_FLAG_OVERFLOW (1 << 21)
113#define UCF64_FPSCR_FLAG_INEXACT (1 << 22)
114#define UCF64_FPSCR_FLAG_HUGEINT (1 << 23)
115#define UCF64_FPSCR_FLAG_DENORMAL (1 << 24)
116#define UCF64_FPSCR_FLAG_UNIMP (1 << 25)
117#define UCF64_FPSCR_FLAG_DIVZERO (1 << 26)
118
119#define UC32_HWCAP_CMOV 4 /* 1 << 2 */
120#define UC32_HWCAP_UCF64 8 /* 1 << 3 */
121
Guan Xuetao6e64da32011-04-12 16:25:59 +0800122#define cpu_exec uc32_cpu_exec
123#define cpu_signal_handler uc32_cpu_signal_handler
Guan Xuetao6e64da32011-04-12 16:25:59 +0800124
Guan Xuetao6e64da32011-04-12 16:25:59 +0800125int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
Guan Xuetao6e64da32011-04-12 16:25:59 +0800126
Guan Xuetao6e64da32011-04-12 16:25:59 +0800127/* MMU modes definitions */
128#define MMU_MODE0_SUFFIX _kernel
129#define MMU_MODE1_SUFFIX _user
130#define MMU_USER_IDX 1
Benjamin Herrenschmidt97ed5cc2015-08-17 17:34:10 +1000131static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
Guan Xuetao6e64da32011-04-12 16:25:59 +0800132{
133 return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
134}
135
Paolo Bonzini022c62c2012-12-17 18:19:49 +0100136#include "exec/cpu-all.h"
Andreas Färberae0f5e92012-02-14 01:16:17 +0100137#include "cpu-qom.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +0100138#include "exec/exec-all.h"
Guan Xuetao6e64da32011-04-12 16:25:59 +0800139
Peter Crosthwaiteea3e9842015-06-18 10:24:55 -0700140int uc32_cpu_exec(CPUState *s);
141
Eduardo Habkost41979662015-02-26 17:37:46 -0300142UniCore32CPU *uc32_cpu_init(const char *cpu_model);
143
Eduardo Habkost2994fd92015-02-26 17:37:49 -0300144#define cpu_init(cpu_model) CPU(uc32_cpu_init(cpu_model))
Eduardo Habkost41979662015-02-26 17:37:46 -0300145
Andreas Färbereb23b552012-03-14 01:38:23 +0100146static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
Guan Xuetao6e64da32011-04-12 16:25:59 +0800147 target_ulong *cs_base, int *flags)
148{
149 *pc = env->regs[31];
150 *cs_base = 0;
151 *flags = 0;
152 if ((env->uncached_asr & ASR_M) != ASR_MODE_USER) {
153 *flags |= (1 << 6);
154 }
155}
156
Andreas Färber75104542013-08-26 03:01:33 +0200157int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
158 int mmu_idx);
Guan Xuetao6e64da32011-04-12 16:25:59 +0800159void uc32_translate_init(void);
Andreas Färber15ecee72012-02-16 00:12:24 +0100160void switch_mode(CPUUniCore32State *, int);
Guan Xuetao6e64da32011-04-12 16:25:59 +0800161
Guan Xuetaod48813d2012-08-10 14:42:23 +0800162#endif /* QEMU_UNICORE32_CPU_H */