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bellard80cabfa2004-03-14 12:20:30 +00001/*
2 * QEMU 8253/8254 interval timer emulation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard80cabfa2004-03-14 12:20:30 +00004 * Copyright (c) 2003-2004 Fabrice Bellard
ths5fafdf22007-09-16 21:08:06 +00005 *
bellard80cabfa2004-03-14 12:20:30 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Markus Armbruster0b8fa322019-05-23 16:35:07 +020024
Peter Maydellb6a0aa02016-01-26 18:17:03 +000025#include "qemu/osdep.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020026#include "hw/irq.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020027#include "qemu/module.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010028#include "qemu/timer.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010029#include "hw/timer/i8254.h"
30#include "hw/timer/i8254_internal.h"
bellard80cabfa2004-03-14 12:20:30 +000031
bellardb0a21b52004-03-31 18:58:38 +000032//#define DEBUG_PIT
33
bellardec844b92004-05-03 23:18:25 +000034#define RW_STATE_LSB 1
35#define RW_STATE_MSB 2
36#define RW_STATE_WORD0 3
37#define RW_STATE_WORD1 4
bellard80cabfa2004-03-14 12:20:30 +000038
Andreas Färbera15d0912012-11-25 18:47:58 +010039#define PIT_CLASS(class) OBJECT_CLASS_CHECK(PITClass, (class), TYPE_I8254)
40#define PIT_GET_CLASS(obj) OBJECT_GET_CLASS(PITClass, (obj), TYPE_I8254)
41
42typedef struct PITClass {
43 PITCommonClass parent_class;
44
45 DeviceRealize parent_realize;
46} PITClass;
47
bellardb0a21b52004-03-31 18:58:38 +000048static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
49
bellard80cabfa2004-03-14 12:20:30 +000050static int pit_get_count(PITChannelState *s)
51{
52 uint64_t d;
53 int counter;
54
Alex Blighbc72ad62013-08-21 16:03:08 +010055 d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->count_load_time, PIT_FREQ,
Rutuja Shah73bcb242016-03-21 21:32:30 +053056 NANOSECONDS_PER_SECOND);
bellard80cabfa2004-03-14 12:20:30 +000057 switch(s->mode) {
58 case 0:
59 case 1:
60 case 4:
61 case 5:
62 counter = (s->count - d) & 0xffff;
63 break;
64 case 3:
65 /* XXX: may be incorrect for odd counts */
66 counter = s->count - ((2 * d) % s->count);
67 break;
68 default:
69 counter = s->count - (d % s->count);
70 break;
71 }
72 return counter;
73}
74
bellard80cabfa2004-03-14 12:20:30 +000075/* val must be 0 or 1 */
Jan Kiszkad11e8592012-03-02 20:28:46 +010076static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc,
77 int val)
bellard80cabfa2004-03-14 12:20:30 +000078{
Jan Kiszkad11e8592012-03-02 20:28:46 +010079 switch (sc->mode) {
bellard80cabfa2004-03-14 12:20:30 +000080 default:
81 case 0:
82 case 4:
83 /* XXX: just disable/enable counting */
84 break;
85 case 1:
86 case 5:
Jan Kiszkad11e8592012-03-02 20:28:46 +010087 if (sc->gate < val) {
bellard80cabfa2004-03-14 12:20:30 +000088 /* restart counting on rising edge */
Alex Blighbc72ad62013-08-21 16:03:08 +010089 sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
Jan Kiszkad11e8592012-03-02 20:28:46 +010090 pit_irq_timer_update(sc, sc->count_load_time);
bellard80cabfa2004-03-14 12:20:30 +000091 }
92 break;
93 case 2:
94 case 3:
Jan Kiszkad11e8592012-03-02 20:28:46 +010095 if (sc->gate < val) {
bellard80cabfa2004-03-14 12:20:30 +000096 /* restart counting on rising edge */
Alex Blighbc72ad62013-08-21 16:03:08 +010097 sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
Jan Kiszkad11e8592012-03-02 20:28:46 +010098 pit_irq_timer_update(sc, sc->count_load_time);
bellard80cabfa2004-03-14 12:20:30 +000099 }
100 /* XXX: disable/enable counting */
101 break;
102 }
Jan Kiszkad11e8592012-03-02 20:28:46 +0100103 sc->gate = val;
bellardfd06c372006-04-24 21:58:30 +0000104}
105
bellard80cabfa2004-03-14 12:20:30 +0000106static inline void pit_load_count(PITChannelState *s, int val)
107{
108 if (val == 0)
109 val = 0x10000;
Alex Blighbc72ad62013-08-21 16:03:08 +0100110 s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
bellard80cabfa2004-03-14 12:20:30 +0000111 s->count = val;
bellardb0a21b52004-03-31 18:58:38 +0000112 pit_irq_timer_update(s, s->count_load_time);
bellard80cabfa2004-03-14 12:20:30 +0000113}
114
bellardec844b92004-05-03 23:18:25 +0000115/* if already latched, do not latch again */
116static void pit_latch_count(PITChannelState *s)
117{
118 if (!s->count_latched) {
119 s->latched_count = pit_get_count(s);
120 s->count_latched = s->rw_mode;
121 }
122}
123
Alexander Graf0505bcd2012-10-08 13:12:31 +0200124static void pit_ioport_write(void *opaque, hwaddr addr,
125 uint64_t val, unsigned size)
bellard80cabfa2004-03-14 12:20:30 +0000126{
Jan Kiszkad11e8592012-03-02 20:28:46 +0100127 PITCommonState *pit = opaque;
bellard80cabfa2004-03-14 12:20:30 +0000128 int channel, access;
129 PITChannelState *s;
130
131 addr &= 3;
132 if (addr == 3) {
133 channel = val >> 6;
bellardec844b92004-05-03 23:18:25 +0000134 if (channel == 3) {
135 /* read back command */
136 for(channel = 0; channel < 3; channel++) {
137 s = &pit->channels[channel];
138 if (val & (2 << channel)) {
139 if (!(val & 0x20)) {
140 pit_latch_count(s);
141 }
142 if (!(val & 0x10) && !s->status_latched) {
143 /* status latch */
144 /* XXX: add BCD and null count */
Jan Kiszka4aa5d282012-02-01 20:31:43 +0100145 s->status =
146 (pit_get_out(s,
Alex Blighbc72ad62013-08-21 16:03:08 +0100147 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) << 7) |
bellardec844b92004-05-03 23:18:25 +0000148 (s->rw_mode << 4) |
149 (s->mode << 1) |
150 s->bcd;
151 s->status_latched = 1;
152 }
153 }
154 }
155 } else {
156 s = &pit->channels[channel];
157 access = (val >> 4) & 3;
158 if (access == 0) {
159 pit_latch_count(s);
160 } else {
161 s->rw_mode = access;
162 s->read_state = access;
163 s->write_state = access;
164
165 s->mode = (val >> 1) & 7;
166 s->bcd = val & 1;
167 /* XXX: update irq timer ? */
168 }
bellard80cabfa2004-03-14 12:20:30 +0000169 }
170 } else {
bellardec844b92004-05-03 23:18:25 +0000171 s = &pit->channels[addr];
172 switch(s->write_state) {
173 default:
bellard80cabfa2004-03-14 12:20:30 +0000174 case RW_STATE_LSB:
175 pit_load_count(s, val);
176 break;
177 case RW_STATE_MSB:
178 pit_load_count(s, val << 8);
179 break;
180 case RW_STATE_WORD0:
bellardec844b92004-05-03 23:18:25 +0000181 s->write_latch = val;
182 s->write_state = RW_STATE_WORD1;
183 break;
bellard80cabfa2004-03-14 12:20:30 +0000184 case RW_STATE_WORD1:
bellardec844b92004-05-03 23:18:25 +0000185 pit_load_count(s, s->write_latch | (val << 8));
186 s->write_state = RW_STATE_WORD0;
bellard80cabfa2004-03-14 12:20:30 +0000187 break;
188 }
189 }
190}
191
Alexander Graf0505bcd2012-10-08 13:12:31 +0200192static uint64_t pit_ioport_read(void *opaque, hwaddr addr,
193 unsigned size)
bellard80cabfa2004-03-14 12:20:30 +0000194{
Jan Kiszkad11e8592012-03-02 20:28:46 +0100195 PITCommonState *pit = opaque;
bellard80cabfa2004-03-14 12:20:30 +0000196 int ret, count;
197 PITChannelState *s;
ths3b46e622007-09-17 08:09:54 +0000198
bellard80cabfa2004-03-14 12:20:30 +0000199 addr &= 3;
Petr Matousekd4862a82015-06-17 12:46:11 +0200200
201 if (addr == 3) {
202 /* Mode/Command register is write only, read is ignored */
203 return 0;
204 }
205
bellardec844b92004-05-03 23:18:25 +0000206 s = &pit->channels[addr];
207 if (s->status_latched) {
208 s->status_latched = 0;
209 ret = s->status;
210 } else if (s->count_latched) {
211 switch(s->count_latched) {
212 default:
213 case RW_STATE_LSB:
bellard80cabfa2004-03-14 12:20:30 +0000214 ret = s->latched_count & 0xff;
bellardec844b92004-05-03 23:18:25 +0000215 s->count_latched = 0;
216 break;
217 case RW_STATE_MSB:
218 ret = s->latched_count >> 8;
219 s->count_latched = 0;
220 break;
221 case RW_STATE_WORD0:
222 ret = s->latched_count & 0xff;
223 s->count_latched = RW_STATE_MSB;
224 break;
225 }
226 } else {
227 switch(s->read_state) {
228 default:
229 case RW_STATE_LSB:
230 count = pit_get_count(s);
231 ret = count & 0xff;
232 break;
233 case RW_STATE_MSB:
234 count = pit_get_count(s);
235 ret = (count >> 8) & 0xff;
236 break;
237 case RW_STATE_WORD0:
238 count = pit_get_count(s);
239 ret = count & 0xff;
240 s->read_state = RW_STATE_WORD1;
241 break;
242 case RW_STATE_WORD1:
243 count = pit_get_count(s);
244 ret = (count >> 8) & 0xff;
245 s->read_state = RW_STATE_WORD0;
246 break;
247 }
bellard80cabfa2004-03-14 12:20:30 +0000248 }
249 return ret;
250}
251
bellardb0a21b52004-03-31 18:58:38 +0000252static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
253{
254 int64_t expire_time;
255 int irq_level;
256
Jan Kiszkace967e22012-02-01 20:31:41 +0100257 if (!s->irq_timer || s->irq_disabled) {
bellardb0a21b52004-03-31 18:58:38 +0000258 return;
Jan Kiszkace967e22012-02-01 20:31:41 +0100259 }
bellardb0a21b52004-03-31 18:58:38 +0000260 expire_time = pit_get_next_transition_time(s, current_time);
Jan Kiszka4aa5d282012-02-01 20:31:43 +0100261 irq_level = pit_get_out(s, current_time);
pbrookd537cf62007-04-07 18:14:41 +0000262 qemu_set_irq(s->irq, irq_level);
bellardb0a21b52004-03-31 18:58:38 +0000263#ifdef DEBUG_PIT
264 printf("irq_level=%d next_delay=%f\n",
ths5fafdf22007-09-16 21:08:06 +0000265 irq_level,
Rutuja Shah73bcb242016-03-21 21:32:30 +0530266 (double)(expire_time - current_time) / NANOSECONDS_PER_SECOND);
bellardb0a21b52004-03-31 18:58:38 +0000267#endif
268 s->next_transition_time = expire_time;
269 if (expire_time != -1)
Alex Blighbc72ad62013-08-21 16:03:08 +0100270 timer_mod(s->irq_timer, expire_time);
bellardb0a21b52004-03-31 18:58:38 +0000271 else
Alex Blighbc72ad62013-08-21 16:03:08 +0100272 timer_del(s->irq_timer);
bellardb0a21b52004-03-31 18:58:38 +0000273}
274
275static void pit_irq_timer(void *opaque)
276{
277 PITChannelState *s = opaque;
278
279 pit_irq_timer_update(s, s->next_transition_time);
280}
281
Blue Swirl64d7e9a2011-02-13 19:54:40 +0000282static void pit_reset(DeviceState *dev)
bellard80cabfa2004-03-14 12:20:30 +0000283{
Andreas Färber3afe7e12012-11-25 18:05:53 +0100284 PITCommonState *pit = PIT_COMMON(dev);
bellard80cabfa2004-03-14 12:20:30 +0000285 PITChannelState *s;
bellard80cabfa2004-03-14 12:20:30 +0000286
Jan Kiszkad11e8592012-03-02 20:28:46 +0100287 pit_reset_common(pit);
288
289 s = &pit->channels[0];
290 if (!s->irq_disabled) {
Alex Blighbc72ad62013-08-21 16:03:08 +0100291 timer_mod(s->irq_timer, s->next_transition_time);
bellard80cabfa2004-03-14 12:20:30 +0000292 }
bellardd7d02e32004-06-20 12:58:36 +0000293}
294
Jan Kiszkace967e22012-02-01 20:31:41 +0100295/* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
296 * reenable it when legacy mode is left again. */
297static void pit_irq_control(void *opaque, int n, int enable)
aliguori16b29ae2008-12-17 23:28:44 +0000298{
Jan Kiszkad11e8592012-03-02 20:28:46 +0100299 PITCommonState *pit = opaque;
Jan Kiszkace967e22012-02-01 20:31:41 +0100300 PITChannelState *s = &pit->channels[0];
301
302 if (enable) {
303 s->irq_disabled = 0;
Alex Blighbc72ad62013-08-21 16:03:08 +0100304 pit_irq_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
Jan Kiszkace967e22012-02-01 20:31:41 +0100305 } else {
306 s->irq_disabled = 1;
Alex Blighbc72ad62013-08-21 16:03:08 +0100307 timer_del(s->irq_timer);
Jan Kiszkace967e22012-02-01 20:31:41 +0100308 }
aliguori16b29ae2008-12-17 23:28:44 +0000309}
310
Richard Henderson60ea6aa2011-08-10 15:28:15 -0700311static const MemoryRegionOps pit_ioport_ops = {
Alexander Graf0505bcd2012-10-08 13:12:31 +0200312 .read = pit_ioport_read,
313 .write = pit_ioport_write,
314 .impl = {
315 .min_access_size = 1,
316 .max_access_size = 1,
317 },
318 .endianness = DEVICE_LITTLE_ENDIAN,
Richard Henderson60ea6aa2011-08-10 15:28:15 -0700319};
320
Jan Kiszka3fbc1c02012-03-02 20:28:47 +0100321static void pit_post_load(PITCommonState *s)
322{
323 PITChannelState *sc = &s->channels[0];
324
325 if (sc->next_transition_time != -1) {
Alex Blighbc72ad62013-08-21 16:03:08 +0100326 timer_mod(sc->irq_timer, sc->next_transition_time);
Jan Kiszka3fbc1c02012-03-02 20:28:47 +0100327 } else {
Alex Blighbc72ad62013-08-21 16:03:08 +0100328 timer_del(sc->irq_timer);
Jan Kiszka3fbc1c02012-03-02 20:28:47 +0100329 }
330}
331
Markus Armbrustera7737e42014-04-25 12:44:21 +0200332static void pit_realizefn(DeviceState *dev, Error **errp)
bellardd7d02e32004-06-20 12:58:36 +0000333{
Andreas Färbera15d0912012-11-25 18:47:58 +0100334 PITCommonState *pit = PIT_COMMON(dev);
335 PITClass *pc = PIT_GET_CLASS(dev);
bellardd7d02e32004-06-20 12:58:36 +0000336 PITChannelState *s;
337
338 s = &pit->channels[0];
339 /* the timer 0 is connected to an IRQ */
Alex Blighbc72ad62013-08-21 16:03:08 +0100340 s->irq_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pit_irq_timer, s);
Andreas Färbera15d0912012-11-25 18:47:58 +0100341 qdev_init_gpio_out(dev, &s->irq, 1);
bellard80cabfa2004-03-14 12:20:30 +0000342
Paolo Bonzini853dca12013-06-06 21:25:08 -0400343 memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops,
344 pit, "pit", 4);
bellardd7d02e32004-06-20 12:58:36 +0000345
Andreas Färbera15d0912012-11-25 18:47:58 +0100346 qdev_init_gpio_in(dev, pit_irq_control, 1);
Jan Kiszkaca22a3a2011-03-06 16:09:49 +0100347
Markus Armbrustera7737e42014-04-25 12:44:21 +0200348 pc->parent_realize(dev, errp);
bellard80cabfa2004-03-14 12:20:30 +0000349}
Blue Swirl64d7e9a2011-02-13 19:54:40 +0000350
Anthony Liguori39bffca2011-12-07 21:34:16 -0600351static Property pit_properties[] = {
Paolo Bonzinic7bcc852014-02-08 11:01:53 +0100352 DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600353 DEFINE_PROP_END_OF_LIST(),
354};
355
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600356static void pit_class_initfn(ObjectClass *klass, void *data)
357{
Andreas Färbera15d0912012-11-25 18:47:58 +0100358 PITClass *pc = PIT_CLASS(klass);
Jan Kiszkad11e8592012-03-02 20:28:46 +0100359 PITCommonClass *k = PIT_COMMON_CLASS(klass);
Anthony Liguori39bffca2011-12-07 21:34:16 -0600360 DeviceClass *dc = DEVICE_CLASS(klass);
Jan Kiszkad11e8592012-03-02 20:28:46 +0100361
Philippe Mathieu-Daudébf853882018-01-13 23:04:12 -0300362 device_class_set_parent_realize(dc, pit_realizefn, &pc->parent_realize);
Jan Kiszkad11e8592012-03-02 20:28:46 +0100363 k->set_channel_gate = pit_set_channel_gate;
364 k->get_channel_info = pit_get_channel_info_common;
Jan Kiszka3fbc1c02012-03-02 20:28:47 +0100365 k->post_load = pit_post_load;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600366 dc->reset = pit_reset;
Marc-André Lureau4f67d302020-01-10 19:30:32 +0400367 device_class_set_props(dc, pit_properties);
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600368}
369
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100370static const TypeInfo pit_info = {
Andreas Färber3afe7e12012-11-25 18:05:53 +0100371 .name = TYPE_I8254,
Jan Kiszkad11e8592012-03-02 20:28:46 +0100372 .parent = TYPE_PIT_COMMON,
373 .instance_size = sizeof(PITCommonState),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600374 .class_init = pit_class_initfn,
Andreas Färbera15d0912012-11-25 18:47:58 +0100375 .class_size = sizeof(PITClass),
Blue Swirl64d7e9a2011-02-13 19:54:40 +0000376};
377
Andreas Färber83f7d432012-02-09 15:20:55 +0100378static void pit_register_types(void)
Blue Swirl64d7e9a2011-02-13 19:54:40 +0000379{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600380 type_register_static(&pit_info);
Blue Swirl64d7e9a2011-02-13 19:54:40 +0000381}
Andreas Färber83f7d432012-02-09 15:20:55 +0100382
383type_init(pit_register_types)