bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU 8253/8254 interval timer emulation |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 24 | |
Peter Maydell | b6a0aa0 | 2016-01-26 18:17:03 +0000 | [diff] [blame] | 25 | #include "qemu/osdep.h" |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 26 | #include "hw/irq.h" |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 27 | #include "qemu/module.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 28 | #include "qemu/timer.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 29 | #include "hw/timer/i8254.h" |
| 30 | #include "hw/timer/i8254_internal.h" |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 31 | |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 32 | //#define DEBUG_PIT |
| 33 | |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 34 | #define RW_STATE_LSB 1 |
| 35 | #define RW_STATE_MSB 2 |
| 36 | #define RW_STATE_WORD0 3 |
| 37 | #define RW_STATE_WORD1 4 |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 38 | |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 39 | #define PIT_CLASS(class) OBJECT_CLASS_CHECK(PITClass, (class), TYPE_I8254) |
| 40 | #define PIT_GET_CLASS(obj) OBJECT_GET_CLASS(PITClass, (obj), TYPE_I8254) |
| 41 | |
| 42 | typedef struct PITClass { |
| 43 | PITCommonClass parent_class; |
| 44 | |
| 45 | DeviceRealize parent_realize; |
| 46 | } PITClass; |
| 47 | |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 48 | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); |
| 49 | |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 50 | static int pit_get_count(PITChannelState *s) |
| 51 | { |
| 52 | uint64_t d; |
| 53 | int counter; |
| 54 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 55 | d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->count_load_time, PIT_FREQ, |
Rutuja Shah | 73bcb24 | 2016-03-21 21:32:30 +0530 | [diff] [blame] | 56 | NANOSECONDS_PER_SECOND); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 57 | switch(s->mode) { |
| 58 | case 0: |
| 59 | case 1: |
| 60 | case 4: |
| 61 | case 5: |
| 62 | counter = (s->count - d) & 0xffff; |
| 63 | break; |
| 64 | case 3: |
| 65 | /* XXX: may be incorrect for odd counts */ |
| 66 | counter = s->count - ((2 * d) % s->count); |
| 67 | break; |
| 68 | default: |
| 69 | counter = s->count - (d % s->count); |
| 70 | break; |
| 71 | } |
| 72 | return counter; |
| 73 | } |
| 74 | |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 75 | /* val must be 0 or 1 */ |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 76 | static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc, |
| 77 | int val) |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 78 | { |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 79 | switch (sc->mode) { |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 80 | default: |
| 81 | case 0: |
| 82 | case 4: |
| 83 | /* XXX: just disable/enable counting */ |
| 84 | break; |
| 85 | case 1: |
| 86 | case 5: |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 87 | if (sc->gate < val) { |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 88 | /* restart counting on rising edge */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 89 | sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 90 | pit_irq_timer_update(sc, sc->count_load_time); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 91 | } |
| 92 | break; |
| 93 | case 2: |
| 94 | case 3: |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 95 | if (sc->gate < val) { |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 96 | /* restart counting on rising edge */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 97 | sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 98 | pit_irq_timer_update(sc, sc->count_load_time); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 99 | } |
| 100 | /* XXX: disable/enable counting */ |
| 101 | break; |
| 102 | } |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 103 | sc->gate = val; |
bellard | fd06c37 | 2006-04-24 21:58:30 +0000 | [diff] [blame] | 104 | } |
| 105 | |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 106 | static inline void pit_load_count(PITChannelState *s, int val) |
| 107 | { |
| 108 | if (val == 0) |
| 109 | val = 0x10000; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 110 | s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 111 | s->count = val; |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 112 | pit_irq_timer_update(s, s->count_load_time); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 113 | } |
| 114 | |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 115 | /* if already latched, do not latch again */ |
| 116 | static void pit_latch_count(PITChannelState *s) |
| 117 | { |
| 118 | if (!s->count_latched) { |
| 119 | s->latched_count = pit_get_count(s); |
| 120 | s->count_latched = s->rw_mode; |
| 121 | } |
| 122 | } |
| 123 | |
Alexander Graf | 0505bcd | 2012-10-08 13:12:31 +0200 | [diff] [blame] | 124 | static void pit_ioport_write(void *opaque, hwaddr addr, |
| 125 | uint64_t val, unsigned size) |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 126 | { |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 127 | PITCommonState *pit = opaque; |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 128 | int channel, access; |
| 129 | PITChannelState *s; |
| 130 | |
| 131 | addr &= 3; |
| 132 | if (addr == 3) { |
| 133 | channel = val >> 6; |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 134 | if (channel == 3) { |
| 135 | /* read back command */ |
| 136 | for(channel = 0; channel < 3; channel++) { |
| 137 | s = &pit->channels[channel]; |
| 138 | if (val & (2 << channel)) { |
| 139 | if (!(val & 0x20)) { |
| 140 | pit_latch_count(s); |
| 141 | } |
| 142 | if (!(val & 0x10) && !s->status_latched) { |
| 143 | /* status latch */ |
| 144 | /* XXX: add BCD and null count */ |
Jan Kiszka | 4aa5d28 | 2012-02-01 20:31:43 +0100 | [diff] [blame] | 145 | s->status = |
| 146 | (pit_get_out(s, |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 147 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) << 7) | |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 148 | (s->rw_mode << 4) | |
| 149 | (s->mode << 1) | |
| 150 | s->bcd; |
| 151 | s->status_latched = 1; |
| 152 | } |
| 153 | } |
| 154 | } |
| 155 | } else { |
| 156 | s = &pit->channels[channel]; |
| 157 | access = (val >> 4) & 3; |
| 158 | if (access == 0) { |
| 159 | pit_latch_count(s); |
| 160 | } else { |
| 161 | s->rw_mode = access; |
| 162 | s->read_state = access; |
| 163 | s->write_state = access; |
| 164 | |
| 165 | s->mode = (val >> 1) & 7; |
| 166 | s->bcd = val & 1; |
| 167 | /* XXX: update irq timer ? */ |
| 168 | } |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 169 | } |
| 170 | } else { |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 171 | s = &pit->channels[addr]; |
| 172 | switch(s->write_state) { |
| 173 | default: |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 174 | case RW_STATE_LSB: |
| 175 | pit_load_count(s, val); |
| 176 | break; |
| 177 | case RW_STATE_MSB: |
| 178 | pit_load_count(s, val << 8); |
| 179 | break; |
| 180 | case RW_STATE_WORD0: |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 181 | s->write_latch = val; |
| 182 | s->write_state = RW_STATE_WORD1; |
| 183 | break; |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 184 | case RW_STATE_WORD1: |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 185 | pit_load_count(s, s->write_latch | (val << 8)); |
| 186 | s->write_state = RW_STATE_WORD0; |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 187 | break; |
| 188 | } |
| 189 | } |
| 190 | } |
| 191 | |
Alexander Graf | 0505bcd | 2012-10-08 13:12:31 +0200 | [diff] [blame] | 192 | static uint64_t pit_ioport_read(void *opaque, hwaddr addr, |
| 193 | unsigned size) |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 194 | { |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 195 | PITCommonState *pit = opaque; |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 196 | int ret, count; |
| 197 | PITChannelState *s; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 198 | |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 199 | addr &= 3; |
Petr Matousek | d4862a8 | 2015-06-17 12:46:11 +0200 | [diff] [blame] | 200 | |
| 201 | if (addr == 3) { |
| 202 | /* Mode/Command register is write only, read is ignored */ |
| 203 | return 0; |
| 204 | } |
| 205 | |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 206 | s = &pit->channels[addr]; |
| 207 | if (s->status_latched) { |
| 208 | s->status_latched = 0; |
| 209 | ret = s->status; |
| 210 | } else if (s->count_latched) { |
| 211 | switch(s->count_latched) { |
| 212 | default: |
| 213 | case RW_STATE_LSB: |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 214 | ret = s->latched_count & 0xff; |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 215 | s->count_latched = 0; |
| 216 | break; |
| 217 | case RW_STATE_MSB: |
| 218 | ret = s->latched_count >> 8; |
| 219 | s->count_latched = 0; |
| 220 | break; |
| 221 | case RW_STATE_WORD0: |
| 222 | ret = s->latched_count & 0xff; |
| 223 | s->count_latched = RW_STATE_MSB; |
| 224 | break; |
| 225 | } |
| 226 | } else { |
| 227 | switch(s->read_state) { |
| 228 | default: |
| 229 | case RW_STATE_LSB: |
| 230 | count = pit_get_count(s); |
| 231 | ret = count & 0xff; |
| 232 | break; |
| 233 | case RW_STATE_MSB: |
| 234 | count = pit_get_count(s); |
| 235 | ret = (count >> 8) & 0xff; |
| 236 | break; |
| 237 | case RW_STATE_WORD0: |
| 238 | count = pit_get_count(s); |
| 239 | ret = count & 0xff; |
| 240 | s->read_state = RW_STATE_WORD1; |
| 241 | break; |
| 242 | case RW_STATE_WORD1: |
| 243 | count = pit_get_count(s); |
| 244 | ret = (count >> 8) & 0xff; |
| 245 | s->read_state = RW_STATE_WORD0; |
| 246 | break; |
| 247 | } |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 248 | } |
| 249 | return ret; |
| 250 | } |
| 251 | |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 252 | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) |
| 253 | { |
| 254 | int64_t expire_time; |
| 255 | int irq_level; |
| 256 | |
Jan Kiszka | ce967e2 | 2012-02-01 20:31:41 +0100 | [diff] [blame] | 257 | if (!s->irq_timer || s->irq_disabled) { |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 258 | return; |
Jan Kiszka | ce967e2 | 2012-02-01 20:31:41 +0100 | [diff] [blame] | 259 | } |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 260 | expire_time = pit_get_next_transition_time(s, current_time); |
Jan Kiszka | 4aa5d28 | 2012-02-01 20:31:43 +0100 | [diff] [blame] | 261 | irq_level = pit_get_out(s, current_time); |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 262 | qemu_set_irq(s->irq, irq_level); |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 263 | #ifdef DEBUG_PIT |
| 264 | printf("irq_level=%d next_delay=%f\n", |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 265 | irq_level, |
Rutuja Shah | 73bcb24 | 2016-03-21 21:32:30 +0530 | [diff] [blame] | 266 | (double)(expire_time - current_time) / NANOSECONDS_PER_SECOND); |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 267 | #endif |
| 268 | s->next_transition_time = expire_time; |
| 269 | if (expire_time != -1) |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 270 | timer_mod(s->irq_timer, expire_time); |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 271 | else |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 272 | timer_del(s->irq_timer); |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 273 | } |
| 274 | |
| 275 | static void pit_irq_timer(void *opaque) |
| 276 | { |
| 277 | PITChannelState *s = opaque; |
| 278 | |
| 279 | pit_irq_timer_update(s, s->next_transition_time); |
| 280 | } |
| 281 | |
Blue Swirl | 64d7e9a | 2011-02-13 19:54:40 +0000 | [diff] [blame] | 282 | static void pit_reset(DeviceState *dev) |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 283 | { |
Andreas Färber | 3afe7e1 | 2012-11-25 18:05:53 +0100 | [diff] [blame] | 284 | PITCommonState *pit = PIT_COMMON(dev); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 285 | PITChannelState *s; |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 286 | |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 287 | pit_reset_common(pit); |
| 288 | |
| 289 | s = &pit->channels[0]; |
| 290 | if (!s->irq_disabled) { |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 291 | timer_mod(s->irq_timer, s->next_transition_time); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 292 | } |
bellard | d7d02e3 | 2004-06-20 12:58:36 +0000 | [diff] [blame] | 293 | } |
| 294 | |
Jan Kiszka | ce967e2 | 2012-02-01 20:31:41 +0100 | [diff] [blame] | 295 | /* When HPET is operating in legacy mode, suppress the ignored timer IRQ, |
| 296 | * reenable it when legacy mode is left again. */ |
| 297 | static void pit_irq_control(void *opaque, int n, int enable) |
aliguori | 16b29ae | 2008-12-17 23:28:44 +0000 | [diff] [blame] | 298 | { |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 299 | PITCommonState *pit = opaque; |
Jan Kiszka | ce967e2 | 2012-02-01 20:31:41 +0100 | [diff] [blame] | 300 | PITChannelState *s = &pit->channels[0]; |
| 301 | |
| 302 | if (enable) { |
| 303 | s->irq_disabled = 0; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 304 | pit_irq_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
Jan Kiszka | ce967e2 | 2012-02-01 20:31:41 +0100 | [diff] [blame] | 305 | } else { |
| 306 | s->irq_disabled = 1; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 307 | timer_del(s->irq_timer); |
Jan Kiszka | ce967e2 | 2012-02-01 20:31:41 +0100 | [diff] [blame] | 308 | } |
aliguori | 16b29ae | 2008-12-17 23:28:44 +0000 | [diff] [blame] | 309 | } |
| 310 | |
Richard Henderson | 60ea6aa | 2011-08-10 15:28:15 -0700 | [diff] [blame] | 311 | static const MemoryRegionOps pit_ioport_ops = { |
Alexander Graf | 0505bcd | 2012-10-08 13:12:31 +0200 | [diff] [blame] | 312 | .read = pit_ioport_read, |
| 313 | .write = pit_ioport_write, |
| 314 | .impl = { |
| 315 | .min_access_size = 1, |
| 316 | .max_access_size = 1, |
| 317 | }, |
| 318 | .endianness = DEVICE_LITTLE_ENDIAN, |
Richard Henderson | 60ea6aa | 2011-08-10 15:28:15 -0700 | [diff] [blame] | 319 | }; |
| 320 | |
Jan Kiszka | 3fbc1c0 | 2012-03-02 20:28:47 +0100 | [diff] [blame] | 321 | static void pit_post_load(PITCommonState *s) |
| 322 | { |
| 323 | PITChannelState *sc = &s->channels[0]; |
| 324 | |
| 325 | if (sc->next_transition_time != -1) { |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 326 | timer_mod(sc->irq_timer, sc->next_transition_time); |
Jan Kiszka | 3fbc1c0 | 2012-03-02 20:28:47 +0100 | [diff] [blame] | 327 | } else { |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 328 | timer_del(sc->irq_timer); |
Jan Kiszka | 3fbc1c0 | 2012-03-02 20:28:47 +0100 | [diff] [blame] | 329 | } |
| 330 | } |
| 331 | |
Markus Armbruster | a7737e4 | 2014-04-25 12:44:21 +0200 | [diff] [blame] | 332 | static void pit_realizefn(DeviceState *dev, Error **errp) |
bellard | d7d02e3 | 2004-06-20 12:58:36 +0000 | [diff] [blame] | 333 | { |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 334 | PITCommonState *pit = PIT_COMMON(dev); |
| 335 | PITClass *pc = PIT_GET_CLASS(dev); |
bellard | d7d02e3 | 2004-06-20 12:58:36 +0000 | [diff] [blame] | 336 | PITChannelState *s; |
| 337 | |
| 338 | s = &pit->channels[0]; |
| 339 | /* the timer 0 is connected to an IRQ */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 340 | s->irq_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pit_irq_timer, s); |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 341 | qdev_init_gpio_out(dev, &s->irq, 1); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 342 | |
Paolo Bonzini | 853dca1 | 2013-06-06 21:25:08 -0400 | [diff] [blame] | 343 | memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops, |
| 344 | pit, "pit", 4); |
bellard | d7d02e3 | 2004-06-20 12:58:36 +0000 | [diff] [blame] | 345 | |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 346 | qdev_init_gpio_in(dev, pit_irq_control, 1); |
Jan Kiszka | ca22a3a | 2011-03-06 16:09:49 +0100 | [diff] [blame] | 347 | |
Markus Armbruster | a7737e4 | 2014-04-25 12:44:21 +0200 | [diff] [blame] | 348 | pc->parent_realize(dev, errp); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 349 | } |
Blue Swirl | 64d7e9a | 2011-02-13 19:54:40 +0000 | [diff] [blame] | 350 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 351 | static Property pit_properties[] = { |
Paolo Bonzini | c7bcc85 | 2014-02-08 11:01:53 +0100 | [diff] [blame] | 352 | DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1), |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 353 | DEFINE_PROP_END_OF_LIST(), |
| 354 | }; |
| 355 | |
Anthony Liguori | 8f04ee0 | 2011-12-04 11:52:49 -0600 | [diff] [blame] | 356 | static void pit_class_initfn(ObjectClass *klass, void *data) |
| 357 | { |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 358 | PITClass *pc = PIT_CLASS(klass); |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 359 | PITCommonClass *k = PIT_COMMON_CLASS(klass); |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 360 | DeviceClass *dc = DEVICE_CLASS(klass); |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 361 | |
Philippe Mathieu-Daudé | bf85388 | 2018-01-13 23:04:12 -0300 | [diff] [blame] | 362 | device_class_set_parent_realize(dc, pit_realizefn, &pc->parent_realize); |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 363 | k->set_channel_gate = pit_set_channel_gate; |
| 364 | k->get_channel_info = pit_get_channel_info_common; |
Jan Kiszka | 3fbc1c0 | 2012-03-02 20:28:47 +0100 | [diff] [blame] | 365 | k->post_load = pit_post_load; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 366 | dc->reset = pit_reset; |
Marc-André Lureau | 4f67d30 | 2020-01-10 19:30:32 +0400 | [diff] [blame] | 367 | device_class_set_props(dc, pit_properties); |
Anthony Liguori | 8f04ee0 | 2011-12-04 11:52:49 -0600 | [diff] [blame] | 368 | } |
| 369 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 370 | static const TypeInfo pit_info = { |
Andreas Färber | 3afe7e1 | 2012-11-25 18:05:53 +0100 | [diff] [blame] | 371 | .name = TYPE_I8254, |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 372 | .parent = TYPE_PIT_COMMON, |
| 373 | .instance_size = sizeof(PITCommonState), |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 374 | .class_init = pit_class_initfn, |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 375 | .class_size = sizeof(PITClass), |
Blue Swirl | 64d7e9a | 2011-02-13 19:54:40 +0000 | [diff] [blame] | 376 | }; |
| 377 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 378 | static void pit_register_types(void) |
Blue Swirl | 64d7e9a | 2011-02-13 19:54:40 +0000 | [diff] [blame] | 379 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 380 | type_register_static(&pit_info); |
Blue Swirl | 64d7e9a | 2011-02-13 19:54:40 +0000 | [diff] [blame] | 381 | } |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 382 | |
| 383 | type_init(pit_register_types) |