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bellardc896fe22008-02-01 10:05:41 +00001/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Richard Henderson951c6302014-09-19 11:39:20 -070024
bellardc896fe22008-02-01 10:05:41 +000025#include "tcg.h"
Richard Henderson944eea92014-04-07 23:08:47 -070026#include "exec/helper-proto.h"
Richard Hendersonc0172302014-04-07 23:36:08 -070027#include "exec/helper-gen.h"
28
Richard Henderson951c6302014-09-19 11:39:20 -070029/* Basic output routines. Not for general consumption. */
bellardc896fe22008-02-01 10:05:41 +000030
Richard Henderson951c6302014-09-19 11:39:20 -070031void tcg_gen_op1(TCGContext *, TCGOpcode, TCGArg);
32void tcg_gen_op2(TCGContext *, TCGOpcode, TCGArg, TCGArg);
33void tcg_gen_op3(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg);
34void tcg_gen_op4(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
35void tcg_gen_op5(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg,
36 TCGArg, TCGArg);
37void tcg_gen_op6(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg,
38 TCGArg, TCGArg, TCGArg);
39
40
41static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
Richard Henderson212c3282012-10-02 11:32:28 -070042{
Richard Henderson951c6302014-09-19 11:39:20 -070043 tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I32(a1));
Richard Henderson212c3282012-10-02 11:32:28 -070044}
45
Richard Henderson951c6302014-09-19 11:39:20 -070046static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
pbrookac56dd42008-02-03 19:56:33 +000047{
Richard Henderson951c6302014-09-19 11:39:20 -070048 tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I64(a1));
pbrooka7812ae2008-11-17 14:43:54 +000049}
50
Richard Henderson951c6302014-09-19 11:39:20 -070051static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
pbrooka7812ae2008-11-17 14:43:54 +000052{
Richard Henderson951c6302014-09-19 11:39:20 -070053 tcg_gen_op1(&tcg_ctx, opc, a1);
pbrookac56dd42008-02-03 19:56:33 +000054}
55
Richard Henderson951c6302014-09-19 11:39:20 -070056static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
bellardc896fe22008-02-01 10:05:41 +000057{
Richard Henderson951c6302014-09-19 11:39:20 -070058 tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2));
bellardc896fe22008-02-01 10:05:41 +000059}
60
Richard Henderson951c6302014-09-19 11:39:20 -070061static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
bellardc896fe22008-02-01 10:05:41 +000062{
Richard Henderson951c6302014-09-19 11:39:20 -070063 tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2));
pbrookac56dd42008-02-03 19:56:33 +000064}
65
Richard Henderson951c6302014-09-19 11:39:20 -070066static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
pbrookac56dd42008-02-03 19:56:33 +000067{
Richard Henderson951c6302014-09-19 11:39:20 -070068 tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), a2);
pbrooka7812ae2008-11-17 14:43:54 +000069}
70
Richard Henderson951c6302014-09-19 11:39:20 -070071static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
pbrooka7812ae2008-11-17 14:43:54 +000072{
Richard Henderson951c6302014-09-19 11:39:20 -070073 tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), a2);
pbrooka7812ae2008-11-17 14:43:54 +000074}
75
Richard Henderson951c6302014-09-19 11:39:20 -070076static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
pbrooka7812ae2008-11-17 14:43:54 +000077{
Richard Henderson951c6302014-09-19 11:39:20 -070078 tcg_gen_op2(&tcg_ctx, opc, a1, a2);
bellardc896fe22008-02-01 10:05:41 +000079}
80
Richard Henderson951c6302014-09-19 11:39:20 -070081static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
82 TCGv_i32 a2, TCGv_i32 a3)
pbrookbcb01262008-05-24 02:24:25 +000083{
Richard Henderson951c6302014-09-19 11:39:20 -070084 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1),
85 GET_TCGV_I32(a2), GET_TCGV_I32(a3));
pbrookbcb01262008-05-24 02:24:25 +000086}
87
Richard Henderson951c6302014-09-19 11:39:20 -070088static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
89 TCGv_i64 a2, TCGv_i64 a3)
bellardc896fe22008-02-01 10:05:41 +000090{
Richard Henderson951c6302014-09-19 11:39:20 -070091 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1),
92 GET_TCGV_I64(a2), GET_TCGV_I64(a3));
pbrookac56dd42008-02-03 19:56:33 +000093}
94
Richard Henderson951c6302014-09-19 11:39:20 -070095static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
96 TCGv_i32 a2, TCGArg a3)
pbrookac56dd42008-02-03 19:56:33 +000097{
Richard Henderson951c6302014-09-19 11:39:20 -070098 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3);
pbrooka7812ae2008-11-17 14:43:54 +000099}
100
Richard Henderson951c6302014-09-19 11:39:20 -0700101static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
102 TCGv_i64 a2, TCGArg a3)
pbrooka7812ae2008-11-17 14:43:54 +0000103{
Richard Henderson951c6302014-09-19 11:39:20 -0700104 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3);
pbrookac56dd42008-02-03 19:56:33 +0000105}
106
Richard Hendersona9751602010-03-19 11:12:29 -0700107static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
108 TCGv_ptr base, TCGArg offset)
pbrookac56dd42008-02-03 19:56:33 +0000109{
Richard Henderson951c6302014-09-19 11:39:20 -0700110 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset);
pbrooka7812ae2008-11-17 14:43:54 +0000111}
112
Richard Hendersona9751602010-03-19 11:12:29 -0700113static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
114 TCGv_ptr base, TCGArg offset)
pbrooka7812ae2008-11-17 14:43:54 +0000115{
Richard Henderson951c6302014-09-19 11:39:20 -0700116 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset);
pbrooka7812ae2008-11-17 14:43:54 +0000117}
118
Richard Henderson951c6302014-09-19 11:39:20 -0700119static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
120 TCGv_i32 a3, TCGv_i32 a4)
pbrooka7812ae2008-11-17 14:43:54 +0000121{
Richard Henderson951c6302014-09-19 11:39:20 -0700122 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
123 GET_TCGV_I32(a3), GET_TCGV_I32(a4));
pbrooka7812ae2008-11-17 14:43:54 +0000124}
125
Richard Henderson951c6302014-09-19 11:39:20 -0700126static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
127 TCGv_i64 a3, TCGv_i64 a4)
pbrooka7812ae2008-11-17 14:43:54 +0000128{
Richard Henderson951c6302014-09-19 11:39:20 -0700129 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
130 GET_TCGV_I64(a3), GET_TCGV_I64(a4));
pbrooka7812ae2008-11-17 14:43:54 +0000131}
132
Richard Henderson951c6302014-09-19 11:39:20 -0700133static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
134 TCGv_i32 a3, TCGArg a4)
pbrooka7812ae2008-11-17 14:43:54 +0000135{
Richard Henderson951c6302014-09-19 11:39:20 -0700136 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
137 GET_TCGV_I32(a3), a4);
pbrookac56dd42008-02-03 19:56:33 +0000138}
139
Richard Henderson951c6302014-09-19 11:39:20 -0700140static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
141 TCGv_i64 a3, TCGArg a4)
pbrookac56dd42008-02-03 19:56:33 +0000142{
Richard Henderson951c6302014-09-19 11:39:20 -0700143 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
144 GET_TCGV_I64(a3), a4);
pbrooka7812ae2008-11-17 14:43:54 +0000145}
146
Richard Henderson951c6302014-09-19 11:39:20 -0700147static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
148 TCGArg a3, TCGArg a4)
pbrooka7812ae2008-11-17 14:43:54 +0000149{
Richard Henderson951c6302014-09-19 11:39:20 -0700150 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4);
bellardc896fe22008-02-01 10:05:41 +0000151}
152
Richard Henderson951c6302014-09-19 11:39:20 -0700153static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
154 TCGArg a3, TCGArg a4)
bellardc896fe22008-02-01 10:05:41 +0000155{
Richard Henderson951c6302014-09-19 11:39:20 -0700156 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4);
pbrookac56dd42008-02-03 19:56:33 +0000157}
158
Richard Henderson951c6302014-09-19 11:39:20 -0700159static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
160 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
pbrookac56dd42008-02-03 19:56:33 +0000161{
Richard Henderson951c6302014-09-19 11:39:20 -0700162 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
163 GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5));
pbrooka7812ae2008-11-17 14:43:54 +0000164}
165
Richard Henderson951c6302014-09-19 11:39:20 -0700166static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
167 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
pbrooka7812ae2008-11-17 14:43:54 +0000168{
Richard Henderson951c6302014-09-19 11:39:20 -0700169 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
170 GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5));
pbrooka7812ae2008-11-17 14:43:54 +0000171}
172
Richard Henderson951c6302014-09-19 11:39:20 -0700173static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
174 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
pbrooka7812ae2008-11-17 14:43:54 +0000175{
Richard Henderson951c6302014-09-19 11:39:20 -0700176 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
177 GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5);
bellardc896fe22008-02-01 10:05:41 +0000178}
179
Richard Henderson951c6302014-09-19 11:39:20 -0700180static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
181 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
bellardc896fe22008-02-01 10:05:41 +0000182{
Richard Henderson951c6302014-09-19 11:39:20 -0700183 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
184 GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5);
pbrookac56dd42008-02-03 19:56:33 +0000185}
186
Richard Henderson951c6302014-09-19 11:39:20 -0700187static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
188 TCGv_i32 a3, TCGArg a4, TCGArg a5)
Richard Hendersonb7767f02011-01-10 19:23:42 -0800189{
Richard Henderson951c6302014-09-19 11:39:20 -0700190 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
191 GET_TCGV_I32(a3), a4, a5);
Richard Hendersonb7767f02011-01-10 19:23:42 -0800192}
193
Richard Henderson951c6302014-09-19 11:39:20 -0700194static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
195 TCGv_i64 a3, TCGArg a4, TCGArg a5)
Richard Hendersonb7767f02011-01-10 19:23:42 -0800196{
Richard Henderson951c6302014-09-19 11:39:20 -0700197 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
198 GET_TCGV_I64(a3), a4, a5);
Richard Hendersonb7767f02011-01-10 19:23:42 -0800199}
200
Richard Henderson951c6302014-09-19 11:39:20 -0700201static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
202 TCGv_i32 a3, TCGv_i32 a4,
203 TCGv_i32 a5, TCGv_i32 a6)
pbrookac56dd42008-02-03 19:56:33 +0000204{
Richard Henderson951c6302014-09-19 11:39:20 -0700205 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
206 GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5),
207 GET_TCGV_I32(a6));
pbrooka7812ae2008-11-17 14:43:54 +0000208}
209
Richard Henderson951c6302014-09-19 11:39:20 -0700210static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
211 TCGv_i64 a3, TCGv_i64 a4,
212 TCGv_i64 a5, TCGv_i64 a6)
pbrooka7812ae2008-11-17 14:43:54 +0000213{
Richard Henderson951c6302014-09-19 11:39:20 -0700214 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
215 GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5),
216 GET_TCGV_I64(a6));
pbrooka7812ae2008-11-17 14:43:54 +0000217}
218
Richard Henderson951c6302014-09-19 11:39:20 -0700219static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
220 TCGv_i32 a3, TCGv_i32 a4,
221 TCGv_i32 a5, TCGArg a6)
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800222{
Richard Henderson951c6302014-09-19 11:39:20 -0700223 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
224 GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6);
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800225}
226
Richard Henderson951c6302014-09-19 11:39:20 -0700227static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
228 TCGv_i64 a3, TCGv_i64 a4,
229 TCGv_i64 a5, TCGArg a6)
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800230{
Richard Henderson951c6302014-09-19 11:39:20 -0700231 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
232 GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6);
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800233}
234
Richard Henderson951c6302014-09-19 11:39:20 -0700235static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
236 TCGv_i32 a3, TCGv_i32 a4,
237 TCGArg a5, TCGArg a6)
pbrooka7812ae2008-11-17 14:43:54 +0000238{
Richard Henderson951c6302014-09-19 11:39:20 -0700239 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
240 GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6);
pbrooka7812ae2008-11-17 14:43:54 +0000241}
242
Richard Henderson951c6302014-09-19 11:39:20 -0700243static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
244 TCGv_i64 a3, TCGv_i64 a4,
245 TCGArg a5, TCGArg a6)
pbrooka7812ae2008-11-17 14:43:54 +0000246{
Richard Henderson951c6302014-09-19 11:39:20 -0700247 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
248 GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6);
bellardc896fe22008-02-01 10:05:41 +0000249}
250
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700251
Richard Henderson951c6302014-09-19 11:39:20 -0700252/* Generic ops. */
253
Richard Henderson42a268c2015-02-13 12:51:55 -0800254static inline void gen_set_label(TCGLabel *l)
bellardc896fe22008-02-01 10:05:41 +0000255{
Richard Henderson42a268c2015-02-13 12:51:55 -0800256 tcg_gen_op1(&tcg_ctx, INDEX_op_set_label, label_arg(l));
bellardc896fe22008-02-01 10:05:41 +0000257}
258
Richard Henderson42a268c2015-02-13 12:51:55 -0800259static inline void tcg_gen_br(TCGLabel *l)
blueswir1fb50d412008-03-21 17:58:45 +0000260{
Richard Henderson42a268c2015-02-13 12:51:55 -0800261 tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l));
Richard Henderson951c6302014-09-19 11:39:20 -0700262}
263
Pranith Kumarf65e19b2016-07-14 16:20:13 -0400264void tcg_gen_mb(TCGBar);
265
Richard Henderson951c6302014-09-19 11:39:20 -0700266/* Helper calls. */
267
268/* 32 bit ops */
269
270void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
271void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
272void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
273void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
274void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
275void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
276void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
277void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
278void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
279void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
280void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
281void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
282void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
283void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
284void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
285void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
286void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
287void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
288void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
Richard Henderson0e28d002016-11-16 09:23:28 +0100289void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
290void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
291void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
292void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
Richard Henderson086920c2016-11-16 17:32:48 +0100293void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
Richard Hendersona768e4e2016-11-21 11:13:39 +0100294void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);
Richard Henderson951c6302014-09-19 11:39:20 -0700295void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
296void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
297void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
298void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
299void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
300 unsigned int ofs, unsigned int len);
Richard Henderson07cc68d2016-10-17 13:21:31 -0700301void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
302 unsigned int ofs, unsigned int len);
Richard Henderson7ec8bab2016-10-14 12:04:32 -0500303void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
304 unsigned int ofs, unsigned int len);
305void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
306 unsigned int ofs, unsigned int len);
Richard Henderson42a268c2015-02-13 12:51:55 -0800307void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
308void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
Richard Henderson951c6302014-09-19 11:39:20 -0700309void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
310 TCGv_i32 arg1, TCGv_i32 arg2);
311void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
312 TCGv_i32 arg1, int32_t arg2);
313void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
314 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
315void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
316 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
317void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
318 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
319void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
320void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
Richard Henderson5087abf2016-09-27 14:23:52 -0700321void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
Richard Henderson951c6302014-09-19 11:39:20 -0700322void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
323void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
324void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
325void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
326void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
327void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
328
329static inline void tcg_gen_discard_i32(TCGv_i32 arg)
330{
331 tcg_gen_op1_i32(INDEX_op_discard, arg);
blueswir1fb50d412008-03-21 17:58:45 +0000332}
333
pbrooka7812ae2008-11-17 14:43:54 +0000334static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +0000335{
Richard Henderson951c6302014-09-19 11:39:20 -0700336 if (!TCGV_EQUAL_I32(ret, arg)) {
pbrooka7812ae2008-11-17 14:43:54 +0000337 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
Richard Henderson951c6302014-09-19 11:39:20 -0700338 }
bellardc896fe22008-02-01 10:05:41 +0000339}
340
pbrooka7812ae2008-11-17 14:43:54 +0000341static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
bellardc896fe22008-02-01 10:05:41 +0000342{
pbrooka7812ae2008-11-17 14:43:54 +0000343 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
bellardc896fe22008-02-01 10:05:41 +0000344}
345
Richard Henderson951c6302014-09-19 11:39:20 -0700346static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
347 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000348{
pbrooka7812ae2008-11-17 14:43:54 +0000349 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000350}
351
Richard Henderson951c6302014-09-19 11:39:20 -0700352static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
353 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000354{
pbrooka7812ae2008-11-17 14:43:54 +0000355 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000356}
357
Richard Henderson951c6302014-09-19 11:39:20 -0700358static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
359 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000360{
pbrooka7812ae2008-11-17 14:43:54 +0000361 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000362}
363
Richard Henderson951c6302014-09-19 11:39:20 -0700364static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
365 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000366{
pbrooka7812ae2008-11-17 14:43:54 +0000367 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000368}
369
Richard Henderson951c6302014-09-19 11:39:20 -0700370static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
371 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000372{
pbrooka7812ae2008-11-17 14:43:54 +0000373 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000374}
375
Richard Henderson951c6302014-09-19 11:39:20 -0700376static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
377 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000378{
pbrooka7812ae2008-11-17 14:43:54 +0000379 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000380}
381
Richard Henderson951c6302014-09-19 11:39:20 -0700382static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
383 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000384{
pbrooka7812ae2008-11-17 14:43:54 +0000385 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000386}
387
Richard Henderson951c6302014-09-19 11:39:20 -0700388static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
389 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000390{
pbrooka7812ae2008-11-17 14:43:54 +0000391 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000392}
393
pbrooka7812ae2008-11-17 14:43:54 +0000394static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000395{
pbrooka7812ae2008-11-17 14:43:54 +0000396 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000397}
398
pbrooka7812ae2008-11-17 14:43:54 +0000399static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000400{
pbrooka7812ae2008-11-17 14:43:54 +0000401 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000402}
403
pbrooka7812ae2008-11-17 14:43:54 +0000404static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000405{
Richard Henderson951c6302014-09-19 11:39:20 -0700406 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000407}
408
pbrooka7812ae2008-11-17 14:43:54 +0000409static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000410{
Richard Henderson951c6302014-09-19 11:39:20 -0700411 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000412}
413
pbrooka7812ae2008-11-17 14:43:54 +0000414static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000415{
Richard Henderson951c6302014-09-19 11:39:20 -0700416 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000417}
418
pbrooka7812ae2008-11-17 14:43:54 +0000419static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000420{
pbrooka7812ae2008-11-17 14:43:54 +0000421 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000422}
423
pbrooka7812ae2008-11-17 14:43:54 +0000424static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000425{
pbrooka7812ae2008-11-17 14:43:54 +0000426 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000427}
428
pbrooka7812ae2008-11-17 14:43:54 +0000429static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000430{
pbrooka7812ae2008-11-17 14:43:54 +0000431 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000432}
433
pbrooka7812ae2008-11-17 14:43:54 +0000434static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000435{
pbrooka7812ae2008-11-17 14:43:54 +0000436 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000437}
438
Richard Henderson951c6302014-09-19 11:39:20 -0700439static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
thsf730fd22008-05-04 08:14:08 +0000440{
Richard Henderson951c6302014-09-19 11:39:20 -0700441 if (TCG_TARGET_HAS_neg_i32) {
442 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700443 } else {
Richard Henderson951c6302014-09-19 11:39:20 -0700444 tcg_gen_subfi_i32(ret, 0, arg);
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700445 }
bellardc896fe22008-02-01 10:05:41 +0000446}
447
Richard Henderson951c6302014-09-19 11:39:20 -0700448static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +0000449{
Richard Henderson951c6302014-09-19 11:39:20 -0700450 if (TCG_TARGET_HAS_not_i32) {
451 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700452 } else {
Richard Henderson951c6302014-09-19 11:39:20 -0700453 tcg_gen_xori_i32(ret, arg, -1);
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700454 }
bellardc896fe22008-02-01 10:05:41 +0000455}
456
Richard Henderson951c6302014-09-19 11:39:20 -0700457/* 64 bit ops */
bellardc896fe22008-02-01 10:05:41 +0000458
Richard Henderson951c6302014-09-19 11:39:20 -0700459void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
460void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
461void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
462void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
463void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
464void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
465void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
466void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
467void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
468void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
469void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
470void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
471void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
472void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
473void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
474void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
475void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
476void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
477void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
Richard Henderson0e28d002016-11-16 09:23:28 +0100478void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
479void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
480void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
481void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
Richard Henderson086920c2016-11-16 17:32:48 +0100482void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
Richard Hendersona768e4e2016-11-21 11:13:39 +0100483void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);
Richard Henderson951c6302014-09-19 11:39:20 -0700484void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
485void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
486void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
487void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
488void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
489 unsigned int ofs, unsigned int len);
Richard Henderson07cc68d2016-10-17 13:21:31 -0700490void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
491 unsigned int ofs, unsigned int len);
Richard Henderson7ec8bab2016-10-14 12:04:32 -0500492void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
493 unsigned int ofs, unsigned int len);
494void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
495 unsigned int ofs, unsigned int len);
Richard Henderson42a268c2015-02-13 12:51:55 -0800496void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
497void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
Richard Henderson951c6302014-09-19 11:39:20 -0700498void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
499 TCGv_i64 arg1, TCGv_i64 arg2);
500void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
501 TCGv_i64 arg1, int64_t arg2);
502void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
503 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
504void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
505 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
506void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
507 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
508void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
509void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
Richard Henderson5087abf2016-09-27 14:23:52 -0700510void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
Richard Henderson951c6302014-09-19 11:39:20 -0700511void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
512void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
513void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
514void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
515void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
516void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
517void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
518void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
519void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
520void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
bellardc896fe22008-02-01 10:05:41 +0000521
Richard Henderson951c6302014-09-19 11:39:20 -0700522#if TCG_TARGET_REG_BITS == 64
523static inline void tcg_gen_discard_i64(TCGv_i64 arg)
524{
525 tcg_gen_op1_i64(INDEX_op_discard, arg);
526}
bellardc896fe22008-02-01 10:05:41 +0000527
pbrooka7812ae2008-11-17 14:43:54 +0000528static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +0000529{
aurel32fe75bcf2009-03-10 08:57:16 +0000530 if (!TCGV_EQUAL_I64(ret, arg)) {
pbrooka7812ae2008-11-17 14:43:54 +0000531 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
Richard Henderson951c6302014-09-19 11:39:20 -0700532 }
bellardc896fe22008-02-01 10:05:41 +0000533}
534
pbrooka7812ae2008-11-17 14:43:54 +0000535static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
bellardc896fe22008-02-01 10:05:41 +0000536{
pbrooka7812ae2008-11-17 14:43:54 +0000537 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
bellardc896fe22008-02-01 10:05:41 +0000538}
539
Peter Maydell6bd4b082011-05-27 13:12:12 +0100540static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000541 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000542{
pbrooka7812ae2008-11-17 14:43:54 +0000543 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000544}
545
Peter Maydell6bd4b082011-05-27 13:12:12 +0100546static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000547 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000548{
pbrooka7812ae2008-11-17 14:43:54 +0000549 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000550}
551
Peter Maydell6bd4b082011-05-27 13:12:12 +0100552static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000553 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000554{
pbrooka7812ae2008-11-17 14:43:54 +0000555 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000556}
557
Peter Maydell6bd4b082011-05-27 13:12:12 +0100558static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000559 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000560{
pbrooka7812ae2008-11-17 14:43:54 +0000561 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000562}
563
Peter Maydell6bd4b082011-05-27 13:12:12 +0100564static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000565 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000566{
pbrooka7812ae2008-11-17 14:43:54 +0000567 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000568}
569
Peter Maydell6bd4b082011-05-27 13:12:12 +0100570static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000571 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000572{
pbrooka7812ae2008-11-17 14:43:54 +0000573 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000574}
575
Richard Henderson951c6302014-09-19 11:39:20 -0700576static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
577 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000578{
pbrooka7812ae2008-11-17 14:43:54 +0000579 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000580}
581
Peter Maydell6bd4b082011-05-27 13:12:12 +0100582static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000583 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000584{
pbrooka7812ae2008-11-17 14:43:54 +0000585 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000586}
587
Peter Maydell6bd4b082011-05-27 13:12:12 +0100588static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000589 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000590{
pbrooka7812ae2008-11-17 14:43:54 +0000591 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000592}
593
Peter Maydell6bd4b082011-05-27 13:12:12 +0100594static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000595 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000596{
pbrooka7812ae2008-11-17 14:43:54 +0000597 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000598}
599
Richard Henderson951c6302014-09-19 11:39:20 -0700600static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
601 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000602{
pbrooka7812ae2008-11-17 14:43:54 +0000603 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000604}
605
pbrooka7812ae2008-11-17 14:43:54 +0000606static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000607{
pbrooka7812ae2008-11-17 14:43:54 +0000608 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000609}
610
pbrooka7812ae2008-11-17 14:43:54 +0000611static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000612{
pbrooka7812ae2008-11-17 14:43:54 +0000613 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000614}
615
pbrooka7812ae2008-11-17 14:43:54 +0000616static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000617{
Richard Henderson951c6302014-09-19 11:39:20 -0700618 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000619}
620
pbrooka7812ae2008-11-17 14:43:54 +0000621static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000622{
Richard Henderson951c6302014-09-19 11:39:20 -0700623 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000624}
625
pbrooka7812ae2008-11-17 14:43:54 +0000626static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000627{
Richard Henderson951c6302014-09-19 11:39:20 -0700628 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000629}
630
pbrooka7812ae2008-11-17 14:43:54 +0000631static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000632{
pbrooka7812ae2008-11-17 14:43:54 +0000633 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000634}
635
pbrooka7812ae2008-11-17 14:43:54 +0000636static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000637{
pbrooka7812ae2008-11-17 14:43:54 +0000638 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000639}
640
pbrooka7812ae2008-11-17 14:43:54 +0000641static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000642{
pbrooka7812ae2008-11-17 14:43:54 +0000643 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000644}
645
pbrooka7812ae2008-11-17 14:43:54 +0000646static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000647{
pbrooka7812ae2008-11-17 14:43:54 +0000648 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000649}
Richard Henderson951c6302014-09-19 11:39:20 -0700650#else /* TCG_TARGET_REG_BITS == 32 */
651static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
652 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000653{
Richard Henderson951c6302014-09-19 11:39:20 -0700654 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000655}
656
Richard Henderson951c6302014-09-19 11:39:20 -0700657static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
658 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000659{
Richard Henderson951c6302014-09-19 11:39:20 -0700660 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000661}
662
Richard Henderson951c6302014-09-19 11:39:20 -0700663static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
664 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000665{
Richard Henderson951c6302014-09-19 11:39:20 -0700666 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000667}
668
Richard Henderson951c6302014-09-19 11:39:20 -0700669static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000670{
Richard Henderson951c6302014-09-19 11:39:20 -0700671 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
672 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
aurel3263597062008-11-02 08:22:54 +0000673}
674
Richard Henderson951c6302014-09-19 11:39:20 -0700675static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
aurel3200457342008-11-02 08:23:04 +0000676{
Richard Henderson951c6302014-09-19 11:39:20 -0700677 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
678 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
aurel3200457342008-11-02 08:23:04 +0000679}
680
Richard Henderson951c6302014-09-19 11:39:20 -0700681void tcg_gen_discard_i64(TCGv_i64 arg);
682void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
683void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
684void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
685void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
686void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
687void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
688void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
689void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
690void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
691void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
692void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
693void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
694void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
695void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
696void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
697void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
698void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
699#endif /* TCG_TARGET_REG_BITS */
pbrook390efc52008-05-11 14:35:37 +0000700
pbrooka7812ae2008-11-17 14:43:54 +0000701static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
pbrook390efc52008-05-11 14:35:37 +0000702{
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700703 if (TCG_TARGET_HAS_neg_i64) {
704 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
705 } else {
Richard Henderson951c6302014-09-19 11:39:20 -0700706 tcg_gen_subfi_i64(ret, 0, arg);
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700707 }
pbrook390efc52008-05-11 14:35:37 +0000708}
709
Richard Henderson951c6302014-09-19 11:39:20 -0700710/* Size changing operations. */
711
712void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
713void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
714void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
Richard Henderson609ad702015-07-24 07:16:00 -0700715void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
716void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
Richard Henderson951c6302014-09-19 11:39:20 -0700717void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
718void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
719
720static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
bellard0b6ce4c2008-05-17 12:40:44 +0000721{
Richard Henderson951c6302014-09-19 11:39:20 -0700722 tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
Richard Henderson77276f62012-09-21 17:18:13 -0700723}
724
Richard Henderson951c6302014-09-19 11:39:20 -0700725/* QEMU specific operations. */
Richard Henderson3c51a982013-02-19 23:51:54 -0800726
bellardc896fe22008-02-01 10:05:41 +0000727#ifndef TARGET_LONG_BITS
728#error must include QEMU headers
729#endif
730
Richard Henderson9aef40e2015-08-30 09:21:33 -0700731#if TARGET_INSN_START_WORDS == 1
732# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
733static inline void tcg_gen_insn_start(target_ulong pc)
Richard Henderson951c6302014-09-19 11:39:20 -0700734{
Richard Henderson9aef40e2015-08-30 09:21:33 -0700735 tcg_gen_op1(&tcg_ctx, INDEX_op_insn_start, pc);
Richard Henderson951c6302014-09-19 11:39:20 -0700736}
Richard Henderson9aef40e2015-08-30 09:21:33 -0700737# else
738static inline void tcg_gen_insn_start(target_ulong pc)
739{
740 tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start,
741 (uint32_t)pc, (uint32_t)(pc >> 32));
742}
743# endif
744#elif TARGET_INSN_START_WORDS == 2
745# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
746static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
747{
748 tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, pc, a1);
749}
750# else
751static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
752{
753 tcg_gen_op4(&tcg_ctx, INDEX_op_insn_start,
754 (uint32_t)pc, (uint32_t)(pc >> 32),
755 (uint32_t)a1, (uint32_t)(a1 >> 32));
756}
757# endif
758#elif TARGET_INSN_START_WORDS == 3
759# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
760static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
761 target_ulong a2)
762{
763 tcg_gen_op3(&tcg_ctx, INDEX_op_insn_start, pc, a1, a2);
764}
765# else
766static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
767 target_ulong a2)
768{
769 tcg_gen_op6(&tcg_ctx, INDEX_op_insn_start,
770 (uint32_t)pc, (uint32_t)(pc >> 32),
771 (uint32_t)a1, (uint32_t)(a1 >> 32),
772 (uint32_t)a2, (uint32_t)(a2 >> 32));
773}
774# endif
775#else
776# error "Unhandled number of operands to insn_start"
777#endif
Richard Henderson951c6302014-09-19 11:39:20 -0700778
779static inline void tcg_gen_exit_tb(uintptr_t val)
780{
781 tcg_gen_op1i(INDEX_op_exit_tb, val);
782}
783
Sergey Fedorov5b053a42016-04-08 19:48:12 +0300784/**
785 * tcg_gen_goto_tb() - output goto_tb TCG operation
786 * @idx: Direct jump slot index (0 or 1)
787 *
788 * See tcg/README for more info about this TCG operation.
789 *
Sergey Fedorov90aa39a2016-04-09 01:00:23 +0300790 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
791 * the pages this TB resides in because we don't take care of direct jumps when
792 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
793 * static address translation, so the destination address is always valid, TBs
794 * are always invalidated properly, and direct jumps are reset when mapping
795 * changes.
Sergey Fedorov5b053a42016-04-08 19:48:12 +0300796 */
Richard Henderson951c6302014-09-19 11:39:20 -0700797void tcg_gen_goto_tb(unsigned idx);
798
Emilio G. Cotacedbcb02017-04-26 23:29:14 -0400799/**
Emilio G. Cota7f116362017-07-11 17:06:48 -0400800 * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid
Emilio G. Cotacedbcb02017-04-26 23:29:14 -0400801 * @addr: Guest address of the target TB
802 *
803 * If the TB is not valid, jump to the epilogue.
804 *
805 * This operation is optional. If the TCG backend does not implement goto_ptr,
806 * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument.
807 */
Emilio G. Cota7f116362017-07-11 17:06:48 -0400808void tcg_gen_lookup_and_goto_ptr(void);
Emilio G. Cotacedbcb02017-04-26 23:29:14 -0400809
pbrooka7812ae2008-11-17 14:43:54 +0000810#if TARGET_LONG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +0000811#define tcg_temp_new() tcg_temp_new_i32()
812#define tcg_global_reg_new tcg_global_reg_new_i32
813#define tcg_global_mem_new tcg_global_mem_new_i32
aurel32df9247b2009-01-01 14:09:05 +0000814#define tcg_temp_local_new() tcg_temp_local_new_i32()
pbrooka7812ae2008-11-17 14:43:54 +0000815#define tcg_temp_free tcg_temp_free_i32
pbrooka7812ae2008-11-17 14:43:54 +0000816#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
Richard Hendersonafcb92b2012-12-07 15:07:17 -0600817#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x)
aurel32fe75bcf2009-03-10 08:57:16 +0000818#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700819#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
820#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
pbrooka7812ae2008-11-17 14:43:54 +0000821#else
pbrooka7812ae2008-11-17 14:43:54 +0000822#define tcg_temp_new() tcg_temp_new_i64()
823#define tcg_global_reg_new tcg_global_reg_new_i64
824#define tcg_global_mem_new tcg_global_mem_new_i64
aurel32df9247b2009-01-01 14:09:05 +0000825#define tcg_temp_local_new() tcg_temp_local_new_i64()
pbrooka7812ae2008-11-17 14:43:54 +0000826#define tcg_temp_free tcg_temp_free_i64
pbrooka7812ae2008-11-17 14:43:54 +0000827#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
Richard Hendersonafcb92b2012-12-07 15:07:17 -0600828#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x)
aurel32fe75bcf2009-03-10 08:57:16 +0000829#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700830#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
831#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
pbrooka7812ae2008-11-17 14:43:54 +0000832#endif
833
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700834void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
835void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
836void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
837void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
838
pbrookac56dd42008-02-03 19:56:33 +0000839static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000840{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700841 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
bellardc896fe22008-02-01 10:05:41 +0000842}
843
pbrookac56dd42008-02-03 19:56:33 +0000844static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000845{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700846 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
bellardc896fe22008-02-01 10:05:41 +0000847}
848
pbrookac56dd42008-02-03 19:56:33 +0000849static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000850{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700851 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
bellardc896fe22008-02-01 10:05:41 +0000852}
853
pbrookac56dd42008-02-03 19:56:33 +0000854static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000855{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700856 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
bellardc896fe22008-02-01 10:05:41 +0000857}
858
pbrookac56dd42008-02-03 19:56:33 +0000859static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000860{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700861 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
bellardc896fe22008-02-01 10:05:41 +0000862}
863
pbrookac56dd42008-02-03 19:56:33 +0000864static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000865{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700866 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
bellardc896fe22008-02-01 10:05:41 +0000867}
868
pbrooka7812ae2008-11-17 14:43:54 +0000869static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000870{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700871 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ);
bellardc896fe22008-02-01 10:05:41 +0000872}
873
pbrookac56dd42008-02-03 19:56:33 +0000874static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000875{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700876 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
bellardc896fe22008-02-01 10:05:41 +0000877}
878
pbrookac56dd42008-02-03 19:56:33 +0000879static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000880{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700881 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
bellardc896fe22008-02-01 10:05:41 +0000882}
883
pbrookac56dd42008-02-03 19:56:33 +0000884static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000885{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700886 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
bellardc896fe22008-02-01 10:05:41 +0000887}
888
pbrooka7812ae2008-11-17 14:43:54 +0000889static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000890{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700891 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
bellardc896fe22008-02-01 10:05:41 +0000892}
893
Richard Hendersonc482cb12016-06-28 11:37:27 -0700894void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
895 TCGArg, TCGMemOp);
896void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
897 TCGArg, TCGMemOp);
898
899void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
900void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
901void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
902void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
903void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
904void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
905void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
906void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
907void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
908void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
909void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
910void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
911void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
912void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
913void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
914void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
915void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
916void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
917
blueswir1f8422f52008-02-24 07:45:43 +0000918#if TARGET_LONG_BITS == 64
blueswir1f8422f52008-02-24 07:45:43 +0000919#define tcg_gen_movi_tl tcg_gen_movi_i64
920#define tcg_gen_mov_tl tcg_gen_mov_i64
921#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
922#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
923#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
924#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
925#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
926#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
927#define tcg_gen_ld_tl tcg_gen_ld_i64
928#define tcg_gen_st8_tl tcg_gen_st8_i64
929#define tcg_gen_st16_tl tcg_gen_st16_i64
930#define tcg_gen_st32_tl tcg_gen_st32_i64
931#define tcg_gen_st_tl tcg_gen_st_i64
932#define tcg_gen_add_tl tcg_gen_add_i64
933#define tcg_gen_addi_tl tcg_gen_addi_i64
934#define tcg_gen_sub_tl tcg_gen_sub_i64
pbrook390efc52008-05-11 14:35:37 +0000935#define tcg_gen_neg_tl tcg_gen_neg_i64
pbrook10460c82008-11-02 13:26:16 +0000936#define tcg_gen_subfi_tl tcg_gen_subfi_i64
blueswir1f8422f52008-02-24 07:45:43 +0000937#define tcg_gen_subi_tl tcg_gen_subi_i64
938#define tcg_gen_and_tl tcg_gen_and_i64
939#define tcg_gen_andi_tl tcg_gen_andi_i64
940#define tcg_gen_or_tl tcg_gen_or_i64
941#define tcg_gen_ori_tl tcg_gen_ori_i64
942#define tcg_gen_xor_tl tcg_gen_xor_i64
943#define tcg_gen_xori_tl tcg_gen_xori_i64
bellard0b6ce4c2008-05-17 12:40:44 +0000944#define tcg_gen_not_tl tcg_gen_not_i64
blueswir1f8422f52008-02-24 07:45:43 +0000945#define tcg_gen_shl_tl tcg_gen_shl_i64
946#define tcg_gen_shli_tl tcg_gen_shli_i64
947#define tcg_gen_shr_tl tcg_gen_shr_i64
948#define tcg_gen_shri_tl tcg_gen_shri_i64
949#define tcg_gen_sar_tl tcg_gen_sar_i64
950#define tcg_gen_sari_tl tcg_gen_sari_i64
blueswir10cf767d2008-03-02 18:20:59 +0000951#define tcg_gen_brcond_tl tcg_gen_brcond_i64
pbrookcb636692008-05-24 02:22:00 +0000952#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800953#define tcg_gen_setcond_tl tcg_gen_setcond_i64
Aurelien Jarnoadd1e7e2010-02-08 12:06:05 +0100954#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
thsf730fd22008-05-04 08:14:08 +0000955#define tcg_gen_mul_tl tcg_gen_mul_i64
956#define tcg_gen_muli_tl tcg_gen_muli_i64
aurel32ab364212009-03-29 01:19:22 +0000957#define tcg_gen_div_tl tcg_gen_div_i64
958#define tcg_gen_rem_tl tcg_gen_rem_i64
aurel32864951a2009-03-29 14:08:54 +0000959#define tcg_gen_divu_tl tcg_gen_divu_i64
960#define tcg_gen_remu_tl tcg_gen_remu_i64
blueswir1a768e4b2008-03-16 19:16:37 +0000961#define tcg_gen_discard_tl tcg_gen_discard_i64
Richard Hendersonecc7b3a2015-07-24 11:49:53 -0700962#define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
blueswir1e4290732008-03-22 08:39:04 +0000963#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
964#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
965#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
966#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
967#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
bellard0b6ce4c2008-05-17 12:40:44 +0000968#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
969#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
970#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
971#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
972#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
973#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
aurel32911d79b2009-03-13 09:35:19 +0000974#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
975#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
976#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
blueswir1945ca822008-09-21 18:32:28 +0000977#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
Richard Henderson3c51a982013-02-19 23:51:54 -0800978#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
aurel32f24cb332008-10-21 11:28:59 +0000979#define tcg_gen_andc_tl tcg_gen_andc_i64
980#define tcg_gen_eqv_tl tcg_gen_eqv_i64
981#define tcg_gen_nand_tl tcg_gen_nand_i64
982#define tcg_gen_nor_tl tcg_gen_nor_i64
983#define tcg_gen_orc_tl tcg_gen_orc_i64
Richard Henderson0e28d002016-11-16 09:23:28 +0100984#define tcg_gen_clz_tl tcg_gen_clz_i64
985#define tcg_gen_ctz_tl tcg_gen_ctz_i64
986#define tcg_gen_clzi_tl tcg_gen_clzi_i64
987#define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
Richard Henderson086920c2016-11-16 17:32:48 +0100988#define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
Richard Hendersona768e4e2016-11-21 11:13:39 +0100989#define tcg_gen_ctpop_tl tcg_gen_ctpop_i64
aurel3215824572008-11-03 07:08:36 +0000990#define tcg_gen_rotl_tl tcg_gen_rotl_i64
991#define tcg_gen_rotli_tl tcg_gen_rotli_i64
992#define tcg_gen_rotr_tl tcg_gen_rotr_i64
993#define tcg_gen_rotri_tl tcg_gen_rotri_i64
Richard Hendersonb7767f02011-01-10 19:23:42 -0800994#define tcg_gen_deposit_tl tcg_gen_deposit_i64
Richard Henderson07cc68d2016-10-17 13:21:31 -0700995#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
Richard Henderson7ec8bab2016-10-14 12:04:32 -0500996#define tcg_gen_extract_tl tcg_gen_extract_i64
997#define tcg_gen_sextract_tl tcg_gen_sextract_i64
blueswir1a98824a2008-03-13 20:46:42 +0000998#define tcg_const_tl tcg_const_i64
aurel32bdffd4a2008-10-21 11:30:45 +0000999#define tcg_const_local_tl tcg_const_local_i64
Richard Hendersonffc5ea02012-09-21 10:13:34 -07001000#define tcg_gen_movcond_tl tcg_gen_movcond_i64
Richard Hendersonf6953a72013-02-19 23:51:56 -08001001#define tcg_gen_add2_tl tcg_gen_add2_i64
1002#define tcg_gen_sub2_tl tcg_gen_sub2_i64
Richard Henderson696a8be2013-02-19 23:51:55 -08001003#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
1004#define tcg_gen_muls2_tl tcg_gen_muls2_i64
Richard Henderson5087abf2016-09-27 14:23:52 -07001005#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
Richard Hendersonc482cb12016-06-28 11:37:27 -07001006#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
1007#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
1008#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
1009#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
1010#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
1011#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
1012#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
1013#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
1014#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
1015#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
blueswir1f8422f52008-02-24 07:45:43 +00001016#else
blueswir1f8422f52008-02-24 07:45:43 +00001017#define tcg_gen_movi_tl tcg_gen_movi_i32
1018#define tcg_gen_mov_tl tcg_gen_mov_i32
1019#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1020#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1021#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1022#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1023#define tcg_gen_ld32u_tl tcg_gen_ld_i32
1024#define tcg_gen_ld32s_tl tcg_gen_ld_i32
1025#define tcg_gen_ld_tl tcg_gen_ld_i32
1026#define tcg_gen_st8_tl tcg_gen_st8_i32
1027#define tcg_gen_st16_tl tcg_gen_st16_i32
1028#define tcg_gen_st32_tl tcg_gen_st_i32
1029#define tcg_gen_st_tl tcg_gen_st_i32
1030#define tcg_gen_add_tl tcg_gen_add_i32
1031#define tcg_gen_addi_tl tcg_gen_addi_i32
1032#define tcg_gen_sub_tl tcg_gen_sub_i32
pbrook390efc52008-05-11 14:35:37 +00001033#define tcg_gen_neg_tl tcg_gen_neg_i32
aurel3200457342008-11-02 08:23:04 +00001034#define tcg_gen_subfi_tl tcg_gen_subfi_i32
blueswir1f8422f52008-02-24 07:45:43 +00001035#define tcg_gen_subi_tl tcg_gen_subi_i32
1036#define tcg_gen_and_tl tcg_gen_and_i32
1037#define tcg_gen_andi_tl tcg_gen_andi_i32
1038#define tcg_gen_or_tl tcg_gen_or_i32
1039#define tcg_gen_ori_tl tcg_gen_ori_i32
1040#define tcg_gen_xor_tl tcg_gen_xor_i32
1041#define tcg_gen_xori_tl tcg_gen_xori_i32
bellard0b6ce4c2008-05-17 12:40:44 +00001042#define tcg_gen_not_tl tcg_gen_not_i32
blueswir1f8422f52008-02-24 07:45:43 +00001043#define tcg_gen_shl_tl tcg_gen_shl_i32
1044#define tcg_gen_shli_tl tcg_gen_shli_i32
1045#define tcg_gen_shr_tl tcg_gen_shr_i32
1046#define tcg_gen_shri_tl tcg_gen_shri_i32
1047#define tcg_gen_sar_tl tcg_gen_sar_i32
1048#define tcg_gen_sari_tl tcg_gen_sari_i32
blueswir10cf767d2008-03-02 18:20:59 +00001049#define tcg_gen_brcond_tl tcg_gen_brcond_i32
pbrookcb636692008-05-24 02:22:00 +00001050#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
Richard Hendersonbe210ac2010-01-07 10:13:31 -08001051#define tcg_gen_setcond_tl tcg_gen_setcond_i32
Aurelien Jarnoadd1e7e2010-02-08 12:06:05 +01001052#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
thsf730fd22008-05-04 08:14:08 +00001053#define tcg_gen_mul_tl tcg_gen_mul_i32
1054#define tcg_gen_muli_tl tcg_gen_muli_i32
aurel32ab364212009-03-29 01:19:22 +00001055#define tcg_gen_div_tl tcg_gen_div_i32
1056#define tcg_gen_rem_tl tcg_gen_rem_i32
aurel32864951a2009-03-29 14:08:54 +00001057#define tcg_gen_divu_tl tcg_gen_divu_i32
1058#define tcg_gen_remu_tl tcg_gen_remu_i32
blueswir1a768e4b2008-03-16 19:16:37 +00001059#define tcg_gen_discard_tl tcg_gen_discard_i32
blueswir1e4290732008-03-22 08:39:04 +00001060#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
Richard Hendersonecc7b3a2015-07-24 11:49:53 -07001061#define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
blueswir1e4290732008-03-22 08:39:04 +00001062#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1063#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1064#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1065#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
bellard0b6ce4c2008-05-17 12:40:44 +00001066#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
1067#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
1068#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
1069#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
1070#define tcg_gen_ext32u_tl tcg_gen_mov_i32
1071#define tcg_gen_ext32s_tl tcg_gen_mov_i32
aurel32911d79b2009-03-13 09:35:19 +00001072#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
1073#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
blueswir1945ca822008-09-21 18:32:28 +00001074#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
Alexander Grafe3eb9802014-06-04 23:09:11 +02001075#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
aurel32f24cb332008-10-21 11:28:59 +00001076#define tcg_gen_andc_tl tcg_gen_andc_i32
1077#define tcg_gen_eqv_tl tcg_gen_eqv_i32
1078#define tcg_gen_nand_tl tcg_gen_nand_i32
1079#define tcg_gen_nor_tl tcg_gen_nor_i32
1080#define tcg_gen_orc_tl tcg_gen_orc_i32
Richard Henderson0e28d002016-11-16 09:23:28 +01001081#define tcg_gen_clz_tl tcg_gen_clz_i32
1082#define tcg_gen_ctz_tl tcg_gen_ctz_i32
1083#define tcg_gen_clzi_tl tcg_gen_clzi_i32
1084#define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
Richard Henderson086920c2016-11-16 17:32:48 +01001085#define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
Richard Hendersona768e4e2016-11-21 11:13:39 +01001086#define tcg_gen_ctpop_tl tcg_gen_ctpop_i32
aurel3215824572008-11-03 07:08:36 +00001087#define tcg_gen_rotl_tl tcg_gen_rotl_i32
1088#define tcg_gen_rotli_tl tcg_gen_rotli_i32
1089#define tcg_gen_rotr_tl tcg_gen_rotr_i32
1090#define tcg_gen_rotri_tl tcg_gen_rotri_i32
Richard Hendersonb7767f02011-01-10 19:23:42 -08001091#define tcg_gen_deposit_tl tcg_gen_deposit_i32
Richard Henderson07cc68d2016-10-17 13:21:31 -07001092#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
Richard Henderson7ec8bab2016-10-14 12:04:32 -05001093#define tcg_gen_extract_tl tcg_gen_extract_i32
1094#define tcg_gen_sextract_tl tcg_gen_sextract_i32
blueswir1a98824a2008-03-13 20:46:42 +00001095#define tcg_const_tl tcg_const_i32
aurel32bdffd4a2008-10-21 11:30:45 +00001096#define tcg_const_local_tl tcg_const_local_i32
Richard Hendersonffc5ea02012-09-21 10:13:34 -07001097#define tcg_gen_movcond_tl tcg_gen_movcond_i32
Richard Hendersonf6953a72013-02-19 23:51:56 -08001098#define tcg_gen_add2_tl tcg_gen_add2_i32
1099#define tcg_gen_sub2_tl tcg_gen_sub2_i32
Richard Henderson696a8be2013-02-19 23:51:55 -08001100#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
1101#define tcg_gen_muls2_tl tcg_gen_muls2_i32
Richard Henderson5087abf2016-09-27 14:23:52 -07001102#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
Richard Hendersonc482cb12016-06-28 11:37:27 -07001103#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
1104#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
1105#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
1106#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
1107#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
1108#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
1109#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
1110#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
1111#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
1112#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
blueswir1f8422f52008-02-24 07:45:43 +00001113#endif
pbrook6ddbc6e2008-03-31 03:46:33 +00001114
Richard Henderson71b92692013-09-09 08:26:49 -07001115#if UINTPTR_MAX == UINT32_MAX
Richard Hendersonf713d6a2013-09-04 08:11:05 -07001116# define tcg_gen_ld_ptr(R, A, O) \
1117 tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
1118# define tcg_gen_discard_ptr(A) \
1119 tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
1120# define tcg_gen_add_ptr(R, A, B) \
1121 tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
1122# define tcg_gen_addi_ptr(R, A, B) \
1123 tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
1124# define tcg_gen_ext_i32_ptr(R, A) \
1125 tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
1126#else
1127# define tcg_gen_ld_ptr(R, A, O) \
1128 tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
1129# define tcg_gen_discard_ptr(A) \
1130 tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
1131# define tcg_gen_add_ptr(R, A, B) \
1132 tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
1133# define tcg_gen_addi_ptr(R, A, B) \
1134 tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
1135# define tcg_gen_ext_i32_ptr(R, A) \
1136 tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
Richard Henderson71b92692013-09-09 08:26:49 -07001137#endif /* UINTPTR_MAX == UINT32_MAX */