bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Tiny Code Generator for QEMU |
| 3 | * |
| 4 | * Copyright (c) 2008 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 24 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 25 | #include "tcg.h" |
Richard Henderson | 944eea9 | 2014-04-07 23:08:47 -0700 | [diff] [blame] | 26 | #include "exec/helper-proto.h" |
Richard Henderson | c017230 | 2014-04-07 23:36:08 -0700 | [diff] [blame] | 27 | #include "exec/helper-gen.h" |
| 28 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 29 | /* Basic output routines. Not for general consumption. */ |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 30 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 31 | void tcg_gen_op1(TCGContext *, TCGOpcode, TCGArg); |
| 32 | void tcg_gen_op2(TCGContext *, TCGOpcode, TCGArg, TCGArg); |
| 33 | void tcg_gen_op3(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg); |
| 34 | void tcg_gen_op4(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); |
| 35 | void tcg_gen_op5(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, |
| 36 | TCGArg, TCGArg); |
| 37 | void tcg_gen_op6(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, |
| 38 | TCGArg, TCGArg, TCGArg); |
| 39 | |
| 40 | |
| 41 | static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) |
Richard Henderson | 212c328 | 2012-10-02 11:32:28 -0700 | [diff] [blame] | 42 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 43 | tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I32(a1)); |
Richard Henderson | 212c328 | 2012-10-02 11:32:28 -0700 | [diff] [blame] | 44 | } |
| 45 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 46 | static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 47 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 48 | tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I64(a1)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 49 | } |
| 50 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 51 | static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 52 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 53 | tcg_gen_op1(&tcg_ctx, opc, a1); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 54 | } |
| 55 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 56 | static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 57 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 58 | tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 59 | } |
| 60 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 61 | static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 62 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 63 | tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2)); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 64 | } |
| 65 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 66 | static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 67 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 68 | tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), a2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 69 | } |
| 70 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 71 | static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 72 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 73 | tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), a2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 74 | } |
| 75 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 76 | static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 77 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 78 | tcg_gen_op2(&tcg_ctx, opc, a1, a2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 79 | } |
| 80 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 81 | static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, |
| 82 | TCGv_i32 a2, TCGv_i32 a3) |
pbrook | bcb0126 | 2008-05-24 02:24:25 +0000 | [diff] [blame] | 83 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 84 | tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), |
| 85 | GET_TCGV_I32(a2), GET_TCGV_I32(a3)); |
pbrook | bcb0126 | 2008-05-24 02:24:25 +0000 | [diff] [blame] | 86 | } |
| 87 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 88 | static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, |
| 89 | TCGv_i64 a2, TCGv_i64 a3) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 90 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 91 | tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), |
| 92 | GET_TCGV_I64(a2), GET_TCGV_I64(a3)); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 93 | } |
| 94 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 95 | static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, |
| 96 | TCGv_i32 a2, TCGArg a3) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 97 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 98 | tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 99 | } |
| 100 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 101 | static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, |
| 102 | TCGv_i64 a2, TCGArg a3) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 103 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 104 | tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 105 | } |
| 106 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 107 | static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
| 108 | TCGv_ptr base, TCGArg offset) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 109 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 110 | tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 111 | } |
| 112 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 113 | static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
| 114 | TCGv_ptr base, TCGArg offset) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 115 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 116 | tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 117 | } |
| 118 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 119 | static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 120 | TCGv_i32 a3, TCGv_i32 a4) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 121 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 122 | tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
| 123 | GET_TCGV_I32(a3), GET_TCGV_I32(a4)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 124 | } |
| 125 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 126 | static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 127 | TCGv_i64 a3, TCGv_i64 a4) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 128 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 129 | tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
| 130 | GET_TCGV_I64(a3), GET_TCGV_I64(a4)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 131 | } |
| 132 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 133 | static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 134 | TCGv_i32 a3, TCGArg a4) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 135 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 136 | tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
| 137 | GET_TCGV_I32(a3), a4); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 138 | } |
| 139 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 140 | static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 141 | TCGv_i64 a3, TCGArg a4) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 142 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 143 | tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
| 144 | GET_TCGV_I64(a3), a4); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 145 | } |
| 146 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 147 | static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 148 | TCGArg a3, TCGArg a4) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 149 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 150 | tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 151 | } |
| 152 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 153 | static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 154 | TCGArg a3, TCGArg a4) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 155 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 156 | tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 157 | } |
| 158 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 159 | static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 160 | TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 161 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 162 | tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
| 163 | GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 164 | } |
| 165 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 166 | static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 167 | TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 168 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 169 | tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
| 170 | GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 171 | } |
| 172 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 173 | static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 174 | TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 175 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 176 | tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
| 177 | GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 178 | } |
| 179 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 180 | static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 181 | TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 182 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 183 | tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
| 184 | GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 185 | } |
| 186 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 187 | static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 188 | TCGv_i32 a3, TCGArg a4, TCGArg a5) |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 189 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 190 | tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
| 191 | GET_TCGV_I32(a3), a4, a5); |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 192 | } |
| 193 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 194 | static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 195 | TCGv_i64 a3, TCGArg a4, TCGArg a5) |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 196 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 197 | tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
| 198 | GET_TCGV_I64(a3), a4, a5); |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 199 | } |
| 200 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 201 | static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 202 | TCGv_i32 a3, TCGv_i32 a4, |
| 203 | TCGv_i32 a5, TCGv_i32 a6) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 204 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 205 | tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
| 206 | GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), |
| 207 | GET_TCGV_I32(a6)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 208 | } |
| 209 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 210 | static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 211 | TCGv_i64 a3, TCGv_i64 a4, |
| 212 | TCGv_i64 a5, TCGv_i64 a6) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 213 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 214 | tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
| 215 | GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), |
| 216 | GET_TCGV_I64(a6)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 217 | } |
| 218 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 219 | static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 220 | TCGv_i32 a3, TCGv_i32 a4, |
| 221 | TCGv_i32 a5, TCGArg a6) |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 222 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 223 | tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
| 224 | GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6); |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 225 | } |
| 226 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 227 | static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 228 | TCGv_i64 a3, TCGv_i64 a4, |
| 229 | TCGv_i64 a5, TCGArg a6) |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 230 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 231 | tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
| 232 | GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6); |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 233 | } |
| 234 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 235 | static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 236 | TCGv_i32 a3, TCGv_i32 a4, |
| 237 | TCGArg a5, TCGArg a6) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 238 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 239 | tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), |
| 240 | GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 241 | } |
| 242 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 243 | static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 244 | TCGv_i64 a3, TCGv_i64 a4, |
| 245 | TCGArg a5, TCGArg a6) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 246 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 247 | tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), |
| 248 | GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 249 | } |
| 250 | |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 251 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 252 | /* Generic ops. */ |
| 253 | |
Richard Henderson | 42a268c | 2015-02-13 12:51:55 -0800 | [diff] [blame] | 254 | static inline void gen_set_label(TCGLabel *l) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 255 | { |
Richard Henderson | 42a268c | 2015-02-13 12:51:55 -0800 | [diff] [blame] | 256 | tcg_gen_op1(&tcg_ctx, INDEX_op_set_label, label_arg(l)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 257 | } |
| 258 | |
Richard Henderson | 42a268c | 2015-02-13 12:51:55 -0800 | [diff] [blame] | 259 | static inline void tcg_gen_br(TCGLabel *l) |
blueswir1 | fb50d41 | 2008-03-21 17:58:45 +0000 | [diff] [blame] | 260 | { |
Richard Henderson | 42a268c | 2015-02-13 12:51:55 -0800 | [diff] [blame] | 261 | tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l)); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 262 | } |
| 263 | |
Pranith Kumar | f65e19b | 2016-07-14 16:20:13 -0400 | [diff] [blame] | 264 | void tcg_gen_mb(TCGBar); |
| 265 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 266 | /* Helper calls. */ |
| 267 | |
| 268 | /* 32 bit ops */ |
| 269 | |
| 270 | void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
| 271 | void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); |
| 272 | void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
| 273 | void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); |
| 274 | void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
| 275 | void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
| 276 | void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); |
| 277 | void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); |
| 278 | void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); |
| 279 | void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
| 280 | void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 281 | void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 282 | void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 283 | void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 284 | void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 285 | void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 286 | void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 287 | void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 288 | void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
Richard Henderson | 0e28d00 | 2016-11-16 09:23:28 +0100 | [diff] [blame] | 289 | void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 290 | void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 291 | void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); |
| 292 | void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); |
Richard Henderson | 086920c | 2016-11-16 17:32:48 +0100 | [diff] [blame] | 293 | void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); |
Richard Henderson | a768e4e | 2016-11-21 11:13:39 +0100 | [diff] [blame] | 294 | void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 295 | void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 296 | void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); |
| 297 | void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 298 | void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); |
| 299 | void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, |
| 300 | unsigned int ofs, unsigned int len); |
Richard Henderson | 07cc68d | 2016-10-17 13:21:31 -0700 | [diff] [blame] | 301 | void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, |
| 302 | unsigned int ofs, unsigned int len); |
Richard Henderson | 7ec8bab | 2016-10-14 12:04:32 -0500 | [diff] [blame] | 303 | void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, |
| 304 | unsigned int ofs, unsigned int len); |
| 305 | void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, |
| 306 | unsigned int ofs, unsigned int len); |
Richard Henderson | 42a268c | 2015-02-13 12:51:55 -0800 | [diff] [blame] | 307 | void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *); |
| 308 | void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 309 | void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, |
| 310 | TCGv_i32 arg1, TCGv_i32 arg2); |
| 311 | void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, |
| 312 | TCGv_i32 arg1, int32_t arg2); |
| 313 | void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, |
| 314 | TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); |
| 315 | void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, |
| 316 | TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); |
| 317 | void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, |
| 318 | TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); |
| 319 | void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); |
| 320 | void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); |
Richard Henderson | 5087abf | 2016-09-27 14:23:52 -0700 | [diff] [blame] | 321 | void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 322 | void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg); |
| 323 | void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); |
| 324 | void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); |
| 325 | void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); |
| 326 | void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg); |
| 327 | void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); |
| 328 | |
| 329 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
| 330 | { |
| 331 | tcg_gen_op1_i32(INDEX_op_discard, arg); |
blueswir1 | fb50d41 | 2008-03-21 17:58:45 +0000 | [diff] [blame] | 332 | } |
| 333 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 334 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 335 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 336 | if (!TCGV_EQUAL_I32(ret, arg)) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 337 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 338 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 339 | } |
| 340 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 341 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 342 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 343 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 344 | } |
| 345 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 346 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, |
| 347 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 348 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 349 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 350 | } |
| 351 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 352 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, |
| 353 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 354 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 355 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 356 | } |
| 357 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 358 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, |
| 359 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 360 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 361 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 362 | } |
| 363 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 364 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, |
| 365 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 366 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 367 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 368 | } |
| 369 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 370 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, |
| 371 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 372 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 373 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 374 | } |
| 375 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 376 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
| 377 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 378 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 379 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 380 | } |
| 381 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 382 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
| 383 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 384 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 385 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 386 | } |
| 387 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 388 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
| 389 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 390 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 391 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 392 | } |
| 393 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 394 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 395 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 396 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 397 | } |
| 398 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 399 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 400 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 401 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 402 | } |
| 403 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 404 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 405 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 406 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 407 | } |
| 408 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 409 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 410 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 411 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 412 | } |
| 413 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 414 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 415 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 416 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 417 | } |
| 418 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 419 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 420 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 421 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 422 | } |
| 423 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 424 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 425 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 426 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 427 | } |
| 428 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 429 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 430 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 431 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 432 | } |
| 433 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 434 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 435 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 436 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 437 | } |
| 438 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 439 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 440 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 441 | if (TCG_TARGET_HAS_neg_i32) { |
| 442 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 443 | } else { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 444 | tcg_gen_subfi_i32(ret, 0, arg); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 445 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 446 | } |
| 447 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 448 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 449 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 450 | if (TCG_TARGET_HAS_not_i32) { |
| 451 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 452 | } else { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 453 | tcg_gen_xori_i32(ret, arg, -1); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 454 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 455 | } |
| 456 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 457 | /* 64 bit ops */ |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 458 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 459 | void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
| 460 | void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); |
| 461 | void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
| 462 | void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); |
| 463 | void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
| 464 | void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
| 465 | void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); |
| 466 | void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); |
| 467 | void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); |
| 468 | void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
| 469 | void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 470 | void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 471 | void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 472 | void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 473 | void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 474 | void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 475 | void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 476 | void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 477 | void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
Richard Henderson | 0e28d00 | 2016-11-16 09:23:28 +0100 | [diff] [blame] | 478 | void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 479 | void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 480 | void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); |
| 481 | void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); |
Richard Henderson | 086920c | 2016-11-16 17:32:48 +0100 | [diff] [blame] | 482 | void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); |
Richard Henderson | a768e4e | 2016-11-21 11:13:39 +0100 | [diff] [blame] | 483 | void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 484 | void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 485 | void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); |
| 486 | void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 487 | void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); |
| 488 | void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, |
| 489 | unsigned int ofs, unsigned int len); |
Richard Henderson | 07cc68d | 2016-10-17 13:21:31 -0700 | [diff] [blame] | 490 | void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, |
| 491 | unsigned int ofs, unsigned int len); |
Richard Henderson | 7ec8bab | 2016-10-14 12:04:32 -0500 | [diff] [blame] | 492 | void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, |
| 493 | unsigned int ofs, unsigned int len); |
| 494 | void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, |
| 495 | unsigned int ofs, unsigned int len); |
Richard Henderson | 42a268c | 2015-02-13 12:51:55 -0800 | [diff] [blame] | 496 | void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *); |
| 497 | void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 498 | void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
| 499 | TCGv_i64 arg1, TCGv_i64 arg2); |
| 500 | void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, |
| 501 | TCGv_i64 arg1, int64_t arg2); |
| 502 | void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, |
| 503 | TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); |
| 504 | void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, |
| 505 | TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); |
| 506 | void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, |
| 507 | TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); |
| 508 | void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); |
| 509 | void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); |
Richard Henderson | 5087abf | 2016-09-27 14:23:52 -0700 | [diff] [blame] | 510 | void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 511 | void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 512 | void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 513 | void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 514 | void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 515 | void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 516 | void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 517 | void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 518 | void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 519 | void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 520 | void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 521 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 522 | #if TCG_TARGET_REG_BITS == 64 |
| 523 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
| 524 | { |
| 525 | tcg_gen_op1_i64(INDEX_op_discard, arg); |
| 526 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 527 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 528 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 529 | { |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 530 | if (!TCGV_EQUAL_I64(ret, arg)) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 531 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 532 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 533 | } |
| 534 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 535 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 536 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 537 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 538 | } |
| 539 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 540 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 541 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 542 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 543 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 544 | } |
| 545 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 546 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 547 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 548 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 549 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 550 | } |
| 551 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 552 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 553 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 554 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 555 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 556 | } |
| 557 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 558 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 559 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 560 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 561 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 562 | } |
| 563 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 564 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 565 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 566 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 567 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 568 | } |
| 569 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 570 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 571 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 572 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 573 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 574 | } |
| 575 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 576 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 577 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 578 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 579 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 580 | } |
| 581 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 582 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 583 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 584 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 585 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 586 | } |
| 587 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 588 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 589 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 590 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 591 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 592 | } |
| 593 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 594 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 595 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 596 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 597 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 598 | } |
| 599 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 600 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 601 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 602 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 603 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 604 | } |
| 605 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 606 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 607 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 608 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 609 | } |
| 610 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 611 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 612 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 613 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 614 | } |
| 615 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 616 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 617 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 618 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 619 | } |
| 620 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 621 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 622 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 623 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 624 | } |
| 625 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 626 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 627 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 628 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 629 | } |
| 630 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 631 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 632 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 633 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 634 | } |
| 635 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 636 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 637 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 638 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 639 | } |
| 640 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 641 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 642 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 643 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 644 | } |
| 645 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 646 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 647 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 648 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 649 | } |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 650 | #else /* TCG_TARGET_REG_BITS == 32 */ |
| 651 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 652 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 653 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 654 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 655 | } |
| 656 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 657 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 658 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 659 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 660 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 661 | } |
| 662 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 663 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 664 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 665 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 666 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 667 | } |
| 668 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 669 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 670 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 671 | tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), |
| 672 | TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 673 | } |
| 674 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 675 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 676 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 677 | tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), |
| 678 | TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 679 | } |
| 680 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 681 | void tcg_gen_discard_i64(TCGv_i64 arg); |
| 682 | void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 683 | void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); |
| 684 | void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 685 | void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 686 | void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 687 | void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 688 | void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 689 | void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 690 | void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 691 | void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); |
| 692 | void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 693 | void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 694 | void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 695 | void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 696 | void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 697 | void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 698 | void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 699 | #endif /* TCG_TARGET_REG_BITS */ |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 700 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 701 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 702 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 703 | if (TCG_TARGET_HAS_neg_i64) { |
| 704 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
| 705 | } else { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 706 | tcg_gen_subfi_i64(ret, 0, arg); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 707 | } |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 708 | } |
| 709 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 710 | /* Size changing operations. */ |
| 711 | |
| 712 | void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg); |
| 713 | void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg); |
| 714 | void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); |
Richard Henderson | 609ad70 | 2015-07-24 07:16:00 -0700 | [diff] [blame] | 715 | void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg); |
| 716 | void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 717 | void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); |
| 718 | void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); |
| 719 | |
| 720 | static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 721 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 722 | tcg_gen_deposit_i64(ret, lo, hi, 32, 32); |
Richard Henderson | 77276f6 | 2012-09-21 17:18:13 -0700 | [diff] [blame] | 723 | } |
| 724 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 725 | /* QEMU specific operations. */ |
Richard Henderson | 3c51a98 | 2013-02-19 23:51:54 -0800 | [diff] [blame] | 726 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 727 | #ifndef TARGET_LONG_BITS |
| 728 | #error must include QEMU headers |
| 729 | #endif |
| 730 | |
Richard Henderson | 9aef40e | 2015-08-30 09:21:33 -0700 | [diff] [blame] | 731 | #if TARGET_INSN_START_WORDS == 1 |
| 732 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS |
| 733 | static inline void tcg_gen_insn_start(target_ulong pc) |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 734 | { |
Richard Henderson | 9aef40e | 2015-08-30 09:21:33 -0700 | [diff] [blame] | 735 | tcg_gen_op1(&tcg_ctx, INDEX_op_insn_start, pc); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 736 | } |
Richard Henderson | 9aef40e | 2015-08-30 09:21:33 -0700 | [diff] [blame] | 737 | # else |
| 738 | static inline void tcg_gen_insn_start(target_ulong pc) |
| 739 | { |
| 740 | tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, |
| 741 | (uint32_t)pc, (uint32_t)(pc >> 32)); |
| 742 | } |
| 743 | # endif |
| 744 | #elif TARGET_INSN_START_WORDS == 2 |
| 745 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS |
| 746 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) |
| 747 | { |
| 748 | tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, pc, a1); |
| 749 | } |
| 750 | # else |
| 751 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) |
| 752 | { |
| 753 | tcg_gen_op4(&tcg_ctx, INDEX_op_insn_start, |
| 754 | (uint32_t)pc, (uint32_t)(pc >> 32), |
| 755 | (uint32_t)a1, (uint32_t)(a1 >> 32)); |
| 756 | } |
| 757 | # endif |
| 758 | #elif TARGET_INSN_START_WORDS == 3 |
| 759 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS |
| 760 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, |
| 761 | target_ulong a2) |
| 762 | { |
| 763 | tcg_gen_op3(&tcg_ctx, INDEX_op_insn_start, pc, a1, a2); |
| 764 | } |
| 765 | # else |
| 766 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, |
| 767 | target_ulong a2) |
| 768 | { |
| 769 | tcg_gen_op6(&tcg_ctx, INDEX_op_insn_start, |
| 770 | (uint32_t)pc, (uint32_t)(pc >> 32), |
| 771 | (uint32_t)a1, (uint32_t)(a1 >> 32), |
| 772 | (uint32_t)a2, (uint32_t)(a2 >> 32)); |
| 773 | } |
| 774 | # endif |
| 775 | #else |
| 776 | # error "Unhandled number of operands to insn_start" |
| 777 | #endif |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 778 | |
| 779 | static inline void tcg_gen_exit_tb(uintptr_t val) |
| 780 | { |
| 781 | tcg_gen_op1i(INDEX_op_exit_tb, val); |
| 782 | } |
| 783 | |
Sergey Fedorov | 5b053a4 | 2016-04-08 19:48:12 +0300 | [diff] [blame] | 784 | /** |
| 785 | * tcg_gen_goto_tb() - output goto_tb TCG operation |
| 786 | * @idx: Direct jump slot index (0 or 1) |
| 787 | * |
| 788 | * See tcg/README for more info about this TCG operation. |
| 789 | * |
Sergey Fedorov | 90aa39a | 2016-04-09 01:00:23 +0300 | [diff] [blame] | 790 | * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within |
| 791 | * the pages this TB resides in because we don't take care of direct jumps when |
| 792 | * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a |
| 793 | * static address translation, so the destination address is always valid, TBs |
| 794 | * are always invalidated properly, and direct jumps are reset when mapping |
| 795 | * changes. |
Sergey Fedorov | 5b053a4 | 2016-04-08 19:48:12 +0300 | [diff] [blame] | 796 | */ |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 797 | void tcg_gen_goto_tb(unsigned idx); |
| 798 | |
Emilio G. Cota | cedbcb0 | 2017-04-26 23:29:14 -0400 | [diff] [blame] | 799 | /** |
Emilio G. Cota | 7f11636 | 2017-07-11 17:06:48 -0400 | [diff] [blame] | 800 | * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid |
Emilio G. Cota | cedbcb0 | 2017-04-26 23:29:14 -0400 | [diff] [blame] | 801 | * @addr: Guest address of the target TB |
| 802 | * |
| 803 | * If the TB is not valid, jump to the epilogue. |
| 804 | * |
| 805 | * This operation is optional. If the TCG backend does not implement goto_ptr, |
| 806 | * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument. |
| 807 | */ |
Emilio G. Cota | 7f11636 | 2017-07-11 17:06:48 -0400 | [diff] [blame] | 808 | void tcg_gen_lookup_and_goto_ptr(void); |
Emilio G. Cota | cedbcb0 | 2017-04-26 23:29:14 -0400 | [diff] [blame] | 809 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 810 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 811 | #define tcg_temp_new() tcg_temp_new_i32() |
| 812 | #define tcg_global_reg_new tcg_global_reg_new_i32 |
| 813 | #define tcg_global_mem_new tcg_global_mem_new_i32 |
aurel32 | df9247b | 2009-01-01 14:09:05 +0000 | [diff] [blame] | 814 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 815 | #define tcg_temp_free tcg_temp_free_i32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 816 | #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) |
Richard Henderson | afcb92b | 2012-12-07 15:07:17 -0600 | [diff] [blame] | 817 | #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x) |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 818 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 819 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 |
| 820 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 821 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 822 | #define tcg_temp_new() tcg_temp_new_i64() |
| 823 | #define tcg_global_reg_new tcg_global_reg_new_i64 |
| 824 | #define tcg_global_mem_new tcg_global_mem_new_i64 |
aurel32 | df9247b | 2009-01-01 14:09:05 +0000 | [diff] [blame] | 825 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 826 | #define tcg_temp_free tcg_temp_free_i64 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 827 | #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) |
Richard Henderson | afcb92b | 2012-12-07 15:07:17 -0600 | [diff] [blame] | 828 | #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x) |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 829 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 830 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 |
| 831 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 832 | #endif |
| 833 | |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 834 | void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); |
| 835 | void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); |
| 836 | void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); |
| 837 | void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); |
| 838 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 839 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 840 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 841 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 842 | } |
| 843 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 844 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 845 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 846 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 847 | } |
| 848 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 849 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 850 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 851 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 852 | } |
| 853 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 854 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 855 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 856 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 857 | } |
| 858 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 859 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 860 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 861 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 862 | } |
| 863 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 864 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 865 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 866 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 867 | } |
| 868 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 869 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 870 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 871 | tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 872 | } |
| 873 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 874 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 875 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 876 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 877 | } |
| 878 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 879 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 880 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 881 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 882 | } |
| 883 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 884 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 885 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 886 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 887 | } |
| 888 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 889 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 890 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 891 | tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 892 | } |
| 893 | |
Richard Henderson | c482cb1 | 2016-06-28 11:37:27 -0700 | [diff] [blame] | 894 | void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, |
| 895 | TCGArg, TCGMemOp); |
| 896 | void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, |
| 897 | TCGArg, TCGMemOp); |
| 898 | |
| 899 | void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 900 | void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 901 | void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 902 | void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 903 | void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 904 | void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 905 | void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 906 | void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 907 | void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 908 | void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 909 | void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 910 | void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 911 | void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 912 | void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 913 | void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 914 | void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 915 | void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 916 | void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 917 | |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 918 | #if TARGET_LONG_BITS == 64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 919 | #define tcg_gen_movi_tl tcg_gen_movi_i64 |
| 920 | #define tcg_gen_mov_tl tcg_gen_mov_i64 |
| 921 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 |
| 922 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 |
| 923 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 |
| 924 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 |
| 925 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 |
| 926 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 |
| 927 | #define tcg_gen_ld_tl tcg_gen_ld_i64 |
| 928 | #define tcg_gen_st8_tl tcg_gen_st8_i64 |
| 929 | #define tcg_gen_st16_tl tcg_gen_st16_i64 |
| 930 | #define tcg_gen_st32_tl tcg_gen_st32_i64 |
| 931 | #define tcg_gen_st_tl tcg_gen_st_i64 |
| 932 | #define tcg_gen_add_tl tcg_gen_add_i64 |
| 933 | #define tcg_gen_addi_tl tcg_gen_addi_i64 |
| 934 | #define tcg_gen_sub_tl tcg_gen_sub_i64 |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 935 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
pbrook | 10460c8 | 2008-11-02 13:26:16 +0000 | [diff] [blame] | 936 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 937 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
| 938 | #define tcg_gen_and_tl tcg_gen_and_i64 |
| 939 | #define tcg_gen_andi_tl tcg_gen_andi_i64 |
| 940 | #define tcg_gen_or_tl tcg_gen_or_i64 |
| 941 | #define tcg_gen_ori_tl tcg_gen_ori_i64 |
| 942 | #define tcg_gen_xor_tl tcg_gen_xor_i64 |
| 943 | #define tcg_gen_xori_tl tcg_gen_xori_i64 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 944 | #define tcg_gen_not_tl tcg_gen_not_i64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 945 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
| 946 | #define tcg_gen_shli_tl tcg_gen_shli_i64 |
| 947 | #define tcg_gen_shr_tl tcg_gen_shr_i64 |
| 948 | #define tcg_gen_shri_tl tcg_gen_shri_i64 |
| 949 | #define tcg_gen_sar_tl tcg_gen_sar_i64 |
| 950 | #define tcg_gen_sari_tl tcg_gen_sari_i64 |
blueswir1 | 0cf767d | 2008-03-02 18:20:59 +0000 | [diff] [blame] | 951 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 952 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 953 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
Aurelien Jarno | add1e7e | 2010-02-08 12:06:05 +0100 | [diff] [blame] | 954 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 955 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
| 956 | #define tcg_gen_muli_tl tcg_gen_muli_i64 |
aurel32 | ab36421 | 2009-03-29 01:19:22 +0000 | [diff] [blame] | 957 | #define tcg_gen_div_tl tcg_gen_div_i64 |
| 958 | #define tcg_gen_rem_tl tcg_gen_rem_i64 |
aurel32 | 864951a | 2009-03-29 14:08:54 +0000 | [diff] [blame] | 959 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
| 960 | #define tcg_gen_remu_tl tcg_gen_remu_i64 |
blueswir1 | a768e4b | 2008-03-16 19:16:37 +0000 | [diff] [blame] | 961 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
Richard Henderson | ecc7b3a | 2015-07-24 11:49:53 -0700 | [diff] [blame] | 962 | #define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32 |
blueswir1 | e429073 | 2008-03-22 08:39:04 +0000 | [diff] [blame] | 963 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 |
| 964 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 |
| 965 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 |
| 966 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 |
| 967 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 968 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
| 969 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 |
| 970 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 |
| 971 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 |
| 972 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 |
| 973 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 |
aurel32 | 911d79b | 2009-03-13 09:35:19 +0000 | [diff] [blame] | 974 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
| 975 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 |
| 976 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 |
blueswir1 | 945ca82 | 2008-09-21 18:32:28 +0000 | [diff] [blame] | 977 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
Richard Henderson | 3c51a98 | 2013-02-19 23:51:54 -0800 | [diff] [blame] | 978 | #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64 |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 979 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
| 980 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 |
| 981 | #define tcg_gen_nand_tl tcg_gen_nand_i64 |
| 982 | #define tcg_gen_nor_tl tcg_gen_nor_i64 |
| 983 | #define tcg_gen_orc_tl tcg_gen_orc_i64 |
Richard Henderson | 0e28d00 | 2016-11-16 09:23:28 +0100 | [diff] [blame] | 984 | #define tcg_gen_clz_tl tcg_gen_clz_i64 |
| 985 | #define tcg_gen_ctz_tl tcg_gen_ctz_i64 |
| 986 | #define tcg_gen_clzi_tl tcg_gen_clzi_i64 |
| 987 | #define tcg_gen_ctzi_tl tcg_gen_ctzi_i64 |
Richard Henderson | 086920c | 2016-11-16 17:32:48 +0100 | [diff] [blame] | 988 | #define tcg_gen_clrsb_tl tcg_gen_clrsb_i64 |
Richard Henderson | a768e4e | 2016-11-21 11:13:39 +0100 | [diff] [blame] | 989 | #define tcg_gen_ctpop_tl tcg_gen_ctpop_i64 |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 990 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
| 991 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 |
| 992 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 |
| 993 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 994 | #define tcg_gen_deposit_tl tcg_gen_deposit_i64 |
Richard Henderson | 07cc68d | 2016-10-17 13:21:31 -0700 | [diff] [blame] | 995 | #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64 |
Richard Henderson | 7ec8bab | 2016-10-14 12:04:32 -0500 | [diff] [blame] | 996 | #define tcg_gen_extract_tl tcg_gen_extract_i64 |
| 997 | #define tcg_gen_sextract_tl tcg_gen_sextract_i64 |
blueswir1 | a98824a | 2008-03-13 20:46:42 +0000 | [diff] [blame] | 998 | #define tcg_const_tl tcg_const_i64 |
aurel32 | bdffd4a | 2008-10-21 11:30:45 +0000 | [diff] [blame] | 999 | #define tcg_const_local_tl tcg_const_local_i64 |
Richard Henderson | ffc5ea0 | 2012-09-21 10:13:34 -0700 | [diff] [blame] | 1000 | #define tcg_gen_movcond_tl tcg_gen_movcond_i64 |
Richard Henderson | f6953a7 | 2013-02-19 23:51:56 -0800 | [diff] [blame] | 1001 | #define tcg_gen_add2_tl tcg_gen_add2_i64 |
| 1002 | #define tcg_gen_sub2_tl tcg_gen_sub2_i64 |
Richard Henderson | 696a8be | 2013-02-19 23:51:55 -0800 | [diff] [blame] | 1003 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 |
| 1004 | #define tcg_gen_muls2_tl tcg_gen_muls2_i64 |
Richard Henderson | 5087abf | 2016-09-27 14:23:52 -0700 | [diff] [blame] | 1005 | #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 |
Richard Henderson | c482cb1 | 2016-06-28 11:37:27 -0700 | [diff] [blame] | 1006 | #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 |
| 1007 | #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 |
| 1008 | #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 |
| 1009 | #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64 |
| 1010 | #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64 |
| 1011 | #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64 |
| 1012 | #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64 |
| 1013 | #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64 |
| 1014 | #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64 |
| 1015 | #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 1016 | #else |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 1017 | #define tcg_gen_movi_tl tcg_gen_movi_i32 |
| 1018 | #define tcg_gen_mov_tl tcg_gen_mov_i32 |
| 1019 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 |
| 1020 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 |
| 1021 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 |
| 1022 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 |
| 1023 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 |
| 1024 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 |
| 1025 | #define tcg_gen_ld_tl tcg_gen_ld_i32 |
| 1026 | #define tcg_gen_st8_tl tcg_gen_st8_i32 |
| 1027 | #define tcg_gen_st16_tl tcg_gen_st16_i32 |
| 1028 | #define tcg_gen_st32_tl tcg_gen_st_i32 |
| 1029 | #define tcg_gen_st_tl tcg_gen_st_i32 |
| 1030 | #define tcg_gen_add_tl tcg_gen_add_i32 |
| 1031 | #define tcg_gen_addi_tl tcg_gen_addi_i32 |
| 1032 | #define tcg_gen_sub_tl tcg_gen_sub_i32 |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 1033 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 1034 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 1035 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
| 1036 | #define tcg_gen_and_tl tcg_gen_and_i32 |
| 1037 | #define tcg_gen_andi_tl tcg_gen_andi_i32 |
| 1038 | #define tcg_gen_or_tl tcg_gen_or_i32 |
| 1039 | #define tcg_gen_ori_tl tcg_gen_ori_i32 |
| 1040 | #define tcg_gen_xor_tl tcg_gen_xor_i32 |
| 1041 | #define tcg_gen_xori_tl tcg_gen_xori_i32 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 1042 | #define tcg_gen_not_tl tcg_gen_not_i32 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 1043 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
| 1044 | #define tcg_gen_shli_tl tcg_gen_shli_i32 |
| 1045 | #define tcg_gen_shr_tl tcg_gen_shr_i32 |
| 1046 | #define tcg_gen_shri_tl tcg_gen_shri_i32 |
| 1047 | #define tcg_gen_sar_tl tcg_gen_sar_i32 |
| 1048 | #define tcg_gen_sari_tl tcg_gen_sari_i32 |
blueswir1 | 0cf767d | 2008-03-02 18:20:59 +0000 | [diff] [blame] | 1049 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 1050 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 1051 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
Aurelien Jarno | add1e7e | 2010-02-08 12:06:05 +0100 | [diff] [blame] | 1052 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 1053 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
| 1054 | #define tcg_gen_muli_tl tcg_gen_muli_i32 |
aurel32 | ab36421 | 2009-03-29 01:19:22 +0000 | [diff] [blame] | 1055 | #define tcg_gen_div_tl tcg_gen_div_i32 |
| 1056 | #define tcg_gen_rem_tl tcg_gen_rem_i32 |
aurel32 | 864951a | 2009-03-29 14:08:54 +0000 | [diff] [blame] | 1057 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
| 1058 | #define tcg_gen_remu_tl tcg_gen_remu_i32 |
blueswir1 | a768e4b | 2008-03-16 19:16:37 +0000 | [diff] [blame] | 1059 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
blueswir1 | e429073 | 2008-03-22 08:39:04 +0000 | [diff] [blame] | 1060 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
Richard Henderson | ecc7b3a | 2015-07-24 11:49:53 -0700 | [diff] [blame] | 1061 | #define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32 |
blueswir1 | e429073 | 2008-03-22 08:39:04 +0000 | [diff] [blame] | 1062 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 |
| 1063 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 |
| 1064 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 |
| 1065 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 1066 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
| 1067 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 |
| 1068 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 |
| 1069 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 |
| 1070 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 |
| 1071 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 |
aurel32 | 911d79b | 2009-03-13 09:35:19 +0000 | [diff] [blame] | 1072 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
| 1073 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 |
blueswir1 | 945ca82 | 2008-09-21 18:32:28 +0000 | [diff] [blame] | 1074 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
Alexander Graf | e3eb980 | 2014-06-04 23:09:11 +0200 | [diff] [blame] | 1075 | #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32 |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1076 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
| 1077 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 |
| 1078 | #define tcg_gen_nand_tl tcg_gen_nand_i32 |
| 1079 | #define tcg_gen_nor_tl tcg_gen_nor_i32 |
| 1080 | #define tcg_gen_orc_tl tcg_gen_orc_i32 |
Richard Henderson | 0e28d00 | 2016-11-16 09:23:28 +0100 | [diff] [blame] | 1081 | #define tcg_gen_clz_tl tcg_gen_clz_i32 |
| 1082 | #define tcg_gen_ctz_tl tcg_gen_ctz_i32 |
| 1083 | #define tcg_gen_clzi_tl tcg_gen_clzi_i32 |
| 1084 | #define tcg_gen_ctzi_tl tcg_gen_ctzi_i32 |
Richard Henderson | 086920c | 2016-11-16 17:32:48 +0100 | [diff] [blame] | 1085 | #define tcg_gen_clrsb_tl tcg_gen_clrsb_i32 |
Richard Henderson | a768e4e | 2016-11-21 11:13:39 +0100 | [diff] [blame] | 1086 | #define tcg_gen_ctpop_tl tcg_gen_ctpop_i32 |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1087 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
| 1088 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 |
| 1089 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 |
| 1090 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 1091 | #define tcg_gen_deposit_tl tcg_gen_deposit_i32 |
Richard Henderson | 07cc68d | 2016-10-17 13:21:31 -0700 | [diff] [blame] | 1092 | #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32 |
Richard Henderson | 7ec8bab | 2016-10-14 12:04:32 -0500 | [diff] [blame] | 1093 | #define tcg_gen_extract_tl tcg_gen_extract_i32 |
| 1094 | #define tcg_gen_sextract_tl tcg_gen_sextract_i32 |
blueswir1 | a98824a | 2008-03-13 20:46:42 +0000 | [diff] [blame] | 1095 | #define tcg_const_tl tcg_const_i32 |
aurel32 | bdffd4a | 2008-10-21 11:30:45 +0000 | [diff] [blame] | 1096 | #define tcg_const_local_tl tcg_const_local_i32 |
Richard Henderson | ffc5ea0 | 2012-09-21 10:13:34 -0700 | [diff] [blame] | 1097 | #define tcg_gen_movcond_tl tcg_gen_movcond_i32 |
Richard Henderson | f6953a7 | 2013-02-19 23:51:56 -0800 | [diff] [blame] | 1098 | #define tcg_gen_add2_tl tcg_gen_add2_i32 |
| 1099 | #define tcg_gen_sub2_tl tcg_gen_sub2_i32 |
Richard Henderson | 696a8be | 2013-02-19 23:51:55 -0800 | [diff] [blame] | 1100 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 |
| 1101 | #define tcg_gen_muls2_tl tcg_gen_muls2_i32 |
Richard Henderson | 5087abf | 2016-09-27 14:23:52 -0700 | [diff] [blame] | 1102 | #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 |
Richard Henderson | c482cb1 | 2016-06-28 11:37:27 -0700 | [diff] [blame] | 1103 | #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 |
| 1104 | #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 |
| 1105 | #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 |
| 1106 | #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32 |
| 1107 | #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32 |
| 1108 | #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32 |
| 1109 | #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32 |
| 1110 | #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32 |
| 1111 | #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32 |
| 1112 | #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 1113 | #endif |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 1114 | |
Richard Henderson | 71b9269 | 2013-09-09 08:26:49 -0700 | [diff] [blame] | 1115 | #if UINTPTR_MAX == UINT32_MAX |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 1116 | # define tcg_gen_ld_ptr(R, A, O) \ |
| 1117 | tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O)) |
| 1118 | # define tcg_gen_discard_ptr(A) \ |
| 1119 | tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A)) |
| 1120 | # define tcg_gen_add_ptr(R, A, B) \ |
| 1121 | tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B)) |
| 1122 | # define tcg_gen_addi_ptr(R, A, B) \ |
| 1123 | tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B)) |
| 1124 | # define tcg_gen_ext_i32_ptr(R, A) \ |
| 1125 | tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A)) |
| 1126 | #else |
| 1127 | # define tcg_gen_ld_ptr(R, A, O) \ |
| 1128 | tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O)) |
| 1129 | # define tcg_gen_discard_ptr(A) \ |
| 1130 | tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A)) |
| 1131 | # define tcg_gen_add_ptr(R, A, B) \ |
| 1132 | tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B)) |
| 1133 | # define tcg_gen_addi_ptr(R, A, B) \ |
| 1134 | tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B)) |
| 1135 | # define tcg_gen_ext_i32_ptr(R, A) \ |
| 1136 | tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A)) |
Richard Henderson | 71b9269 | 2013-09-09 08:26:49 -0700 | [diff] [blame] | 1137 | #endif /* UINTPTR_MAX == UINT32_MAX */ |