aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1 | /* |
| 2 | * PowerPC implementation of KVM hooks |
| 3 | * |
| 4 | * Copyright IBM Corp. 2007 |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 6 | * |
| 7 | * Authors: |
| 8 | * Jerone Young <jyoung5@us.ibm.com> |
| 9 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> |
| 10 | * Hollis Blanchard <hollisb@us.ibm.com> |
| 11 | * |
| 12 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 13 | * See the COPYING file in the top-level directory. |
| 14 | * |
| 15 | */ |
| 16 | |
Alexander Graf | eadaada | 2011-07-21 02:29:15 +0200 | [diff] [blame] | 17 | #include <dirent.h> |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 18 | #include <sys/types.h> |
| 19 | #include <sys/ioctl.h> |
| 20 | #include <sys/mman.h> |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 21 | #include <sys/vfs.h> |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 22 | |
| 23 | #include <linux/kvm.h> |
| 24 | |
| 25 | #include "qemu-common.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 26 | #include "qemu/timer.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 27 | #include "sysemu/sysemu.h" |
| 28 | #include "sysemu/kvm.h" |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 29 | #include "kvm_ppc.h" |
| 30 | #include "cpu.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 31 | #include "sysemu/cpus.h" |
| 32 | #include "sysemu/device_tree.h" |
David Gibson | d5aea6f | 2013-03-12 00:31:18 +0000 | [diff] [blame] | 33 | #include "mmu-hash64.h" |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 34 | |
Alexander Graf | f61b4be | 2011-08-09 17:57:37 +0200 | [diff] [blame] | 35 | #include "hw/sysbus.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 36 | #include "hw/ppc/spapr.h" |
| 37 | #include "hw/ppc/spapr_vio.h" |
Alexey Kardashevskiy | 98a8b52 | 2014-05-01 20:37:09 +1000 | [diff] [blame] | 38 | #include "hw/ppc/ppc.h" |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 39 | #include "sysemu/watchdog.h" |
Alexey Kardashevskiy | b36f100 | 2014-02-04 15:12:34 +1100 | [diff] [blame] | 40 | #include "trace.h" |
Bharat Bhushan | 88365d1 | 2014-07-14 14:45:37 +0530 | [diff] [blame] | 41 | #include "exec/gdbstub.h" |
Alexander Graf | f61b4be | 2011-08-09 17:57:37 +0200 | [diff] [blame] | 42 | |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 43 | //#define DEBUG_KVM |
| 44 | |
| 45 | #ifdef DEBUG_KVM |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 46 | #define DPRINTF(fmt, ...) \ |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 47 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
| 48 | #else |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 49 | #define DPRINTF(fmt, ...) \ |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 50 | do { } while (0) |
| 51 | #endif |
| 52 | |
Alexander Graf | eadaada | 2011-07-21 02:29:15 +0200 | [diff] [blame] | 53 | #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" |
| 54 | |
Jan Kiszka | 94a8d39 | 2011-01-21 21:48:17 +0100 | [diff] [blame] | 55 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
| 56 | KVM_CAP_LAST_INFO |
| 57 | }; |
| 58 | |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 59 | static int cap_interrupt_unset = false; |
| 60 | static int cap_interrupt_level = false; |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 61 | static int cap_segstate; |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 62 | static int cap_booke_sregs; |
David Gibson | e97c363 | 2011-09-29 21:39:10 +0000 | [diff] [blame] | 63 | static int cap_ppc_smt; |
David Gibson | 354ac20 | 2011-09-29 21:39:11 +0000 | [diff] [blame] | 64 | static int cap_ppc_rma; |
David Gibson | 0f5cb29 | 2011-09-29 21:39:12 +0000 | [diff] [blame] | 65 | static int cap_spapr_tce; |
Alexey Kardashevskiy | da95324 | 2014-05-27 15:36:30 +1000 | [diff] [blame] | 66 | static int cap_spapr_multitce; |
Alexey Kardashevskiy | 9bb62a0 | 2014-06-10 15:39:21 +1000 | [diff] [blame] | 67 | static int cap_spapr_vfio; |
David Gibson | f1af19d | 2012-09-12 16:57:09 +0000 | [diff] [blame] | 68 | static int cap_hior; |
David Gibson | d67d40e | 2013-02-20 16:41:50 +0000 | [diff] [blame] | 69 | static int cap_one_reg; |
Stuart Yoder | 3b96112 | 2013-03-30 06:40:49 +0000 | [diff] [blame] | 70 | static int cap_epr; |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 71 | static int cap_ppc_watchdog; |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 72 | static int cap_papr; |
Alexey Kardashevskiy | e68cb8b | 2013-07-18 14:33:03 -0500 | [diff] [blame] | 73 | static int cap_htab_fd; |
Alexander Graf | 87a91de | 2014-06-04 12:14:08 +0200 | [diff] [blame] | 74 | static int cap_fixup_hcalls; |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 75 | |
Bharat Bhushan | 3c902d4 | 2014-07-14 14:45:35 +0530 | [diff] [blame] | 76 | static uint32_t debug_inst_opcode; |
| 77 | |
Alexander Graf | c821c2b | 2010-04-18 23:10:17 +0200 | [diff] [blame] | 78 | /* XXX We have a race condition where we actually have a level triggered |
| 79 | * interrupt, but the infrastructure can't expose that yet, so the guest |
| 80 | * takes but ignores it, goes to sleep and never gets notified that there's |
| 81 | * still an interrupt pending. |
Alexander Graf | c6a94ba | 2010-02-09 17:37:10 +0100 | [diff] [blame] | 82 | * |
Alexander Graf | c821c2b | 2010-04-18 23:10:17 +0200 | [diff] [blame] | 83 | * As a quick workaround, let's just wake up again 20 ms after we injected |
| 84 | * an interrupt. That way we can assure that we're always reinjecting |
| 85 | * interrupts in case the guest swallowed them. |
Alexander Graf | c6a94ba | 2010-02-09 17:37:10 +0100 | [diff] [blame] | 86 | */ |
| 87 | static QEMUTimer *idle_timer; |
| 88 | |
Andreas Färber | d5a6814 | 2012-05-03 04:02:03 +0200 | [diff] [blame] | 89 | static void kvm_kick_cpu(void *opaque) |
Alexander Graf | c6a94ba | 2010-02-09 17:37:10 +0100 | [diff] [blame] | 90 | { |
Andreas Färber | d5a6814 | 2012-05-03 04:02:03 +0200 | [diff] [blame] | 91 | PowerPCCPU *cpu = opaque; |
Andreas Färber | d5a6814 | 2012-05-03 04:02:03 +0200 | [diff] [blame] | 92 | |
Andreas Färber | c08d742 | 2012-05-03 04:34:15 +0200 | [diff] [blame] | 93 | qemu_cpu_kick(CPU(cpu)); |
Alexander Graf | c6a94ba | 2010-02-09 17:37:10 +0100 | [diff] [blame] | 94 | } |
| 95 | |
Andreas Färber | 5ba4576 | 2013-02-23 11:22:12 +0000 | [diff] [blame] | 96 | static int kvm_ppc_register_host_cpu_type(void); |
| 97 | |
Jan Kiszka | cad1e28 | 2011-01-21 21:48:16 +0100 | [diff] [blame] | 98 | int kvm_arch_init(KVMState *s) |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 99 | { |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 100 | cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 101 | cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 102 | cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 103 | cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); |
David Gibson | e97c363 | 2011-09-29 21:39:10 +0000 | [diff] [blame] | 104 | cap_ppc_smt = kvm_check_extension(s, KVM_CAP_PPC_SMT); |
David Gibson | 354ac20 | 2011-09-29 21:39:11 +0000 | [diff] [blame] | 105 | cap_ppc_rma = kvm_check_extension(s, KVM_CAP_PPC_RMA); |
David Gibson | 0f5cb29 | 2011-09-29 21:39:12 +0000 | [diff] [blame] | 106 | cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); |
Alexey Kardashevskiy | da95324 | 2014-05-27 15:36:30 +1000 | [diff] [blame] | 107 | cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE); |
Alexey Kardashevskiy | 9bb62a0 | 2014-06-10 15:39:21 +1000 | [diff] [blame] | 108 | cap_spapr_vfio = false; |
David Gibson | d67d40e | 2013-02-20 16:41:50 +0000 | [diff] [blame] | 109 | cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG); |
David Gibson | f1af19d | 2012-09-12 16:57:09 +0000 | [diff] [blame] | 110 | cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); |
Stuart Yoder | 3b96112 | 2013-03-30 06:40:49 +0000 | [diff] [blame] | 111 | cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR); |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 112 | cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 113 | /* Note: we don't set cap_papr here, because this capability is |
| 114 | * only activated after this by kvmppc_set_papr() */ |
Alexey Kardashevskiy | e68cb8b | 2013-07-18 14:33:03 -0500 | [diff] [blame] | 115 | cap_htab_fd = kvm_check_extension(s, KVM_CAP_PPC_HTAB_FD); |
Alexander Graf | 87a91de | 2014-06-04 12:14:08 +0200 | [diff] [blame] | 116 | cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL); |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 117 | |
| 118 | if (!cap_interrupt_level) { |
| 119 | fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the " |
| 120 | "VM to stall at times!\n"); |
| 121 | } |
| 122 | |
Andreas Färber | 5ba4576 | 2013-02-23 11:22:12 +0000 | [diff] [blame] | 123 | kvm_ppc_register_host_cpu_type(); |
| 124 | |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 125 | return 0; |
| 126 | } |
| 127 | |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 128 | static int kvm_arch_sync_sregs(PowerPCCPU *cpu) |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 129 | { |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 130 | CPUPPCState *cenv = &cpu->env; |
| 131 | CPUState *cs = CPU(cpu); |
Alexander Graf | 861bbc80 | 2009-07-17 13:51:43 +0200 | [diff] [blame] | 132 | struct kvm_sregs sregs; |
Scott Wood | 5666ca4 | 2011-04-11 18:34:34 -0500 | [diff] [blame] | 133 | int ret; |
| 134 | |
| 135 | if (cenv->excp_model == POWERPC_EXCP_BOOKE) { |
Alexander Graf | 64e07be | 2011-04-16 02:00:36 +0200 | [diff] [blame] | 136 | /* What we're really trying to say is "if we're on BookE, we use |
| 137 | the native PVR for now". This is the only sane way to check |
| 138 | it though, so we potentially confuse users that they can run |
| 139 | BookE guests on BookS. Let's hope nobody dares enough :) */ |
Scott Wood | 5666ca4 | 2011-04-11 18:34:34 -0500 | [diff] [blame] | 140 | return 0; |
| 141 | } else { |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 142 | if (!cap_segstate) { |
Alexander Graf | 64e07be | 2011-04-16 02:00:36 +0200 | [diff] [blame] | 143 | fprintf(stderr, "kvm error: missing PVR setting capability\n"); |
| 144 | return -ENOSYS; |
Scott Wood | 5666ca4 | 2011-04-11 18:34:34 -0500 | [diff] [blame] | 145 | } |
Scott Wood | 5666ca4 | 2011-04-11 18:34:34 -0500 | [diff] [blame] | 146 | } |
| 147 | |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 148 | ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); |
Scott Wood | 5666ca4 | 2011-04-11 18:34:34 -0500 | [diff] [blame] | 149 | if (ret) { |
| 150 | return ret; |
| 151 | } |
Alexander Graf | 861bbc80 | 2009-07-17 13:51:43 +0200 | [diff] [blame] | 152 | |
| 153 | sregs.pvr = cenv->spr[SPR_PVR]; |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 154 | return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); |
Scott Wood | 5666ca4 | 2011-04-11 18:34:34 -0500 | [diff] [blame] | 155 | } |
| 156 | |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 157 | /* Set up a shared TLB array with KVM */ |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 158 | static int kvm_booke206_tlb_init(PowerPCCPU *cpu) |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 159 | { |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 160 | CPUPPCState *env = &cpu->env; |
| 161 | CPUState *cs = CPU(cpu); |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 162 | struct kvm_book3e_206_tlb_params params = {}; |
| 163 | struct kvm_config_tlb cfg = {}; |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 164 | unsigned int entries = 0; |
| 165 | int ret, i; |
| 166 | |
| 167 | if (!kvm_enabled() || |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 168 | !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) { |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 169 | return 0; |
| 170 | } |
| 171 | |
| 172 | assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); |
| 173 | |
| 174 | for (i = 0; i < BOOKE206_MAX_TLBN; i++) { |
| 175 | params.tlb_sizes[i] = booke206_tlb_size(env, i); |
| 176 | params.tlb_ways[i] = booke206_tlb_ways(env, i); |
| 177 | entries += params.tlb_sizes[i]; |
| 178 | } |
| 179 | |
| 180 | assert(entries == env->nb_tlb); |
| 181 | assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); |
| 182 | |
| 183 | env->tlb_dirty = true; |
| 184 | |
| 185 | cfg.array = (uintptr_t)env->tlb.tlbm; |
| 186 | cfg.array_len = sizeof(ppcmas_tlb_t) * entries; |
| 187 | cfg.params = (uintptr_t)¶ms; |
| 188 | cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; |
| 189 | |
Cornelia Huck | 48add81 | 2014-04-09 17:21:57 +0200 | [diff] [blame] | 190 | ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg); |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 191 | if (ret < 0) { |
| 192 | fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n", |
| 193 | __func__, strerror(-ret)); |
| 194 | return ret; |
| 195 | } |
| 196 | |
| 197 | env->kvm_sw_tlb = true; |
| 198 | return 0; |
| 199 | } |
| 200 | |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 201 | |
| 202 | #if defined(TARGET_PPC64) |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 203 | static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 204 | struct kvm_ppc_smmu_info *info) |
| 205 | { |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 206 | CPUPPCState *env = &cpu->env; |
| 207 | CPUState *cs = CPU(cpu); |
| 208 | |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 209 | memset(info, 0, sizeof(*info)); |
| 210 | |
| 211 | /* We don't have the new KVM_PPC_GET_SMMU_INFO ioctl, so |
| 212 | * need to "guess" what the supported page sizes are. |
| 213 | * |
| 214 | * For that to work we make a few assumptions: |
| 215 | * |
| 216 | * - If KVM_CAP_PPC_GET_PVINFO is supported we are running "PR" |
| 217 | * KVM which only supports 4K and 16M pages, but supports them |
| 218 | * regardless of the backing store characteritics. We also don't |
| 219 | * support 1T segments. |
| 220 | * |
| 221 | * This is safe as if HV KVM ever supports that capability or PR |
| 222 | * KVM grows supports for more page/segment sizes, those versions |
| 223 | * will have implemented KVM_CAP_PPC_GET_SMMU_INFO and thus we |
| 224 | * will not hit this fallback |
| 225 | * |
| 226 | * - Else we are running HV KVM. This means we only support page |
| 227 | * sizes that fit in the backing store. Additionally we only |
| 228 | * advertize 64K pages if the processor is ARCH 2.06 and we assume |
| 229 | * P7 encodings for the SLB and hash table. Here too, we assume |
| 230 | * support for any newer processor will mean a kernel that |
| 231 | * implements KVM_CAP_PPC_GET_SMMU_INFO and thus doesn't hit |
| 232 | * this fallback. |
| 233 | */ |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 234 | if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO)) { |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 235 | /* No flags */ |
| 236 | info->flags = 0; |
| 237 | info->slb_size = 64; |
| 238 | |
| 239 | /* Standard 4k base page size segment */ |
| 240 | info->sps[0].page_shift = 12; |
| 241 | info->sps[0].slb_enc = 0; |
| 242 | info->sps[0].enc[0].page_shift = 12; |
| 243 | info->sps[0].enc[0].pte_enc = 0; |
| 244 | |
| 245 | /* Standard 16M large page size segment */ |
| 246 | info->sps[1].page_shift = 24; |
| 247 | info->sps[1].slb_enc = SLB_VSID_L; |
| 248 | info->sps[1].enc[0].page_shift = 24; |
| 249 | info->sps[1].enc[0].pte_enc = 0; |
| 250 | } else { |
| 251 | int i = 0; |
| 252 | |
| 253 | /* HV KVM has backing store size restrictions */ |
| 254 | info->flags = KVM_PPC_PAGE_SIZES_REAL; |
| 255 | |
| 256 | if (env->mmu_model & POWERPC_MMU_1TSEG) { |
| 257 | info->flags |= KVM_PPC_1T_SEGMENTS; |
| 258 | } |
| 259 | |
| 260 | if (env->mmu_model == POWERPC_MMU_2_06) { |
| 261 | info->slb_size = 32; |
| 262 | } else { |
| 263 | info->slb_size = 64; |
| 264 | } |
| 265 | |
| 266 | /* Standard 4k base page size segment */ |
| 267 | info->sps[i].page_shift = 12; |
| 268 | info->sps[i].slb_enc = 0; |
| 269 | info->sps[i].enc[0].page_shift = 12; |
| 270 | info->sps[i].enc[0].pte_enc = 0; |
| 271 | i++; |
| 272 | |
| 273 | /* 64K on MMU 2.06 */ |
| 274 | if (env->mmu_model == POWERPC_MMU_2_06) { |
| 275 | info->sps[i].page_shift = 16; |
| 276 | info->sps[i].slb_enc = 0x110; |
| 277 | info->sps[i].enc[0].page_shift = 16; |
| 278 | info->sps[i].enc[0].pte_enc = 1; |
| 279 | i++; |
| 280 | } |
| 281 | |
| 282 | /* Standard 16M large page size segment */ |
| 283 | info->sps[i].page_shift = 24; |
| 284 | info->sps[i].slb_enc = SLB_VSID_L; |
| 285 | info->sps[i].enc[0].page_shift = 24; |
| 286 | info->sps[i].enc[0].pte_enc = 0; |
| 287 | } |
| 288 | } |
| 289 | |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 290 | static void kvm_get_smmu_info(PowerPCCPU *cpu, struct kvm_ppc_smmu_info *info) |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 291 | { |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 292 | CPUState *cs = CPU(cpu); |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 293 | int ret; |
| 294 | |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 295 | if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) { |
| 296 | ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_SMMU_INFO, info); |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 297 | if (ret == 0) { |
| 298 | return; |
| 299 | } |
| 300 | } |
| 301 | |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 302 | kvm_get_fallback_smmu_info(cpu, info); |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 303 | } |
| 304 | |
| 305 | static long getrampagesize(void) |
| 306 | { |
| 307 | struct statfs fs; |
| 308 | int ret; |
| 309 | |
| 310 | if (!mem_path) { |
| 311 | /* guest RAM is backed by normal anonymous pages */ |
| 312 | return getpagesize(); |
| 313 | } |
| 314 | |
| 315 | do { |
| 316 | ret = statfs(mem_path, &fs); |
| 317 | } while (ret != 0 && errno == EINTR); |
| 318 | |
| 319 | if (ret != 0) { |
| 320 | fprintf(stderr, "Couldn't statfs() memory path: %s\n", |
| 321 | strerror(errno)); |
| 322 | exit(1); |
| 323 | } |
| 324 | |
| 325 | #define HUGETLBFS_MAGIC 0x958458f6 |
| 326 | |
| 327 | if (fs.f_type != HUGETLBFS_MAGIC) { |
| 328 | /* Explicit mempath, but it's ordinary pages */ |
| 329 | return getpagesize(); |
| 330 | } |
| 331 | |
| 332 | /* It's hugepage, return the huge page size */ |
| 333 | return fs.f_bsize; |
| 334 | } |
| 335 | |
| 336 | static bool kvm_valid_page_size(uint32_t flags, long rampgsize, uint32_t shift) |
| 337 | { |
| 338 | if (!(flags & KVM_PPC_PAGE_SIZES_REAL)) { |
| 339 | return true; |
| 340 | } |
| 341 | |
| 342 | return (1ul << shift) <= rampgsize; |
| 343 | } |
| 344 | |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 345 | static void kvm_fixup_page_sizes(PowerPCCPU *cpu) |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 346 | { |
| 347 | static struct kvm_ppc_smmu_info smmu_info; |
| 348 | static bool has_smmu_info; |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 349 | CPUPPCState *env = &cpu->env; |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 350 | long rampagesize; |
| 351 | int iq, ik, jq, jk; |
| 352 | |
| 353 | /* We only handle page sizes for 64-bit server guests for now */ |
| 354 | if (!(env->mmu_model & POWERPC_MMU_64)) { |
| 355 | return; |
| 356 | } |
| 357 | |
| 358 | /* Collect MMU info from kernel if not already */ |
| 359 | if (!has_smmu_info) { |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 360 | kvm_get_smmu_info(cpu, &smmu_info); |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 361 | has_smmu_info = true; |
| 362 | } |
| 363 | |
| 364 | rampagesize = getrampagesize(); |
| 365 | |
| 366 | /* Convert to QEMU form */ |
| 367 | memset(&env->sps, 0, sizeof(env->sps)); |
| 368 | |
Alexander Graf | 08215d8 | 2014-05-11 18:37:00 +0200 | [diff] [blame] | 369 | /* |
| 370 | * XXX This loop should be an entry wide AND of the capabilities that |
| 371 | * the selected CPU has with the capabilities that KVM supports. |
| 372 | */ |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 373 | for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) { |
| 374 | struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq]; |
| 375 | struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik]; |
| 376 | |
| 377 | if (!kvm_valid_page_size(smmu_info.flags, rampagesize, |
| 378 | ksps->page_shift)) { |
| 379 | continue; |
| 380 | } |
| 381 | qsps->page_shift = ksps->page_shift; |
| 382 | qsps->slb_enc = ksps->slb_enc; |
| 383 | for (jk = jq = 0; jk < KVM_PPC_PAGE_SIZES_MAX_SZ; jk++) { |
| 384 | if (!kvm_valid_page_size(smmu_info.flags, rampagesize, |
| 385 | ksps->enc[jk].page_shift)) { |
| 386 | continue; |
| 387 | } |
| 388 | qsps->enc[jq].page_shift = ksps->enc[jk].page_shift; |
| 389 | qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc; |
| 390 | if (++jq >= PPC_PAGE_SIZES_MAX_SZ) { |
| 391 | break; |
| 392 | } |
| 393 | } |
| 394 | if (++iq >= PPC_PAGE_SIZES_MAX_SZ) { |
| 395 | break; |
| 396 | } |
| 397 | } |
| 398 | env->slb_nr = smmu_info.slb_size; |
Alexander Graf | 08215d8 | 2014-05-11 18:37:00 +0200 | [diff] [blame] | 399 | if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 400 | env->mmu_model &= ~POWERPC_MMU_1TSEG; |
| 401 | } |
| 402 | } |
| 403 | #else /* defined (TARGET_PPC64) */ |
| 404 | |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 405 | static inline void kvm_fixup_page_sizes(PowerPCCPU *cpu) |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 406 | { |
| 407 | } |
| 408 | |
| 409 | #endif /* !defined (TARGET_PPC64) */ |
| 410 | |
Eduardo Habkost | b164e48 | 2013-01-22 18:25:01 -0200 | [diff] [blame] | 411 | unsigned long kvm_arch_vcpu_id(CPUState *cpu) |
| 412 | { |
Alexey Kardashevskiy | 0f20ba6 | 2014-02-02 01:45:52 +1100 | [diff] [blame] | 413 | return ppc_get_vcpu_dt_id(POWERPC_CPU(cpu)); |
Eduardo Habkost | b164e48 | 2013-01-22 18:25:01 -0200 | [diff] [blame] | 414 | } |
| 415 | |
Bharat Bhushan | 88365d1 | 2014-07-14 14:45:37 +0530 | [diff] [blame] | 416 | /* e500 supports 2 h/w breakpoint and 2 watchpoint. |
| 417 | * book3s supports only 1 watchpoint, so array size |
| 418 | * of 4 is sufficient for now. |
| 419 | */ |
| 420 | #define MAX_HW_BKPTS 4 |
| 421 | |
| 422 | static struct HWBreakpoint { |
| 423 | target_ulong addr; |
| 424 | int type; |
| 425 | } hw_debug_points[MAX_HW_BKPTS]; |
| 426 | |
| 427 | static CPUWatchpoint hw_watchpoint; |
| 428 | |
| 429 | /* Default there is no breakpoint and watchpoint supported */ |
| 430 | static int max_hw_breakpoint; |
| 431 | static int max_hw_watchpoint; |
| 432 | static int nb_hw_breakpoint; |
| 433 | static int nb_hw_watchpoint; |
| 434 | |
| 435 | static void kvmppc_hw_debug_points_init(CPUPPCState *cenv) |
| 436 | { |
| 437 | if (cenv->excp_model == POWERPC_EXCP_BOOKE) { |
| 438 | max_hw_breakpoint = 2; |
| 439 | max_hw_watchpoint = 2; |
| 440 | } |
| 441 | |
| 442 | if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) { |
| 443 | fprintf(stderr, "Error initializing h/w breakpoints\n"); |
| 444 | return; |
| 445 | } |
| 446 | } |
| 447 | |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 448 | int kvm_arch_init_vcpu(CPUState *cs) |
Scott Wood | 5666ca4 | 2011-04-11 18:34:34 -0500 | [diff] [blame] | 449 | { |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 450 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 451 | CPUPPCState *cenv = &cpu->env; |
Scott Wood | 5666ca4 | 2011-04-11 18:34:34 -0500 | [diff] [blame] | 452 | int ret; |
| 453 | |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 454 | /* Gather server mmu info from KVM and update the CPU state */ |
Andreas Färber | a60f24b | 2012-12-01 05:35:08 +0100 | [diff] [blame] | 455 | kvm_fixup_page_sizes(cpu); |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 456 | |
| 457 | /* Synchronize sregs with kvm */ |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 458 | ret = kvm_arch_sync_sregs(cpu); |
Scott Wood | 5666ca4 | 2011-04-11 18:34:34 -0500 | [diff] [blame] | 459 | if (ret) { |
| 460 | return ret; |
| 461 | } |
Alexander Graf | 861bbc80 | 2009-07-17 13:51:43 +0200 | [diff] [blame] | 462 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 463 | idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, kvm_kick_cpu, cpu); |
Alexander Graf | c821c2b | 2010-04-18 23:10:17 +0200 | [diff] [blame] | 464 | |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 465 | /* Some targets support access to KVM's guest TLB. */ |
| 466 | switch (cenv->mmu_model) { |
| 467 | case POWERPC_MMU_BOOKE206: |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 468 | ret = kvm_booke206_tlb_init(cpu); |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 469 | break; |
| 470 | default: |
| 471 | break; |
| 472 | } |
| 473 | |
Bharat Bhushan | 3c902d4 | 2014-07-14 14:45:35 +0530 | [diff] [blame] | 474 | kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode); |
Bharat Bhushan | 88365d1 | 2014-07-14 14:45:37 +0530 | [diff] [blame] | 475 | kvmppc_hw_debug_points_init(cenv); |
Bharat Bhushan | 3c902d4 | 2014-07-14 14:45:35 +0530 | [diff] [blame] | 476 | |
Alexander Graf | 861bbc80 | 2009-07-17 13:51:43 +0200 | [diff] [blame] | 477 | return ret; |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 478 | } |
| 479 | |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 480 | static void kvm_sw_tlb_put(PowerPCCPU *cpu) |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 481 | { |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 482 | CPUPPCState *env = &cpu->env; |
| 483 | CPUState *cs = CPU(cpu); |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 484 | struct kvm_dirty_tlb dirty_tlb; |
| 485 | unsigned char *bitmap; |
| 486 | int ret; |
| 487 | |
| 488 | if (!env->kvm_sw_tlb) { |
| 489 | return; |
| 490 | } |
| 491 | |
| 492 | bitmap = g_malloc((env->nb_tlb + 7) / 8); |
| 493 | memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); |
| 494 | |
| 495 | dirty_tlb.bitmap = (uintptr_t)bitmap; |
| 496 | dirty_tlb.num_dirty = env->nb_tlb; |
| 497 | |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 498 | ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb); |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 499 | if (ret) { |
| 500 | fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", |
| 501 | __func__, strerror(-ret)); |
| 502 | } |
| 503 | |
| 504 | g_free(bitmap); |
| 505 | } |
| 506 | |
David Gibson | d67d40e | 2013-02-20 16:41:50 +0000 | [diff] [blame] | 507 | static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) |
| 508 | { |
| 509 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 510 | CPUPPCState *env = &cpu->env; |
| 511 | union { |
| 512 | uint32_t u32; |
| 513 | uint64_t u64; |
| 514 | } val; |
| 515 | struct kvm_one_reg reg = { |
| 516 | .id = id, |
| 517 | .addr = (uintptr_t) &val, |
| 518 | }; |
| 519 | int ret; |
| 520 | |
| 521 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
| 522 | if (ret != 0) { |
Alexey Kardashevskiy | b36f100 | 2014-02-04 15:12:34 +1100 | [diff] [blame] | 523 | trace_kvm_failed_spr_get(spr, strerror(errno)); |
David Gibson | d67d40e | 2013-02-20 16:41:50 +0000 | [diff] [blame] | 524 | } else { |
| 525 | switch (id & KVM_REG_SIZE_MASK) { |
| 526 | case KVM_REG_SIZE_U32: |
| 527 | env->spr[spr] = val.u32; |
| 528 | break; |
| 529 | |
| 530 | case KVM_REG_SIZE_U64: |
| 531 | env->spr[spr] = val.u64; |
| 532 | break; |
| 533 | |
| 534 | default: |
| 535 | /* Don't handle this size yet */ |
| 536 | abort(); |
| 537 | } |
| 538 | } |
| 539 | } |
| 540 | |
| 541 | static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) |
| 542 | { |
| 543 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 544 | CPUPPCState *env = &cpu->env; |
| 545 | union { |
| 546 | uint32_t u32; |
| 547 | uint64_t u64; |
| 548 | } val; |
| 549 | struct kvm_one_reg reg = { |
| 550 | .id = id, |
| 551 | .addr = (uintptr_t) &val, |
| 552 | }; |
| 553 | int ret; |
| 554 | |
| 555 | switch (id & KVM_REG_SIZE_MASK) { |
| 556 | case KVM_REG_SIZE_U32: |
| 557 | val.u32 = env->spr[spr]; |
| 558 | break; |
| 559 | |
| 560 | case KVM_REG_SIZE_U64: |
| 561 | val.u64 = env->spr[spr]; |
| 562 | break; |
| 563 | |
| 564 | default: |
| 565 | /* Don't handle this size yet */ |
| 566 | abort(); |
| 567 | } |
| 568 | |
| 569 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
| 570 | if (ret != 0) { |
Alexey Kardashevskiy | b36f100 | 2014-02-04 15:12:34 +1100 | [diff] [blame] | 571 | trace_kvm_failed_spr_set(spr, strerror(errno)); |
David Gibson | d67d40e | 2013-02-20 16:41:50 +0000 | [diff] [blame] | 572 | } |
| 573 | } |
| 574 | |
David Gibson | 70b7984 | 2013-02-20 16:41:51 +0000 | [diff] [blame] | 575 | static int kvm_put_fp(CPUState *cs) |
| 576 | { |
| 577 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 578 | CPUPPCState *env = &cpu->env; |
| 579 | struct kvm_one_reg reg; |
| 580 | int i; |
| 581 | int ret; |
| 582 | |
| 583 | if (env->insns_flags & PPC_FLOAT) { |
| 584 | uint64_t fpscr = env->fpscr; |
| 585 | bool vsx = !!(env->insns_flags2 & PPC2_VSX); |
| 586 | |
| 587 | reg.id = KVM_REG_PPC_FPSCR; |
| 588 | reg.addr = (uintptr_t)&fpscr; |
| 589 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
| 590 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 591 | DPRINTF("Unable to set FPSCR to KVM: %s\n", strerror(errno)); |
David Gibson | 70b7984 | 2013-02-20 16:41:51 +0000 | [diff] [blame] | 592 | return ret; |
| 593 | } |
| 594 | |
| 595 | for (i = 0; i < 32; i++) { |
| 596 | uint64_t vsr[2]; |
| 597 | |
| 598 | vsr[0] = float64_val(env->fpr[i]); |
| 599 | vsr[1] = env->vsr[i]; |
| 600 | reg.addr = (uintptr_t) &vsr; |
| 601 | reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); |
| 602 | |
| 603 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
| 604 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 605 | DPRINTF("Unable to set %s%d to KVM: %s\n", vsx ? "VSR" : "FPR", |
David Gibson | 70b7984 | 2013-02-20 16:41:51 +0000 | [diff] [blame] | 606 | i, strerror(errno)); |
| 607 | return ret; |
| 608 | } |
| 609 | } |
| 610 | } |
| 611 | |
| 612 | if (env->insns_flags & PPC_ALTIVEC) { |
| 613 | reg.id = KVM_REG_PPC_VSCR; |
| 614 | reg.addr = (uintptr_t)&env->vscr; |
| 615 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
| 616 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 617 | DPRINTF("Unable to set VSCR to KVM: %s\n", strerror(errno)); |
David Gibson | 70b7984 | 2013-02-20 16:41:51 +0000 | [diff] [blame] | 618 | return ret; |
| 619 | } |
| 620 | |
| 621 | for (i = 0; i < 32; i++) { |
| 622 | reg.id = KVM_REG_PPC_VR(i); |
| 623 | reg.addr = (uintptr_t)&env->avr[i]; |
| 624 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
| 625 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 626 | DPRINTF("Unable to set VR%d to KVM: %s\n", i, strerror(errno)); |
David Gibson | 70b7984 | 2013-02-20 16:41:51 +0000 | [diff] [blame] | 627 | return ret; |
| 628 | } |
| 629 | } |
| 630 | } |
| 631 | |
| 632 | return 0; |
| 633 | } |
| 634 | |
| 635 | static int kvm_get_fp(CPUState *cs) |
| 636 | { |
| 637 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 638 | CPUPPCState *env = &cpu->env; |
| 639 | struct kvm_one_reg reg; |
| 640 | int i; |
| 641 | int ret; |
| 642 | |
| 643 | if (env->insns_flags & PPC_FLOAT) { |
| 644 | uint64_t fpscr; |
| 645 | bool vsx = !!(env->insns_flags2 & PPC2_VSX); |
| 646 | |
| 647 | reg.id = KVM_REG_PPC_FPSCR; |
| 648 | reg.addr = (uintptr_t)&fpscr; |
| 649 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
| 650 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 651 | DPRINTF("Unable to get FPSCR from KVM: %s\n", strerror(errno)); |
David Gibson | 70b7984 | 2013-02-20 16:41:51 +0000 | [diff] [blame] | 652 | return ret; |
| 653 | } else { |
| 654 | env->fpscr = fpscr; |
| 655 | } |
| 656 | |
| 657 | for (i = 0; i < 32; i++) { |
| 658 | uint64_t vsr[2]; |
| 659 | |
| 660 | reg.addr = (uintptr_t) &vsr; |
| 661 | reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); |
| 662 | |
| 663 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
| 664 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 665 | DPRINTF("Unable to get %s%d from KVM: %s\n", |
David Gibson | 70b7984 | 2013-02-20 16:41:51 +0000 | [diff] [blame] | 666 | vsx ? "VSR" : "FPR", i, strerror(errno)); |
| 667 | return ret; |
| 668 | } else { |
| 669 | env->fpr[i] = vsr[0]; |
| 670 | if (vsx) { |
| 671 | env->vsr[i] = vsr[1]; |
| 672 | } |
| 673 | } |
| 674 | } |
| 675 | } |
| 676 | |
| 677 | if (env->insns_flags & PPC_ALTIVEC) { |
| 678 | reg.id = KVM_REG_PPC_VSCR; |
| 679 | reg.addr = (uintptr_t)&env->vscr; |
| 680 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
| 681 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 682 | DPRINTF("Unable to get VSCR from KVM: %s\n", strerror(errno)); |
David Gibson | 70b7984 | 2013-02-20 16:41:51 +0000 | [diff] [blame] | 683 | return ret; |
| 684 | } |
| 685 | |
| 686 | for (i = 0; i < 32; i++) { |
| 687 | reg.id = KVM_REG_PPC_VR(i); |
| 688 | reg.addr = (uintptr_t)&env->avr[i]; |
| 689 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
| 690 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 691 | DPRINTF("Unable to get VR%d from KVM: %s\n", |
David Gibson | 70b7984 | 2013-02-20 16:41:51 +0000 | [diff] [blame] | 692 | i, strerror(errno)); |
| 693 | return ret; |
| 694 | } |
| 695 | } |
| 696 | } |
| 697 | |
| 698 | return 0; |
| 699 | } |
| 700 | |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 701 | #if defined(TARGET_PPC64) |
| 702 | static int kvm_get_vpa(CPUState *cs) |
| 703 | { |
| 704 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 705 | CPUPPCState *env = &cpu->env; |
| 706 | struct kvm_one_reg reg; |
| 707 | int ret; |
| 708 | |
| 709 | reg.id = KVM_REG_PPC_VPA_ADDR; |
| 710 | reg.addr = (uintptr_t)&env->vpa_addr; |
| 711 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
| 712 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 713 | DPRINTF("Unable to get VPA address from KVM: %s\n", strerror(errno)); |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 714 | return ret; |
| 715 | } |
| 716 | |
| 717 | assert((uintptr_t)&env->slb_shadow_size |
| 718 | == ((uintptr_t)&env->slb_shadow_addr + 8)); |
| 719 | reg.id = KVM_REG_PPC_VPA_SLB; |
| 720 | reg.addr = (uintptr_t)&env->slb_shadow_addr; |
| 721 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
| 722 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 723 | DPRINTF("Unable to get SLB shadow state from KVM: %s\n", |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 724 | strerror(errno)); |
| 725 | return ret; |
| 726 | } |
| 727 | |
| 728 | assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8)); |
| 729 | reg.id = KVM_REG_PPC_VPA_DTL; |
| 730 | reg.addr = (uintptr_t)&env->dtl_addr; |
| 731 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); |
| 732 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 733 | DPRINTF("Unable to get dispatch trace log state from KVM: %s\n", |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 734 | strerror(errno)); |
| 735 | return ret; |
| 736 | } |
| 737 | |
| 738 | return 0; |
| 739 | } |
| 740 | |
| 741 | static int kvm_put_vpa(CPUState *cs) |
| 742 | { |
| 743 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 744 | CPUPPCState *env = &cpu->env; |
| 745 | struct kvm_one_reg reg; |
| 746 | int ret; |
| 747 | |
| 748 | /* SLB shadow or DTL can't be registered unless a master VPA is |
| 749 | * registered. That means when restoring state, if a VPA *is* |
| 750 | * registered, we need to set that up first. If not, we need to |
| 751 | * deregister the others before deregistering the master VPA */ |
| 752 | assert(env->vpa_addr || !(env->slb_shadow_addr || env->dtl_addr)); |
| 753 | |
| 754 | if (env->vpa_addr) { |
| 755 | reg.id = KVM_REG_PPC_VPA_ADDR; |
| 756 | reg.addr = (uintptr_t)&env->vpa_addr; |
| 757 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
| 758 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 759 | DPRINTF("Unable to set VPA address to KVM: %s\n", strerror(errno)); |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 760 | return ret; |
| 761 | } |
| 762 | } |
| 763 | |
| 764 | assert((uintptr_t)&env->slb_shadow_size |
| 765 | == ((uintptr_t)&env->slb_shadow_addr + 8)); |
| 766 | reg.id = KVM_REG_PPC_VPA_SLB; |
| 767 | reg.addr = (uintptr_t)&env->slb_shadow_addr; |
| 768 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
| 769 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 770 | DPRINTF("Unable to set SLB shadow state to KVM: %s\n", strerror(errno)); |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 771 | return ret; |
| 772 | } |
| 773 | |
| 774 | assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8)); |
| 775 | reg.id = KVM_REG_PPC_VPA_DTL; |
| 776 | reg.addr = (uintptr_t)&env->dtl_addr; |
| 777 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
| 778 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 779 | DPRINTF("Unable to set dispatch trace log state to KVM: %s\n", |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 780 | strerror(errno)); |
| 781 | return ret; |
| 782 | } |
| 783 | |
| 784 | if (!env->vpa_addr) { |
| 785 | reg.id = KVM_REG_PPC_VPA_ADDR; |
| 786 | reg.addr = (uintptr_t)&env->vpa_addr; |
| 787 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
| 788 | if (ret < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 789 | DPRINTF("Unable to set VPA address to KVM: %s\n", strerror(errno)); |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 790 | return ret; |
| 791 | } |
| 792 | } |
| 793 | |
| 794 | return 0; |
| 795 | } |
| 796 | #endif /* TARGET_PPC64 */ |
| 797 | |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 798 | int kvm_arch_put_registers(CPUState *cs, int level) |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 799 | { |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 800 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 801 | CPUPPCState *env = &cpu->env; |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 802 | struct kvm_regs regs; |
| 803 | int ret; |
| 804 | int i; |
| 805 | |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 806 | ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); |
| 807 | if (ret < 0) { |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 808 | return ret; |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 809 | } |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 810 | |
| 811 | regs.ctr = env->ctr; |
| 812 | regs.lr = env->lr; |
Richard Henderson | da91a00 | 2013-02-19 23:52:13 -0800 | [diff] [blame] | 813 | regs.xer = cpu_read_xer(env); |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 814 | regs.msr = env->msr; |
| 815 | regs.pc = env->nip; |
| 816 | |
| 817 | regs.srr0 = env->spr[SPR_SRR0]; |
| 818 | regs.srr1 = env->spr[SPR_SRR1]; |
| 819 | |
| 820 | regs.sprg0 = env->spr[SPR_SPRG0]; |
| 821 | regs.sprg1 = env->spr[SPR_SPRG1]; |
| 822 | regs.sprg2 = env->spr[SPR_SPRG2]; |
| 823 | regs.sprg3 = env->spr[SPR_SPRG3]; |
| 824 | regs.sprg4 = env->spr[SPR_SPRG4]; |
| 825 | regs.sprg5 = env->spr[SPR_SPRG5]; |
| 826 | regs.sprg6 = env->spr[SPR_SPRG6]; |
| 827 | regs.sprg7 = env->spr[SPR_SPRG7]; |
| 828 | |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 829 | regs.pid = env->spr[SPR_BOOKE_PID]; |
| 830 | |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 831 | for (i = 0;i < 32; i++) |
| 832 | regs.gpr[i] = env->gpr[i]; |
| 833 | |
Alexey Kardashevskiy | 4bddaf5 | 2013-06-15 11:51:51 +1000 | [diff] [blame] | 834 | regs.cr = 0; |
| 835 | for (i = 0; i < 8; i++) { |
| 836 | regs.cr |= (env->crf[i] & 15) << (4 * (7 - i)); |
| 837 | } |
| 838 | |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 839 | ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 840 | if (ret < 0) |
| 841 | return ret; |
| 842 | |
David Gibson | 70b7984 | 2013-02-20 16:41:51 +0000 | [diff] [blame] | 843 | kvm_put_fp(cs); |
| 844 | |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 845 | if (env->tlb_dirty) { |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 846 | kvm_sw_tlb_put(cpu); |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 847 | env->tlb_dirty = false; |
| 848 | } |
| 849 | |
David Gibson | f1af19d | 2012-09-12 16:57:09 +0000 | [diff] [blame] | 850 | if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) { |
| 851 | struct kvm_sregs sregs; |
| 852 | |
| 853 | sregs.pvr = env->spr[SPR_PVR]; |
| 854 | |
| 855 | sregs.u.s.sdr1 = env->spr[SPR_SDR1]; |
| 856 | |
| 857 | /* Sync SLB */ |
| 858 | #ifdef TARGET_PPC64 |
Aneesh Kumar K.V | d83af16 | 2013-10-01 21:49:31 +0530 | [diff] [blame] | 859 | for (i = 0; i < ARRAY_SIZE(env->slb); i++) { |
David Gibson | f1af19d | 2012-09-12 16:57:09 +0000 | [diff] [blame] | 860 | sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid; |
Alexey Kardashevskiy | 69b31b9 | 2014-01-31 13:24:00 +1100 | [diff] [blame] | 861 | if (env->slb[i].esid & SLB_ESID_V) { |
| 862 | sregs.u.s.ppc64.slb[i].slbe |= i; |
| 863 | } |
David Gibson | f1af19d | 2012-09-12 16:57:09 +0000 | [diff] [blame] | 864 | sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid; |
| 865 | } |
| 866 | #endif |
| 867 | |
| 868 | /* Sync SRs */ |
| 869 | for (i = 0; i < 16; i++) { |
| 870 | sregs.u.s.ppc32.sr[i] = env->sr[i]; |
| 871 | } |
| 872 | |
| 873 | /* Sync BATs */ |
| 874 | for (i = 0; i < 8; i++) { |
Alexander Graf | ef8beb0 | 2012-10-05 04:34:40 +0200 | [diff] [blame] | 875 | /* Beware. We have to swap upper and lower bits here */ |
| 876 | sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32) |
| 877 | | env->DBAT[1][i]; |
| 878 | sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32) |
| 879 | | env->IBAT[1][i]; |
David Gibson | f1af19d | 2012-09-12 16:57:09 +0000 | [diff] [blame] | 880 | } |
| 881 | |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 882 | ret = kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); |
David Gibson | f1af19d | 2012-09-12 16:57:09 +0000 | [diff] [blame] | 883 | if (ret) { |
| 884 | return ret; |
| 885 | } |
| 886 | } |
| 887 | |
| 888 | if (cap_hior && (level >= KVM_PUT_RESET_STATE)) { |
David Gibson | d67d40e | 2013-02-20 16:41:50 +0000 | [diff] [blame] | 889 | kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); |
| 890 | } |
David Gibson | f1af19d | 2012-09-12 16:57:09 +0000 | [diff] [blame] | 891 | |
David Gibson | d67d40e | 2013-02-20 16:41:50 +0000 | [diff] [blame] | 892 | if (cap_one_reg) { |
| 893 | int i; |
| 894 | |
| 895 | /* We deliberately ignore errors here, for kernels which have |
| 896 | * the ONE_REG calls, but don't support the specific |
| 897 | * registers, there's a reasonable chance things will still |
| 898 | * work, at least until we try to migrate. */ |
| 899 | for (i = 0; i < 1024; i++) { |
| 900 | uint64_t id = env->spr_cb[i].one_reg_id; |
| 901 | |
| 902 | if (id != 0) { |
| 903 | kvm_put_one_spr(cs, id, i); |
| 904 | } |
David Gibson | f1af19d | 2012-09-12 16:57:09 +0000 | [diff] [blame] | 905 | } |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 906 | |
| 907 | #ifdef TARGET_PPC64 |
Alexey Kardashevskiy | 80b3f79 | 2014-06-04 22:51:00 +1000 | [diff] [blame] | 908 | if (msr_ts) { |
| 909 | for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { |
| 910 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); |
| 911 | } |
| 912 | for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { |
| 913 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); |
| 914 | } |
| 915 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); |
| 916 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); |
| 917 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); |
| 918 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); |
| 919 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); |
| 920 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); |
| 921 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); |
| 922 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); |
| 923 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); |
| 924 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); |
| 925 | } |
| 926 | |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 927 | if (cap_papr) { |
| 928 | if (kvm_put_vpa(cs) < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 929 | DPRINTF("Warning: Unable to set VPA information to KVM\n"); |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 930 | } |
| 931 | } |
Alexey Kardashevskiy | 98a8b52 | 2014-05-01 20:37:09 +1000 | [diff] [blame] | 932 | |
| 933 | kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 934 | #endif /* TARGET_PPC64 */ |
David Gibson | f1af19d | 2012-09-12 16:57:09 +0000 | [diff] [blame] | 935 | } |
| 936 | |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 937 | return ret; |
| 938 | } |
| 939 | |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 940 | static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor) |
| 941 | { |
| 942 | env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR]; |
| 943 | } |
| 944 | |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 945 | int kvm_arch_get_registers(CPUState *cs) |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 946 | { |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 947 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 948 | CPUPPCState *env = &cpu->env; |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 949 | struct kvm_regs regs; |
Alexander Graf | ba5e509 | 2009-12-02 23:19:47 +0100 | [diff] [blame] | 950 | struct kvm_sregs sregs; |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 951 | uint32_t cr; |
Alexander Graf | 138b38b | 2010-11-25 08:20:46 +0100 | [diff] [blame] | 952 | int i, ret; |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 953 | |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 954 | ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 955 | if (ret < 0) |
| 956 | return ret; |
| 957 | |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 958 | cr = regs.cr; |
| 959 | for (i = 7; i >= 0; i--) { |
| 960 | env->crf[i] = cr & 15; |
| 961 | cr >>= 4; |
| 962 | } |
Alexander Graf | ba5e509 | 2009-12-02 23:19:47 +0100 | [diff] [blame] | 963 | |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 964 | env->ctr = regs.ctr; |
| 965 | env->lr = regs.lr; |
Richard Henderson | da91a00 | 2013-02-19 23:52:13 -0800 | [diff] [blame] | 966 | cpu_write_xer(env, regs.xer); |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 967 | env->msr = regs.msr; |
| 968 | env->nip = regs.pc; |
| 969 | |
| 970 | env->spr[SPR_SRR0] = regs.srr0; |
| 971 | env->spr[SPR_SRR1] = regs.srr1; |
| 972 | |
| 973 | env->spr[SPR_SPRG0] = regs.sprg0; |
| 974 | env->spr[SPR_SPRG1] = regs.sprg1; |
| 975 | env->spr[SPR_SPRG2] = regs.sprg2; |
| 976 | env->spr[SPR_SPRG3] = regs.sprg3; |
| 977 | env->spr[SPR_SPRG4] = regs.sprg4; |
| 978 | env->spr[SPR_SPRG5] = regs.sprg5; |
| 979 | env->spr[SPR_SPRG6] = regs.sprg6; |
| 980 | env->spr[SPR_SPRG7] = regs.sprg7; |
| 981 | |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 982 | env->spr[SPR_BOOKE_PID] = regs.pid; |
| 983 | |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 984 | for (i = 0;i < 32; i++) |
| 985 | env->gpr[i] = regs.gpr[i]; |
| 986 | |
David Gibson | 70b7984 | 2013-02-20 16:41:51 +0000 | [diff] [blame] | 987 | kvm_get_fp(cs); |
| 988 | |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 989 | if (cap_booke_sregs) { |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 990 | ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 991 | if (ret < 0) { |
| 992 | return ret; |
| 993 | } |
| 994 | |
| 995 | if (sregs.u.e.features & KVM_SREGS_E_BASE) { |
| 996 | env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; |
| 997 | env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; |
| 998 | env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; |
| 999 | env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; |
| 1000 | env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; |
| 1001 | env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; |
| 1002 | env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; |
| 1003 | env->spr[SPR_DECR] = sregs.u.e.dec; |
| 1004 | env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; |
| 1005 | env->spr[SPR_TBU] = sregs.u.e.tb >> 32; |
| 1006 | env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; |
| 1007 | } |
| 1008 | |
| 1009 | if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { |
| 1010 | env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; |
| 1011 | env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; |
| 1012 | env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; |
| 1013 | env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; |
| 1014 | env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; |
| 1015 | } |
| 1016 | |
| 1017 | if (sregs.u.e.features & KVM_SREGS_E_64) { |
| 1018 | env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; |
| 1019 | } |
| 1020 | |
| 1021 | if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { |
| 1022 | env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; |
| 1023 | } |
| 1024 | |
| 1025 | if (sregs.u.e.features & KVM_SREGS_E_IVOR) { |
| 1026 | env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1027 | kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1028 | env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1029 | kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1030 | env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1031 | kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1032 | env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1033 | kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1034 | env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1035 | kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1036 | env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1037 | kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1038 | env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1039 | kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1040 | env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1041 | kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1042 | env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1043 | kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1044 | env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1045 | kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1046 | env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1047 | kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1048 | env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1049 | kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1050 | env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1051 | kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1052 | env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1053 | kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1054 | env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1055 | kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1056 | env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1057 | kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1058 | |
| 1059 | if (sregs.u.e.features & KVM_SREGS_E_SPE) { |
| 1060 | env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1061 | kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1062 | env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1063 | kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1064 | env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1065 | kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1066 | } |
| 1067 | |
| 1068 | if (sregs.u.e.features & KVM_SREGS_E_PM) { |
| 1069 | env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1070 | kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1071 | } |
| 1072 | |
| 1073 | if (sregs.u.e.features & KVM_SREGS_E_PC) { |
| 1074 | env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1075 | kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1076 | env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; |
Bharat Bhushan | c371c2e | 2014-07-14 14:45:36 +0530 | [diff] [blame] | 1077 | kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1078 | } |
| 1079 | } |
| 1080 | |
| 1081 | if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { |
| 1082 | env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; |
| 1083 | env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; |
| 1084 | env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; |
| 1085 | env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; |
| 1086 | env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; |
| 1087 | env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; |
| 1088 | env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; |
| 1089 | env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; |
| 1090 | env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; |
| 1091 | env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; |
| 1092 | } |
| 1093 | |
| 1094 | if (sregs.u.e.features & KVM_SREGS_EXP) { |
| 1095 | env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; |
| 1096 | } |
| 1097 | |
| 1098 | if (sregs.u.e.features & KVM_SREGS_E_PD) { |
| 1099 | env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; |
| 1100 | env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; |
| 1101 | } |
| 1102 | |
| 1103 | if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { |
| 1104 | env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; |
| 1105 | env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; |
| 1106 | env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; |
| 1107 | |
| 1108 | if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { |
| 1109 | env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; |
| 1110 | env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; |
| 1111 | } |
| 1112 | } |
Alexander Graf | fafc0b6 | 2011-05-25 15:04:42 +0200 | [diff] [blame] | 1113 | } |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1114 | |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1115 | if (cap_segstate) { |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 1116 | ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1117 | if (ret < 0) { |
| 1118 | return ret; |
| 1119 | } |
| 1120 | |
Aneesh Kumar K.V | f3c75d4 | 2014-02-20 18:52:17 +0100 | [diff] [blame] | 1121 | if (!env->external_htab) { |
| 1122 | ppc_store_sdr1(env, sregs.u.s.sdr1); |
| 1123 | } |
Alexander Graf | ba5e509 | 2009-12-02 23:19:47 +0100 | [diff] [blame] | 1124 | |
| 1125 | /* Sync SLB */ |
Alexander Graf | 82c09f2 | 2009-12-19 01:58:59 +0100 | [diff] [blame] | 1126 | #ifdef TARGET_PPC64 |
Aneesh Kumar K.V | 4b4d4a2 | 2013-10-01 21:49:28 +0530 | [diff] [blame] | 1127 | /* |
| 1128 | * The packed SLB array we get from KVM_GET_SREGS only contains |
| 1129 | * information about valid entries. So we flush our internal |
| 1130 | * copy to get rid of stale ones, then put all valid SLB entries |
| 1131 | * back in. |
| 1132 | */ |
| 1133 | memset(env->slb, 0, sizeof(env->slb)); |
Aneesh Kumar K.V | d83af16 | 2013-10-01 21:49:31 +0530 | [diff] [blame] | 1134 | for (i = 0; i < ARRAY_SIZE(env->slb); i++) { |
Aneesh Kumar K.V | 4b4d4a2 | 2013-10-01 21:49:28 +0530 | [diff] [blame] | 1135 | target_ulong rb = sregs.u.s.ppc64.slb[i].slbe; |
| 1136 | target_ulong rs = sregs.u.s.ppc64.slb[i].slbv; |
| 1137 | /* |
| 1138 | * Only restore valid entries |
| 1139 | */ |
| 1140 | if (rb & SLB_ESID_V) { |
| 1141 | ppc_store_slb(env, rb, rs); |
| 1142 | } |
Alexander Graf | ba5e509 | 2009-12-02 23:19:47 +0100 | [diff] [blame] | 1143 | } |
Alexander Graf | 82c09f2 | 2009-12-19 01:58:59 +0100 | [diff] [blame] | 1144 | #endif |
Alexander Graf | ba5e509 | 2009-12-02 23:19:47 +0100 | [diff] [blame] | 1145 | |
| 1146 | /* Sync SRs */ |
| 1147 | for (i = 0; i < 16; i++) { |
| 1148 | env->sr[i] = sregs.u.s.ppc32.sr[i]; |
| 1149 | } |
| 1150 | |
| 1151 | /* Sync BATs */ |
| 1152 | for (i = 0; i < 8; i++) { |
| 1153 | env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; |
| 1154 | env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; |
| 1155 | env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; |
| 1156 | env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; |
| 1157 | } |
Alexander Graf | fafc0b6 | 2011-05-25 15:04:42 +0200 | [diff] [blame] | 1158 | } |
Alexander Graf | ba5e509 | 2009-12-02 23:19:47 +0100 | [diff] [blame] | 1159 | |
David Gibson | d67d40e | 2013-02-20 16:41:50 +0000 | [diff] [blame] | 1160 | if (cap_hior) { |
| 1161 | kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); |
| 1162 | } |
| 1163 | |
| 1164 | if (cap_one_reg) { |
| 1165 | int i; |
| 1166 | |
| 1167 | /* We deliberately ignore errors here, for kernels which have |
| 1168 | * the ONE_REG calls, but don't support the specific |
| 1169 | * registers, there's a reasonable chance things will still |
| 1170 | * work, at least until we try to migrate. */ |
| 1171 | for (i = 0; i < 1024; i++) { |
| 1172 | uint64_t id = env->spr_cb[i].one_reg_id; |
| 1173 | |
| 1174 | if (id != 0) { |
| 1175 | kvm_get_one_spr(cs, id, i); |
| 1176 | } |
| 1177 | } |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 1178 | |
| 1179 | #ifdef TARGET_PPC64 |
Alexey Kardashevskiy | 80b3f79 | 2014-06-04 22:51:00 +1000 | [diff] [blame] | 1180 | if (msr_ts) { |
| 1181 | for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { |
| 1182 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); |
| 1183 | } |
| 1184 | for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { |
| 1185 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); |
| 1186 | } |
| 1187 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); |
| 1188 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); |
| 1189 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); |
| 1190 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); |
| 1191 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); |
| 1192 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); |
| 1193 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); |
| 1194 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); |
| 1195 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); |
| 1196 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); |
| 1197 | } |
| 1198 | |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 1199 | if (cap_papr) { |
| 1200 | if (kvm_get_vpa(cs) < 0) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 1201 | DPRINTF("Warning: Unable to get VPA information from KVM\n"); |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 1202 | } |
| 1203 | } |
Alexey Kardashevskiy | 98a8b52 | 2014-05-01 20:37:09 +1000 | [diff] [blame] | 1204 | |
| 1205 | kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 1206 | #endif |
David Gibson | d67d40e | 2013-02-20 16:41:50 +0000 | [diff] [blame] | 1207 | } |
| 1208 | |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1209 | return 0; |
| 1210 | } |
| 1211 | |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 1212 | int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 1213 | { |
| 1214 | unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; |
| 1215 | |
| 1216 | if (irq != PPC_INTERRUPT_EXT) { |
| 1217 | return 0; |
| 1218 | } |
| 1219 | |
| 1220 | if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) { |
| 1221 | return 0; |
| 1222 | } |
| 1223 | |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 1224 | kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 1225 | |
| 1226 | return 0; |
| 1227 | } |
| 1228 | |
Alexander Graf | 1641533 | 2009-07-17 13:51:46 +0200 | [diff] [blame] | 1229 | #if defined(TARGET_PPCEMB) |
| 1230 | #define PPC_INPUT_INT PPC40x_INPUT_INT |
| 1231 | #elif defined(TARGET_PPC64) |
| 1232 | #define PPC_INPUT_INT PPC970_INPUT_INT |
| 1233 | #else |
| 1234 | #define PPC_INPUT_INT PPC6xx_INPUT_INT |
| 1235 | #endif |
| 1236 | |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 1237 | void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1238 | { |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 1239 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 1240 | CPUPPCState *env = &cpu->env; |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1241 | int r; |
| 1242 | unsigned irq; |
| 1243 | |
Stefan Weil | 5cbdb3a | 2012-04-07 09:23:39 +0200 | [diff] [blame] | 1244 | /* PowerPC QEMU tracks the various core input pins (interrupt, critical |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1245 | * interrupt, reset, etc) in PPC-specific env->irq_input_state. */ |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 1246 | if (!cap_interrupt_level && |
| 1247 | run->ready_for_interrupt_injection && |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 1248 | (cs->interrupt_request & CPU_INTERRUPT_HARD) && |
Alexander Graf | 1641533 | 2009-07-17 13:51:46 +0200 | [diff] [blame] | 1249 | (env->irq_input_state & (1<<PPC_INPUT_INT))) |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1250 | { |
| 1251 | /* For now KVM disregards the 'irq' argument. However, in the |
| 1252 | * future KVM could cache it in-kernel to avoid a heavyweight exit |
| 1253 | * when reading the UIC. |
| 1254 | */ |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 1255 | irq = KVM_INTERRUPT_SET; |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1256 | |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 1257 | DPRINTF("injected interrupt %d\n", irq); |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 1258 | r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq); |
Andreas Färber | 55e5c28 | 2012-12-17 06:18:02 +0100 | [diff] [blame] | 1259 | if (r < 0) { |
| 1260 | printf("cpu %d fail inject %x\n", cs->cpu_index, irq); |
| 1261 | } |
Alexander Graf | c821c2b | 2010-04-18 23:10:17 +0200 | [diff] [blame] | 1262 | |
| 1263 | /* Always wake up soon in case the interrupt was level based */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 1264 | timer_mod(idle_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
Alexander Graf | c821c2b | 2010-04-18 23:10:17 +0200 | [diff] [blame] | 1265 | (get_ticks_per_sec() / 50)); |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1266 | } |
| 1267 | |
| 1268 | /* We don't know if there are more interrupts pending after this. However, |
| 1269 | * the guest will return to userspace in the course of handling this one |
| 1270 | * anyways, so we will get a chance to deliver the rest. */ |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1271 | } |
| 1272 | |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 1273 | void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1274 | { |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1275 | } |
| 1276 | |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 1277 | int kvm_arch_process_async_events(CPUState *cs) |
Marcelo Tosatti | 0af691d | 2010-05-04 09:45:27 -0300 | [diff] [blame] | 1278 | { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 1279 | return cs->halted; |
Marcelo Tosatti | 0af691d | 2010-05-04 09:45:27 -0300 | [diff] [blame] | 1280 | } |
| 1281 | |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 1282 | static int kvmppc_handle_halt(PowerPCCPU *cpu) |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1283 | { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 1284 | CPUState *cs = CPU(cpu); |
| 1285 | CPUPPCState *env = &cpu->env; |
| 1286 | |
| 1287 | if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { |
| 1288 | cs->halted = 1; |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 1289 | cs->exception_index = EXCP_HLT; |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1290 | } |
| 1291 | |
Jan Kiszka | bb4ea39 | 2011-03-15 12:26:28 +0100 | [diff] [blame] | 1292 | return 0; |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1293 | } |
| 1294 | |
| 1295 | /* map dcr access to existing qemu dcr emulation */ |
Andreas Färber | 1328c2b | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 1296 | static int kvmppc_handle_dcr_read(CPUPPCState *env, uint32_t dcrn, uint32_t *data) |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1297 | { |
| 1298 | if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) |
| 1299 | fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); |
| 1300 | |
Jan Kiszka | bb4ea39 | 2011-03-15 12:26:28 +0100 | [diff] [blame] | 1301 | return 0; |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1302 | } |
| 1303 | |
Andreas Färber | 1328c2b | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 1304 | static int kvmppc_handle_dcr_write(CPUPPCState *env, uint32_t dcrn, uint32_t data) |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1305 | { |
| 1306 | if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) |
| 1307 | fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); |
| 1308 | |
Jan Kiszka | bb4ea39 | 2011-03-15 12:26:28 +0100 | [diff] [blame] | 1309 | return 0; |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1310 | } |
| 1311 | |
Bharat Bhushan | 8a0548f | 2014-07-14 14:45:38 +0530 | [diff] [blame] | 1312 | int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
| 1313 | { |
| 1314 | /* Mixed endian case is not handled */ |
| 1315 | uint32_t sc = debug_inst_opcode; |
| 1316 | |
| 1317 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, |
| 1318 | sizeof(sc), 0) || |
| 1319 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) { |
| 1320 | return -EINVAL; |
| 1321 | } |
| 1322 | |
| 1323 | return 0; |
| 1324 | } |
| 1325 | |
| 1326 | int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
| 1327 | { |
| 1328 | uint32_t sc; |
| 1329 | |
| 1330 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) || |
| 1331 | sc != debug_inst_opcode || |
| 1332 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, |
| 1333 | sizeof(sc), 1)) { |
| 1334 | return -EINVAL; |
| 1335 | } |
| 1336 | |
| 1337 | return 0; |
| 1338 | } |
| 1339 | |
Bharat Bhushan | 88365d1 | 2014-07-14 14:45:37 +0530 | [diff] [blame] | 1340 | static int find_hw_breakpoint(target_ulong addr, int type) |
| 1341 | { |
| 1342 | int n; |
| 1343 | |
| 1344 | assert((nb_hw_breakpoint + nb_hw_watchpoint) |
| 1345 | <= ARRAY_SIZE(hw_debug_points)); |
| 1346 | |
| 1347 | for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { |
| 1348 | if (hw_debug_points[n].addr == addr && |
| 1349 | hw_debug_points[n].type == type) { |
| 1350 | return n; |
| 1351 | } |
| 1352 | } |
| 1353 | |
| 1354 | return -1; |
| 1355 | } |
| 1356 | |
| 1357 | static int find_hw_watchpoint(target_ulong addr, int *flag) |
| 1358 | { |
| 1359 | int n; |
| 1360 | |
| 1361 | n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS); |
| 1362 | if (n >= 0) { |
| 1363 | *flag = BP_MEM_ACCESS; |
| 1364 | return n; |
| 1365 | } |
| 1366 | |
| 1367 | n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE); |
| 1368 | if (n >= 0) { |
| 1369 | *flag = BP_MEM_WRITE; |
| 1370 | return n; |
| 1371 | } |
| 1372 | |
| 1373 | n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ); |
| 1374 | if (n >= 0) { |
| 1375 | *flag = BP_MEM_READ; |
| 1376 | return n; |
| 1377 | } |
| 1378 | |
| 1379 | return -1; |
| 1380 | } |
| 1381 | |
| 1382 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, |
| 1383 | target_ulong len, int type) |
| 1384 | { |
| 1385 | if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) { |
| 1386 | return -ENOBUFS; |
| 1387 | } |
| 1388 | |
| 1389 | hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr; |
| 1390 | hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type; |
| 1391 | |
| 1392 | switch (type) { |
| 1393 | case GDB_BREAKPOINT_HW: |
| 1394 | if (nb_hw_breakpoint >= max_hw_breakpoint) { |
| 1395 | return -ENOBUFS; |
| 1396 | } |
| 1397 | |
| 1398 | if (find_hw_breakpoint(addr, type) >= 0) { |
| 1399 | return -EEXIST; |
| 1400 | } |
| 1401 | |
| 1402 | nb_hw_breakpoint++; |
| 1403 | break; |
| 1404 | |
| 1405 | case GDB_WATCHPOINT_WRITE: |
| 1406 | case GDB_WATCHPOINT_READ: |
| 1407 | case GDB_WATCHPOINT_ACCESS: |
| 1408 | if (nb_hw_watchpoint >= max_hw_watchpoint) { |
| 1409 | return -ENOBUFS; |
| 1410 | } |
| 1411 | |
| 1412 | if (find_hw_breakpoint(addr, type) >= 0) { |
| 1413 | return -EEXIST; |
| 1414 | } |
| 1415 | |
| 1416 | nb_hw_watchpoint++; |
| 1417 | break; |
| 1418 | |
| 1419 | default: |
| 1420 | return -ENOSYS; |
| 1421 | } |
| 1422 | |
| 1423 | return 0; |
| 1424 | } |
| 1425 | |
| 1426 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, |
| 1427 | target_ulong len, int type) |
| 1428 | { |
| 1429 | int n; |
| 1430 | |
| 1431 | n = find_hw_breakpoint(addr, type); |
| 1432 | if (n < 0) { |
| 1433 | return -ENOENT; |
| 1434 | } |
| 1435 | |
| 1436 | switch (type) { |
| 1437 | case GDB_BREAKPOINT_HW: |
| 1438 | nb_hw_breakpoint--; |
| 1439 | break; |
| 1440 | |
| 1441 | case GDB_WATCHPOINT_WRITE: |
| 1442 | case GDB_WATCHPOINT_READ: |
| 1443 | case GDB_WATCHPOINT_ACCESS: |
| 1444 | nb_hw_watchpoint--; |
| 1445 | break; |
| 1446 | |
| 1447 | default: |
| 1448 | return -ENOSYS; |
| 1449 | } |
| 1450 | hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint]; |
| 1451 | |
| 1452 | return 0; |
| 1453 | } |
| 1454 | |
| 1455 | void kvm_arch_remove_all_hw_breakpoints(void) |
| 1456 | { |
| 1457 | nb_hw_breakpoint = nb_hw_watchpoint = 0; |
| 1458 | } |
| 1459 | |
Bharat Bhushan | 8a0548f | 2014-07-14 14:45:38 +0530 | [diff] [blame] | 1460 | void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) |
| 1461 | { |
Bharat Bhushan | 88365d1 | 2014-07-14 14:45:37 +0530 | [diff] [blame] | 1462 | int n; |
| 1463 | |
Bharat Bhushan | 8a0548f | 2014-07-14 14:45:38 +0530 | [diff] [blame] | 1464 | /* Software Breakpoint updates */ |
| 1465 | if (kvm_sw_breakpoints_active(cs)) { |
| 1466 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
| 1467 | } |
Bharat Bhushan | 88365d1 | 2014-07-14 14:45:37 +0530 | [diff] [blame] | 1468 | |
| 1469 | assert((nb_hw_breakpoint + nb_hw_watchpoint) |
| 1470 | <= ARRAY_SIZE(hw_debug_points)); |
| 1471 | assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp)); |
| 1472 | |
| 1473 | if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { |
| 1474 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; |
| 1475 | memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp)); |
| 1476 | for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { |
| 1477 | switch (hw_debug_points[n].type) { |
| 1478 | case GDB_BREAKPOINT_HW: |
| 1479 | dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT; |
| 1480 | break; |
| 1481 | case GDB_WATCHPOINT_WRITE: |
| 1482 | dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE; |
| 1483 | break; |
| 1484 | case GDB_WATCHPOINT_READ: |
| 1485 | dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ; |
| 1486 | break; |
| 1487 | case GDB_WATCHPOINT_ACCESS: |
| 1488 | dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE | |
| 1489 | KVMPPC_DEBUG_WATCH_READ; |
| 1490 | break; |
| 1491 | default: |
| 1492 | cpu_abort(cs, "Unsupported breakpoint type\n"); |
| 1493 | } |
| 1494 | dbg->arch.bp[n].addr = hw_debug_points[n].addr; |
| 1495 | } |
| 1496 | } |
Bharat Bhushan | 8a0548f | 2014-07-14 14:45:38 +0530 | [diff] [blame] | 1497 | } |
| 1498 | |
| 1499 | static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run) |
| 1500 | { |
| 1501 | CPUState *cs = CPU(cpu); |
| 1502 | CPUPPCState *env = &cpu->env; |
| 1503 | struct kvm_debug_exit_arch *arch_info = &run->debug.arch; |
| 1504 | int handle = 0; |
Bharat Bhushan | 88365d1 | 2014-07-14 14:45:37 +0530 | [diff] [blame] | 1505 | int n; |
| 1506 | int flag = 0; |
Bharat Bhushan | 8a0548f | 2014-07-14 14:45:38 +0530 | [diff] [blame] | 1507 | |
Bharat Bhushan | 88365d1 | 2014-07-14 14:45:37 +0530 | [diff] [blame] | 1508 | if (cs->singlestep_enabled) { |
| 1509 | handle = 1; |
| 1510 | } else if (arch_info->status) { |
| 1511 | if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { |
| 1512 | if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) { |
| 1513 | n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW); |
| 1514 | if (n >= 0) { |
| 1515 | handle = 1; |
| 1516 | } |
| 1517 | } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ | |
| 1518 | KVMPPC_DEBUG_WATCH_WRITE)) { |
| 1519 | n = find_hw_watchpoint(arch_info->address, &flag); |
| 1520 | if (n >= 0) { |
| 1521 | handle = 1; |
| 1522 | cs->watchpoint_hit = &hw_watchpoint; |
| 1523 | hw_watchpoint.vaddr = hw_debug_points[n].addr; |
| 1524 | hw_watchpoint.flags = flag; |
| 1525 | } |
| 1526 | } |
| 1527 | } |
| 1528 | } else if (kvm_find_sw_breakpoint(cs, arch_info->address)) { |
Bharat Bhushan | 8a0548f | 2014-07-14 14:45:38 +0530 | [diff] [blame] | 1529 | handle = 1; |
| 1530 | } else { |
| 1531 | /* QEMU is not able to handle debug exception, so inject |
| 1532 | * program exception to guest; |
| 1533 | * Yes program exception NOT debug exception !! |
Bharat Bhushan | 88365d1 | 2014-07-14 14:45:37 +0530 | [diff] [blame] | 1534 | * When QEMU is using debug resources then debug exception must |
| 1535 | * be always set. To achieve this we set MSR_DE and also set |
| 1536 | * MSRP_DEP so guest cannot change MSR_DE. |
| 1537 | * When emulating debug resource for guest we want guest |
| 1538 | * to control MSR_DE (enable/disable debug interrupt on need). |
| 1539 | * Supporting both configurations are NOT possible. |
| 1540 | * So the result is that we cannot share debug resources |
| 1541 | * between QEMU and Guest on BOOKE architecture. |
| 1542 | * In the current design QEMU gets the priority over guest, |
| 1543 | * this means that if QEMU is using debug resources then guest |
| 1544 | * cannot use them; |
Bharat Bhushan | 8a0548f | 2014-07-14 14:45:38 +0530 | [diff] [blame] | 1545 | * For software breakpoint QEMU uses a privileged instruction; |
| 1546 | * So there cannot be any reason that we are here for guest |
| 1547 | * set debug exception, only possibility is guest executed a |
| 1548 | * privileged / illegal instruction and that's why we are |
| 1549 | * injecting a program interrupt. |
| 1550 | */ |
| 1551 | |
| 1552 | cpu_synchronize_state(cs); |
| 1553 | /* env->nip is PC, so increment this by 4 to use |
| 1554 | * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4. |
| 1555 | */ |
| 1556 | env->nip += 4; |
| 1557 | cs->exception_index = POWERPC_EXCP_PROGRAM; |
| 1558 | env->error_code = POWERPC_EXCP_INVAL; |
| 1559 | ppc_cpu_do_interrupt(cs); |
| 1560 | } |
| 1561 | |
| 1562 | return handle; |
| 1563 | } |
| 1564 | |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 1565 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1566 | { |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 1567 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 1568 | CPUPPCState *env = &cpu->env; |
Jan Kiszka | bb4ea39 | 2011-03-15 12:26:28 +0100 | [diff] [blame] | 1569 | int ret; |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1570 | |
| 1571 | switch (run->exit_reason) { |
| 1572 | case KVM_EXIT_DCR: |
| 1573 | if (run->dcr.is_write) { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 1574 | DPRINTF("handle dcr write\n"); |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1575 | ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); |
| 1576 | } else { |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 1577 | DPRINTF("handle dcr read\n"); |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1578 | ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); |
| 1579 | } |
| 1580 | break; |
| 1581 | case KVM_EXIT_HLT: |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 1582 | DPRINTF("handle halt\n"); |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 1583 | ret = kvmppc_handle_halt(cpu); |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1584 | break; |
David Gibson | c6304a4 | 2013-03-13 15:53:27 +0000 | [diff] [blame] | 1585 | #if defined(TARGET_PPC64) |
Alexander Graf | f61b4be | 2011-08-09 17:57:37 +0200 | [diff] [blame] | 1586 | case KVM_EXIT_PAPR_HCALL: |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 1587 | DPRINTF("handle PAPR hypercall\n"); |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 1588 | run->papr_hcall.ret = spapr_hypercall(cpu, |
Andreas Färber | aa100fa | 2012-05-03 06:13:14 +0200 | [diff] [blame] | 1589 | run->papr_hcall.nr, |
Alexander Graf | f61b4be | 2011-08-09 17:57:37 +0200 | [diff] [blame] | 1590 | run->papr_hcall.args); |
David Gibson | 78e8fde | 2012-08-06 18:44:45 +0000 | [diff] [blame] | 1591 | ret = 0; |
Alexander Graf | f61b4be | 2011-08-09 17:57:37 +0200 | [diff] [blame] | 1592 | break; |
| 1593 | #endif |
Alexander Graf | 5b95b8b | 2013-01-17 11:54:38 +0100 | [diff] [blame] | 1594 | case KVM_EXIT_EPR: |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 1595 | DPRINTF("handle epr\n"); |
Alexander Graf | 933b19e | 2014-02-14 09:15:21 +0100 | [diff] [blame] | 1596 | run->epr.epr = ldl_phys(cs->as, env->mpic_iack); |
Alexander Graf | 5b95b8b | 2013-01-17 11:54:38 +0100 | [diff] [blame] | 1597 | ret = 0; |
| 1598 | break; |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 1599 | case KVM_EXIT_WATCHDOG: |
Peter Maydell | da56ff9 | 2013-07-29 13:16:38 +0100 | [diff] [blame] | 1600 | DPRINTF("handle watchdog expiry\n"); |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 1601 | watchdog_perform_action(); |
| 1602 | ret = 0; |
| 1603 | break; |
| 1604 | |
Bharat Bhushan | 8a0548f | 2014-07-14 14:45:38 +0530 | [diff] [blame] | 1605 | case KVM_EXIT_DEBUG: |
| 1606 | DPRINTF("handle debug exception\n"); |
| 1607 | if (kvm_handle_debug(cpu, run)) { |
| 1608 | ret = EXCP_DEBUG; |
| 1609 | break; |
| 1610 | } |
| 1611 | /* re-enter, this exception was guest-internal */ |
| 1612 | ret = 0; |
| 1613 | break; |
| 1614 | |
Jan Kiszka | 73aaec4 | 2011-01-21 21:48:06 +0100 | [diff] [blame] | 1615 | default: |
| 1616 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); |
| 1617 | ret = -1; |
| 1618 | break; |
aurel32 | d76d165 | 2008-12-16 10:43:58 +0000 | [diff] [blame] | 1619 | } |
| 1620 | |
| 1621 | return ret; |
| 1622 | } |
| 1623 | |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 1624 | int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) |
| 1625 | { |
| 1626 | CPUState *cs = CPU(cpu); |
| 1627 | uint32_t bits = tsr_bits; |
| 1628 | struct kvm_one_reg reg = { |
| 1629 | .id = KVM_REG_PPC_OR_TSR, |
| 1630 | .addr = (uintptr_t) &bits, |
| 1631 | }; |
| 1632 | |
| 1633 | return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
| 1634 | } |
| 1635 | |
| 1636 | int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) |
| 1637 | { |
| 1638 | |
| 1639 | CPUState *cs = CPU(cpu); |
| 1640 | uint32_t bits = tsr_bits; |
| 1641 | struct kvm_one_reg reg = { |
| 1642 | .id = KVM_REG_PPC_CLEAR_TSR, |
| 1643 | .addr = (uintptr_t) &bits, |
| 1644 | }; |
| 1645 | |
| 1646 | return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
| 1647 | } |
| 1648 | |
| 1649 | int kvmppc_set_tcr(PowerPCCPU *cpu) |
| 1650 | { |
| 1651 | CPUState *cs = CPU(cpu); |
| 1652 | CPUPPCState *env = &cpu->env; |
| 1653 | uint32_t tcr = env->spr[SPR_BOOKE_TCR]; |
| 1654 | |
| 1655 | struct kvm_one_reg reg = { |
| 1656 | .id = KVM_REG_PPC_TCR, |
| 1657 | .addr = (uintptr_t) &tcr, |
| 1658 | }; |
| 1659 | |
| 1660 | return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); |
| 1661 | } |
| 1662 | |
| 1663 | int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) |
| 1664 | { |
| 1665 | CPUState *cs = CPU(cpu); |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 1666 | int ret; |
| 1667 | |
| 1668 | if (!kvm_enabled()) { |
| 1669 | return -1; |
| 1670 | } |
| 1671 | |
| 1672 | if (!cap_ppc_watchdog) { |
| 1673 | printf("warning: KVM does not support watchdog"); |
| 1674 | return -1; |
| 1675 | } |
| 1676 | |
Cornelia Huck | 48add81 | 2014-04-09 17:21:57 +0200 | [diff] [blame] | 1677 | ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0); |
Bharat Bhushan | 31f2cb8 | 2013-02-24 18:16:21 +0000 | [diff] [blame] | 1678 | if (ret < 0) { |
| 1679 | fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n", |
| 1680 | __func__, strerror(-ret)); |
| 1681 | return ret; |
| 1682 | } |
| 1683 | |
| 1684 | return ret; |
| 1685 | } |
| 1686 | |
Alexander Graf | dc333cd | 2010-02-09 17:37:05 +0100 | [diff] [blame] | 1687 | static int read_cpuinfo(const char *field, char *value, int len) |
| 1688 | { |
| 1689 | FILE *f; |
| 1690 | int ret = -1; |
| 1691 | int field_len = strlen(field); |
| 1692 | char line[512]; |
| 1693 | |
| 1694 | f = fopen("/proc/cpuinfo", "r"); |
| 1695 | if (!f) { |
| 1696 | return -1; |
| 1697 | } |
| 1698 | |
| 1699 | do { |
Nikunj A Dadhania | ef95144 | 2014-07-09 16:08:37 +0530 | [diff] [blame] | 1700 | if (!fgets(line, sizeof(line), f)) { |
Alexander Graf | dc333cd | 2010-02-09 17:37:05 +0100 | [diff] [blame] | 1701 | break; |
| 1702 | } |
| 1703 | if (!strncmp(line, field, field_len)) { |
Jim Meyering | ae21506 | 2012-10-04 13:09:52 +0200 | [diff] [blame] | 1704 | pstrcpy(value, len, line); |
Alexander Graf | dc333cd | 2010-02-09 17:37:05 +0100 | [diff] [blame] | 1705 | ret = 0; |
| 1706 | break; |
| 1707 | } |
| 1708 | } while(*line); |
| 1709 | |
| 1710 | fclose(f); |
| 1711 | |
| 1712 | return ret; |
| 1713 | } |
| 1714 | |
| 1715 | uint32_t kvmppc_get_tbfreq(void) |
| 1716 | { |
| 1717 | char line[512]; |
| 1718 | char *ns; |
| 1719 | uint32_t retval = get_ticks_per_sec(); |
| 1720 | |
| 1721 | if (read_cpuinfo("timebase", line, sizeof(line))) { |
| 1722 | return retval; |
| 1723 | } |
| 1724 | |
| 1725 | if (!(ns = strchr(line, ':'))) { |
| 1726 | return retval; |
| 1727 | } |
| 1728 | |
| 1729 | ns++; |
| 1730 | |
| 1731 | retval = atoi(ns); |
| 1732 | return retval; |
| 1733 | } |
Gleb Natapov | 4513d92 | 2010-05-10 11:21:34 +0300 | [diff] [blame] | 1734 | |
Nikunj A Dadhania | ef95144 | 2014-07-09 16:08:37 +0530 | [diff] [blame] | 1735 | bool kvmppc_get_host_serial(char **value) |
| 1736 | { |
| 1737 | return g_file_get_contents("/proc/device-tree/system-id", value, NULL, |
| 1738 | NULL); |
| 1739 | } |
| 1740 | |
| 1741 | bool kvmppc_get_host_model(char **value) |
| 1742 | { |
| 1743 | return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL); |
| 1744 | } |
| 1745 | |
Alexander Graf | eadaada | 2011-07-21 02:29:15 +0200 | [diff] [blame] | 1746 | /* Try to find a device tree node for a CPU with clock-frequency property */ |
| 1747 | static int kvmppc_find_cpu_dt(char *buf, int buf_len) |
| 1748 | { |
| 1749 | struct dirent *dirp; |
| 1750 | DIR *dp; |
| 1751 | |
| 1752 | if ((dp = opendir(PROC_DEVTREE_CPU)) == NULL) { |
| 1753 | printf("Can't open directory " PROC_DEVTREE_CPU "\n"); |
| 1754 | return -1; |
| 1755 | } |
| 1756 | |
| 1757 | buf[0] = '\0'; |
| 1758 | while ((dirp = readdir(dp)) != NULL) { |
| 1759 | FILE *f; |
| 1760 | snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, |
| 1761 | dirp->d_name); |
| 1762 | f = fopen(buf, "r"); |
| 1763 | if (f) { |
| 1764 | snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); |
| 1765 | fclose(f); |
| 1766 | break; |
| 1767 | } |
| 1768 | buf[0] = '\0'; |
| 1769 | } |
| 1770 | closedir(dp); |
| 1771 | if (buf[0] == '\0') { |
| 1772 | printf("Unknown host!\n"); |
| 1773 | return -1; |
| 1774 | } |
| 1775 | |
| 1776 | return 0; |
| 1777 | } |
| 1778 | |
David Gibson | 9bc884b | 2011-10-10 18:31:00 +0000 | [diff] [blame] | 1779 | /* Read a CPU node property from the host device tree that's a single |
| 1780 | * integer (32-bit or 64-bit). Returns 0 if anything goes wrong |
| 1781 | * (can't find or open the property, or doesn't understand the |
| 1782 | * format) */ |
| 1783 | static uint64_t kvmppc_read_int_cpu_dt(const char *propname) |
Alexander Graf | eadaada | 2011-07-21 02:29:15 +0200 | [diff] [blame] | 1784 | { |
Chen Gang | cc64b1a | 2014-10-15 21:48:07 +0800 | [diff] [blame] | 1785 | char buf[PATH_MAX], *tmp; |
David Gibson | 9bc884b | 2011-10-10 18:31:00 +0000 | [diff] [blame] | 1786 | union { |
| 1787 | uint32_t v32; |
| 1788 | uint64_t v64; |
| 1789 | } u; |
Alexander Graf | eadaada | 2011-07-21 02:29:15 +0200 | [diff] [blame] | 1790 | FILE *f; |
| 1791 | int len; |
| 1792 | |
| 1793 | if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { |
David Gibson | 9bc884b | 2011-10-10 18:31:00 +0000 | [diff] [blame] | 1794 | return -1; |
Alexander Graf | eadaada | 2011-07-21 02:29:15 +0200 | [diff] [blame] | 1795 | } |
| 1796 | |
Chen Gang | cc64b1a | 2014-10-15 21:48:07 +0800 | [diff] [blame] | 1797 | tmp = g_strdup_printf("%s/%s", buf, propname); |
Alexander Graf | eadaada | 2011-07-21 02:29:15 +0200 | [diff] [blame] | 1798 | |
Chen Gang | cc64b1a | 2014-10-15 21:48:07 +0800 | [diff] [blame] | 1799 | f = fopen(tmp, "rb"); |
| 1800 | g_free(tmp); |
Alexander Graf | eadaada | 2011-07-21 02:29:15 +0200 | [diff] [blame] | 1801 | if (!f) { |
| 1802 | return -1; |
| 1803 | } |
| 1804 | |
David Gibson | 9bc884b | 2011-10-10 18:31:00 +0000 | [diff] [blame] | 1805 | len = fread(&u, 1, sizeof(u), f); |
Alexander Graf | eadaada | 2011-07-21 02:29:15 +0200 | [diff] [blame] | 1806 | fclose(f); |
| 1807 | switch (len) { |
David Gibson | 9bc884b | 2011-10-10 18:31:00 +0000 | [diff] [blame] | 1808 | case 4: |
| 1809 | /* property is a 32-bit quantity */ |
| 1810 | return be32_to_cpu(u.v32); |
| 1811 | case 8: |
| 1812 | return be64_to_cpu(u.v64); |
Alexander Graf | eadaada | 2011-07-21 02:29:15 +0200 | [diff] [blame] | 1813 | } |
| 1814 | |
| 1815 | return 0; |
| 1816 | } |
| 1817 | |
David Gibson | 9bc884b | 2011-10-10 18:31:00 +0000 | [diff] [blame] | 1818 | uint64_t kvmppc_get_clockfreq(void) |
| 1819 | { |
| 1820 | return kvmppc_read_int_cpu_dt("clock-frequency"); |
| 1821 | } |
| 1822 | |
David Gibson | 6659394 | 2011-10-10 18:31:01 +0000 | [diff] [blame] | 1823 | uint32_t kvmppc_get_vmx(void) |
| 1824 | { |
| 1825 | return kvmppc_read_int_cpu_dt("ibm,vmx"); |
| 1826 | } |
| 1827 | |
| 1828 | uint32_t kvmppc_get_dfp(void) |
| 1829 | { |
| 1830 | return kvmppc_read_int_cpu_dt("ibm,dfp"); |
| 1831 | } |
| 1832 | |
Stuart Yoder | 1a61a9a | 2013-01-03 12:37:02 +0000 | [diff] [blame] | 1833 | static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) |
| 1834 | { |
| 1835 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 1836 | CPUState *cs = CPU(cpu); |
Alexander Graf | 45024f0 | 2010-08-03 15:22:42 +0200 | [diff] [blame] | 1837 | |
Alexander Graf | 6fd33a7 | 2014-07-14 19:17:35 +0200 | [diff] [blame] | 1838 | if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && |
Stuart Yoder | 1a61a9a | 2013-01-03 12:37:02 +0000 | [diff] [blame] | 1839 | !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { |
| 1840 | return 0; |
| 1841 | } |
Alexander Graf | 45024f0 | 2010-08-03 15:22:42 +0200 | [diff] [blame] | 1842 | |
Stuart Yoder | 1a61a9a | 2013-01-03 12:37:02 +0000 | [diff] [blame] | 1843 | return 1; |
| 1844 | } |
| 1845 | |
| 1846 | int kvmppc_get_hasidle(CPUPPCState *env) |
| 1847 | { |
| 1848 | struct kvm_ppc_pvinfo pvinfo; |
| 1849 | |
| 1850 | if (!kvmppc_get_pvinfo(env, &pvinfo) && |
| 1851 | (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) { |
| 1852 | return 1; |
| 1853 | } |
| 1854 | |
| 1855 | return 0; |
| 1856 | } |
| 1857 | |
| 1858 | int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) |
| 1859 | { |
| 1860 | uint32_t *hc = (uint32_t*)buf; |
| 1861 | struct kvm_ppc_pvinfo pvinfo; |
| 1862 | |
| 1863 | if (!kvmppc_get_pvinfo(env, &pvinfo)) { |
| 1864 | memcpy(buf, pvinfo.hcall, buf_len); |
Alexander Graf | 45024f0 | 2010-08-03 15:22:42 +0200 | [diff] [blame] | 1865 | return 0; |
| 1866 | } |
Alexander Graf | 45024f0 | 2010-08-03 15:22:42 +0200 | [diff] [blame] | 1867 | |
| 1868 | /* |
Alexander Graf | d13fc32 | 2014-06-11 12:19:03 +0200 | [diff] [blame] | 1869 | * Fallback to always fail hypercalls regardless of endianness: |
Alexander Graf | 45024f0 | 2010-08-03 15:22:42 +0200 | [diff] [blame] | 1870 | * |
Alexander Graf | d13fc32 | 2014-06-11 12:19:03 +0200 | [diff] [blame] | 1871 | * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian) |
Alexander Graf | 45024f0 | 2010-08-03 15:22:42 +0200 | [diff] [blame] | 1872 | * li r3, -1 |
Alexander Graf | d13fc32 | 2014-06-11 12:19:03 +0200 | [diff] [blame] | 1873 | * b .+8 (becomes nop in wrong endian) |
| 1874 | * bswap32(li r3, -1) |
Alexander Graf | 45024f0 | 2010-08-03 15:22:42 +0200 | [diff] [blame] | 1875 | */ |
| 1876 | |
Alexander Graf | d13fc32 | 2014-06-11 12:19:03 +0200 | [diff] [blame] | 1877 | hc[0] = cpu_to_be32(0x08000048); |
| 1878 | hc[1] = cpu_to_be32(0x3860ffff); |
| 1879 | hc[2] = cpu_to_be32(0x48000008); |
| 1880 | hc[3] = cpu_to_be32(bswap32(0x3860ffff)); |
Alexander Graf | 45024f0 | 2010-08-03 15:22:42 +0200 | [diff] [blame] | 1881 | |
| 1882 | return 0; |
| 1883 | } |
| 1884 | |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 1885 | void kvmppc_set_papr(PowerPCCPU *cpu) |
Alexander Graf | f61b4be | 2011-08-09 17:57:37 +0200 | [diff] [blame] | 1886 | { |
Andreas Färber | 1bc2265 | 2012-10-31 06:06:49 +0100 | [diff] [blame] | 1887 | CPUState *cs = CPU(cpu); |
Alexander Graf | f61b4be | 2011-08-09 17:57:37 +0200 | [diff] [blame] | 1888 | int ret; |
| 1889 | |
Cornelia Huck | 48add81 | 2014-04-09 17:21:57 +0200 | [diff] [blame] | 1890 | ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0); |
Alexander Graf | f61b4be | 2011-08-09 17:57:37 +0200 | [diff] [blame] | 1891 | if (ret) { |
Andreas Färber | a47dddd | 2013-09-03 17:38:47 +0200 | [diff] [blame] | 1892 | cpu_abort(cs, "This KVM version does not support PAPR\n"); |
Alexander Graf | f61b4be | 2011-08-09 17:57:37 +0200 | [diff] [blame] | 1893 | } |
David Gibson | 9b00ea4 | 2013-04-07 19:08:22 +0000 | [diff] [blame] | 1894 | |
| 1895 | /* Update the capability flag so we sync the right information |
| 1896 | * with kvm */ |
| 1897 | cap_papr = 1; |
Alexander Graf | f61b4be | 2011-08-09 17:57:37 +0200 | [diff] [blame] | 1898 | } |
| 1899 | |
Alexey Kardashevskiy | 6db5bb0 | 2014-05-23 12:26:58 +1000 | [diff] [blame] | 1900 | int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version) |
| 1901 | { |
| 1902 | return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &cpu_version); |
| 1903 | } |
| 1904 | |
Alexander Graf | 5b95b8b | 2013-01-17 11:54:38 +0100 | [diff] [blame] | 1905 | void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) |
| 1906 | { |
Alexander Graf | 5b95b8b | 2013-01-17 11:54:38 +0100 | [diff] [blame] | 1907 | CPUState *cs = CPU(cpu); |
Alexander Graf | 5b95b8b | 2013-01-17 11:54:38 +0100 | [diff] [blame] | 1908 | int ret; |
| 1909 | |
Cornelia Huck | 48add81 | 2014-04-09 17:21:57 +0200 | [diff] [blame] | 1910 | ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy); |
Alexander Graf | 5b95b8b | 2013-01-17 11:54:38 +0100 | [diff] [blame] | 1911 | if (ret && mpic_proxy) { |
Andreas Färber | a47dddd | 2013-09-03 17:38:47 +0200 | [diff] [blame] | 1912 | cpu_abort(cs, "This KVM version does not support EPR\n"); |
Alexander Graf | 5b95b8b | 2013-01-17 11:54:38 +0100 | [diff] [blame] | 1913 | } |
| 1914 | } |
| 1915 | |
David Gibson | e97c363 | 2011-09-29 21:39:10 +0000 | [diff] [blame] | 1916 | int kvmppc_smt_threads(void) |
| 1917 | { |
| 1918 | return cap_ppc_smt ? cap_ppc_smt : 1; |
| 1919 | } |
| 1920 | |
David Gibson | 7f763a5 | 2012-09-12 16:57:12 +0000 | [diff] [blame] | 1921 | #ifdef TARGET_PPC64 |
Alexey Kardashevskiy | 658fa66 | 2014-07-11 01:03:41 +1000 | [diff] [blame] | 1922 | off_t kvmppc_alloc_rma(void **rma) |
David Gibson | 354ac20 | 2011-09-29 21:39:11 +0000 | [diff] [blame] | 1923 | { |
David Gibson | 354ac20 | 2011-09-29 21:39:11 +0000 | [diff] [blame] | 1924 | off_t size; |
| 1925 | int fd; |
| 1926 | struct kvm_allocate_rma ret; |
David Gibson | 354ac20 | 2011-09-29 21:39:11 +0000 | [diff] [blame] | 1927 | |
| 1928 | /* If cap_ppc_rma == 0, contiguous RMA allocation is not supported |
| 1929 | * if cap_ppc_rma == 1, contiguous RMA allocation is supported, but |
| 1930 | * not necessary on this hardware |
| 1931 | * if cap_ppc_rma == 2, contiguous RMA allocation is needed on this hardware |
| 1932 | * |
| 1933 | * FIXME: We should allow the user to force contiguous RMA |
| 1934 | * allocation in the cap_ppc_rma==1 case. |
| 1935 | */ |
| 1936 | if (cap_ppc_rma < 2) { |
| 1937 | return 0; |
| 1938 | } |
| 1939 | |
| 1940 | fd = kvm_vm_ioctl(kvm_state, KVM_ALLOCATE_RMA, &ret); |
| 1941 | if (fd < 0) { |
| 1942 | fprintf(stderr, "KVM: Error on KVM_ALLOCATE_RMA: %s\n", |
| 1943 | strerror(errno)); |
| 1944 | return -1; |
| 1945 | } |
| 1946 | |
| 1947 | size = MIN(ret.rma_size, 256ul << 20); |
| 1948 | |
Alexey Kardashevskiy | 658fa66 | 2014-07-11 01:03:41 +1000 | [diff] [blame] | 1949 | *rma = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); |
| 1950 | if (*rma == MAP_FAILED) { |
David Gibson | 354ac20 | 2011-09-29 21:39:11 +0000 | [diff] [blame] | 1951 | fprintf(stderr, "KVM: Error mapping RMA: %s\n", strerror(errno)); |
| 1952 | return -1; |
| 1953 | }; |
| 1954 | |
David Gibson | 354ac20 | 2011-09-29 21:39:11 +0000 | [diff] [blame] | 1955 | return size; |
| 1956 | } |
| 1957 | |
David Gibson | 7f763a5 | 2012-09-12 16:57:12 +0000 | [diff] [blame] | 1958 | uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift) |
| 1959 | { |
David Gibson | f36951c | 2013-04-07 19:08:18 +0000 | [diff] [blame] | 1960 | struct kvm_ppc_smmu_info info; |
| 1961 | long rampagesize, best_page_shift; |
| 1962 | int i; |
| 1963 | |
David Gibson | 7f763a5 | 2012-09-12 16:57:12 +0000 | [diff] [blame] | 1964 | if (cap_ppc_rma >= 2) { |
| 1965 | return current_size; |
| 1966 | } |
David Gibson | f36951c | 2013-04-07 19:08:18 +0000 | [diff] [blame] | 1967 | |
| 1968 | /* Find the largest hardware supported page size that's less than |
| 1969 | * or equal to the (logical) backing page size of guest RAM */ |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 1970 | kvm_get_smmu_info(POWERPC_CPU(first_cpu), &info); |
David Gibson | f36951c | 2013-04-07 19:08:18 +0000 | [diff] [blame] | 1971 | rampagesize = getrampagesize(); |
| 1972 | best_page_shift = 0; |
| 1973 | |
| 1974 | for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) { |
| 1975 | struct kvm_ppc_one_seg_page_size *sps = &info.sps[i]; |
| 1976 | |
| 1977 | if (!sps->page_shift) { |
| 1978 | continue; |
| 1979 | } |
| 1980 | |
| 1981 | if ((sps->page_shift > best_page_shift) |
| 1982 | && ((1UL << sps->page_shift) <= rampagesize)) { |
| 1983 | best_page_shift = sps->page_shift; |
| 1984 | } |
| 1985 | } |
| 1986 | |
David Gibson | 7f763a5 | 2012-09-12 16:57:12 +0000 | [diff] [blame] | 1987 | return MIN(current_size, |
David Gibson | f36951c | 2013-04-07 19:08:18 +0000 | [diff] [blame] | 1988 | 1ULL << (best_page_shift + hash_shift - 7)); |
David Gibson | 7f763a5 | 2012-09-12 16:57:12 +0000 | [diff] [blame] | 1989 | } |
| 1990 | #endif |
| 1991 | |
Alexey Kardashevskiy | da95324 | 2014-05-27 15:36:30 +1000 | [diff] [blame] | 1992 | bool kvmppc_spapr_use_multitce(void) |
| 1993 | { |
| 1994 | return cap_spapr_multitce; |
| 1995 | } |
| 1996 | |
Alexey Kardashevskiy | 9bb62a0 | 2014-06-10 15:39:21 +1000 | [diff] [blame] | 1997 | void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd, |
| 1998 | bool vfio_accel) |
David Gibson | 0f5cb29 | 2011-09-29 21:39:12 +0000 | [diff] [blame] | 1999 | { |
| 2000 | struct kvm_create_spapr_tce args = { |
| 2001 | .liobn = liobn, |
| 2002 | .window_size = window_size, |
| 2003 | }; |
| 2004 | long len; |
| 2005 | int fd; |
| 2006 | void *table; |
| 2007 | |
David Gibson | b5aec39 | 2012-02-27 17:18:07 +0000 | [diff] [blame] | 2008 | /* Must set fd to -1 so we don't try to munmap when called for |
| 2009 | * destroying the table, which the upper layers -will- do |
| 2010 | */ |
| 2011 | *pfd = -1; |
Alexey Kardashevskiy | 9bb62a0 | 2014-06-10 15:39:21 +1000 | [diff] [blame] | 2012 | if (!cap_spapr_tce || (vfio_accel && !cap_spapr_vfio)) { |
David Gibson | 0f5cb29 | 2011-09-29 21:39:12 +0000 | [diff] [blame] | 2013 | return NULL; |
| 2014 | } |
| 2015 | |
| 2016 | fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args); |
| 2017 | if (fd < 0) { |
David Gibson | b5aec39 | 2012-02-27 17:18:07 +0000 | [diff] [blame] | 2018 | fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n", |
| 2019 | liobn); |
David Gibson | 0f5cb29 | 2011-09-29 21:39:12 +0000 | [diff] [blame] | 2020 | return NULL; |
| 2021 | } |
| 2022 | |
Anthony Liguori | a83000f | 2013-07-18 14:32:58 -0500 | [diff] [blame] | 2023 | len = (window_size / SPAPR_TCE_PAGE_SIZE) * sizeof(uint64_t); |
David Gibson | 0f5cb29 | 2011-09-29 21:39:12 +0000 | [diff] [blame] | 2024 | /* FIXME: round this up to page size */ |
| 2025 | |
David Gibson | 74b41e5 | 2011-10-27 15:56:31 +0000 | [diff] [blame] | 2026 | table = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); |
David Gibson | 0f5cb29 | 2011-09-29 21:39:12 +0000 | [diff] [blame] | 2027 | if (table == MAP_FAILED) { |
David Gibson | b5aec39 | 2012-02-27 17:18:07 +0000 | [diff] [blame] | 2028 | fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n", |
| 2029 | liobn); |
David Gibson | 0f5cb29 | 2011-09-29 21:39:12 +0000 | [diff] [blame] | 2030 | close(fd); |
| 2031 | return NULL; |
| 2032 | } |
| 2033 | |
| 2034 | *pfd = fd; |
| 2035 | return table; |
| 2036 | } |
| 2037 | |
Alexey Kardashevskiy | 523e7b8 | 2014-05-27 15:36:35 +1000 | [diff] [blame] | 2038 | int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table) |
David Gibson | 0f5cb29 | 2011-09-29 21:39:12 +0000 | [diff] [blame] | 2039 | { |
| 2040 | long len; |
| 2041 | |
| 2042 | if (fd < 0) { |
| 2043 | return -1; |
| 2044 | } |
| 2045 | |
Alexey Kardashevskiy | 523e7b8 | 2014-05-27 15:36:35 +1000 | [diff] [blame] | 2046 | len = nb_table * sizeof(uint64_t); |
David Gibson | 0f5cb29 | 2011-09-29 21:39:12 +0000 | [diff] [blame] | 2047 | if ((munmap(table, len) < 0) || |
| 2048 | (close(fd) < 0)) { |
David Gibson | b5aec39 | 2012-02-27 17:18:07 +0000 | [diff] [blame] | 2049 | fprintf(stderr, "KVM: Unexpected error removing TCE table: %s", |
| 2050 | strerror(errno)); |
David Gibson | 0f5cb29 | 2011-09-29 21:39:12 +0000 | [diff] [blame] | 2051 | /* Leak the table */ |
| 2052 | } |
| 2053 | |
| 2054 | return 0; |
| 2055 | } |
| 2056 | |
David Gibson | 7f763a5 | 2012-09-12 16:57:12 +0000 | [diff] [blame] | 2057 | int kvmppc_reset_htab(int shift_hint) |
| 2058 | { |
| 2059 | uint32_t shift = shift_hint; |
| 2060 | |
David Gibson | ace9a2c | 2012-09-19 21:08:42 +0000 | [diff] [blame] | 2061 | if (!kvm_enabled()) { |
| 2062 | /* Full emulation, tell caller to allocate htab itself */ |
| 2063 | return 0; |
| 2064 | } |
| 2065 | if (kvm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) { |
David Gibson | 7f763a5 | 2012-09-12 16:57:12 +0000 | [diff] [blame] | 2066 | int ret; |
| 2067 | ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift); |
David Gibson | ace9a2c | 2012-09-19 21:08:42 +0000 | [diff] [blame] | 2068 | if (ret == -ENOTTY) { |
| 2069 | /* At least some versions of PR KVM advertise the |
| 2070 | * capability, but don't implement the ioctl(). Oops. |
| 2071 | * Return 0 so that we allocate the htab in qemu, as is |
| 2072 | * correct for PR. */ |
| 2073 | return 0; |
| 2074 | } else if (ret < 0) { |
David Gibson | 7f763a5 | 2012-09-12 16:57:12 +0000 | [diff] [blame] | 2075 | return ret; |
| 2076 | } |
| 2077 | return shift; |
| 2078 | } |
| 2079 | |
David Gibson | ace9a2c | 2012-09-19 21:08:42 +0000 | [diff] [blame] | 2080 | /* We have a kernel that predates the htab reset calls. For PR |
| 2081 | * KVM, we need to allocate the htab ourselves, for an HV KVM of |
| 2082 | * this era, it has allocated a 16MB fixed size hash table |
| 2083 | * already. Kernels of this era have the GET_PVINFO capability |
| 2084 | * only on PR, so we use this hack to determine the right |
| 2085 | * answer */ |
| 2086 | if (kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_PVINFO)) { |
| 2087 | /* PR - tell caller to allocate htab */ |
| 2088 | return 0; |
| 2089 | } else { |
| 2090 | /* HV - assume 16MB kernel allocated htab */ |
| 2091 | return 24; |
| 2092 | } |
David Gibson | 7f763a5 | 2012-09-12 16:57:12 +0000 | [diff] [blame] | 2093 | } |
| 2094 | |
David Gibson | a1e9858 | 2011-10-12 22:40:32 +0000 | [diff] [blame] | 2095 | static inline uint32_t mfpvr(void) |
| 2096 | { |
| 2097 | uint32_t pvr; |
| 2098 | |
| 2099 | asm ("mfpvr %0" |
| 2100 | : "=r"(pvr)); |
| 2101 | return pvr; |
| 2102 | } |
| 2103 | |
David Gibson | a734258 | 2011-10-17 18:15:41 +0000 | [diff] [blame] | 2104 | static void alter_insns(uint64_t *word, uint64_t flags, bool on) |
| 2105 | { |
| 2106 | if (on) { |
| 2107 | *word |= flags; |
| 2108 | } else { |
| 2109 | *word &= ~flags; |
| 2110 | } |
| 2111 | } |
| 2112 | |
Andreas Färber | 2985b86 | 2013-01-06 08:31:30 +0000 | [diff] [blame] | 2113 | static void kvmppc_host_cpu_initfn(Object *obj) |
David Gibson | a1e9858 | 2011-10-12 22:40:32 +0000 | [diff] [blame] | 2114 | { |
Andreas Färber | 2985b86 | 2013-01-06 08:31:30 +0000 | [diff] [blame] | 2115 | assert(kvm_enabled()); |
| 2116 | } |
| 2117 | |
| 2118 | static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) |
| 2119 | { |
| 2120 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
David Gibson | a734258 | 2011-10-17 18:15:41 +0000 | [diff] [blame] | 2121 | uint32_t vmx = kvmppc_get_vmx(); |
| 2122 | uint32_t dfp = kvmppc_get_dfp(); |
David Gibson | 0cbad81 | 2013-04-07 19:08:19 +0000 | [diff] [blame] | 2123 | uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size"); |
| 2124 | uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size"); |
David Gibson | a1e9858 | 2011-10-12 22:40:32 +0000 | [diff] [blame] | 2125 | |
Andreas Färber | cfe34f4 | 2013-02-17 23:16:41 +0000 | [diff] [blame] | 2126 | /* Now fix up the class with information we can query from the host */ |
Alexey Kardashevskiy | 3bc9ccc | 2013-09-27 18:05:03 +1000 | [diff] [blame] | 2127 | pcc->pvr = mfpvr(); |
David Gibson | a734258 | 2011-10-17 18:15:41 +0000 | [diff] [blame] | 2128 | |
Alexander Graf | 70bca53 | 2011-10-24 20:43:22 +0200 | [diff] [blame] | 2129 | if (vmx != -1) { |
| 2130 | /* Only override when we know what the host supports */ |
Andreas Färber | cfe34f4 | 2013-02-17 23:16:41 +0000 | [diff] [blame] | 2131 | alter_insns(&pcc->insns_flags, PPC_ALTIVEC, vmx > 0); |
| 2132 | alter_insns(&pcc->insns_flags2, PPC2_VSX, vmx > 1); |
Alexander Graf | 70bca53 | 2011-10-24 20:43:22 +0200 | [diff] [blame] | 2133 | } |
| 2134 | if (dfp != -1) { |
| 2135 | /* Only override when we know what the host supports */ |
Andreas Färber | cfe34f4 | 2013-02-17 23:16:41 +0000 | [diff] [blame] | 2136 | alter_insns(&pcc->insns_flags2, PPC2_DFP, dfp); |
Alexander Graf | 70bca53 | 2011-10-24 20:43:22 +0200 | [diff] [blame] | 2137 | } |
David Gibson | 0cbad81 | 2013-04-07 19:08:19 +0000 | [diff] [blame] | 2138 | |
| 2139 | if (dcache_size != -1) { |
| 2140 | pcc->l1_dcache_size = dcache_size; |
| 2141 | } |
| 2142 | |
| 2143 | if (icache_size != -1) { |
| 2144 | pcc->l1_icache_size = icache_size; |
| 2145 | } |
David Gibson | a1e9858 | 2011-10-12 22:40:32 +0000 | [diff] [blame] | 2146 | } |
| 2147 | |
Stuart Yoder | 3b96112 | 2013-03-30 06:40:49 +0000 | [diff] [blame] | 2148 | bool kvmppc_has_cap_epr(void) |
| 2149 | { |
| 2150 | return cap_epr; |
| 2151 | } |
| 2152 | |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 2153 | bool kvmppc_has_cap_htab_fd(void) |
| 2154 | { |
| 2155 | return cap_htab_fd; |
| 2156 | } |
| 2157 | |
Alexander Graf | 87a91de | 2014-06-04 12:14:08 +0200 | [diff] [blame] | 2158 | bool kvmppc_has_cap_fixup_hcalls(void) |
| 2159 | { |
| 2160 | return cap_fixup_hcalls; |
| 2161 | } |
| 2162 | |
Alexey Kardashevskiy | 5b79b1c | 2014-04-12 03:34:25 +1000 | [diff] [blame] | 2163 | static PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) |
| 2164 | { |
| 2165 | ObjectClass *oc = OBJECT_CLASS(pcc); |
| 2166 | |
| 2167 | while (oc && !object_class_is_abstract(oc)) { |
| 2168 | oc = object_class_get_parent(oc); |
| 2169 | } |
| 2170 | assert(oc); |
| 2171 | |
| 2172 | return POWERPC_CPU_CLASS(oc); |
| 2173 | } |
| 2174 | |
Andreas Färber | 5ba4576 | 2013-02-23 11:22:12 +0000 | [diff] [blame] | 2175 | static int kvm_ppc_register_host_cpu_type(void) |
| 2176 | { |
| 2177 | TypeInfo type_info = { |
| 2178 | .name = TYPE_HOST_POWERPC_CPU, |
| 2179 | .instance_init = kvmppc_host_cpu_initfn, |
| 2180 | .class_init = kvmppc_host_cpu_class_init, |
| 2181 | }; |
| 2182 | uint32_t host_pvr = mfpvr(); |
| 2183 | PowerPCCPUClass *pvr_pcc; |
Alexey Kardashevskiy | 5b79b1c | 2014-04-12 03:34:25 +1000 | [diff] [blame] | 2184 | DeviceClass *dc; |
Andreas Färber | 5ba4576 | 2013-02-23 11:22:12 +0000 | [diff] [blame] | 2185 | |
| 2186 | pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); |
| 2187 | if (pvr_pcc == NULL) { |
Alexey Kardashevskiy | 3bc9ccc | 2013-09-27 18:05:03 +1000 | [diff] [blame] | 2188 | pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr); |
| 2189 | } |
| 2190 | if (pvr_pcc == NULL) { |
Andreas Färber | 5ba4576 | 2013-02-23 11:22:12 +0000 | [diff] [blame] | 2191 | return -1; |
| 2192 | } |
| 2193 | type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); |
| 2194 | type_register(&type_info); |
Alexey Kardashevskiy | 5b79b1c | 2014-04-12 03:34:25 +1000 | [diff] [blame] | 2195 | |
| 2196 | /* Register generic family CPU class for a family */ |
| 2197 | pvr_pcc = ppc_cpu_get_family_class(pvr_pcc); |
| 2198 | dc = DEVICE_CLASS(pvr_pcc); |
| 2199 | type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); |
| 2200 | type_info.name = g_strdup_printf("%s-"TYPE_POWERPC_CPU, dc->desc); |
| 2201 | type_register(&type_info); |
| 2202 | |
Andreas Färber | 5ba4576 | 2013-02-23 11:22:12 +0000 | [diff] [blame] | 2203 | return 0; |
| 2204 | } |
| 2205 | |
David Gibson | feaa64c | 2013-09-26 16:18:35 +1000 | [diff] [blame] | 2206 | int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function) |
| 2207 | { |
| 2208 | struct kvm_rtas_token_args args = { |
| 2209 | .token = token, |
| 2210 | }; |
| 2211 | |
| 2212 | if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) { |
| 2213 | return -ENOENT; |
| 2214 | } |
| 2215 | |
| 2216 | strncpy(args.name, function, sizeof(args.name)); |
| 2217 | |
| 2218 | return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args); |
| 2219 | } |
David Gibson | 12b1143 | 2012-04-04 15:02:05 +1000 | [diff] [blame] | 2220 | |
Alexey Kardashevskiy | e68cb8b | 2013-07-18 14:33:03 -0500 | [diff] [blame] | 2221 | int kvmppc_get_htab_fd(bool write) |
| 2222 | { |
| 2223 | struct kvm_get_htab_fd s = { |
| 2224 | .flags = write ? KVM_GET_HTAB_WRITE : 0, |
| 2225 | .start_index = 0, |
| 2226 | }; |
| 2227 | |
| 2228 | if (!cap_htab_fd) { |
| 2229 | fprintf(stderr, "KVM version doesn't support saving the hash table\n"); |
| 2230 | return -1; |
| 2231 | } |
| 2232 | |
| 2233 | return kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s); |
| 2234 | } |
| 2235 | |
| 2236 | int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) |
| 2237 | { |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 2238 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
Alexey Kardashevskiy | e68cb8b | 2013-07-18 14:33:03 -0500 | [diff] [blame] | 2239 | uint8_t buf[bufsize]; |
| 2240 | ssize_t rc; |
| 2241 | |
| 2242 | do { |
| 2243 | rc = read(fd, buf, bufsize); |
| 2244 | if (rc < 0) { |
| 2245 | fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n", |
| 2246 | strerror(errno)); |
| 2247 | return rc; |
| 2248 | } else if (rc) { |
| 2249 | /* Kernel already retuns data in BE format for the file */ |
| 2250 | qemu_put_buffer(f, buf, rc); |
| 2251 | } |
| 2252 | } while ((rc != 0) |
| 2253 | && ((max_ns < 0) |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 2254 | || ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns))); |
Alexey Kardashevskiy | e68cb8b | 2013-07-18 14:33:03 -0500 | [diff] [blame] | 2255 | |
| 2256 | return (rc == 0) ? 1 : 0; |
| 2257 | } |
| 2258 | |
| 2259 | int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, |
| 2260 | uint16_t n_valid, uint16_t n_invalid) |
| 2261 | { |
| 2262 | struct kvm_get_htab_header *buf; |
| 2263 | size_t chunksize = sizeof(*buf) + n_valid*HASH_PTE_SIZE_64; |
| 2264 | ssize_t rc; |
| 2265 | |
| 2266 | buf = alloca(chunksize); |
| 2267 | /* This is KVM on ppc, so this is all big-endian */ |
| 2268 | buf->index = index; |
| 2269 | buf->n_valid = n_valid; |
| 2270 | buf->n_invalid = n_invalid; |
| 2271 | |
| 2272 | qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64*n_valid); |
| 2273 | |
| 2274 | rc = write(fd, buf, chunksize); |
| 2275 | if (rc < 0) { |
| 2276 | fprintf(stderr, "Error writing KVM hash table: %s\n", |
| 2277 | strerror(errno)); |
| 2278 | return rc; |
| 2279 | } |
| 2280 | if (rc != chunksize) { |
| 2281 | /* We should never get a short write on a single chunk */ |
| 2282 | fprintf(stderr, "Short write, restoring KVM hash table\n"); |
| 2283 | return -1; |
| 2284 | } |
| 2285 | return 0; |
| 2286 | } |
| 2287 | |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 2288 | bool kvm_arch_stop_on_emulation_error(CPUState *cpu) |
Gleb Natapov | 4513d92 | 2010-05-10 11:21:34 +0300 | [diff] [blame] | 2289 | { |
| 2290 | return true; |
| 2291 | } |
Jan Kiszka | a1b87fe | 2011-02-01 22:15:51 +0100 | [diff] [blame] | 2292 | |
Andreas Färber | 20d695a | 2012-10-31 06:57:49 +0100 | [diff] [blame] | 2293 | int kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr) |
Jan Kiszka | a1b87fe | 2011-02-01 22:15:51 +0100 | [diff] [blame] | 2294 | { |
| 2295 | return 1; |
| 2296 | } |
| 2297 | |
| 2298 | int kvm_arch_on_sigbus(int code, void *addr) |
| 2299 | { |
| 2300 | return 1; |
| 2301 | } |
Scott Wood | 8216966 | 2013-06-12 17:26:54 +1000 | [diff] [blame] | 2302 | |
| 2303 | void kvm_arch_init_irq_routing(KVMState *s) |
| 2304 | { |
| 2305 | } |
Greg Kurz | c65f9a0 | 2013-12-11 14:15:34 +0100 | [diff] [blame] | 2306 | |
Aneesh Kumar K.V | 7c43bca | 2014-02-20 18:52:24 +0100 | [diff] [blame] | 2307 | struct kvm_get_htab_buf { |
| 2308 | struct kvm_get_htab_header header; |
| 2309 | /* |
| 2310 | * We require one extra byte for read |
| 2311 | */ |
| 2312 | target_ulong hpte[(HPTES_PER_GROUP * 2) + 1]; |
| 2313 | }; |
| 2314 | |
| 2315 | uint64_t kvmppc_hash64_read_pteg(PowerPCCPU *cpu, target_ulong pte_index) |
| 2316 | { |
| 2317 | int htab_fd; |
| 2318 | struct kvm_get_htab_fd ghf; |
| 2319 | struct kvm_get_htab_buf *hpte_buf; |
| 2320 | |
| 2321 | ghf.flags = 0; |
| 2322 | ghf.start_index = pte_index; |
| 2323 | htab_fd = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &ghf); |
| 2324 | if (htab_fd < 0) { |
| 2325 | goto error_out; |
| 2326 | } |
| 2327 | |
| 2328 | hpte_buf = g_malloc0(sizeof(*hpte_buf)); |
| 2329 | /* |
| 2330 | * Read the hpte group |
| 2331 | */ |
| 2332 | if (read(htab_fd, hpte_buf, sizeof(*hpte_buf)) < 0) { |
| 2333 | goto out_close; |
| 2334 | } |
| 2335 | |
| 2336 | close(htab_fd); |
| 2337 | return (uint64_t)(uintptr_t) hpte_buf->hpte; |
| 2338 | |
| 2339 | out_close: |
| 2340 | g_free(hpte_buf); |
| 2341 | close(htab_fd); |
| 2342 | error_out: |
| 2343 | return 0; |
| 2344 | } |
| 2345 | |
| 2346 | void kvmppc_hash64_free_pteg(uint64_t token) |
| 2347 | { |
| 2348 | struct kvm_get_htab_buf *htab_buf; |
| 2349 | |
| 2350 | htab_buf = container_of((void *)(uintptr_t) token, struct kvm_get_htab_buf, |
| 2351 | hpte); |
| 2352 | g_free(htab_buf); |
| 2353 | return; |
| 2354 | } |
Aneesh Kumar K.V | c138593 | 2014-02-20 18:52:38 +0100 | [diff] [blame] | 2355 | |
| 2356 | void kvmppc_hash64_write_pte(CPUPPCState *env, target_ulong pte_index, |
| 2357 | target_ulong pte0, target_ulong pte1) |
| 2358 | { |
| 2359 | int htab_fd; |
| 2360 | struct kvm_get_htab_fd ghf; |
| 2361 | struct kvm_get_htab_buf hpte_buf; |
| 2362 | |
| 2363 | ghf.flags = 0; |
| 2364 | ghf.start_index = 0; /* Ignored */ |
| 2365 | htab_fd = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &ghf); |
| 2366 | if (htab_fd < 0) { |
| 2367 | goto error_out; |
| 2368 | } |
| 2369 | |
| 2370 | hpte_buf.header.n_valid = 1; |
| 2371 | hpte_buf.header.n_invalid = 0; |
| 2372 | hpte_buf.header.index = pte_index; |
| 2373 | hpte_buf.hpte[0] = pte0; |
| 2374 | hpte_buf.hpte[1] = pte1; |
| 2375 | /* |
| 2376 | * Write the hpte entry. |
| 2377 | * CAUTION: write() has the warn_unused_result attribute. Hence we |
| 2378 | * need to check the return value, even though we do nothing. |
| 2379 | */ |
| 2380 | if (write(htab_fd, &hpte_buf, sizeof(hpte_buf)) < 0) { |
| 2381 | goto out_close; |
| 2382 | } |
| 2383 | |
| 2384 | out_close: |
| 2385 | close(htab_fd); |
| 2386 | return; |
| 2387 | |
| 2388 | error_out: |
| 2389 | return; |
| 2390 | } |