aurel32 | 8dd3dca | 2008-05-04 13:11:44 +0000 | [diff] [blame] | 1 | #include "hw/hw.h" |
| 2 | #include "hw/boards.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 3 | #include "sysemu/kvm.h" |
Alexey Kardashevskiy | a90db15 | 2013-07-18 14:32:54 -0500 | [diff] [blame] | 4 | #include "helper_regs.h" |
aurel32 | 8dd3dca | 2008-05-04 13:11:44 +0000 | [diff] [blame] | 5 | |
Alexey Kardashevskiy | a90db15 | 2013-07-18 14:32:54 -0500 | [diff] [blame] | 6 | static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) |
aurel32 | 8dd3dca | 2008-05-04 13:11:44 +0000 | [diff] [blame] | 7 | { |
Alexey Kardashevskiy | a90db15 | 2013-07-18 14:32:54 -0500 | [diff] [blame] | 8 | PowerPCCPU *cpu = opaque; |
| 9 | CPUPPCState *env = &cpu->env; |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 10 | unsigned int i, j; |
David Gibson | bb59390 | 2011-04-01 15:15:15 +1100 | [diff] [blame] | 11 | target_ulong sdr1; |
David Gibson | 3030442 | 2012-10-29 17:24:59 +0000 | [diff] [blame] | 12 | uint32_t fpscr; |
Richard Henderson | da91a00 | 2013-02-19 23:52:13 -0800 | [diff] [blame] | 13 | target_ulong xer; |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 14 | |
| 15 | for (i = 0; i < 32; i++) |
| 16 | qemu_get_betls(f, &env->gpr[i]); |
| 17 | #if !defined(TARGET_PPC64) |
| 18 | for (i = 0; i < 32; i++) |
| 19 | qemu_get_betls(f, &env->gprh[i]); |
| 20 | #endif |
| 21 | qemu_get_betls(f, &env->lr); |
| 22 | qemu_get_betls(f, &env->ctr); |
| 23 | for (i = 0; i < 8; i++) |
| 24 | qemu_get_be32s(f, &env->crf[i]); |
Richard Henderson | da91a00 | 2013-02-19 23:52:13 -0800 | [diff] [blame] | 25 | qemu_get_betls(f, &xer); |
| 26 | cpu_write_xer(env, xer); |
Nathan Froyd | 18b21a2 | 2009-08-03 08:43:25 -0700 | [diff] [blame] | 27 | qemu_get_betls(f, &env->reserve_addr); |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 28 | qemu_get_betls(f, &env->msr); |
| 29 | for (i = 0; i < 4; i++) |
| 30 | qemu_get_betls(f, &env->tgpr[i]); |
| 31 | for (i = 0; i < 32; i++) { |
| 32 | union { |
| 33 | float64 d; |
| 34 | uint64_t l; |
| 35 | } u; |
| 36 | u.l = qemu_get_be64(f); |
| 37 | env->fpr[i] = u.d; |
| 38 | } |
David Gibson | 3030442 | 2012-10-29 17:24:59 +0000 | [diff] [blame] | 39 | qemu_get_be32s(f, &fpscr); |
| 40 | env->fpscr = fpscr; |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 41 | qemu_get_sbe32s(f, &env->access_type); |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 42 | #if defined(TARGET_PPC64) |
David Gibson | 9baea4a | 2013-03-12 00:31:03 +0000 | [diff] [blame] | 43 | qemu_get_betls(f, &env->spr[SPR_ASR]); |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 44 | qemu_get_sbe32s(f, &env->slb_nr); |
| 45 | #endif |
David Gibson | bb59390 | 2011-04-01 15:15:15 +1100 | [diff] [blame] | 46 | qemu_get_betls(f, &sdr1); |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 47 | for (i = 0; i < 32; i++) |
| 48 | qemu_get_betls(f, &env->sr[i]); |
| 49 | for (i = 0; i < 2; i++) |
| 50 | for (j = 0; j < 8; j++) |
| 51 | qemu_get_betls(f, &env->DBAT[i][j]); |
| 52 | for (i = 0; i < 2; i++) |
| 53 | for (j = 0; j < 8; j++) |
| 54 | qemu_get_betls(f, &env->IBAT[i][j]); |
| 55 | qemu_get_sbe32s(f, &env->nb_tlb); |
| 56 | qemu_get_sbe32s(f, &env->tlb_per_way); |
| 57 | qemu_get_sbe32s(f, &env->nb_ways); |
| 58 | qemu_get_sbe32s(f, &env->last_way); |
| 59 | qemu_get_sbe32s(f, &env->id_tlbs); |
| 60 | qemu_get_sbe32s(f, &env->nb_pids); |
Alexander Graf | 1c53acc | 2011-06-17 01:00:28 +0200 | [diff] [blame] | 61 | if (env->tlb.tlb6) { |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 62 | // XXX assumes 6xx |
| 63 | for (i = 0; i < env->nb_tlb; i++) { |
Alexander Graf | 1c53acc | 2011-06-17 01:00:28 +0200 | [diff] [blame] | 64 | qemu_get_betls(f, &env->tlb.tlb6[i].pte0); |
| 65 | qemu_get_betls(f, &env->tlb.tlb6[i].pte1); |
| 66 | qemu_get_betls(f, &env->tlb.tlb6[i].EPN); |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 67 | } |
| 68 | } |
| 69 | for (i = 0; i < 4; i++) |
| 70 | qemu_get_betls(f, &env->pb[i]); |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 71 | for (i = 0; i < 1024; i++) |
| 72 | qemu_get_betls(f, &env->spr[i]); |
David Gibson | bb59390 | 2011-04-01 15:15:15 +1100 | [diff] [blame] | 73 | ppc_store_sdr1(env, sdr1); |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 74 | qemu_get_be32s(f, &env->vscr); |
| 75 | qemu_get_be64s(f, &env->spe_acc); |
| 76 | qemu_get_be32s(f, &env->spe_fscr); |
| 77 | qemu_get_betls(f, &env->msr_mask); |
| 78 | qemu_get_be32s(f, &env->flags); |
| 79 | qemu_get_sbe32s(f, &env->error_code); |
| 80 | qemu_get_be32s(f, &env->pending_interrupts); |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 81 | qemu_get_be32s(f, &env->irq_input_state); |
| 82 | for (i = 0; i < POWERPC_EXCP_NB; i++) |
| 83 | qemu_get_betls(f, &env->excp_vectors[i]); |
| 84 | qemu_get_betls(f, &env->excp_prefix); |
| 85 | qemu_get_betls(f, &env->ivor_mask); |
| 86 | qemu_get_betls(f, &env->ivpr_mask); |
| 87 | qemu_get_betls(f, &env->hreset_vector); |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 88 | qemu_get_betls(f, &env->nip); |
| 89 | qemu_get_betls(f, &env->hflags); |
| 90 | qemu_get_betls(f, &env->hflags_nmsr); |
| 91 | qemu_get_sbe32s(f, &env->mmu_idx); |
David Gibson | 011aba2 | 2012-09-20 17:42:28 +0000 | [diff] [blame] | 92 | qemu_get_sbe32(f); /* Discard unused power_mode */ |
blueswir1 | a456d59 | 2008-12-30 19:01:44 +0000 | [diff] [blame] | 93 | |
aurel32 | 8dd3dca | 2008-05-04 13:11:44 +0000 | [diff] [blame] | 94 | return 0; |
| 95 | } |
Alexey Kardashevskiy | a90db15 | 2013-07-18 14:32:54 -0500 | [diff] [blame] | 96 | |
| 97 | static int get_avr(QEMUFile *f, void *pv, size_t size) |
| 98 | { |
| 99 | ppc_avr_t *v = pv; |
| 100 | |
| 101 | v->u64[0] = qemu_get_be64(f); |
| 102 | v->u64[1] = qemu_get_be64(f); |
| 103 | |
| 104 | return 0; |
| 105 | } |
| 106 | |
| 107 | static void put_avr(QEMUFile *f, void *pv, size_t size) |
| 108 | { |
| 109 | ppc_avr_t *v = pv; |
| 110 | |
| 111 | qemu_put_be64(f, v->u64[0]); |
| 112 | qemu_put_be64(f, v->u64[1]); |
| 113 | } |
| 114 | |
| 115 | const VMStateInfo vmstate_info_avr = { |
| 116 | .name = "avr", |
| 117 | .get = get_avr, |
| 118 | .put = put_avr, |
| 119 | }; |
| 120 | |
| 121 | #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ |
| 122 | VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) |
| 123 | |
| 124 | #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ |
| 125 | VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) |
| 126 | |
| 127 | static void cpu_pre_save(void *opaque) |
| 128 | { |
| 129 | PowerPCCPU *cpu = opaque; |
| 130 | CPUPPCState *env = &cpu->env; |
| 131 | int i; |
| 132 | |
| 133 | env->spr[SPR_LR] = env->lr; |
| 134 | env->spr[SPR_CTR] = env->ctr; |
| 135 | env->spr[SPR_XER] = env->xer; |
| 136 | #if defined(TARGET_PPC64) |
| 137 | env->spr[SPR_CFAR] = env->cfar; |
| 138 | #endif |
| 139 | env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; |
| 140 | |
| 141 | for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { |
| 142 | env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i]; |
| 143 | env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i]; |
| 144 | env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i]; |
| 145 | env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i]; |
| 146 | } |
| 147 | for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { |
| 148 | env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4]; |
| 149 | env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4]; |
| 150 | env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4]; |
| 151 | env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4]; |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | static int cpu_post_load(void *opaque, int version_id) |
| 156 | { |
| 157 | PowerPCCPU *cpu = opaque; |
| 158 | CPUPPCState *env = &cpu->env; |
| 159 | int i; |
| 160 | |
| 161 | env->lr = env->spr[SPR_LR]; |
| 162 | env->ctr = env->spr[SPR_CTR]; |
| 163 | env->xer = env->spr[SPR_XER]; |
| 164 | #if defined(TARGET_PPC64) |
| 165 | env->cfar = env->spr[SPR_CFAR]; |
| 166 | #endif |
| 167 | env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; |
| 168 | |
| 169 | for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { |
| 170 | env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i]; |
| 171 | env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1]; |
| 172 | env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i]; |
| 173 | env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1]; |
| 174 | } |
| 175 | for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { |
| 176 | env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i]; |
| 177 | env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1]; |
| 178 | env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i]; |
| 179 | env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1]; |
| 180 | } |
| 181 | |
| 182 | /* Restore htab_base and htab_mask variables */ |
| 183 | ppc_store_sdr1(env, env->spr[SPR_SDR1]); |
| 184 | |
| 185 | hreg_compute_hflags(env); |
| 186 | hreg_compute_mem_idx(env); |
| 187 | |
| 188 | return 0; |
| 189 | } |
| 190 | |
| 191 | static bool fpu_needed(void *opaque) |
| 192 | { |
| 193 | PowerPCCPU *cpu = opaque; |
| 194 | |
| 195 | return (cpu->env.insns_flags & PPC_FLOAT); |
| 196 | } |
| 197 | |
| 198 | static const VMStateDescription vmstate_fpu = { |
| 199 | .name = "cpu/fpu", |
| 200 | .version_id = 1, |
| 201 | .minimum_version_id = 1, |
| 202 | .minimum_version_id_old = 1, |
| 203 | .fields = (VMStateField []) { |
| 204 | VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), |
| 205 | VMSTATE_UINTTL(env.fpscr, PowerPCCPU), |
| 206 | VMSTATE_END_OF_LIST() |
| 207 | }, |
| 208 | }; |
| 209 | |
| 210 | static bool altivec_needed(void *opaque) |
| 211 | { |
| 212 | PowerPCCPU *cpu = opaque; |
| 213 | |
| 214 | return (cpu->env.insns_flags & PPC_ALTIVEC); |
| 215 | } |
| 216 | |
| 217 | static const VMStateDescription vmstate_altivec = { |
| 218 | .name = "cpu/altivec", |
| 219 | .version_id = 1, |
| 220 | .minimum_version_id = 1, |
| 221 | .minimum_version_id_old = 1, |
| 222 | .fields = (VMStateField []) { |
| 223 | VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), |
| 224 | VMSTATE_UINT32(env.vscr, PowerPCCPU), |
| 225 | VMSTATE_END_OF_LIST() |
| 226 | }, |
| 227 | }; |
| 228 | |
| 229 | static bool vsx_needed(void *opaque) |
| 230 | { |
| 231 | PowerPCCPU *cpu = opaque; |
| 232 | |
| 233 | return (cpu->env.insns_flags2 & PPC2_VSX); |
| 234 | } |
| 235 | |
| 236 | static const VMStateDescription vmstate_vsx = { |
| 237 | .name = "cpu/vsx", |
| 238 | .version_id = 1, |
| 239 | .minimum_version_id = 1, |
| 240 | .minimum_version_id_old = 1, |
| 241 | .fields = (VMStateField []) { |
| 242 | VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), |
| 243 | VMSTATE_END_OF_LIST() |
| 244 | }, |
| 245 | }; |
| 246 | |
| 247 | static bool sr_needed(void *opaque) |
| 248 | { |
| 249 | #ifdef TARGET_PPC64 |
| 250 | PowerPCCPU *cpu = opaque; |
| 251 | |
| 252 | return !(cpu->env.mmu_model & POWERPC_MMU_64); |
| 253 | #else |
| 254 | return true; |
| 255 | #endif |
| 256 | } |
| 257 | |
| 258 | static const VMStateDescription vmstate_sr = { |
| 259 | .name = "cpu/sr", |
| 260 | .version_id = 1, |
| 261 | .minimum_version_id = 1, |
| 262 | .minimum_version_id_old = 1, |
| 263 | .fields = (VMStateField []) { |
| 264 | VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), |
| 265 | VMSTATE_END_OF_LIST() |
| 266 | }, |
| 267 | }; |
| 268 | |
| 269 | #ifdef TARGET_PPC64 |
| 270 | static int get_slbe(QEMUFile *f, void *pv, size_t size) |
| 271 | { |
| 272 | ppc_slb_t *v = pv; |
| 273 | |
| 274 | v->esid = qemu_get_be64(f); |
| 275 | v->vsid = qemu_get_be64(f); |
| 276 | |
| 277 | return 0; |
| 278 | } |
| 279 | |
| 280 | static void put_slbe(QEMUFile *f, void *pv, size_t size) |
| 281 | { |
| 282 | ppc_slb_t *v = pv; |
| 283 | |
| 284 | qemu_put_be64(f, v->esid); |
| 285 | qemu_put_be64(f, v->vsid); |
| 286 | } |
| 287 | |
| 288 | const VMStateInfo vmstate_info_slbe = { |
| 289 | .name = "slbe", |
| 290 | .get = get_slbe, |
| 291 | .put = put_slbe, |
| 292 | }; |
| 293 | |
| 294 | #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ |
| 295 | VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) |
| 296 | |
| 297 | #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ |
| 298 | VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) |
| 299 | |
| 300 | static bool slb_needed(void *opaque) |
| 301 | { |
| 302 | PowerPCCPU *cpu = opaque; |
| 303 | |
| 304 | /* We don't support any of the old segment table based 64-bit CPUs */ |
| 305 | return (cpu->env.mmu_model & POWERPC_MMU_64); |
| 306 | } |
| 307 | |
| 308 | static const VMStateDescription vmstate_slb = { |
| 309 | .name = "cpu/slb", |
| 310 | .version_id = 1, |
| 311 | .minimum_version_id = 1, |
| 312 | .minimum_version_id_old = 1, |
| 313 | .fields = (VMStateField []) { |
| 314 | VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU), |
| 315 | VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, 64), |
| 316 | VMSTATE_END_OF_LIST() |
| 317 | } |
| 318 | }; |
| 319 | #endif /* TARGET_PPC64 */ |
| 320 | |
| 321 | static const VMStateDescription vmstate_tlb6xx_entry = { |
| 322 | .name = "cpu/tlb6xx_entry", |
| 323 | .version_id = 1, |
| 324 | .minimum_version_id = 1, |
| 325 | .minimum_version_id_old = 1, |
| 326 | .fields = (VMStateField []) { |
| 327 | VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), |
| 328 | VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), |
| 329 | VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), |
| 330 | VMSTATE_END_OF_LIST() |
| 331 | }, |
| 332 | }; |
| 333 | |
| 334 | static bool tlb6xx_needed(void *opaque) |
| 335 | { |
| 336 | PowerPCCPU *cpu = opaque; |
| 337 | CPUPPCState *env = &cpu->env; |
| 338 | |
| 339 | return env->nb_tlb && (env->tlb_type == TLB_6XX); |
| 340 | } |
| 341 | |
| 342 | static const VMStateDescription vmstate_tlb6xx = { |
| 343 | .name = "cpu/tlb6xx", |
| 344 | .version_id = 1, |
| 345 | .minimum_version_id = 1, |
| 346 | .minimum_version_id_old = 1, |
| 347 | .fields = (VMStateField []) { |
| 348 | VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), |
| 349 | VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, |
| 350 | env.nb_tlb, |
| 351 | vmstate_tlb6xx_entry, |
| 352 | ppc6xx_tlb_t), |
| 353 | VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), |
| 354 | VMSTATE_END_OF_LIST() |
| 355 | } |
| 356 | }; |
| 357 | |
| 358 | static const VMStateDescription vmstate_tlbemb_entry = { |
| 359 | .name = "cpu/tlbemb_entry", |
| 360 | .version_id = 1, |
| 361 | .minimum_version_id = 1, |
| 362 | .minimum_version_id_old = 1, |
| 363 | .fields = (VMStateField []) { |
| 364 | VMSTATE_UINT64(RPN, ppcemb_tlb_t), |
| 365 | VMSTATE_UINTTL(EPN, ppcemb_tlb_t), |
| 366 | VMSTATE_UINTTL(PID, ppcemb_tlb_t), |
| 367 | VMSTATE_UINTTL(size, ppcemb_tlb_t), |
| 368 | VMSTATE_UINT32(prot, ppcemb_tlb_t), |
| 369 | VMSTATE_UINT32(attr, ppcemb_tlb_t), |
| 370 | VMSTATE_END_OF_LIST() |
| 371 | }, |
| 372 | }; |
| 373 | |
| 374 | static bool tlbemb_needed(void *opaque) |
| 375 | { |
| 376 | PowerPCCPU *cpu = opaque; |
| 377 | CPUPPCState *env = &cpu->env; |
| 378 | |
| 379 | return env->nb_tlb && (env->tlb_type == TLB_EMB); |
| 380 | } |
| 381 | |
| 382 | static bool pbr403_needed(void *opaque) |
| 383 | { |
| 384 | PowerPCCPU *cpu = opaque; |
| 385 | uint32_t pvr = cpu->env.spr[SPR_PVR]; |
| 386 | |
| 387 | return (pvr & 0xffff0000) == 0x00200000; |
| 388 | } |
| 389 | |
| 390 | static const VMStateDescription vmstate_pbr403 = { |
| 391 | .name = "cpu/pbr403", |
| 392 | .version_id = 1, |
| 393 | .minimum_version_id = 1, |
| 394 | .minimum_version_id_old = 1, |
| 395 | .fields = (VMStateField []) { |
| 396 | VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), |
| 397 | VMSTATE_END_OF_LIST() |
| 398 | }, |
| 399 | }; |
| 400 | |
| 401 | static const VMStateDescription vmstate_tlbemb = { |
| 402 | .name = "cpu/tlb6xx", |
| 403 | .version_id = 1, |
| 404 | .minimum_version_id = 1, |
| 405 | .minimum_version_id_old = 1, |
| 406 | .fields = (VMStateField []) { |
| 407 | VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), |
| 408 | VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, |
| 409 | env.nb_tlb, |
| 410 | vmstate_tlbemb_entry, |
| 411 | ppcemb_tlb_t), |
| 412 | /* 403 protection registers */ |
| 413 | VMSTATE_END_OF_LIST() |
| 414 | }, |
| 415 | .subsections = (VMStateSubsection []) { |
| 416 | { |
| 417 | .vmsd = &vmstate_pbr403, |
| 418 | .needed = pbr403_needed, |
| 419 | } , { |
| 420 | /* empty */ |
| 421 | } |
| 422 | } |
| 423 | }; |
| 424 | |
| 425 | static const VMStateDescription vmstate_tlbmas_entry = { |
| 426 | .name = "cpu/tlbmas_entry", |
| 427 | .version_id = 1, |
| 428 | .minimum_version_id = 1, |
| 429 | .minimum_version_id_old = 1, |
| 430 | .fields = (VMStateField []) { |
| 431 | VMSTATE_UINT32(mas8, ppcmas_tlb_t), |
| 432 | VMSTATE_UINT32(mas1, ppcmas_tlb_t), |
| 433 | VMSTATE_UINT64(mas2, ppcmas_tlb_t), |
| 434 | VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), |
| 435 | VMSTATE_END_OF_LIST() |
| 436 | }, |
| 437 | }; |
| 438 | |
| 439 | static bool tlbmas_needed(void *opaque) |
| 440 | { |
| 441 | PowerPCCPU *cpu = opaque; |
| 442 | CPUPPCState *env = &cpu->env; |
| 443 | |
| 444 | return env->nb_tlb && (env->tlb_type == TLB_MAS); |
| 445 | } |
| 446 | |
| 447 | static const VMStateDescription vmstate_tlbmas = { |
| 448 | .name = "cpu/tlbmas", |
| 449 | .version_id = 1, |
| 450 | .minimum_version_id = 1, |
| 451 | .minimum_version_id_old = 1, |
| 452 | .fields = (VMStateField []) { |
| 453 | VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), |
| 454 | VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, |
| 455 | env.nb_tlb, |
| 456 | vmstate_tlbmas_entry, |
| 457 | ppcmas_tlb_t), |
| 458 | VMSTATE_END_OF_LIST() |
| 459 | } |
| 460 | }; |
| 461 | |
| 462 | const VMStateDescription vmstate_ppc_cpu = { |
| 463 | .name = "cpu", |
| 464 | .version_id = 5, |
| 465 | .minimum_version_id = 5, |
| 466 | .minimum_version_id_old = 4, |
| 467 | .load_state_old = cpu_load_old, |
| 468 | .pre_save = cpu_pre_save, |
| 469 | .post_load = cpu_post_load, |
| 470 | .fields = (VMStateField []) { |
| 471 | /* Verify we haven't changed the pvr */ |
| 472 | VMSTATE_UINTTL_EQUAL(env.spr[SPR_PVR], PowerPCCPU), |
| 473 | |
| 474 | /* User mode architected state */ |
| 475 | VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), |
| 476 | #if !defined(TARGET_PPC64) |
| 477 | VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), |
| 478 | #endif |
| 479 | VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), |
| 480 | VMSTATE_UINTTL(env.nip, PowerPCCPU), |
| 481 | |
| 482 | /* SPRs */ |
| 483 | VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), |
| 484 | VMSTATE_UINT64(env.spe_acc, PowerPCCPU), |
| 485 | |
| 486 | /* Reservation */ |
| 487 | VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), |
| 488 | |
| 489 | /* Supervisor mode architected state */ |
| 490 | VMSTATE_UINTTL(env.msr, PowerPCCPU), |
| 491 | |
| 492 | /* Internal state */ |
| 493 | VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), |
| 494 | /* FIXME: access_type? */ |
| 495 | |
| 496 | /* Sanity checking */ |
| 497 | VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU), |
| 498 | VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU), |
| 499 | VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU), |
| 500 | VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU), |
| 501 | VMSTATE_END_OF_LIST() |
| 502 | }, |
| 503 | .subsections = (VMStateSubsection []) { |
| 504 | { |
| 505 | .vmsd = &vmstate_fpu, |
| 506 | .needed = fpu_needed, |
| 507 | } , { |
| 508 | .vmsd = &vmstate_altivec, |
| 509 | .needed = altivec_needed, |
| 510 | } , { |
| 511 | .vmsd = &vmstate_vsx, |
| 512 | .needed = vsx_needed, |
| 513 | } , { |
| 514 | .vmsd = &vmstate_sr, |
| 515 | .needed = sr_needed, |
| 516 | } , { |
| 517 | #ifdef TARGET_PPC64 |
| 518 | .vmsd = &vmstate_slb, |
| 519 | .needed = slb_needed, |
| 520 | } , { |
| 521 | #endif /* TARGET_PPC64 */ |
| 522 | .vmsd = &vmstate_tlb6xx, |
| 523 | .needed = tlb6xx_needed, |
| 524 | } , { |
| 525 | .vmsd = &vmstate_tlbemb, |
| 526 | .needed = tlbemb_needed, |
| 527 | } , { |
| 528 | .vmsd = &vmstate_tlbmas, |
| 529 | .needed = tlbmas_needed, |
| 530 | } , { |
| 531 | /* empty */ |
| 532 | } |
| 533 | } |
| 534 | }; |