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ths81fdc5f2007-10-08 13:04:02 +00001/*
2 * CRIS helper routines
3 *
4 * Copyright (c) 2007 AXIS Communications
5 * Written by Edgar E. Iglesias
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
ths81fdc5f2007-10-08 13:04:02 +000019 */
20
Blue Swirl3e457172011-07-13 12:44:15 +000021#include "cpu.h"
22#include "dyngen-exec.h"
edgar_igl786c02f2008-03-14 01:08:09 +000023#include "mmu.h"
edgar_igl30abcfc2008-05-27 21:10:56 +000024#include "helper.h"
edgar_iglc38ac982009-01-07 13:19:21 +000025#include "host-utils.h"
ths81fdc5f2007-10-08 13:04:02 +000026
aliguorid12d51d2009-01-15 21:48:06 +000027//#define CRIS_OP_HELPER_DEBUG
28
29
30#ifdef CRIS_OP_HELPER_DEBUG
31#define D(x) x
aliguori93fcfe32009-01-15 22:34:14 +000032#define D_LOG(...) qemu_log(__VA__ARGS__)
aliguorid12d51d2009-01-15 21:48:06 +000033#else
pbrooke2eef172008-06-08 01:09:01 +000034#define D(x)
aliguorid12d51d2009-01-15 21:48:06 +000035#define D_LOG(...) do { } while (0)
36#endif
pbrooke2eef172008-06-08 01:09:01 +000037
38#if !defined(CONFIG_USER_ONLY)
Blue Swirl3e457172011-07-13 12:44:15 +000039#include "softmmu_exec.h"
pbrooke2eef172008-06-08 01:09:01 +000040
ths81fdc5f2007-10-08 13:04:02 +000041#define MMUSUFFIX _mmu
ths81fdc5f2007-10-08 13:04:02 +000042
43#define SHIFT 0
44#include "softmmu_template.h"
45
46#define SHIFT 1
47#include "softmmu_template.h"
48
49#define SHIFT 2
50#include "softmmu_template.h"
51
52#define SHIFT 3
53#include "softmmu_template.h"
54
55/* Try to fill the TLB and return an exception if error. If retaddr is
56 NULL, it means that the function was called in C code (i.e. not
57 from generated code or from helper.c) */
58/* XXX: fix it to restore all registers */
Blue Swirlbccd9ec2011-07-04 20:57:05 +000059void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
60 void *retaddr)
ths81fdc5f2007-10-08 13:04:02 +000061{
62 TranslationBlock *tb;
63 CPUState *saved_env;
bellard44f86252007-11-11 12:35:55 +000064 unsigned long pc;
ths81fdc5f2007-10-08 13:04:02 +000065 int ret;
66
ths81fdc5f2007-10-08 13:04:02 +000067 saved_env = env;
Blue Swirlbccd9ec2011-07-04 20:57:05 +000068 env = env1;
edgar_iglb41f7df2008-05-02 22:16:17 +000069
aliguorid12d51d2009-01-15 21:48:06 +000070 D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__,
71 env->pc, env->debug1, retaddr);
Blue Swirl97b348e2011-08-01 16:12:17 +000072 ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
ths551bd272008-07-03 17:57:36 +000073 if (unlikely(ret)) {
ths81fdc5f2007-10-08 13:04:02 +000074 if (retaddr) {
75 /* now we have a real cpu fault */
bellard44f86252007-11-11 12:35:55 +000076 pc = (unsigned long)retaddr;
ths81fdc5f2007-10-08 13:04:02 +000077 tb = tb_find_pc(pc);
78 if (tb) {
79 /* the PC is inside the translated code. It means that we have
80 a virtual CPU fault */
Stefan Weil618ba8e2011-04-18 06:39:53 +000081 cpu_restore_state(tb, env, pc);
edgar_igl30abcfc2008-05-27 21:10:56 +000082
83 /* Evaluate flags after retranslation. */
84 helper_top_evaluate_flags();
ths81fdc5f2007-10-08 13:04:02 +000085 }
86 }
Blue Swirl1162c042011-05-14 12:52:35 +000087 cpu_loop_exit(env);
ths81fdc5f2007-10-08 13:04:02 +000088 }
89 env = saved_env;
90}
91
pbrooke2eef172008-06-08 01:09:01 +000092#endif
93
edgar_igldceaf392008-05-07 15:24:53 +000094void helper_raise_exception(uint32_t index)
edgar_igl786c02f2008-03-14 01:08:09 +000095{
edgar_igldceaf392008-05-07 15:24:53 +000096 env->exception_index = index;
Blue Swirl1162c042011-05-14 12:52:35 +000097 cpu_loop_exit(env);
edgar_igl786c02f2008-03-14 01:08:09 +000098}
99
edgar_iglcf1d97f2008-05-13 10:59:14 +0000100void helper_tlb_flush_pid(uint32_t pid)
101{
102#if !defined(CONFIG_USER_ONLY)
edgar_igl28de16d2008-09-22 20:51:28 +0000103 pid &= 0xff;
104 if (pid != (env->pregs[PR_PID] & 0xff))
105 cris_mmu_flush_pid(env, env->pregs[PR_PID]);
edgar_iglcf1d97f2008-05-13 10:59:14 +0000106#endif
107}
108
edgar_igla1aebcb2008-10-07 22:48:41 +0000109void helper_spc_write(uint32_t new_spc)
110{
111#if !defined(CONFIG_USER_ONLY)
112 tlb_flush_page(env, env->pregs[PR_SPC]);
113 tlb_flush_page(env, new_spc);
114#endif
115}
116
edgar_igl30abcfc2008-05-27 21:10:56 +0000117void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
edgar_iglb41f7df2008-05-02 22:16:17 +0000118{
aliguori93fcfe32009-01-15 22:34:14 +0000119 qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
edgar_iglb41f7df2008-05-02 22:16:17 +0000120}
121
edgar_iglcf1d97f2008-05-13 10:59:14 +0000122/* Used by the tlb decoder. */
123#define EXTRACT_FIELD(src, start, end) \
124 (((src) >> start) & ((1 << (end - start + 1)) - 1))
125
edgar_igldceaf392008-05-07 15:24:53 +0000126void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
127{
128 uint32_t srs;
129 srs = env->pregs[PR_SRS];
130 srs &= 3;
131 env->sregs[srs][sreg] = env->regs[reg];
132
133#if !defined(CONFIG_USER_ONLY)
134 if (srs == 1 || srs == 2) {
135 if (sreg == 6) {
136 /* Writes to tlb-hi write to mm_cause as a side
137 effect. */
edgar_igl6913ba52008-06-30 15:27:47 +0000138 env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
139 env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
edgar_igldceaf392008-05-07 15:24:53 +0000140 }
141 else if (sreg == 5) {
142 uint32_t set;
143 uint32_t idx;
144 uint32_t lo, hi;
145 uint32_t vaddr;
edgar_iglcf1d97f2008-05-13 10:59:14 +0000146 int tlb_v;
edgar_igldceaf392008-05-07 15:24:53 +0000147
148 idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
149 set >>= 4;
150 set &= 3;
151
152 idx &= 15;
153 /* We've just made a write to tlb_lo. */
154 lo = env->sregs[SFR_RW_MM_TLB_LO];
155 /* Writes are done via r_mm_cause. */
156 hi = env->sregs[SFR_R_MM_CAUSE];
edgar_iglcf1d97f2008-05-13 10:59:14 +0000157
158 vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
159 13, 31);
160 vaddr <<= TARGET_PAGE_BITS;
161 tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
162 3, 3);
edgar_igldceaf392008-05-07 15:24:53 +0000163 env->tlbsets[srs - 1][set][idx].lo = lo;
164 env->tlbsets[srs - 1][set][idx].hi = hi;
edgar_iglcf1d97f2008-05-13 10:59:14 +0000165
aliguorid12d51d2009-01-15 21:48:06 +0000166 D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
167 vaddr, tlb_v, env->pc);
Edgar E. Iglesias3e18c6b2010-10-07 21:20:52 +0200168 if (tlb_v) {
169 tlb_flush_page(env, vaddr);
170 }
edgar_igldceaf392008-05-07 15:24:53 +0000171 }
172 }
173#endif
174}
175
176void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
177{
178 uint32_t srs;
179 env->pregs[PR_SRS] &= 3;
180 srs = env->pregs[PR_SRS];
181
182#if !defined(CONFIG_USER_ONLY)
183 if (srs == 1 || srs == 2)
184 {
185 uint32_t set;
186 uint32_t idx;
187 uint32_t lo, hi;
188
189 idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
190 set >>= 4;
191 set &= 3;
192 idx &= 15;
193
194 /* Update the mirror regs. */
195 hi = env->tlbsets[srs - 1][set][idx].hi;
196 lo = env->tlbsets[srs - 1][set][idx].lo;
197 env->sregs[SFR_RW_MM_TLB_HI] = hi;
198 env->sregs[SFR_RW_MM_TLB_LO] = lo;
199 }
200#endif
201 env->regs[reg] = env->sregs[srs][sreg];
edgar_igldceaf392008-05-07 15:24:53 +0000202}
203
204static void cris_ccs_rshift(CPUState *env)
205{
206 uint32_t ccs;
207
208 /* Apply the ccs shift. */
209 ccs = env->pregs[PR_CCS];
210 ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
211 if (ccs & U_FLAG)
212 {
213 /* Enter user mode. */
214 env->ksp = env->regs[R_SP];
215 env->regs[R_SP] = env->pregs[PR_USP];
216 }
217
218 env->pregs[PR_CCS] = ccs;
219}
220
edgar_iglb41f7df2008-05-02 22:16:17 +0000221void helper_rfe(void)
222{
edgar_iglbf443332008-06-06 11:17:17 +0000223 int rflag = env->pregs[PR_CCS] & R_FLAG;
224
aliguorid12d51d2009-01-15 21:48:06 +0000225 D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
edgar_iglb41f7df2008-05-02 22:16:17 +0000226 env->pregs[PR_ERP], env->pregs[PR_PID],
227 env->pregs[PR_CCS],
aliguorid12d51d2009-01-15 21:48:06 +0000228 env->btarget);
edgar_igldceaf392008-05-07 15:24:53 +0000229
230 cris_ccs_rshift(env);
231
232 /* RFE sets the P_FLAG only if the R_FLAG is not set. */
edgar_iglbf443332008-06-06 11:17:17 +0000233 if (!rflag)
edgar_igldceaf392008-05-07 15:24:53 +0000234 env->pregs[PR_CCS] |= P_FLAG;
edgar_iglb41f7df2008-05-02 22:16:17 +0000235}
236
edgar_igl5bf8f1a2008-06-09 23:07:50 +0000237void helper_rfn(void)
238{
239 int rflag = env->pregs[PR_CCS] & R_FLAG;
240
aliguorid12d51d2009-01-15 21:48:06 +0000241 D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
edgar_igl5bf8f1a2008-06-09 23:07:50 +0000242 env->pregs[PR_ERP], env->pregs[PR_PID],
243 env->pregs[PR_CCS],
aliguorid12d51d2009-01-15 21:48:06 +0000244 env->btarget);
edgar_igl5bf8f1a2008-06-09 23:07:50 +0000245
246 cris_ccs_rshift(env);
247
248 /* Set the P_FLAG only if the R_FLAG is not set. */
249 if (!rflag)
250 env->pregs[PR_CCS] |= P_FLAG;
251
252 /* Always set the M flag. */
253 env->pregs[PR_CCS] |= M_FLAG;
254}
255
edgar_iglc38ac982009-01-07 13:19:21 +0000256uint32_t helper_lz(uint32_t t0)
257{
258 return clz32(t0);
259}
260
edgar_iglabd5c942009-01-07 13:11:22 +0000261uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
262{
263 /* FIXME: clean this up. */
264
265 /* des ref:
266 The N flag is set according to the selected bit in the dest reg.
267 The Z flag is set if the selected bit and all bits to the right are
268 zero.
269 The X flag is cleared.
270 Other flags are left untouched.
271 The destination reg is not affected.*/
272 unsigned int fz, sbit, bset, mask, masked_t0;
273
274 sbit = t1 & 31;
275 bset = !!(t0 & (1 << sbit));
276 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
277 masked_t0 = t0 & mask;
278 fz = !(masked_t0 | bset);
279
280 /* Clear the X, N and Z flags. */
281 ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
Edgar E. Iglesias95475212010-02-15 11:20:30 +0100282 if (env->pregs[PR_VR] < 32)
283 ccs &= ~(V_FLAG | C_FLAG);
edgar_iglabd5c942009-01-07 13:11:22 +0000284 /* Set the N and Z flags accordingly. */
285 ccs |= (bset << 3) | (fz << 2);
286 return ccs;
287}
288
edgar_igl62318682009-01-07 23:38:41 +0000289static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
edgar_iglb41f7df2008-05-02 22:16:17 +0000290{
edgar_igla8cf66b2009-01-07 12:25:15 +0000291 unsigned int x, z, mask;
edgar_iglb41f7df2008-05-02 22:16:17 +0000292
293 /* Extended arithmetics, leave the z flag alone. */
edgar_igl30abcfc2008-05-27 21:10:56 +0000294 x = env->cc_x;
edgar_igla8cf66b2009-01-07 12:25:15 +0000295 mask = env->cc_mask | X_FLAG;
296 if (x) {
297 z = flags & Z_FLAG;
298 mask = mask & ~z;
299 }
300 flags &= mask;
edgar_iglb41f7df2008-05-02 22:16:17 +0000301
302 /* all insn clear the x-flag except setf or clrf. */
edgar_igl62318682009-01-07 23:38:41 +0000303 ccs &= ~mask;
304 ccs |= flags;
305 return ccs;
edgar_iglb41f7df2008-05-02 22:16:17 +0000306}
307
edgar_igl62318682009-01-07 23:38:41 +0000308uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
edgar_iglb41f7df2008-05-02 22:16:17 +0000309{
edgar_iglb41f7df2008-05-02 22:16:17 +0000310 uint32_t flags = 0;
edgar_igldceaf392008-05-07 15:24:53 +0000311 int64_t tmp;
edgar_iglb41f7df2008-05-02 22:16:17 +0000312 int dneg;
313
edgar_iglb41f7df2008-05-02 22:16:17 +0000314 dneg = ((int32_t)res) < 0;
315
edgar_igldceaf392008-05-07 15:24:53 +0000316 tmp = mof;
317 tmp <<= 32;
318 tmp |= res;
edgar_iglb41f7df2008-05-02 22:16:17 +0000319 if (tmp == 0)
320 flags |= Z_FLAG;
321 else if (tmp < 0)
322 flags |= N_FLAG;
323 if ((dneg && mof != -1)
324 || (!dneg && mof != 0))
325 flags |= V_FLAG;
edgar_igl62318682009-01-07 23:38:41 +0000326 return evaluate_flags_writeback(flags, ccs);
edgar_iglb41f7df2008-05-02 22:16:17 +0000327}
328
edgar_igl62318682009-01-07 23:38:41 +0000329uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
edgar_iglb41f7df2008-05-02 22:16:17 +0000330{
edgar_iglb41f7df2008-05-02 22:16:17 +0000331 uint32_t flags = 0;
edgar_igldceaf392008-05-07 15:24:53 +0000332 uint64_t tmp;
edgar_iglb41f7df2008-05-02 22:16:17 +0000333
edgar_igldceaf392008-05-07 15:24:53 +0000334 tmp = mof;
335 tmp <<= 32;
336 tmp |= res;
edgar_iglb41f7df2008-05-02 22:16:17 +0000337 if (tmp == 0)
338 flags |= Z_FLAG;
339 else if (tmp >> 63)
340 flags |= N_FLAG;
341 if (mof)
342 flags |= V_FLAG;
343
edgar_igl62318682009-01-07 23:38:41 +0000344 return evaluate_flags_writeback(flags, ccs);
edgar_iglb41f7df2008-05-02 22:16:17 +0000345}
346
edgar_igl62318682009-01-07 23:38:41 +0000347uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
348 uint32_t src, uint32_t dst, uint32_t res)
edgar_iglb41f7df2008-05-02 22:16:17 +0000349{
edgar_iglb41f7df2008-05-02 22:16:17 +0000350 uint32_t flags = 0;
351
edgar_igl62318682009-01-07 23:38:41 +0000352 src = src & 0x80000000;
353 dst = dst & 0x80000000;
edgar_iglb41f7df2008-05-02 22:16:17 +0000354
355 if ((res & 0x80000000L) != 0L)
356 {
357 flags |= N_FLAG;
edgar_igla8cf66b2009-01-07 12:25:15 +0000358 if (!src && !dst)
edgar_iglb41f7df2008-05-02 22:16:17 +0000359 flags |= V_FLAG;
edgar_igla8cf66b2009-01-07 12:25:15 +0000360 else if (src & dst)
edgar_iglb41f7df2008-05-02 22:16:17 +0000361 flags |= R_FLAG;
edgar_iglb41f7df2008-05-02 22:16:17 +0000362 }
363 else
364 {
365 if (res == 0L)
366 flags |= Z_FLAG;
edgar_igla8cf66b2009-01-07 12:25:15 +0000367 if (src & dst)
edgar_iglb41f7df2008-05-02 22:16:17 +0000368 flags |= V_FLAG;
edgar_igla8cf66b2009-01-07 12:25:15 +0000369 if (dst | src)
edgar_iglb41f7df2008-05-02 22:16:17 +0000370 flags |= R_FLAG;
371 }
372
edgar_igl62318682009-01-07 23:38:41 +0000373 return evaluate_flags_writeback(flags, ccs);
edgar_iglb41f7df2008-05-02 22:16:17 +0000374}
375
edgar_igl62318682009-01-07 23:38:41 +0000376uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
377 uint32_t src, uint32_t dst, uint32_t res)
edgar_iglb41f7df2008-05-02 22:16:17 +0000378{
edgar_iglb41f7df2008-05-02 22:16:17 +0000379 uint32_t flags = 0;
380
edgar_igl62318682009-01-07 23:38:41 +0000381 src = src & 0x80000000;
382 dst = dst & 0x80000000;
edgar_iglb41f7df2008-05-02 22:16:17 +0000383
384 if ((res & 0x80000000L) != 0L)
385 {
386 flags |= N_FLAG;
edgar_igla8cf66b2009-01-07 12:25:15 +0000387 if (!src && !dst)
edgar_iglb41f7df2008-05-02 22:16:17 +0000388 flags |= V_FLAG;
edgar_igla8cf66b2009-01-07 12:25:15 +0000389 else if (src & dst)
edgar_iglb41f7df2008-05-02 22:16:17 +0000390 flags |= C_FLAG;
edgar_iglb41f7df2008-05-02 22:16:17 +0000391 }
392 else
393 {
394 if (res == 0L)
395 flags |= Z_FLAG;
edgar_igla8cf66b2009-01-07 12:25:15 +0000396 if (src & dst)
edgar_iglb41f7df2008-05-02 22:16:17 +0000397 flags |= V_FLAG;
edgar_igla8cf66b2009-01-07 12:25:15 +0000398 if (dst | src)
edgar_iglb41f7df2008-05-02 22:16:17 +0000399 flags |= C_FLAG;
400 }
401
edgar_igl62318682009-01-07 23:38:41 +0000402 return evaluate_flags_writeback(flags, ccs);
edgar_igla8cf66b2009-01-07 12:25:15 +0000403}
404
edgar_igl62318682009-01-07 23:38:41 +0000405uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
406 uint32_t src, uint32_t dst, uint32_t res)
edgar_igla8cf66b2009-01-07 12:25:15 +0000407{
edgar_igla8cf66b2009-01-07 12:25:15 +0000408 uint32_t flags = 0;
409
edgar_igl62318682009-01-07 23:38:41 +0000410 src = (~src) & 0x80000000;
411 dst = dst & 0x80000000;
edgar_igla8cf66b2009-01-07 12:25:15 +0000412
413 if ((res & 0x80000000L) != 0L)
414 {
415 flags |= N_FLAG;
416 if (!src && !dst)
417 flags |= V_FLAG;
418 else if (src & dst)
419 flags |= C_FLAG;
edgar_iglb41f7df2008-05-02 22:16:17 +0000420 }
edgar_igla8cf66b2009-01-07 12:25:15 +0000421 else
422 {
423 if (res == 0L)
424 flags |= Z_FLAG;
425 if (src & dst)
426 flags |= V_FLAG;
427 if (dst | src)
428 flags |= C_FLAG;
429 }
430
431 flags ^= C_FLAG;
edgar_igl62318682009-01-07 23:38:41 +0000432 return evaluate_flags_writeback(flags, ccs);
edgar_iglb41f7df2008-05-02 22:16:17 +0000433}
434
edgar_igl62318682009-01-07 23:38:41 +0000435uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
edgar_iglb41f7df2008-05-02 22:16:17 +0000436{
edgar_iglb41f7df2008-05-02 22:16:17 +0000437 uint32_t flags = 0;
438
edgar_iglb41f7df2008-05-02 22:16:17 +0000439 if ((int32_t)res < 0)
440 flags |= N_FLAG;
441 else if (res == 0L)
442 flags |= Z_FLAG;
443
edgar_igl62318682009-01-07 23:38:41 +0000444 return evaluate_flags_writeback(flags, ccs);
edgar_iglb41f7df2008-05-02 22:16:17 +0000445}
edgar_igl62318682009-01-07 23:38:41 +0000446uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
edgar_iglb41f7df2008-05-02 22:16:17 +0000447{
edgar_iglb41f7df2008-05-02 22:16:17 +0000448 uint32_t flags = 0;
edgar_iglb41f7df2008-05-02 22:16:17 +0000449
450 if ((int16_t)res < 0L)
451 flags |= N_FLAG;
452 else if (res == 0)
453 flags |= Z_FLAG;
454
edgar_igl62318682009-01-07 23:38:41 +0000455 return evaluate_flags_writeback(flags, ccs);
edgar_iglb41f7df2008-05-02 22:16:17 +0000456}
457
458/* TODO: This is expensive. We could split things up and only evaluate part of
459 CCR on a need to know basis. For now, we simply re-evaluate everything. */
edgar_igl62318682009-01-07 23:38:41 +0000460void helper_evaluate_flags(void)
edgar_iglb41f7df2008-05-02 22:16:17 +0000461{
edgar_igl62318682009-01-07 23:38:41 +0000462 uint32_t src, dst, res;
edgar_iglb41f7df2008-05-02 22:16:17 +0000463 uint32_t flags = 0;
464
465 src = env->cc_src;
466 dst = env->cc_dest;
467 res = env->cc_result;
468
edgar_igl30abcfc2008-05-27 21:10:56 +0000469 if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
470 src = ~src;
edgar_iglb41f7df2008-05-02 22:16:17 +0000471
472 /* Now, evaluate the flags. This stuff is based on
473 Per Zander's CRISv10 simulator. */
474 switch (env->cc_size)
475 {
476 case 1:
477 if ((res & 0x80L) != 0L)
478 {
479 flags |= N_FLAG;
480 if (((src & 0x80L) == 0L)
481 && ((dst & 0x80L) == 0L))
482 {
483 flags |= V_FLAG;
484 }
485 else if (((src & 0x80L) != 0L)
486 && ((dst & 0x80L) != 0L))
487 {
488 flags |= C_FLAG;
489 }
490 }
491 else
492 {
493 if ((res & 0xFFL) == 0L)
494 {
495 flags |= Z_FLAG;
496 }
497 if (((src & 0x80L) != 0L)
498 && ((dst & 0x80L) != 0L))
499 {
500 flags |= V_FLAG;
501 }
502 if ((dst & 0x80L) != 0L
503 || (src & 0x80L) != 0L)
504 {
505 flags |= C_FLAG;
506 }
507 }
508 break;
509 case 2:
510 if ((res & 0x8000L) != 0L)
511 {
512 flags |= N_FLAG;
513 if (((src & 0x8000L) == 0L)
514 && ((dst & 0x8000L) == 0L))
515 {
516 flags |= V_FLAG;
517 }
518 else if (((src & 0x8000L) != 0L)
519 && ((dst & 0x8000L) != 0L))
520 {
521 flags |= C_FLAG;
522 }
523 }
524 else
525 {
526 if ((res & 0xFFFFL) == 0L)
527 {
528 flags |= Z_FLAG;
529 }
530 if (((src & 0x8000L) != 0L)
531 && ((dst & 0x8000L) != 0L))
532 {
533 flags |= V_FLAG;
534 }
535 if ((dst & 0x8000L) != 0L
536 || (src & 0x8000L) != 0L)
537 {
538 flags |= C_FLAG;
539 }
540 }
541 break;
542 case 4:
543 if ((res & 0x80000000L) != 0L)
544 {
545 flags |= N_FLAG;
546 if (((src & 0x80000000L) == 0L)
547 && ((dst & 0x80000000L) == 0L))
548 {
549 flags |= V_FLAG;
550 }
551 else if (((src & 0x80000000L) != 0L) &&
552 ((dst & 0x80000000L) != 0L))
553 {
554 flags |= C_FLAG;
555 }
556 }
557 else
558 {
559 if (res == 0L)
560 flags |= Z_FLAG;
561 if (((src & 0x80000000L) != 0L)
562 && ((dst & 0x80000000L) != 0L))
563 flags |= V_FLAG;
564 if ((dst & 0x80000000L) != 0L
565 || (src & 0x80000000L) != 0L)
566 flags |= C_FLAG;
567 }
568 break;
569 default:
570 break;
571 }
572
edgar_igl62318682009-01-07 23:38:41 +0000573 if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
edgar_iglb41f7df2008-05-02 22:16:17 +0000574 flags ^= C_FLAG;
edgar_igl62318682009-01-07 23:38:41 +0000575
576 env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
edgar_iglb41f7df2008-05-02 22:16:17 +0000577}
edgar_igl30abcfc2008-05-27 21:10:56 +0000578
579void helper_top_evaluate_flags(void)
580{
581 switch (env->cc_op)
582 {
583 case CC_OP_MCP:
edgar_igl62318682009-01-07 23:38:41 +0000584 env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
585 env->pregs[PR_CCS], env->cc_src,
586 env->cc_dest, env->cc_result);
edgar_igl30abcfc2008-05-27 21:10:56 +0000587 break;
588 case CC_OP_MULS:
edgar_igl62318682009-01-07 23:38:41 +0000589 env->pregs[PR_CCS] = helper_evaluate_flags_muls(
590 env->pregs[PR_CCS], env->cc_result,
591 env->pregs[PR_MOF]);
edgar_igl30abcfc2008-05-27 21:10:56 +0000592 break;
593 case CC_OP_MULU:
edgar_igl62318682009-01-07 23:38:41 +0000594 env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
595 env->pregs[PR_CCS], env->cc_result,
596 env->pregs[PR_MOF]);
edgar_igl30abcfc2008-05-27 21:10:56 +0000597 break;
598 case CC_OP_MOVE:
599 case CC_OP_AND:
600 case CC_OP_OR:
601 case CC_OP_XOR:
602 case CC_OP_ASR:
603 case CC_OP_LSR:
604 case CC_OP_LSL:
edgar_igl62318682009-01-07 23:38:41 +0000605 switch (env->cc_size)
606 {
607 case 4:
608 env->pregs[PR_CCS] =
609 helper_evaluate_flags_move_4(
610 env->pregs[PR_CCS],
611 env->cc_result);
612 break;
613 case 2:
614 env->pregs[PR_CCS] =
615 helper_evaluate_flags_move_2(
616 env->pregs[PR_CCS],
617 env->cc_result);
618 break;
619 default:
620 helper_evaluate_flags();
621 break;
622 }
623 break;
edgar_igl30abcfc2008-05-27 21:10:56 +0000624 case CC_OP_FLAGS:
625 /* live. */
626 break;
edgar_igla8cf66b2009-01-07 12:25:15 +0000627 case CC_OP_SUB:
628 case CC_OP_CMP:
629 if (env->cc_size == 4)
edgar_igl62318682009-01-07 23:38:41 +0000630 env->pregs[PR_CCS] =
631 helper_evaluate_flags_sub_4(
632 env->pregs[PR_CCS],
633 env->cc_src, env->cc_dest,
634 env->cc_result);
edgar_igla8cf66b2009-01-07 12:25:15 +0000635 else
636 helper_evaluate_flags();
637 break;
edgar_igl30abcfc2008-05-27 21:10:56 +0000638 default:
639 {
640 switch (env->cc_size)
641 {
edgar_igl62318682009-01-07 23:38:41 +0000642 case 4:
643 env->pregs[PR_CCS] =
644 helper_evaluate_flags_alu_4(
645 env->pregs[PR_CCS],
646 env->cc_src, env->cc_dest,
647 env->cc_result);
648 break;
649 default:
650 helper_evaluate_flags();
651 break;
edgar_igl30abcfc2008-05-27 21:10:56 +0000652 }
653 }
654 break;
655 }
656}