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Isaku Yamahata8135aee2010-10-20 17:18:53 +09001/*
2 * ioh3420.c
3 * Intel X58 north bridge IOH
4 * PCI Express root port device id 3420
5 *
6 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010023#include "hw/pci/pci_ids.h"
24#include "hw/pci/msi.h"
25#include "hw/pci/pcie.h"
Paolo Bonzini47b43a12013-03-18 17:36:02 +010026#include "ioh3420.h"
Isaku Yamahata8135aee2010-10-20 17:18:53 +090027
28#define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */
29#define PCI_DEVICE_ID_IOH_REV 0x2
30#define IOH_EP_SSVID_OFFSET 0x40
31#define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL
32#define IOH_EP_SSVID_SSID 0
33#define IOH_EP_MSI_OFFSET 0x60
34#define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT
35#define IOH_EP_MSI_NR_VECTOR 2
36#define IOH_EP_EXP_OFFSET 0x90
37#define IOH_EP_AER_OFFSET 0x100
38
Isaku Yamahata61620c22010-11-16 17:26:10 +090039/*
40 * If two MSI vector are allocated, Advanced Error Interrupt Message Number
41 * is 1. otherwise 0.
42 * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number.
43 */
44static uint8_t ioh3420_aer_vector(const PCIDevice *d)
45{
46 switch (msi_nr_vectors_allocated(d)) {
47 case 1:
48 return 0;
49 case 2:
50 return 1;
51 case 4:
52 case 8:
53 case 16:
54 case 32:
55 default:
56 break;
57 }
58 abort();
59 return 0;
60}
61
62static void ioh3420_aer_vector_update(PCIDevice *d)
63{
64 pcie_aer_root_set_vector(d, ioh3420_aer_vector(d));
65}
66
Isaku Yamahata8135aee2010-10-20 17:18:53 +090067static void ioh3420_write_config(PCIDevice *d,
68 uint32_t address, uint32_t val, int len)
69{
Isaku Yamahata61620c22010-11-16 17:26:10 +090070 uint32_t root_cmd =
71 pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
72
Isaku Yamahata8135aee2010-10-20 17:18:53 +090073 pci_bridge_write_config(d, address, val, len);
Isaku Yamahata61620c22010-11-16 17:26:10 +090074 ioh3420_aer_vector_update(d);
Michael S. Tsirkin6bde6aa2010-10-25 07:46:47 +020075 pcie_cap_slot_write_config(d, address, val, len);
Isaku Yamahata61620c22010-11-16 17:26:10 +090076 pcie_aer_write_config(d, address, val, len);
77 pcie_aer_root_write_config(d, address, val, len, root_cmd);
Isaku Yamahata8135aee2010-10-20 17:18:53 +090078}
79
80static void ioh3420_reset(DeviceState *qdev)
81{
Anthony Liguori40021f02011-12-04 12:22:06 -060082 PCIDevice *d = PCI_DEVICE(qdev);
Jan Kiszkacbd2d432012-05-15 20:09:56 -030083
Isaku Yamahata61620c22010-11-16 17:26:10 +090084 ioh3420_aer_vector_update(d);
Isaku Yamahata8135aee2010-10-20 17:18:53 +090085 pcie_cap_root_reset(d);
86 pcie_cap_deverr_reset(d);
87 pcie_cap_slot_reset(d);
Knut Omanga74b8702014-08-24 15:32:20 +020088 pcie_cap_arifwd_reset(d);
Isaku Yamahata61620c22010-11-16 17:26:10 +090089 pcie_aer_root_reset(d);
Isaku Yamahata8135aee2010-10-20 17:18:53 +090090 pci_bridge_reset(qdev);
91 pci_bridge_disable_base_limit(d);
Isaku Yamahata8135aee2010-10-20 17:18:53 +090092}
93
94static int ioh3420_initfn(PCIDevice *d)
95{
Andreas Färberbcb75752013-07-12 19:56:00 +020096 PCIEPort *p = PCIE_PORT(d);
97 PCIESlot *s = PCIE_SLOT(d);
Isaku Yamahata8135aee2010-10-20 17:18:53 +090098 int rc;
99
Alex Williamsonafb661e2013-03-14 16:01:17 -0600100 rc = pci_bridge_initfn(d, TYPE_PCIE_BUS);
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900101 if (rc < 0) {
102 return rc;
103 }
104
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900105 pcie_port_init_reg(d);
106
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900107 rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
108 IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
109 if (rc < 0) {
Isaku Yamahata61620c22010-11-16 17:26:10 +0900110 goto err_bridge;
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900111 }
112 rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
113 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
114 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
115 if (rc < 0) {
Isaku Yamahata61620c22010-11-16 17:26:10 +0900116 goto err_bridge;
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900117 }
118 rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port);
119 if (rc < 0) {
Isaku Yamahata61620c22010-11-16 17:26:10 +0900120 goto err_msi;
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900121 }
Knut Omang821be9d2014-08-24 15:32:18 +0200122
Knut Omanga74b8702014-08-24 15:32:20 +0200123 pcie_cap_arifwd_init(d);
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900124 pcie_cap_deverr_init(d);
125 pcie_cap_slot_init(d, s->slot);
126 pcie_chassis_create(s->chassis);
127 rc = pcie_chassis_add_slot(s);
128 if (rc < 0) {
Isaku Yamahata61620c22010-11-16 17:26:10 +0900129 goto err_pcie_cap;
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900130 }
131 pcie_cap_root_init(d);
Isaku Yamahata61620c22010-11-16 17:26:10 +0900132 rc = pcie_aer_init(d, IOH_EP_AER_OFFSET);
133 if (rc < 0) {
134 goto err;
135 }
136 pcie_aer_root_init(d);
137 ioh3420_aer_vector_update(d);
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900138 return 0;
Isaku Yamahata61620c22010-11-16 17:26:10 +0900139
140err:
141 pcie_chassis_del_slot(s);
142err_pcie_cap:
143 pcie_cap_exit(d);
144err_msi:
145 msi_uninit(d);
146err_bridge:
Alex Williamsonf90c2bc2012-07-03 22:39:27 -0600147 pci_bridge_exitfn(d);
Isaku Yamahata61620c22010-11-16 17:26:10 +0900148 return rc;
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900149}
150
Alex Williamsonf90c2bc2012-07-03 22:39:27 -0600151static void ioh3420_exitfn(PCIDevice *d)
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900152{
Andreas Färberbcb75752013-07-12 19:56:00 +0200153 PCIESlot *s = PCIE_SLOT(d);
Isaku Yamahata61620c22010-11-16 17:26:10 +0900154
155 pcie_aer_exit(d);
156 pcie_chassis_del_slot(s);
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900157 pcie_cap_exit(d);
Isaku Yamahata61620c22010-11-16 17:26:10 +0900158 msi_uninit(d);
Alex Williamsonf90c2bc2012-07-03 22:39:27 -0600159 pci_bridge_exitfn(d);
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900160}
161
Marcel Apfelbaumf23b6bd2014-06-23 17:32:48 +0300162static Property ioh3420_props[] = {
163 DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
164 QEMU_PCIE_SLTCAP_PCP_BITNR, true),
165 DEFINE_PROP_END_OF_LIST()
166};
167
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900168static const VMStateDescription vmstate_ioh3420 = {
169 .name = "ioh-3240-express-root-port",
170 .version_id = 1,
171 .minimum_version_id = 1,
Michael S. Tsirkin6bde6aa2010-10-25 07:46:47 +0200172 .post_load = pcie_cap_slot_post_load,
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900173 .fields = (VMStateField[]) {
Andreas Färberbcb75752013-07-12 19:56:00 +0200174 VMSTATE_PCIE_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
175 VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
176 PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900177 VMSTATE_END_OF_LIST()
178 }
179};
180
Anthony Liguori40021f02011-12-04 12:22:06 -0600181static void ioh3420_class_init(ObjectClass *klass, void *data)
182{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600183 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -0600184 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900185
Anthony Liguori40021f02011-12-04 12:22:06 -0600186 k->is_express = 1;
187 k->is_bridge = 1;
188 k->config_write = ioh3420_write_config;
189 k->init = ioh3420_initfn;
190 k->exit = ioh3420_exitfn;
191 k->vendor_id = PCI_VENDOR_ID_INTEL;
192 k->device_id = PCI_DEVICE_ID_IOH_EPORT;
193 k->revision = PCI_DEVICE_ID_IOH_REV;
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +0300194 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
Anthony Liguori39bffca2011-12-07 21:34:16 -0600195 dc->desc = "Intel IOH device id 3420 PCIE Root Port";
196 dc->reset = ioh3420_reset;
197 dc->vmsd = &vmstate_ioh3420;
Marcel Apfelbaumf23b6bd2014-06-23 17:32:48 +0300198 dc->props = ioh3420_props;
Anthony Liguori40021f02011-12-04 12:22:06 -0600199}
200
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100201static const TypeInfo ioh3420_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600202 .name = "ioh3420",
Andreas Färberbcb75752013-07-12 19:56:00 +0200203 .parent = TYPE_PCIE_SLOT,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600204 .class_init = ioh3420_class_init,
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900205};
206
Andreas Färber83f7d432012-02-09 15:20:55 +0100207static void ioh3420_register_types(void)
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900208{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600209 type_register_static(&ioh3420_info);
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900210}
211
Andreas Färber83f7d432012-02-09 15:20:55 +0100212type_init(ioh3420_register_types)
Isaku Yamahata8135aee2010-10-20 17:18:53 +0900213
214/*
215 * Local variables:
216 * c-indent-level: 4
217 * c-basic-offset: 4
218 * tab-width: 8
219 * indent-tab-mode: nil
220 * End:
221 */