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pbrook7e1543c2007-06-30 17:32:17 +00001/*
2 * ARM AMBA PrimeCell PL031 RTC
3 *
4 * Copyright (c) 2007 CodeSourcery
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
Paolo Bonzini6b620ca2012-01-13 17:44:23 +010010 * Contributions after 2012-01-13 are licensed under the terms of the
11 * GNU GPL, version 2 or (at your option) any later version.
pbrook7e1543c2007-06-30 17:32:17 +000012 */
13
Peter Maydell8ef94f02016-01-26 18:17:05 +000014#include "qemu/osdep.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010015#include "hw/sysbus.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010016#include "qemu/timer.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010017#include "sysemu/sysemu.h"
Veronia Bahaaf348b6d2016-03-20 19:16:19 +020018#include "qemu/cutils.h"
Paolo Bonzini03dd0242015-12-15 13:16:16 +010019#include "qemu/log.h"
pbrook7e1543c2007-06-30 17:32:17 +000020
21//#define DEBUG_PL031
22
23#ifdef DEBUG_PL031
Blue Swirl001faf32009-05-13 17:53:17 +000024#define DPRINTF(fmt, ...) \
25do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
pbrook7e1543c2007-06-30 17:32:17 +000026#else
Blue Swirl001faf32009-05-13 17:53:17 +000027#define DPRINTF(fmt, ...) do {} while(0)
pbrook7e1543c2007-06-30 17:32:17 +000028#endif
29
30#define RTC_DR 0x00 /* Data read register */
31#define RTC_MR 0x04 /* Match register */
32#define RTC_LR 0x08 /* Data load register */
33#define RTC_CR 0x0c /* Control register */
34#define RTC_IMSC 0x10 /* Interrupt mask and set register */
35#define RTC_RIS 0x14 /* Raw interrupt status register */
36#define RTC_MIS 0x18 /* Masked interrupt status register */
37#define RTC_ICR 0x1c /* Interrupt clear register */
38
Andreas Färberd3b80042013-07-27 15:10:14 +020039#define TYPE_PL031 "pl031"
40#define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031)
41
Andreas Färberb91f0df2013-07-27 15:07:44 +020042typedef struct PL031State {
Andreas Färberd3b80042013-07-27 15:10:14 +020043 SysBusDevice parent_obj;
44
Avi Kivity9edbe482011-10-10 17:18:44 +020045 MemoryRegion iomem;
pbrook7e1543c2007-06-30 17:32:17 +000046 QEMUTimer *timer;
47 qemu_irq irq;
pbrook7e1543c2007-06-30 17:32:17 +000048
Paolo Bonzinib0f26632012-03-30 10:31:23 +000049 /* Needed to preserve the tick_count across migration, even if the
50 * absolute value of the rtc_clock is different on the source and
51 * destination.
52 */
53 uint32_t tick_offset_vmstate;
pbrook7e1543c2007-06-30 17:32:17 +000054 uint32_t tick_offset;
55
56 uint32_t mr;
57 uint32_t lr;
58 uint32_t cr;
59 uint32_t im;
60 uint32_t is;
Andreas Färberb91f0df2013-07-27 15:07:44 +020061} PL031State;
pbrook7e1543c2007-06-30 17:32:17 +000062
63static const unsigned char pl031_id[] = {
64 0x31, 0x10, 0x14, 0x00, /* Device ID */
65 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
66};
67
Andreas Färberb91f0df2013-07-27 15:07:44 +020068static void pl031_update(PL031State *s)
pbrook7e1543c2007-06-30 17:32:17 +000069{
70 qemu_set_irq(s->irq, s->is & s->im);
71}
72
73static void pl031_interrupt(void * opaque)
74{
Andreas Färberb91f0df2013-07-27 15:07:44 +020075 PL031State *s = (PL031State *)opaque;
pbrook7e1543c2007-06-30 17:32:17 +000076
Peter Maydell13a16f12012-02-16 09:56:10 +000077 s->is = 1;
pbrook7e1543c2007-06-30 17:32:17 +000078 DPRINTF("Alarm raised\n");
79 pl031_update(s);
80}
81
Andreas Färberb91f0df2013-07-27 15:07:44 +020082static uint32_t pl031_get_count(PL031State *s)
pbrook7e1543c2007-06-30 17:32:17 +000083{
Alex Bligh884f17c2013-08-21 16:03:04 +010084 int64_t now = qemu_clock_get_ns(rtc_clock);
Rutuja Shah73bcb242016-03-21 21:32:30 +053085 return s->tick_offset + now / NANOSECONDS_PER_SECOND;
pbrook7e1543c2007-06-30 17:32:17 +000086}
87
Andreas Färberb91f0df2013-07-27 15:07:44 +020088static void pl031_set_alarm(PL031State *s)
pbrook7e1543c2007-06-30 17:32:17 +000089{
pbrook7e1543c2007-06-30 17:32:17 +000090 uint32_t ticks;
91
pbrook7e1543c2007-06-30 17:32:17 +000092 /* The timer wraps around. This subtraction also wraps in the same way,
93 and gives correct results when alarm < now_ticks. */
Paolo Bonzinib0f26632012-03-30 10:31:23 +000094 ticks = s->mr - pl031_get_count(s);
pbrook7e1543c2007-06-30 17:32:17 +000095 DPRINTF("Alarm set in %ud ticks\n", ticks);
96 if (ticks == 0) {
Alex Blighbc72ad62013-08-21 16:03:08 +010097 timer_del(s->timer);
pbrook7e1543c2007-06-30 17:32:17 +000098 pl031_interrupt(s);
99 } else {
Alex Bligh884f17c2013-08-21 16:03:04 +0100100 int64_t now = qemu_clock_get_ns(rtc_clock);
Rutuja Shah73bcb242016-03-21 21:32:30 +0530101 timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND);
pbrook7e1543c2007-06-30 17:32:17 +0000102 }
103}
104
Avi Kivitya8170e52012-10-23 12:30:10 +0200105static uint64_t pl031_read(void *opaque, hwaddr offset,
Avi Kivity9edbe482011-10-10 17:18:44 +0200106 unsigned size)
pbrook7e1543c2007-06-30 17:32:17 +0000107{
Andreas Färberb91f0df2013-07-27 15:07:44 +0200108 PL031State *s = (PL031State *)opaque;
pbrook7e1543c2007-06-30 17:32:17 +0000109
pbrook7e1543c2007-06-30 17:32:17 +0000110 if (offset >= 0xfe0 && offset < 0x1000)
111 return pl031_id[(offset - 0xfe0) >> 2];
112
113 switch (offset) {
114 case RTC_DR:
115 return pl031_get_count(s);
116 case RTC_MR:
117 return s->mr;
118 case RTC_IMSC:
119 return s->im;
120 case RTC_RIS:
121 return s->is;
122 case RTC_LR:
123 return s->lr;
124 case RTC_CR:
125 /* RTC is permanently enabled. */
126 return 1;
127 case RTC_MIS:
128 return s->is & s->im;
129 case RTC_ICR:
Peter Maydella5089c02012-10-18 14:11:42 +0100130 qemu_log_mask(LOG_GUEST_ERROR,
131 "pl031: read of write-only register at offset 0x%x\n",
132 (int)offset);
pbrook7e1543c2007-06-30 17:32:17 +0000133 break;
134 default:
Peter Maydella5089c02012-10-18 14:11:42 +0100135 qemu_log_mask(LOG_GUEST_ERROR,
136 "pl031_read: Bad offset 0x%x\n", (int)offset);
pbrook7e1543c2007-06-30 17:32:17 +0000137 break;
138 }
139
140 return 0;
141}
142
Avi Kivitya8170e52012-10-23 12:30:10 +0200143static void pl031_write(void * opaque, hwaddr offset,
Avi Kivity9edbe482011-10-10 17:18:44 +0200144 uint64_t value, unsigned size)
pbrook7e1543c2007-06-30 17:32:17 +0000145{
Andreas Färberb91f0df2013-07-27 15:07:44 +0200146 PL031State *s = (PL031State *)opaque;
pbrook7e1543c2007-06-30 17:32:17 +0000147
pbrook7e1543c2007-06-30 17:32:17 +0000148
149 switch (offset) {
150 case RTC_LR:
151 s->tick_offset += value - pl031_get_count(s);
152 pl031_set_alarm(s);
153 break;
154 case RTC_MR:
155 s->mr = value;
156 pl031_set_alarm(s);
157 break;
158 case RTC_IMSC:
159 s->im = value & 1;
160 DPRINTF("Interrupt mask %d\n", s->im);
161 pl031_update(s);
162 break;
163 case RTC_ICR:
Stefan Weilff2712b2011-04-28 17:20:35 +0200164 /* The PL031 documentation (DDI0224B) states that the interrupt is
pbrook7e1543c2007-06-30 17:32:17 +0000165 cleared when bit 0 of the written value is set. However the
166 arm926e documentation (DDI0287B) states that the interrupt is
167 cleared when any value is written. */
168 DPRINTF("Interrupt cleared");
169 s->is = 0;
170 pl031_update(s);
171 break;
172 case RTC_CR:
173 /* Written value is ignored. */
174 break;
175
176 case RTC_DR:
177 case RTC_MIS:
178 case RTC_RIS:
Peter Maydella5089c02012-10-18 14:11:42 +0100179 qemu_log_mask(LOG_GUEST_ERROR,
180 "pl031: write to read-only register at offset 0x%x\n",
181 (int)offset);
pbrook7e1543c2007-06-30 17:32:17 +0000182 break;
183
184 default:
Peter Maydella5089c02012-10-18 14:11:42 +0100185 qemu_log_mask(LOG_GUEST_ERROR,
186 "pl031_write: Bad offset 0x%x\n", (int)offset);
pbrook7e1543c2007-06-30 17:32:17 +0000187 break;
188 }
189}
190
Avi Kivity9edbe482011-10-10 17:18:44 +0200191static const MemoryRegionOps pl031_ops = {
192 .read = pl031_read,
193 .write = pl031_write,
194 .endianness = DEVICE_NATIVE_ENDIAN,
pbrook7e1543c2007-06-30 17:32:17 +0000195};
196
xiaoqiang.zhao81dcc492016-02-18 14:16:21 +0000197static void pl031_init(Object *obj)
pbrook7e1543c2007-06-30 17:32:17 +0000198{
xiaoqiang.zhao81dcc492016-02-18 14:16:21 +0000199 PL031State *s = PL031(obj);
200 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
balrogf6503052008-02-17 11:42:19 +0000201 struct tm tm;
pbrook7e1543c2007-06-30 17:32:17 +0000202
xiaoqiang.zhao81dcc492016-02-18 14:16:21 +0000203 memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
Avi Kivity750ecd42011-11-27 11:38:10 +0200204 sysbus_init_mmio(dev, &s->iomem);
pbrook7e1543c2007-06-30 17:32:17 +0000205
Paul Brooka63bdb32009-05-14 22:35:07 +0100206 sysbus_init_irq(dev, &s->irq);
balrogf6503052008-02-17 11:42:19 +0000207 qemu_get_timedate(&tm, 0);
Alex Bligh884f17c2013-08-21 16:03:04 +0100208 s->tick_offset = mktimegm(&tm) -
Rutuja Shah73bcb242016-03-21 21:32:30 +0530209 qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
pbrook7e1543c2007-06-30 17:32:17 +0000210
Alex Bligh884f17c2013-08-21 16:03:04 +0100211 s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
pbrook7e1543c2007-06-30 17:32:17 +0000212}
Paul Brooka63bdb32009-05-14 22:35:07 +0100213
Dr. David Alan Gilbert44b1ff32017-09-25 12:29:12 +0100214static int pl031_pre_save(void *opaque)
Paolo Bonzinib0f26632012-03-30 10:31:23 +0000215{
Andreas Färberb91f0df2013-07-27 15:07:44 +0200216 PL031State *s = opaque;
Paolo Bonzinib0f26632012-03-30 10:31:23 +0000217
218 /* tick_offset is base_time - rtc_clock base time. Instead, we want to
Alex Blighbc72ad62013-08-21 16:03:08 +0100219 * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility. */
220 int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
Rutuja Shah73bcb242016-03-21 21:32:30 +0530221 s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
Dr. David Alan Gilbert44b1ff32017-09-25 12:29:12 +0100222
223 return 0;
Paolo Bonzinib0f26632012-03-30 10:31:23 +0000224}
225
Paolo Bonziniac204b82012-03-30 10:31:22 +0000226static int pl031_post_load(void *opaque, int version_id)
227{
Andreas Färberb91f0df2013-07-27 15:07:44 +0200228 PL031State *s = opaque;
Paolo Bonziniac204b82012-03-30 10:31:22 +0000229
Alex Blighbc72ad62013-08-21 16:03:08 +0100230 int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
Rutuja Shah73bcb242016-03-21 21:32:30 +0530231 s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND;
Paolo Bonziniac204b82012-03-30 10:31:22 +0000232 pl031_set_alarm(s);
233 return 0;
234}
235
236static const VMStateDescription vmstate_pl031 = {
237 .name = "pl031",
238 .version_id = 1,
239 .minimum_version_id = 1,
Paolo Bonzinib0f26632012-03-30 10:31:23 +0000240 .pre_save = pl031_pre_save,
Paolo Bonziniac204b82012-03-30 10:31:22 +0000241 .post_load = pl031_post_load,
242 .fields = (VMStateField[]) {
Andreas Färberb91f0df2013-07-27 15:07:44 +0200243 VMSTATE_UINT32(tick_offset_vmstate, PL031State),
244 VMSTATE_UINT32(mr, PL031State),
245 VMSTATE_UINT32(lr, PL031State),
246 VMSTATE_UINT32(cr, PL031State),
247 VMSTATE_UINT32(im, PL031State),
248 VMSTATE_UINT32(is, PL031State),
Paolo Bonziniac204b82012-03-30 10:31:22 +0000249 VMSTATE_END_OF_LIST()
250 }
251};
252
Anthony Liguori999e12b2012-01-24 13:12:29 -0600253static void pl031_class_init(ObjectClass *klass, void *data)
254{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600255 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600256
Anthony Liguori39bffca2011-12-07 21:34:16 -0600257 dc->vmsd = &vmstate_pl031;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600258}
259
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100260static const TypeInfo pl031_info = {
Andreas Färberd3b80042013-07-27 15:10:14 +0200261 .name = TYPE_PL031,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600262 .parent = TYPE_SYS_BUS_DEVICE,
Andreas Färberb91f0df2013-07-27 15:07:44 +0200263 .instance_size = sizeof(PL031State),
xiaoqiang.zhao81dcc492016-02-18 14:16:21 +0000264 .instance_init = pl031_init,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600265 .class_init = pl031_class_init,
Peter Maydell0dc55952010-12-23 17:19:55 +0000266};
267
Andreas Färber83f7d432012-02-09 15:20:55 +0100268static void pl031_register_types(void)
Paul Brooka63bdb32009-05-14 22:35:07 +0100269{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600270 type_register_static(&pl031_info);
Paul Brooka63bdb32009-05-14 22:35:07 +0100271}
272
Andreas Färber83f7d432012-02-09 15:20:55 +0100273type_init(pl031_register_types)