pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * ARM AMBA PrimeCell PL031 RTC |
| 3 | * |
| 4 | * Copyright (c) 2007 CodeSourcery |
| 5 | * |
| 6 | * This file is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
Paolo Bonzini | 6b620ca | 2012-01-13 17:44:23 +0100 | [diff] [blame] | 10 | * Contributions after 2012-01-13 are licensed under the terms of the |
| 11 | * GNU GPL, version 2 or (at your option) any later version. |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 12 | */ |
| 13 | |
Peter Maydell | 8ef94f0 | 2016-01-26 18:17:05 +0000 | [diff] [blame] | 14 | #include "qemu/osdep.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 15 | #include "hw/sysbus.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 16 | #include "qemu/timer.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 17 | #include "sysemu/sysemu.h" |
Veronia Bahaa | f348b6d | 2016-03-20 19:16:19 +0200 | [diff] [blame] | 18 | #include "qemu/cutils.h" |
Paolo Bonzini | 03dd024 | 2015-12-15 13:16:16 +0100 | [diff] [blame] | 19 | #include "qemu/log.h" |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 20 | |
| 21 | //#define DEBUG_PL031 |
| 22 | |
| 23 | #ifdef DEBUG_PL031 |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 24 | #define DPRINTF(fmt, ...) \ |
| 25 | do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0) |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 26 | #else |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 27 | #define DPRINTF(fmt, ...) do {} while(0) |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 28 | #endif |
| 29 | |
| 30 | #define RTC_DR 0x00 /* Data read register */ |
| 31 | #define RTC_MR 0x04 /* Match register */ |
| 32 | #define RTC_LR 0x08 /* Data load register */ |
| 33 | #define RTC_CR 0x0c /* Control register */ |
| 34 | #define RTC_IMSC 0x10 /* Interrupt mask and set register */ |
| 35 | #define RTC_RIS 0x14 /* Raw interrupt status register */ |
| 36 | #define RTC_MIS 0x18 /* Masked interrupt status register */ |
| 37 | #define RTC_ICR 0x1c /* Interrupt clear register */ |
| 38 | |
Andreas Färber | d3b8004 | 2013-07-27 15:10:14 +0200 | [diff] [blame] | 39 | #define TYPE_PL031 "pl031" |
| 40 | #define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031) |
| 41 | |
Andreas Färber | b91f0df | 2013-07-27 15:07:44 +0200 | [diff] [blame] | 42 | typedef struct PL031State { |
Andreas Färber | d3b8004 | 2013-07-27 15:10:14 +0200 | [diff] [blame] | 43 | SysBusDevice parent_obj; |
| 44 | |
Avi Kivity | 9edbe48 | 2011-10-10 17:18:44 +0200 | [diff] [blame] | 45 | MemoryRegion iomem; |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 46 | QEMUTimer *timer; |
| 47 | qemu_irq irq; |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 48 | |
Paolo Bonzini | b0f2663 | 2012-03-30 10:31:23 +0000 | [diff] [blame] | 49 | /* Needed to preserve the tick_count across migration, even if the |
| 50 | * absolute value of the rtc_clock is different on the source and |
| 51 | * destination. |
| 52 | */ |
| 53 | uint32_t tick_offset_vmstate; |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 54 | uint32_t tick_offset; |
| 55 | |
| 56 | uint32_t mr; |
| 57 | uint32_t lr; |
| 58 | uint32_t cr; |
| 59 | uint32_t im; |
| 60 | uint32_t is; |
Andreas Färber | b91f0df | 2013-07-27 15:07:44 +0200 | [diff] [blame] | 61 | } PL031State; |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 62 | |
| 63 | static const unsigned char pl031_id[] = { |
| 64 | 0x31, 0x10, 0x14, 0x00, /* Device ID */ |
| 65 | 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ |
| 66 | }; |
| 67 | |
Andreas Färber | b91f0df | 2013-07-27 15:07:44 +0200 | [diff] [blame] | 68 | static void pl031_update(PL031State *s) |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 69 | { |
| 70 | qemu_set_irq(s->irq, s->is & s->im); |
| 71 | } |
| 72 | |
| 73 | static void pl031_interrupt(void * opaque) |
| 74 | { |
Andreas Färber | b91f0df | 2013-07-27 15:07:44 +0200 | [diff] [blame] | 75 | PL031State *s = (PL031State *)opaque; |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 76 | |
Peter Maydell | 13a16f1 | 2012-02-16 09:56:10 +0000 | [diff] [blame] | 77 | s->is = 1; |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 78 | DPRINTF("Alarm raised\n"); |
| 79 | pl031_update(s); |
| 80 | } |
| 81 | |
Andreas Färber | b91f0df | 2013-07-27 15:07:44 +0200 | [diff] [blame] | 82 | static uint32_t pl031_get_count(PL031State *s) |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 83 | { |
Alex Bligh | 884f17c | 2013-08-21 16:03:04 +0100 | [diff] [blame] | 84 | int64_t now = qemu_clock_get_ns(rtc_clock); |
Rutuja Shah | 73bcb24 | 2016-03-21 21:32:30 +0530 | [diff] [blame] | 85 | return s->tick_offset + now / NANOSECONDS_PER_SECOND; |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 86 | } |
| 87 | |
Andreas Färber | b91f0df | 2013-07-27 15:07:44 +0200 | [diff] [blame] | 88 | static void pl031_set_alarm(PL031State *s) |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 89 | { |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 90 | uint32_t ticks; |
| 91 | |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 92 | /* The timer wraps around. This subtraction also wraps in the same way, |
| 93 | and gives correct results when alarm < now_ticks. */ |
Paolo Bonzini | b0f2663 | 2012-03-30 10:31:23 +0000 | [diff] [blame] | 94 | ticks = s->mr - pl031_get_count(s); |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 95 | DPRINTF("Alarm set in %ud ticks\n", ticks); |
| 96 | if (ticks == 0) { |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 97 | timer_del(s->timer); |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 98 | pl031_interrupt(s); |
| 99 | } else { |
Alex Bligh | 884f17c | 2013-08-21 16:03:04 +0100 | [diff] [blame] | 100 | int64_t now = qemu_clock_get_ns(rtc_clock); |
Rutuja Shah | 73bcb24 | 2016-03-21 21:32:30 +0530 | [diff] [blame] | 101 | timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND); |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 102 | } |
| 103 | } |
| 104 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 105 | static uint64_t pl031_read(void *opaque, hwaddr offset, |
Avi Kivity | 9edbe48 | 2011-10-10 17:18:44 +0200 | [diff] [blame] | 106 | unsigned size) |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 107 | { |
Andreas Färber | b91f0df | 2013-07-27 15:07:44 +0200 | [diff] [blame] | 108 | PL031State *s = (PL031State *)opaque; |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 109 | |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 110 | if (offset >= 0xfe0 && offset < 0x1000) |
| 111 | return pl031_id[(offset - 0xfe0) >> 2]; |
| 112 | |
| 113 | switch (offset) { |
| 114 | case RTC_DR: |
| 115 | return pl031_get_count(s); |
| 116 | case RTC_MR: |
| 117 | return s->mr; |
| 118 | case RTC_IMSC: |
| 119 | return s->im; |
| 120 | case RTC_RIS: |
| 121 | return s->is; |
| 122 | case RTC_LR: |
| 123 | return s->lr; |
| 124 | case RTC_CR: |
| 125 | /* RTC is permanently enabled. */ |
| 126 | return 1; |
| 127 | case RTC_MIS: |
| 128 | return s->is & s->im; |
| 129 | case RTC_ICR: |
Peter Maydell | a5089c0 | 2012-10-18 14:11:42 +0100 | [diff] [blame] | 130 | qemu_log_mask(LOG_GUEST_ERROR, |
| 131 | "pl031: read of write-only register at offset 0x%x\n", |
| 132 | (int)offset); |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 133 | break; |
| 134 | default: |
Peter Maydell | a5089c0 | 2012-10-18 14:11:42 +0100 | [diff] [blame] | 135 | qemu_log_mask(LOG_GUEST_ERROR, |
| 136 | "pl031_read: Bad offset 0x%x\n", (int)offset); |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 137 | break; |
| 138 | } |
| 139 | |
| 140 | return 0; |
| 141 | } |
| 142 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 143 | static void pl031_write(void * opaque, hwaddr offset, |
Avi Kivity | 9edbe48 | 2011-10-10 17:18:44 +0200 | [diff] [blame] | 144 | uint64_t value, unsigned size) |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 145 | { |
Andreas Färber | b91f0df | 2013-07-27 15:07:44 +0200 | [diff] [blame] | 146 | PL031State *s = (PL031State *)opaque; |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 147 | |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 148 | |
| 149 | switch (offset) { |
| 150 | case RTC_LR: |
| 151 | s->tick_offset += value - pl031_get_count(s); |
| 152 | pl031_set_alarm(s); |
| 153 | break; |
| 154 | case RTC_MR: |
| 155 | s->mr = value; |
| 156 | pl031_set_alarm(s); |
| 157 | break; |
| 158 | case RTC_IMSC: |
| 159 | s->im = value & 1; |
| 160 | DPRINTF("Interrupt mask %d\n", s->im); |
| 161 | pl031_update(s); |
| 162 | break; |
| 163 | case RTC_ICR: |
Stefan Weil | ff2712b | 2011-04-28 17:20:35 +0200 | [diff] [blame] | 164 | /* The PL031 documentation (DDI0224B) states that the interrupt is |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 165 | cleared when bit 0 of the written value is set. However the |
| 166 | arm926e documentation (DDI0287B) states that the interrupt is |
| 167 | cleared when any value is written. */ |
| 168 | DPRINTF("Interrupt cleared"); |
| 169 | s->is = 0; |
| 170 | pl031_update(s); |
| 171 | break; |
| 172 | case RTC_CR: |
| 173 | /* Written value is ignored. */ |
| 174 | break; |
| 175 | |
| 176 | case RTC_DR: |
| 177 | case RTC_MIS: |
| 178 | case RTC_RIS: |
Peter Maydell | a5089c0 | 2012-10-18 14:11:42 +0100 | [diff] [blame] | 179 | qemu_log_mask(LOG_GUEST_ERROR, |
| 180 | "pl031: write to read-only register at offset 0x%x\n", |
| 181 | (int)offset); |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 182 | break; |
| 183 | |
| 184 | default: |
Peter Maydell | a5089c0 | 2012-10-18 14:11:42 +0100 | [diff] [blame] | 185 | qemu_log_mask(LOG_GUEST_ERROR, |
| 186 | "pl031_write: Bad offset 0x%x\n", (int)offset); |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 187 | break; |
| 188 | } |
| 189 | } |
| 190 | |
Avi Kivity | 9edbe48 | 2011-10-10 17:18:44 +0200 | [diff] [blame] | 191 | static const MemoryRegionOps pl031_ops = { |
| 192 | .read = pl031_read, |
| 193 | .write = pl031_write, |
| 194 | .endianness = DEVICE_NATIVE_ENDIAN, |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 195 | }; |
| 196 | |
xiaoqiang.zhao | 81dcc49 | 2016-02-18 14:16:21 +0000 | [diff] [blame] | 197 | static void pl031_init(Object *obj) |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 198 | { |
xiaoqiang.zhao | 81dcc49 | 2016-02-18 14:16:21 +0000 | [diff] [blame] | 199 | PL031State *s = PL031(obj); |
| 200 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 201 | struct tm tm; |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 202 | |
xiaoqiang.zhao | 81dcc49 | 2016-02-18 14:16:21 +0000 | [diff] [blame] | 203 | memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000); |
Avi Kivity | 750ecd4 | 2011-11-27 11:38:10 +0200 | [diff] [blame] | 204 | sysbus_init_mmio(dev, &s->iomem); |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 205 | |
Paul Brook | a63bdb3 | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 206 | sysbus_init_irq(dev, &s->irq); |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 207 | qemu_get_timedate(&tm, 0); |
Alex Bligh | 884f17c | 2013-08-21 16:03:04 +0100 | [diff] [blame] | 208 | s->tick_offset = mktimegm(&tm) - |
Rutuja Shah | 73bcb24 | 2016-03-21 21:32:30 +0530 | [diff] [blame] | 209 | qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 210 | |
Alex Bligh | 884f17c | 2013-08-21 16:03:04 +0100 | [diff] [blame] | 211 | s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s); |
pbrook | 7e1543c | 2007-06-30 17:32:17 +0000 | [diff] [blame] | 212 | } |
Paul Brook | a63bdb3 | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 213 | |
Dr. David Alan Gilbert | 44b1ff3 | 2017-09-25 12:29:12 +0100 | [diff] [blame] | 214 | static int pl031_pre_save(void *opaque) |
Paolo Bonzini | b0f2663 | 2012-03-30 10:31:23 +0000 | [diff] [blame] | 215 | { |
Andreas Färber | b91f0df | 2013-07-27 15:07:44 +0200 | [diff] [blame] | 216 | PL031State *s = opaque; |
Paolo Bonzini | b0f2663 | 2012-03-30 10:31:23 +0000 | [diff] [blame] | 217 | |
| 218 | /* tick_offset is base_time - rtc_clock base time. Instead, we want to |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 219 | * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility. */ |
| 220 | int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
Rutuja Shah | 73bcb24 | 2016-03-21 21:32:30 +0530 | [diff] [blame] | 221 | s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND; |
Dr. David Alan Gilbert | 44b1ff3 | 2017-09-25 12:29:12 +0100 | [diff] [blame] | 222 | |
| 223 | return 0; |
Paolo Bonzini | b0f2663 | 2012-03-30 10:31:23 +0000 | [diff] [blame] | 224 | } |
| 225 | |
Paolo Bonzini | ac204b8 | 2012-03-30 10:31:22 +0000 | [diff] [blame] | 226 | static int pl031_post_load(void *opaque, int version_id) |
| 227 | { |
Andreas Färber | b91f0df | 2013-07-27 15:07:44 +0200 | [diff] [blame] | 228 | PL031State *s = opaque; |
Paolo Bonzini | ac204b8 | 2012-03-30 10:31:22 +0000 | [diff] [blame] | 229 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 230 | int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
Rutuja Shah | 73bcb24 | 2016-03-21 21:32:30 +0530 | [diff] [blame] | 231 | s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND; |
Paolo Bonzini | ac204b8 | 2012-03-30 10:31:22 +0000 | [diff] [blame] | 232 | pl031_set_alarm(s); |
| 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | static const VMStateDescription vmstate_pl031 = { |
| 237 | .name = "pl031", |
| 238 | .version_id = 1, |
| 239 | .minimum_version_id = 1, |
Paolo Bonzini | b0f2663 | 2012-03-30 10:31:23 +0000 | [diff] [blame] | 240 | .pre_save = pl031_pre_save, |
Paolo Bonzini | ac204b8 | 2012-03-30 10:31:22 +0000 | [diff] [blame] | 241 | .post_load = pl031_post_load, |
| 242 | .fields = (VMStateField[]) { |
Andreas Färber | b91f0df | 2013-07-27 15:07:44 +0200 | [diff] [blame] | 243 | VMSTATE_UINT32(tick_offset_vmstate, PL031State), |
| 244 | VMSTATE_UINT32(mr, PL031State), |
| 245 | VMSTATE_UINT32(lr, PL031State), |
| 246 | VMSTATE_UINT32(cr, PL031State), |
| 247 | VMSTATE_UINT32(im, PL031State), |
| 248 | VMSTATE_UINT32(is, PL031State), |
Paolo Bonzini | ac204b8 | 2012-03-30 10:31:22 +0000 | [diff] [blame] | 249 | VMSTATE_END_OF_LIST() |
| 250 | } |
| 251 | }; |
| 252 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 253 | static void pl031_class_init(ObjectClass *klass, void *data) |
| 254 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 255 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 256 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 257 | dc->vmsd = &vmstate_pl031; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 258 | } |
| 259 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 260 | static const TypeInfo pl031_info = { |
Andreas Färber | d3b8004 | 2013-07-27 15:10:14 +0200 | [diff] [blame] | 261 | .name = TYPE_PL031, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 262 | .parent = TYPE_SYS_BUS_DEVICE, |
Andreas Färber | b91f0df | 2013-07-27 15:07:44 +0200 | [diff] [blame] | 263 | .instance_size = sizeof(PL031State), |
xiaoqiang.zhao | 81dcc49 | 2016-02-18 14:16:21 +0000 | [diff] [blame] | 264 | .instance_init = pl031_init, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 265 | .class_init = pl031_class_init, |
Peter Maydell | 0dc5595 | 2010-12-23 17:19:55 +0000 | [diff] [blame] | 266 | }; |
| 267 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 268 | static void pl031_register_types(void) |
Paul Brook | a63bdb3 | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 269 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 270 | type_register_static(&pl031_info); |
Paul Brook | a63bdb3 | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 271 | } |
| 272 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 273 | type_init(pl031_register_types) |