Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU sun4u IOMMU emulation |
| 3 | * |
| 4 | * Copyright (c) 2006 Fabrice Bellard |
| 5 | * Copyright (c) 2012,2013 Artyom Tarasenko |
| 6 | * Copyright (c) 2017 Mark Cave-Ayland |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 9 | * of this software and associated documentation files (the "Software"), to deal |
| 10 | * in the Software without restriction, including without limitation the rights |
| 11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 12 | * copies of the Software, and to permit persons to whom the Software is |
| 13 | * furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice shall be included in |
| 16 | * all copies or substantial portions of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 24 | * THE SOFTWARE. |
| 25 | */ |
| 26 | |
| 27 | #include "qemu/osdep.h" |
| 28 | #include "hw/sysbus.h" |
| 29 | #include "hw/sparc/sun4u_iommu.h" |
| 30 | #include "exec/address-spaces.h" |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 31 | #include "qemu/log.h" |
Mark Cave-Ayland | 09ecbb7 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 32 | #include "trace.h" |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 33 | |
| 34 | |
| 35 | #define IOMMU_PAGE_SIZE_8K (1ULL << 13) |
| 36 | #define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1)) |
| 37 | #define IOMMU_PAGE_SIZE_64K (1ULL << 16) |
| 38 | #define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1)) |
| 39 | |
| 40 | #define IOMMU_CTRL 0x0 |
| 41 | #define IOMMU_CTRL_TBW_SIZE (1ULL << 2) |
| 42 | #define IOMMU_CTRL_MMU_EN (1ULL) |
| 43 | |
| 44 | #define IOMMU_CTRL_TSB_SHIFT 16 |
| 45 | |
| 46 | #define IOMMU_BASE 0x8 |
| 47 | #define IOMMU_FLUSH 0x10 |
| 48 | |
| 49 | #define IOMMU_TTE_DATA_V (1ULL << 63) |
| 50 | #define IOMMU_TTE_DATA_SIZE (1ULL << 61) |
| 51 | #define IOMMU_TTE_DATA_W (1ULL << 1) |
| 52 | |
| 53 | #define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL |
| 54 | #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL |
| 55 | |
| 56 | #define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL |
| 57 | #define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL |
| 58 | #define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL |
| 59 | #define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL |
| 60 | #define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL |
| 61 | #define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL |
| 62 | #define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL |
| 63 | #define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL |
| 64 | |
| 65 | #define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL |
| 66 | #define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL |
| 67 | #define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL |
| 68 | #define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL |
| 69 | #define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL |
| 70 | #define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL |
| 71 | |
| 72 | |
| 73 | /* Called from RCU critical section */ |
Mark Cave-Ayland | 4c9fbc3 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 74 | static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu, |
| 75 | hwaddr addr, |
| 76 | IOMMUAccessFlags flag) |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 77 | { |
| 78 | IOMMUState *is = container_of(iommu, IOMMUState, iommu); |
| 79 | hwaddr baseaddr, offset; |
| 80 | uint64_t tte; |
| 81 | uint32_t tsbsize; |
| 82 | IOMMUTLBEntry ret = { |
| 83 | .target_as = &address_space_memory, |
| 84 | .iova = 0, |
| 85 | .translated_addr = 0, |
| 86 | .addr_mask = ~(hwaddr)0, |
| 87 | .perm = IOMMU_NONE, |
| 88 | }; |
| 89 | |
| 90 | if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) { |
| 91 | /* IOMMU disabled, passthrough using standard 8K page */ |
| 92 | ret.iova = addr & IOMMU_PAGE_MASK_8K; |
| 93 | ret.translated_addr = addr; |
| 94 | ret.addr_mask = IOMMU_PAGE_MASK_8K; |
| 95 | ret.perm = IOMMU_RW; |
| 96 | |
| 97 | return ret; |
| 98 | } |
| 99 | |
| 100 | baseaddr = is->regs[IOMMU_BASE >> 3]; |
| 101 | tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7; |
| 102 | |
| 103 | if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) { |
| 104 | /* 64K */ |
| 105 | switch (tsbsize) { |
| 106 | case 0: |
| 107 | offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13; |
| 108 | break; |
| 109 | case 1: |
| 110 | offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13; |
| 111 | break; |
| 112 | case 2: |
| 113 | offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13; |
| 114 | break; |
| 115 | case 3: |
| 116 | offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13; |
| 117 | break; |
| 118 | case 4: |
| 119 | offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13; |
| 120 | break; |
| 121 | case 5: |
| 122 | offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13; |
| 123 | break; |
| 124 | default: |
| 125 | /* Not implemented, error */ |
| 126 | return ret; |
| 127 | } |
| 128 | } else { |
| 129 | /* 8K */ |
| 130 | switch (tsbsize) { |
| 131 | case 0: |
| 132 | offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10; |
| 133 | break; |
| 134 | case 1: |
| 135 | offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10; |
| 136 | break; |
| 137 | case 2: |
| 138 | offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10; |
| 139 | break; |
| 140 | case 3: |
| 141 | offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10; |
| 142 | break; |
| 143 | case 4: |
| 144 | offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10; |
| 145 | break; |
| 146 | case 5: |
| 147 | offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10; |
| 148 | break; |
| 149 | case 6: |
| 150 | offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10; |
| 151 | break; |
| 152 | case 7: |
| 153 | offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10; |
| 154 | break; |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | tte = address_space_ldq_be(&address_space_memory, baseaddr + offset, |
| 159 | MEMTXATTRS_UNSPECIFIED, NULL); |
| 160 | |
| 161 | if (!(tte & IOMMU_TTE_DATA_V)) { |
| 162 | /* Invalid mapping */ |
| 163 | return ret; |
| 164 | } |
| 165 | |
| 166 | if (tte & IOMMU_TTE_DATA_W) { |
| 167 | /* Writeable */ |
| 168 | ret.perm = IOMMU_RW; |
| 169 | } else { |
| 170 | ret.perm = IOMMU_RO; |
| 171 | } |
| 172 | |
| 173 | /* Extract phys */ |
| 174 | if (tte & IOMMU_TTE_DATA_SIZE) { |
| 175 | /* 64K */ |
| 176 | ret.iova = addr & IOMMU_PAGE_MASK_64K; |
| 177 | ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K; |
| 178 | ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1); |
| 179 | } else { |
| 180 | /* 8K */ |
| 181 | ret.iova = addr & IOMMU_PAGE_MASK_8K; |
| 182 | ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K; |
| 183 | ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1); |
| 184 | } |
| 185 | |
Mark Cave-Ayland | 602c993 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 186 | trace_sun4u_iommu_translate(ret.iova, ret.translated_addr, tte); |
| 187 | |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 188 | return ret; |
| 189 | } |
| 190 | |
| 191 | static void iommu_mem_write(void *opaque, hwaddr addr, |
| 192 | uint64_t val, unsigned size) |
| 193 | { |
| 194 | IOMMUState *is = opaque; |
| 195 | |
Mark Cave-Ayland | 09ecbb7 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 196 | trace_sun4u_iommu_mem_write(addr, val, size); |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 197 | |
| 198 | switch (addr) { |
| 199 | case IOMMU_CTRL: |
| 200 | if (size == 4) { |
| 201 | is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL; |
| 202 | is->regs[IOMMU_CTRL >> 3] |= val << 32; |
| 203 | } else { |
| 204 | is->regs[IOMMU_CTRL >> 3] = val; |
| 205 | } |
| 206 | break; |
| 207 | case IOMMU_CTRL + 0x4: |
| 208 | is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL; |
| 209 | is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL; |
| 210 | break; |
| 211 | case IOMMU_BASE: |
| 212 | if (size == 4) { |
| 213 | is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL; |
| 214 | is->regs[IOMMU_BASE >> 3] |= val << 32; |
| 215 | } else { |
| 216 | is->regs[IOMMU_BASE >> 3] = val; |
| 217 | } |
| 218 | break; |
| 219 | case IOMMU_BASE + 0x4: |
| 220 | is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL; |
| 221 | is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL; |
| 222 | break; |
| 223 | case IOMMU_FLUSH: |
| 224 | case IOMMU_FLUSH + 0x4: |
| 225 | break; |
| 226 | default: |
| 227 | qemu_log_mask(LOG_UNIMP, |
Mark Cave-Ayland | 4c9fbc3 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 228 | "sun4u-iommu: Unimplemented register write " |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 229 | "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", |
| 230 | addr, size, val); |
| 231 | break; |
| 232 | } |
| 233 | } |
| 234 | |
| 235 | static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size) |
| 236 | { |
| 237 | IOMMUState *is = opaque; |
| 238 | uint64_t val; |
| 239 | |
| 240 | switch (addr) { |
| 241 | case IOMMU_CTRL: |
| 242 | if (size == 4) { |
| 243 | val = is->regs[IOMMU_CTRL >> 3] >> 32; |
| 244 | } else { |
| 245 | val = is->regs[IOMMU_CTRL >> 3]; |
| 246 | } |
| 247 | break; |
| 248 | case IOMMU_CTRL + 0x4: |
| 249 | val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL; |
| 250 | break; |
| 251 | case IOMMU_BASE: |
| 252 | if (size == 4) { |
| 253 | val = is->regs[IOMMU_BASE >> 3] >> 32; |
| 254 | } else { |
| 255 | val = is->regs[IOMMU_BASE >> 3]; |
| 256 | } |
| 257 | break; |
| 258 | case IOMMU_BASE + 0x4: |
| 259 | val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL; |
| 260 | break; |
| 261 | case IOMMU_FLUSH: |
| 262 | case IOMMU_FLUSH + 0x4: |
| 263 | val = 0; |
| 264 | break; |
| 265 | default: |
| 266 | qemu_log_mask(LOG_UNIMP, |
Mark Cave-Ayland | 4c9fbc3 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 267 | "sun4u-iommu: Unimplemented register read " |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 268 | "reg 0x%" HWADDR_PRIx " size 0x%x\n", |
| 269 | addr, size); |
| 270 | val = 0; |
| 271 | break; |
| 272 | } |
| 273 | |
Mark Cave-Ayland | 09ecbb7 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 274 | trace_sun4u_iommu_mem_read(addr, val, size); |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 275 | |
| 276 | return val; |
| 277 | } |
| 278 | |
| 279 | static const MemoryRegionOps iommu_mem_ops = { |
| 280 | .read = iommu_mem_read, |
| 281 | .write = iommu_mem_write, |
| 282 | .endianness = DEVICE_BIG_ENDIAN, |
| 283 | }; |
| 284 | |
| 285 | static void iommu_reset(DeviceState *d) |
| 286 | { |
| 287 | IOMMUState *s = SUN4U_IOMMU(d); |
| 288 | |
| 289 | memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t)); |
| 290 | } |
| 291 | |
| 292 | static void iommu_init(Object *obj) |
| 293 | { |
| 294 | IOMMUState *s = SUN4U_IOMMU(obj); |
| 295 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 296 | |
| 297 | memory_region_init_iommu(&s->iommu, sizeof(s->iommu), |
Mark Cave-Ayland | 4c9fbc3 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 298 | TYPE_SUN4U_IOMMU_MEMORY_REGION, OBJECT(s), |
| 299 | "iommu-sun4u", UINT64_MAX); |
| 300 | address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as"); |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 301 | |
| 302 | memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", |
| 303 | IOMMU_NREGS * sizeof(uint64_t)); |
| 304 | sysbus_init_mmio(sbd, &s->iomem); |
| 305 | } |
| 306 | |
| 307 | static void iommu_class_init(ObjectClass *klass, void *data) |
| 308 | { |
| 309 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 310 | |
| 311 | dc->reset = iommu_reset; |
| 312 | } |
| 313 | |
Mark Cave-Ayland | 4c9fbc3 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 314 | static const TypeInfo iommu_info = { |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 315 | .name = TYPE_SUN4U_IOMMU, |
| 316 | .parent = TYPE_SYS_BUS_DEVICE, |
| 317 | .instance_size = sizeof(IOMMUState), |
| 318 | .instance_init = iommu_init, |
| 319 | .class_init = iommu_class_init, |
| 320 | }; |
| 321 | |
Mark Cave-Ayland | 4c9fbc3 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 322 | static void sun4u_iommu_memory_region_class_init(ObjectClass *klass, void *data) |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 323 | { |
| 324 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); |
| 325 | |
Mark Cave-Ayland | 4c9fbc3 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 326 | imrc->translate = sun4u_translate_iommu; |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 327 | } |
| 328 | |
Mark Cave-Ayland | 4c9fbc3 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 329 | static const TypeInfo sun4u_iommu_memory_region_info = { |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 330 | .parent = TYPE_IOMMU_MEMORY_REGION, |
Mark Cave-Ayland | 4c9fbc3 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 331 | .name = TYPE_SUN4U_IOMMU_MEMORY_REGION, |
| 332 | .class_init = sun4u_iommu_memory_region_class_init, |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 333 | }; |
| 334 | |
Mark Cave-Ayland | 4c9fbc3 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 335 | static void iommu_register_types(void) |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 336 | { |
Mark Cave-Ayland | 4c9fbc3 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 337 | type_register_static(&iommu_info); |
| 338 | type_register_static(&sun4u_iommu_memory_region_info); |
Mark Cave-Ayland | 0ea833c | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 339 | } |
| 340 | |
Mark Cave-Ayland | 4c9fbc3 | 2018-01-08 18:16:34 +0000 | [diff] [blame] | 341 | type_init(iommu_register_types) |