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Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * QEMU loongson 3a5000 develop board emulation
4 *
5 * Copyright (c) 2021 Loongson Technology Corporation Limited
6 */
7#include "qemu/osdep.h"
8#include "qemu/units.h"
9#include "qemu/datadir.h"
10#include "qapi/error.h"
11#include "hw/boards.h"
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +080012#include "hw/char/serial.h"
Bibo Maoa7701b62024-05-14 10:51:09 +080013#include "sysemu/kvm.h"
Song Gao2b284fa2024-05-28 16:38:55 +080014#include "sysemu/tcg.h"
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +080015#include "sysemu/sysemu.h"
16#include "sysemu/qtest.h"
17#include "sysemu/runstate.h"
18#include "sysemu/reset.h"
19#include "sysemu/rtc.h"
20#include "hw/loongarch/virt.h"
21#include "exec/address-spaces.h"
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +080022#include "hw/irq.h"
23#include "net/net.h"
Xiaojuan Yang6a6f26f2022-06-06 20:43:29 +080024#include "hw/loader.h"
25#include "elf.h"
Bibo Maoef2f1142024-07-15 16:23:48 +020026#include "hw/intc/loongarch_ipi.h"
Xiaojuan Yang69d9c742022-06-06 20:43:25 +080027#include "hw/intc/loongarch_extioi.h"
28#include "hw/intc/loongarch_pch_pic.h"
29#include "hw/intc/loongarch_pch_msi.h"
30#include "hw/pci-host/ls7a.h"
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +080031#include "hw/pci-host/gpex.h"
32#include "hw/misc/unimp.h"
Xiaojuan Yang27ad7562022-07-12 16:32:01 +080033#include "hw/loongarch/fw_cfg.h"
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +080034#include "target/loongarch/cpu.h"
Xiaojuan Yang3efa6fa2022-07-12 16:32:04 +080035#include "hw/firmware/smbios.h"
Xiaojuan Yang735143f2022-07-12 16:32:05 +080036#include "hw/acpi/aml-build.h"
37#include "qapi/qapi-visit-common.h"
38#include "hw/acpi/generic_event_device.h"
39#include "hw/mem/nvdimm.h"
Xiaojuan Yangfda3f152022-07-12 16:32:06 +080040#include "sysemu/device_tree.h"
41#include <libfdt.h>
Xiaojuan Yanga1f7d782022-08-10 15:50:35 +080042#include "hw/core/sysbus-fdt.h"
43#include "hw/platform-bus.h"
Xiaojuan Yangf8ab9aa2022-08-10 16:41:52 +080044#include "hw/display/ramfb.h"
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +080045#include "hw/mem/pc-dimm.h"
Xiaojuan Yang3dfbb6d2022-10-28 09:40:07 +080046#include "sysemu/tpm.h"
Xiaojuan Yang288431a2022-11-07 10:09:47 +080047#include "sysemu/block-backend.h"
48#include "hw/block/flash.h"
Bibo Maofe43cc52024-05-28 16:20:53 +080049#include "hw/virtio/virtio-iommu.h"
Richard Hendersoncc37d982023-03-15 17:43:13 +000050#include "qemu/error-report.h"
51
Song Gao2b284fa2024-05-28 16:38:55 +080052static bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvms)
53{
54 if (lvms->veiointc == ON_OFF_AUTO_OFF) {
55 return false;
56 }
57 return true;
58}
59
60static void virt_get_veiointc(Object *obj, Visitor *v, const char *name,
61 void *opaque, Error **errp)
62{
63 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj);
64 OnOffAuto veiointc = lvms->veiointc;
65
66 visit_type_OnOffAuto(v, name, &veiointc, errp);
67}
68
69static void virt_set_veiointc(Object *obj, Visitor *v, const char *name,
70 void *opaque, Error **errp)
71{
72 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj);
73
74 visit_type_OnOffAuto(v, name, &lvms->veiointc, errp);
75}
76
Bibo Maod804ad92024-05-08 11:11:07 +080077static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms,
Xianglai Lic6e98472024-02-19 18:34:14 +080078 const char *name,
79 const char *alias_prop_name)
Xiaojuan Yang288431a2022-11-07 10:09:47 +080080{
81 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
82
83 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
84 qdev_prop_set_uint8(dev, "width", 4);
85 qdev_prop_set_uint8(dev, "device-width", 2);
86 qdev_prop_set_bit(dev, "big-endian", false);
87 qdev_prop_set_uint16(dev, "id0", 0x89);
88 qdev_prop_set_uint16(dev, "id1", 0x18);
89 qdev_prop_set_uint16(dev, "id2", 0x00);
90 qdev_prop_set_uint16(dev, "id3", 0x00);
Xianglai Lic6e98472024-02-19 18:34:14 +080091 qdev_prop_set_string(dev, "name", name);
Bibo Maod804ad92024-05-08 11:11:07 +080092 object_property_add_child(OBJECT(lvms), name, OBJECT(dev));
93 object_property_add_alias(OBJECT(lvms), alias_prop_name,
Xiaojuan Yang288431a2022-11-07 10:09:47 +080094 OBJECT(dev), "drive");
Xianglai Lic6e98472024-02-19 18:34:14 +080095 return PFLASH_CFI01(dev);
96}
Xiaojuan Yang288431a2022-11-07 10:09:47 +080097
Bibo Maod804ad92024-05-08 11:11:07 +080098static void virt_flash_create(LoongArchVirtMachineState *lvms)
Xianglai Lic6e98472024-02-19 18:34:14 +080099{
Bibo Maod804ad92024-05-08 11:11:07 +0800100 lvms->flash[0] = virt_flash_create1(lvms, "virt.flash0", "pflash0");
101 lvms->flash[1] = virt_flash_create1(lvms, "virt.flash1", "pflash1");
Xianglai Lic6e98472024-02-19 18:34:14 +0800102}
103
104static void virt_flash_map1(PFlashCFI01 *flash,
105 hwaddr base, hwaddr size,
106 MemoryRegion *sysmem)
107{
108 DeviceState *dev = DEVICE(flash);
109 BlockBackend *blk;
110 hwaddr real_size = size;
111
112 blk = pflash_cfi01_get_blk(flash);
113 if (blk) {
114 real_size = blk_getlength(blk);
115 assert(real_size && real_size <= size);
116 }
117
118 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE));
119 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
120
121 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE);
122 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
123 memory_region_add_subregion(sysmem, base,
124 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
Xiaojuan Yang288431a2022-11-07 10:09:47 +0800125}
126
Bibo Maod804ad92024-05-08 11:11:07 +0800127static void virt_flash_map(LoongArchVirtMachineState *lvms,
Xiaojuan Yang288431a2022-11-07 10:09:47 +0800128 MemoryRegion *sysmem)
129{
Bibo Maod804ad92024-05-08 11:11:07 +0800130 PFlashCFI01 *flash0 = lvms->flash[0];
131 PFlashCFI01 *flash1 = lvms->flash[1];
Xiaojuan Yang288431a2022-11-07 10:09:47 +0800132
Xianglai Lic6e98472024-02-19 18:34:14 +0800133 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem);
134 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem);
Xiaojuan Yang288431a2022-11-07 10:09:47 +0800135}
136
Bibo Maod804ad92024-05-08 11:11:07 +0800137static void fdt_add_cpuic_node(LoongArchVirtMachineState *lvms,
Song Gaoa0663ef2024-04-26 17:15:44 +0800138 uint32_t *cpuintc_phandle)
139{
Bibo Maod804ad92024-05-08 11:11:07 +0800140 MachineState *ms = MACHINE(lvms);
Song Gaoa0663ef2024-04-26 17:15:44 +0800141 char *nodename;
142
143 *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt);
144 nodename = g_strdup_printf("/cpuic");
145 qemu_fdt_add_subnode(ms->fdt, nodename);
146 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle);
147 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
148 "loongson,cpu-interrupt-controller");
149 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
150 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
151 g_free(nodename);
152}
153
Bibo Maod804ad92024-05-08 11:11:07 +0800154static void fdt_add_eiointc_node(LoongArchVirtMachineState *lvms,
Song Gao975a5af2024-04-26 17:15:45 +0800155 uint32_t *cpuintc_phandle,
156 uint32_t *eiointc_phandle)
157{
Bibo Maod804ad92024-05-08 11:11:07 +0800158 MachineState *ms = MACHINE(lvms);
Song Gao975a5af2024-04-26 17:15:45 +0800159 char *nodename;
160 hwaddr extioi_base = APIC_BASE;
161 hwaddr extioi_size = EXTIOI_SIZE;
162
163 *eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt);
164 nodename = g_strdup_printf("/eiointc@%" PRIx64, extioi_base);
165 qemu_fdt_add_subnode(ms->fdt, nodename);
166 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle);
167 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
168 "loongson,ls2k2000-eiointc");
169 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
170 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
171 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
172 *cpuintc_phandle);
173 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3);
174 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0,
175 extioi_base, 0x0, extioi_size);
176 g_free(nodename);
177}
178
Bibo Maod804ad92024-05-08 11:11:07 +0800179static void fdt_add_pch_pic_node(LoongArchVirtMachineState *lvms,
Song Gao2904f502024-04-26 17:15:46 +0800180 uint32_t *eiointc_phandle,
181 uint32_t *pch_pic_phandle)
182{
Bibo Maod804ad92024-05-08 11:11:07 +0800183 MachineState *ms = MACHINE(lvms);
Song Gao2904f502024-04-26 17:15:46 +0800184 char *nodename;
185 hwaddr pch_pic_base = VIRT_PCH_REG_BASE;
186 hwaddr pch_pic_size = VIRT_PCH_REG_SIZE;
187
188 *pch_pic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
189 nodename = g_strdup_printf("/platic@%" PRIx64, pch_pic_base);
190 qemu_fdt_add_subnode(ms->fdt, nodename);
191 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_pic_phandle);
192 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
193 "loongson,pch-pic-1.0");
194 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0,
195 pch_pic_base, 0, pch_pic_size);
196 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
197 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2);
198 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
199 *eiointc_phandle);
200 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,pic-base-vec", 0);
201 g_free(nodename);
202}
203
Bibo Maod804ad92024-05-08 11:11:07 +0800204static void fdt_add_pch_msi_node(LoongArchVirtMachineState *lvms,
Song Gao572d45e2024-04-26 17:15:47 +0800205 uint32_t *eiointc_phandle,
206 uint32_t *pch_msi_phandle)
207{
Bibo Maod804ad92024-05-08 11:11:07 +0800208 MachineState *ms = MACHINE(lvms);
Song Gao572d45e2024-04-26 17:15:47 +0800209 char *nodename;
210 hwaddr pch_msi_base = VIRT_PCH_MSI_ADDR_LOW;
211 hwaddr pch_msi_size = VIRT_PCH_MSI_SIZE;
212
213 *pch_msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
214 nodename = g_strdup_printf("/msi@%" PRIx64, pch_msi_base);
215 qemu_fdt_add_subnode(ms->fdt, nodename);
216 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_msi_phandle);
217 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
218 "loongson,pch-msi-1.0");
219 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg",
220 0, pch_msi_base,
221 0, pch_msi_size);
222 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
223 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
224 *eiointc_phandle);
225 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-base-vec",
226 VIRT_PCH_PIC_IRQ_NUM);
227 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-num-vecs",
228 EXTIOI_IRQS - VIRT_PCH_PIC_IRQ_NUM);
229 g_free(nodename);
230}
231
Bibo Maod804ad92024-05-08 11:11:07 +0800232static void fdt_add_flash_node(LoongArchVirtMachineState *lvms)
Xiaojuan Yang288431a2022-11-07 10:09:47 +0800233{
Bibo Maod804ad92024-05-08 11:11:07 +0800234 MachineState *ms = MACHINE(lvms);
Xiaojuan Yang288431a2022-11-07 10:09:47 +0800235 char *nodename;
Xianglai Lic6e98472024-02-19 18:34:14 +0800236 MemoryRegion *flash_mem;
Xiaojuan Yang288431a2022-11-07 10:09:47 +0800237
Xianglai Lic6e98472024-02-19 18:34:14 +0800238 hwaddr flash0_base;
239 hwaddr flash0_size;
Xiaojuan Yang288431a2022-11-07 10:09:47 +0800240
Xianglai Lic6e98472024-02-19 18:34:14 +0800241 hwaddr flash1_base;
242 hwaddr flash1_size;
243
Bibo Maod804ad92024-05-08 11:11:07 +0800244 flash_mem = pflash_cfi01_get_memory(lvms->flash[0]);
Xianglai Lic6e98472024-02-19 18:34:14 +0800245 flash0_base = flash_mem->addr;
246 flash0_size = memory_region_size(flash_mem);
247
Bibo Maod804ad92024-05-08 11:11:07 +0800248 flash_mem = pflash_cfi01_get_memory(lvms->flash[1]);
Xianglai Lic6e98472024-02-19 18:34:14 +0800249 flash1_base = flash_mem->addr;
250 flash1_size = memory_region_size(flash_mem);
251
252 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base);
Xiaojuan Yang288431a2022-11-07 10:09:47 +0800253 qemu_fdt_add_subnode(ms->fdt, nodename);
254 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
255 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
Xianglai Lic6e98472024-02-19 18:34:14 +0800256 2, flash0_base, 2, flash0_size,
257 2, flash1_base, 2, flash1_size);
Xiaojuan Yang288431a2022-11-07 10:09:47 +0800258 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
259 g_free(nodename);
260}
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800261
Bibo Maod804ad92024-05-08 11:11:07 +0800262static void fdt_add_rtc_node(LoongArchVirtMachineState *lvms,
Song Gao841ef2c2024-04-26 17:15:51 +0800263 uint32_t *pch_pic_phandle)
Xiaojuan Yangca5bf7a2022-10-28 09:40:06 +0800264{
265 char *nodename;
266 hwaddr base = VIRT_RTC_REG_BASE;
267 hwaddr size = VIRT_RTC_LEN;
Bibo Maod804ad92024-05-08 11:11:07 +0800268 MachineState *ms = MACHINE(lvms);
Xiaojuan Yangca5bf7a2022-10-28 09:40:06 +0800269
270 nodename = g_strdup_printf("/rtc@%" PRIx64, base);
271 qemu_fdt_add_subnode(ms->fdt, nodename);
Song Gao841ef2c2024-04-26 17:15:51 +0800272 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
273 "loongson,ls7a-rtc");
Xiaojuan Yange8c82032022-11-16 11:49:35 +0800274 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
Song Gao841ef2c2024-04-26 17:15:51 +0800275 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
276 VIRT_RTC_IRQ - VIRT_GSI_BASE , 0x4);
277 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
278 *pch_pic_phandle);
Xiaojuan Yangca5bf7a2022-10-28 09:40:06 +0800279 g_free(nodename);
280}
281
Bibo Maod804ad92024-05-08 11:11:07 +0800282static void fdt_add_uart_node(LoongArchVirtMachineState *lvms,
Jason A. Donenfeldb3d4ef82024-09-07 16:34:39 +0200283 uint32_t *pch_pic_phandle, hwaddr base,
284 int irq, bool chosen)
Xiaojuan Yangca5bf7a2022-10-28 09:40:06 +0800285{
286 char *nodename;
Xiaojuan Yangca5bf7a2022-10-28 09:40:06 +0800287 hwaddr size = VIRT_UART_SIZE;
Bibo Maod804ad92024-05-08 11:11:07 +0800288 MachineState *ms = MACHINE(lvms);
Xiaojuan Yangca5bf7a2022-10-28 09:40:06 +0800289
290 nodename = g_strdup_printf("/serial@%" PRIx64, base);
291 qemu_fdt_add_subnode(ms->fdt, nodename);
292 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a");
293 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
294 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
Jason A. Donenfeldb3d4ef82024-09-07 16:34:39 +0200295 if (chosen)
296 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
297 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", irq, 0x4);
Song Gaof5cce572024-04-26 17:15:50 +0800298 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
299 *pch_pic_phandle);
Xiaojuan Yangca5bf7a2022-10-28 09:40:06 +0800300 g_free(nodename);
301}
302
Bibo Maod804ad92024-05-08 11:11:07 +0800303static void create_fdt(LoongArchVirtMachineState *lvms)
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800304{
Bibo Maod804ad92024-05-08 11:11:07 +0800305 MachineState *ms = MACHINE(lvms);
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800306
Bibo Maod804ad92024-05-08 11:11:07 +0800307 ms->fdt = create_device_tree(&lvms->fdt_size);
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800308 if (!ms->fdt) {
309 error_report("create_device_tree() failed");
310 exit(1);
311 }
312
313 /* Header */
314 qemu_fdt_setprop_string(ms->fdt, "/", "compatible",
315 "linux,dummy-loongson3");
316 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
317 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
Xiaojuan Yang0208ba72022-11-10 14:14:40 +0800318 qemu_fdt_add_subnode(ms->fdt, "/chosen");
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800319}
320
Bibo Maod804ad92024-05-08 11:11:07 +0800321static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800322{
323 int num;
Bibo Maod804ad92024-05-08 11:11:07 +0800324 const MachineState *ms = MACHINE(lvms);
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800325 int smp_cpus = ms->smp.cpus;
326
327 qemu_fdt_add_subnode(ms->fdt, "/cpus");
328 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
329 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
330
331 /* cpu nodes */
332 for (num = smp_cpus - 1; num >= 0; num--) {
333 char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
334 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
Tianrui Zhao0cf14782023-05-18 14:58:15 +0800335 CPUState *cs = CPU(cpu);
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800336
337 qemu_fdt_add_subnode(ms->fdt, nodename);
338 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
339 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
340 cpu->dtb_compatible);
Tianrui Zhao0cf14782023-05-18 14:58:15 +0800341 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
342 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
343 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
344 }
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800345 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
346 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
347 qemu_fdt_alloc_phandle(ms->fdt));
348 g_free(nodename);
349 }
350
351 /*cpu map */
352 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
353
354 for (num = smp_cpus - 1; num >= 0; num--) {
355 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num);
356 char *map_path;
357
358 if (ms->smp.threads > 1) {
359 map_path = g_strdup_printf(
360 "/cpus/cpu-map/socket%d/core%d/thread%d",
361 num / (ms->smp.cores * ms->smp.threads),
362 (num / ms->smp.threads) % ms->smp.cores,
363 num % ms->smp.threads);
364 } else {
365 map_path = g_strdup_printf(
366 "/cpus/cpu-map/socket%d/core%d",
367 num / ms->smp.cores,
368 num % ms->smp.cores);
369 }
370 qemu_fdt_add_path(ms->fdt, map_path);
371 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
372
373 g_free(map_path);
374 g_free(cpu_path);
375 }
376}
377
Bibo Maod804ad92024-05-08 11:11:07 +0800378static void fdt_add_fw_cfg_node(const LoongArchVirtMachineState *lvms)
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800379{
380 char *nodename;
381 hwaddr base = VIRT_FWCFG_BASE;
Bibo Maod804ad92024-05-08 11:11:07 +0800382 const MachineState *ms = MACHINE(lvms);
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800383
384 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base);
385 qemu_fdt_add_subnode(ms->fdt, nodename);
386 qemu_fdt_setprop_string(ms->fdt, nodename,
387 "compatible", "qemu,fw-cfg-mmio");
388 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
Xiaojuan Yangfeae45d2022-08-10 16:53:36 +0800389 2, base, 2, 0x18);
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800390 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
391 g_free(nodename);
392}
393
Bibo Maod804ad92024-05-08 11:11:07 +0800394static void fdt_add_pcie_irq_map_node(const LoongArchVirtMachineState *lvms,
Song Gao07bf0b62024-04-26 17:15:48 +0800395 char *nodename,
396 uint32_t *pch_pic_phandle)
397{
398 int pin, dev;
399 uint32_t irq_map_stride = 0;
400 uint32_t full_irq_map[GPEX_NUM_IRQS *GPEX_NUM_IRQS * 10] = {};
401 uint32_t *irq_map = full_irq_map;
Bibo Maod804ad92024-05-08 11:11:07 +0800402 const MachineState *ms = MACHINE(lvms);
Song Gao07bf0b62024-04-26 17:15:48 +0800403
404 /* This code creates a standard swizzle of interrupts such that
405 * each device's first interrupt is based on it's PCI_SLOT number.
406 * (See pci_swizzle_map_irq_fn())
407 *
408 * We only need one entry per interrupt in the table (not one per
409 * possible slot) seeing the interrupt-map-mask will allow the table
410 * to wrap to any number of devices.
411 */
412
413 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
414 int devfn = dev * 0x8;
415
416 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
417 int irq_nr = 16 + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
418 int i = 0;
419
420 /* Fill PCI address cells */
421 irq_map[i] = cpu_to_be32(devfn << 8);
422 i += 3;
423
424 /* Fill PCI Interrupt cells */
425 irq_map[i] = cpu_to_be32(pin + 1);
426 i += 1;
427
428 /* Fill interrupt controller phandle and cells */
429 irq_map[i++] = cpu_to_be32(*pch_pic_phandle);
430 irq_map[i++] = cpu_to_be32(irq_nr);
431
432 if (!irq_map_stride) {
433 irq_map_stride = i;
434 }
435 irq_map += irq_map_stride;
436 }
437 }
438
439
440 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map,
441 GPEX_NUM_IRQS * GPEX_NUM_IRQS *
442 irq_map_stride * sizeof(uint32_t));
443 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
444 0x1800, 0, 0, 0x7);
445}
446
Bibo Maod804ad92024-05-08 11:11:07 +0800447static void fdt_add_pcie_node(const LoongArchVirtMachineState *lvms,
Song Gao07bf0b62024-04-26 17:15:48 +0800448 uint32_t *pch_pic_phandle,
449 uint32_t *pch_msi_phandle)
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800450{
451 char *nodename;
Xiaojuan Yang74725232022-07-29 15:30:18 +0800452 hwaddr base_mmio = VIRT_PCI_MEM_BASE;
453 hwaddr size_mmio = VIRT_PCI_MEM_SIZE;
454 hwaddr base_pio = VIRT_PCI_IO_BASE;
455 hwaddr size_pio = VIRT_PCI_IO_SIZE;
456 hwaddr base_pcie = VIRT_PCI_CFG_BASE;
457 hwaddr size_pcie = VIRT_PCI_CFG_SIZE;
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800458 hwaddr base = base_pcie;
459
Bibo Maod804ad92024-05-08 11:11:07 +0800460 const MachineState *ms = MACHINE(lvms);
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800461
462 nodename = g_strdup_printf("/pcie@%" PRIx64, base);
463 qemu_fdt_add_subnode(ms->fdt, nodename);
464 qemu_fdt_setprop_string(ms->fdt, nodename,
465 "compatible", "pci-host-ecam-generic");
466 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
467 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
468 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
469 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
470 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
Xiaojuan Yang74725232022-07-29 15:30:18 +0800471 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1));
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800472 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
473 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
474 2, base_pcie, 2, size_pcie);
475 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
Xiaojuan Yang74725232022-07-29 15:30:18 +0800476 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET,
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800477 2, base_pio, 2, size_pio,
478 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
479 2, base_mmio, 2, size_mmio);
Song Gao07bf0b62024-04-26 17:15:48 +0800480 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
481 0, *pch_msi_phandle, 0, 0x10000);
482
Bibo Maod804ad92024-05-08 11:11:07 +0800483 fdt_add_pcie_irq_map_node(lvms, nodename, pch_pic_phandle);
Song Gao07bf0b62024-04-26 17:15:48 +0800484
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800485 g_free(nodename);
Xiaojuan Yangfda3f152022-07-12 16:32:06 +0800486}
487
Tianrui Zhao0cf14782023-05-18 14:58:15 +0800488static void fdt_add_memory_node(MachineState *ms,
489 uint64_t base, uint64_t size, int node_id)
490{
491 char *nodename = g_strdup_printf("/memory@%" PRIx64, base);
492
493 qemu_fdt_add_subnode(ms->fdt, nodename);
Jiaxun Yang6204af72024-05-20 22:06:31 +0100494 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", base >> 32, base,
495 size >> 32, size);
Tianrui Zhao0cf14782023-05-18 14:58:15 +0800496 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
497
498 if (ms->numa_state && ms->numa_state->num_nodes) {
499 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id);
500 }
501
502 g_free(nodename);
503}
504
Bibo Mao09ec6572024-05-15 17:39:23 +0800505static void fdt_add_memory_nodes(MachineState *ms)
506{
507 hwaddr base, size, ram_size, gap;
508 int i, nb_numa_nodes, nodes;
509 NodeInfo *numa_info;
510
511 ram_size = ms->ram_size;
512 base = VIRT_LOWMEM_BASE;
513 gap = VIRT_LOWMEM_SIZE;
514 nodes = nb_numa_nodes = ms->numa_state->num_nodes;
515 numa_info = ms->numa_state->nodes;
516 if (!nodes) {
517 nodes = 1;
518 }
519
520 for (i = 0; i < nodes; i++) {
521 if (nb_numa_nodes) {
522 size = numa_info[i].node_mem;
523 } else {
524 size = ram_size;
525 }
526
527 /*
528 * memory for the node splited into two part
529 * lowram: [base, +gap)
530 * highram: [VIRT_HIGHMEM_BASE, +(len - gap))
531 */
532 if (size >= gap) {
533 fdt_add_memory_node(ms, base, gap, i);
534 size -= gap;
535 base = VIRT_HIGHMEM_BASE;
536 gap = ram_size - VIRT_LOWMEM_SIZE;
537 }
538
539 if (size) {
540 fdt_add_memory_node(ms, base, size, i);
541 base += size;
542 gap -= size;
543 }
544 }
545}
546
Bibo Maod804ad92024-05-08 11:11:07 +0800547static void virt_build_smbios(LoongArchVirtMachineState *lvms)
Xiaojuan Yang3efa6fa2022-07-12 16:32:04 +0800548{
Bibo Maod804ad92024-05-08 11:11:07 +0800549 MachineState *ms = MACHINE(lvms);
550 MachineClass *mc = MACHINE_GET_CLASS(lvms);
Xiaojuan Yang3efa6fa2022-07-12 16:32:04 +0800551 uint8_t *smbios_tables, *smbios_anchor;
552 size_t smbios_tables_len, smbios_anchor_len;
553 const char *product = "QEMU Virtual Machine";
554
Bibo Maod804ad92024-05-08 11:11:07 +0800555 if (!lvms->fw_cfg) {
Xiaojuan Yang3efa6fa2022-07-12 16:32:04 +0800556 return;
557 }
558
Philippe Mathieu-Daudéc3381282024-03-27 10:08:05 +0100559 smbios_set_defaults("QEMU", product, mc->name);
Xiaojuan Yang3efa6fa2022-07-12 16:32:04 +0800560
Igor Mammedov69ea07a2024-03-14 16:22:54 +0100561 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64,
562 NULL, 0,
563 &smbios_tables, &smbios_tables_len,
Xiaojuan Yang3efa6fa2022-07-12 16:32:04 +0800564 &smbios_anchor, &smbios_anchor_len, &error_fatal);
565
566 if (smbios_anchor) {
Bibo Maod804ad92024-05-08 11:11:07 +0800567 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-tables",
Xiaojuan Yang3efa6fa2022-07-12 16:32:04 +0800568 smbios_tables, smbios_tables_len);
Bibo Maod804ad92024-05-08 11:11:07 +0800569 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-anchor",
Xiaojuan Yang3efa6fa2022-07-12 16:32:04 +0800570 smbios_anchor, smbios_anchor_len);
571 }
572}
573
Bibo Maod804ad92024-05-08 11:11:07 +0800574static void virt_done(Notifier *notifier, void *data)
Xiaojuan Yang3efa6fa2022-07-12 16:32:04 +0800575{
Bibo Maod804ad92024-05-08 11:11:07 +0800576 LoongArchVirtMachineState *lvms = container_of(notifier,
577 LoongArchVirtMachineState, machine_done);
578 virt_build_smbios(lvms);
579 loongarch_acpi_setup(lvms);
Xiaojuan Yang3efa6fa2022-07-12 16:32:04 +0800580}
581
Song Gao0d588c42023-01-10 11:29:16 +0800582static void virt_powerdown_req(Notifier *notifier, void *opaque)
583{
Bibo Maod804ad92024-05-08 11:11:07 +0800584 LoongArchVirtMachineState *s;
Song Gao0d588c42023-01-10 11:29:16 +0800585
Bibo Maod804ad92024-05-08 11:11:07 +0800586 s = container_of(notifier, LoongArchVirtMachineState, powerdown_notifier);
Song Gao0d588c42023-01-10 11:29:16 +0800587 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS);
588}
589
Xiaojuan Yang27ad7562022-07-12 16:32:01 +0800590static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type)
591{
592 /* Ensure there are no duplicate entries. */
593 for (unsigned i = 0; i < memmap_entries; i++) {
594 assert(memmap_table[i].address != address);
595 }
596
597 memmap_table = g_renew(struct memmap_entry, memmap_table,
598 memmap_entries + 1);
599 memmap_table[memmap_entries].address = cpu_to_le64(address);
600 memmap_table[memmap_entries].length = cpu_to_le64(length);
601 memmap_table[memmap_entries].type = cpu_to_le32(type);
602 memmap_table[memmap_entries].reserved = 0;
603 memmap_entries++;
604}
605
Bibo Maod804ad92024-05-08 11:11:07 +0800606static DeviceState *create_acpi_ged(DeviceState *pch_pic,
607 LoongArchVirtMachineState *lvms)
Xiaojuan Yang735143f2022-07-12 16:32:05 +0800608{
609 DeviceState *dev;
Bibo Maod804ad92024-05-08 11:11:07 +0800610 MachineState *ms = MACHINE(lvms);
Xiaojuan Yang735143f2022-07-12 16:32:05 +0800611 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
612
613 if (ms->ram_slots) {
614 event |= ACPI_GED_MEM_HOTPLUG_EVT;
615 }
616 dev = qdev_new(TYPE_ACPI_GED);
617 qdev_prop_set_uint32(dev, "ged-event", event);
Philippe Mathieu-Daudébec4be72023-10-18 08:37:06 +0200618 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
Xiaojuan Yang735143f2022-07-12 16:32:05 +0800619
620 /* ged event */
621 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR);
622 /* memory hotplug */
623 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR);
624 /* ged regs used for reset and power down */
625 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR);
626
627 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
Bibo Mao456eb812022-12-28 11:07:19 +0800628 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE));
Xiaojuan Yang735143f2022-07-12 16:32:05 +0800629 return dev;
630}
631
Xiaojuan Yanga1f7d782022-08-10 15:50:35 +0800632static DeviceState *create_platform_bus(DeviceState *pch_pic)
633{
634 DeviceState *dev;
635 SysBusDevice *sysbus;
636 int i, irq;
637 MemoryRegion *sysmem = get_system_memory();
638
639 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
640 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
641 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS);
642 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE);
643 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
644
645 sysbus = SYS_BUS_DEVICE(dev);
646 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
Bibo Mao456eb812022-12-28 11:07:19 +0800647 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i;
Xiaojuan Yanga1f7d782022-08-10 15:50:35 +0800648 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq));
649 }
650
651 memory_region_add_subregion(sysmem,
652 VIRT_PLATFORM_BUS_BASEADDRESS,
653 sysbus_mmio_get_region(sysbus, 0));
654 return dev;
655}
656
Bibo Maod804ad92024-05-08 11:11:07 +0800657static void virt_devices_init(DeviceState *pch_pic,
658 LoongArchVirtMachineState *lvms,
Song Gao07bf0b62024-04-26 17:15:48 +0800659 uint32_t *pch_pic_phandle,
660 uint32_t *pch_msi_phandle)
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +0800661{
Bibo Maod804ad92024-05-08 11:11:07 +0800662 MachineClass *mc = MACHINE_GET_CLASS(lvms);
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +0800663 DeviceState *gpex_dev;
664 SysBusDevice *d;
665 PCIBus *pci_bus;
666 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg;
Song Gao89daabe2023-10-12 14:41:23 +0800667 MemoryRegion *mmio_alias, *mmio_reg;
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +0800668 int i;
669
670 gpex_dev = qdev_new(TYPE_GPEX_HOST);
671 d = SYS_BUS_DEVICE(gpex_dev);
672 sysbus_realize_and_unref(d, &error_fatal);
673 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus;
Bibo Maod804ad92024-05-08 11:11:07 +0800674 lvms->pci_bus = pci_bus;
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +0800675
676 /* Map only part size_ecam bytes of ECAM space */
677 ecam_alias = g_new0(MemoryRegion, 1);
678 ecam_reg = sysbus_mmio_get_region(d, 0);
679 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam",
Xiaojuan Yang74725232022-07-29 15:30:18 +0800680 ecam_reg, 0, VIRT_PCI_CFG_SIZE);
681 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE,
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +0800682 ecam_alias);
683
684 /* Map PCI mem space */
685 mmio_alias = g_new0(MemoryRegion, 1);
686 mmio_reg = sysbus_mmio_get_region(d, 1);
687 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio",
Xiaojuan Yang74725232022-07-29 15:30:18 +0800688 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE);
689 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE,
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +0800690 mmio_alias);
691
692 /* Map PCI IO port space. */
693 pio_alias = g_new0(MemoryRegion, 1);
694 pio_reg = sysbus_mmio_get_region(d, 2);
695 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg,
Xiaojuan Yang74725232022-07-29 15:30:18 +0800696 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE);
697 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE,
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +0800698 pio_alias);
699
700 for (i = 0; i < GPEX_NUM_IRQS; i++) {
701 sysbus_connect_irq(d, i,
702 qdev_get_gpio_in(pch_pic, 16 + i));
703 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
704 }
705
Song Gao07bf0b62024-04-26 17:15:48 +0800706 /* Add pcie node */
Bibo Maod804ad92024-05-08 11:11:07 +0800707 fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle);
Song Gao07bf0b62024-04-26 17:15:48 +0800708
Jason A. Donenfeldb3d4ef82024-09-07 16:34:39 +0200709 /*
710 * Create uart fdt node in reverse order so that they appear
711 * in the finished device tree lowest address first
712 */
713 for (i = VIRT_UART_COUNT; i --> 0;) {
714 hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE;
715 int irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE;
716 serial_mm_init(get_system_memory(), base, 0,
717 qdev_get_gpio_in(pch_pic, irq),
718 115200, serial_hd(i), DEVICE_LITTLE_ENDIAN);
719 fdt_add_uart_node(lvms, pch_pic_phandle, base, irq, i == 0);
720 }
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +0800721
722 /* Network init */
David Woodhouse13af77e2023-10-21 21:21:03 +0100723 pci_init_nic_devices(pci_bus, mc->default_nic);
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +0800724
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +0800725 /*
726 * There are some invalid guest memory access.
727 * Create some unimplemented devices to emulate this.
728 */
729 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);
Xiaojuan Yang74725232022-07-29 15:30:18 +0800730 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
Xiaojuan Yangc117f682022-06-06 20:43:28 +0800731 qdev_get_gpio_in(pch_pic,
Bibo Mao456eb812022-12-28 11:07:19 +0800732 VIRT_RTC_IRQ - VIRT_GSI_BASE));
Bibo Maod804ad92024-05-08 11:11:07 +0800733 fdt_add_rtc_node(lvms, pch_pic_phandle);
Xiaojuan Yang9e6602d2022-06-06 20:43:30 +0800734
Xiaojuan Yang735143f2022-07-12 16:32:05 +0800735 /* acpi ged */
Bibo Maod804ad92024-05-08 11:11:07 +0800736 lvms->acpi_ged = create_acpi_ged(pch_pic, lvms);
Xiaojuan Yanga1f7d782022-08-10 15:50:35 +0800737 /* platform bus */
Bibo Maod804ad92024-05-08 11:11:07 +0800738 lvms->platform_bus_dev = create_platform_bus(pch_pic);
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +0800739}
740
Bibo Maod804ad92024-05-08 11:11:07 +0800741static void virt_irq_init(LoongArchVirtMachineState *lvms)
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800742{
Bibo Maod804ad92024-05-08 11:11:07 +0800743 MachineState *ms = MACHINE(lvms);
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800744 DeviceState *pch_pic, *pch_msi, *cpudev;
745 DeviceState *ipi, *extioi;
746 SysBusDevice *d;
747 LoongArchCPU *lacpu;
748 CPULoongArchState *env;
749 CPUState *cpu_state;
Tianrui Zhao6027d272022-12-13 20:50:16 +0800750 int cpu, pin, i, start, num;
Song Gao572d45e2024-04-26 17:15:47 +0800751 uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800752
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800753 /*
Song Gaodc6f37e2024-05-28 16:38:53 +0800754 * Extended IRQ model.
755 * |
756 * +-----------+ +-------------|--------+ +-----------+
757 * | IPI/Timer | --> | CPUINTC(0-3)|(4-255) | <-- | IPI/Timer |
758 * +-----------+ +-------------|--------+ +-----------+
759 * ^ |
760 * |
761 * +---------+
762 * | EIOINTC |
763 * +---------+
764 * ^ ^
765 * | |
766 * +---------+ +---------+
767 * | PCH-PIC | | PCH-MSI |
768 * +---------+ +---------+
769 * ^ ^ ^
770 * | | |
771 * +--------+ +---------+ +---------+
772 * | UARTs | | Devices | | Devices |
773 * +--------+ +---------+ +---------+
774 *
775 * Virt extended IRQ model.
776 *
777 * +-----+ +---------------+ +-------+
778 * | IPI |--> | CPUINTC(0-255)| <-- | Timer |
779 * +-----+ +---------------+ +-------+
780 * ^
781 * |
782 * +-----------+
783 * | V-EIOINTC |
784 * +-----------+
785 * ^ ^
786 * | |
787 * +---------+ +---------+
788 * | PCH-PIC | | PCH-MSI |
789 * +---------+ +---------+
790 * ^ ^ ^
791 * | | |
792 * +--------+ +---------+ +---------+
793 * | UARTs | | Devices | | Devices |
794 * +--------+ +---------+ +---------+
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800795 */
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800796
797 /* Create IPI device */
Bibo Maoef2f1142024-07-15 16:23:48 +0200798 ipi = qdev_new(TYPE_LOONGARCH_IPI);
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800799 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus);
800 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
801
802 /* IPI iocsr memory region */
Bibo Maod804ad92024-05-08 11:11:07 +0800803 memory_region_add_subregion(&lvms->system_iocsr, SMP_IPI_MAILBOX,
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800804 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0));
Bibo Maod804ad92024-05-08 11:11:07 +0800805 memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR,
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800806 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
807
Song Gaoa0663ef2024-04-26 17:15:44 +0800808 /* Add cpu interrupt-controller */
Bibo Maod804ad92024-05-08 11:11:07 +0800809 fdt_add_cpuic_node(lvms, &cpuintc_phandle);
Song Gaoa0663ef2024-04-26 17:15:44 +0800810
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800811 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
812 cpu_state = qemu_get_cpu(cpu);
813 cpudev = DEVICE(cpu_state);
814 lacpu = LOONGARCH_CPU(cpu_state);
815 env = &(lacpu->env);
Bibo Maod804ad92024-05-08 11:11:07 +0800816 env->address_space_iocsr = &lvms->as_iocsr;
Song Gao78464f02023-04-06 14:57:27 +0800817
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800818 /* connect ipi irq to cpu irq */
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800819 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI));
Tianrui Zhao758a7472023-05-17 09:22:00 +0800820 env->ipistate = ipi;
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800821 }
822
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800823 /* Create EXTIOI device */
824 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
Bibo Mao10a8f7d2023-12-15 11:07:36 +0800825 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus);
Song Gao2b284fa2024-05-28 16:38:55 +0800826 if (virt_is_veiointc_enabled(lvms)) {
827 qdev_prop_set_bit(extioi, "has-virtualization-extension", true);
828 }
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800829 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal);
Bibo Maod804ad92024-05-08 11:11:07 +0800830 memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE,
Song Gao2b284fa2024-05-28 16:38:55 +0800831 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0));
832 if (virt_is_veiointc_enabled(lvms)) {
833 memory_region_add_subregion(&lvms->system_iocsr, EXTIOI_VIRT_BASE,
834 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 1));
835 }
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800836
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800837 /*
838 * connect ext irq to the cpu irq
839 * cpu_pin[9:2] <= intc_pin[7:0]
840 */
Bibo Mao10a8f7d2023-12-15 11:07:36 +0800841 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800842 cpudev = DEVICE(qemu_get_cpu(cpu));
843 for (pin = 0; pin < LS3A_INTC_IP; pin++) {
844 qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
845 qdev_get_gpio_in(cpudev, pin + 2));
846 }
847 }
848
Song Gao975a5af2024-04-26 17:15:45 +0800849 /* Add Extend I/O Interrupt Controller node */
Bibo Maod804ad92024-05-08 11:11:07 +0800850 fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
Song Gao975a5af2024-04-26 17:15:45 +0800851
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800852 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
Tianrui Zhaof4d10ce2022-12-27 11:19:57 +0800853 num = VIRT_PCH_PIC_IRQ_NUM;
Tianrui Zhao270950b2022-12-14 09:57:18 +0800854 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800855 d = SYS_BUS_DEVICE(pch_pic);
856 sysbus_realize_and_unref(d, &error_fatal);
Xiaojuan Yang74725232022-07-29 15:30:18 +0800857 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800858 sysbus_mmio_get_region(d, 0));
859 memory_region_add_subregion(get_system_memory(),
Xiaojuan Yang74725232022-07-29 15:30:18 +0800860 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET,
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800861 sysbus_mmio_get_region(d, 1));
862 memory_region_add_subregion(get_system_memory(),
Xiaojuan Yang74725232022-07-29 15:30:18 +0800863 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800864 sysbus_mmio_get_region(d, 2));
865
Tianrui Zhao270950b2022-12-14 09:57:18 +0800866 /* Connect pch_pic irqs to extioi */
Song Gao78bcc3c2023-09-26 15:12:53 +0800867 for (i = 0; i < num; i++) {
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800868 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
869 }
870
Song Gao2904f502024-04-26 17:15:46 +0800871 /* Add PCH PIC node */
Bibo Maod804ad92024-05-08 11:11:07 +0800872 fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
Song Gao2904f502024-04-26 17:15:46 +0800873
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800874 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
Tianrui Zhao270950b2022-12-14 09:57:18 +0800875 start = num;
Tianrui Zhao6027d272022-12-13 20:50:16 +0800876 num = EXTIOI_IRQS - start;
877 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
878 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800879 d = SYS_BUS_DEVICE(pch_msi);
880 sysbus_realize_and_unref(d, &error_fatal);
Xiaojuan Yang74725232022-07-29 15:30:18 +0800881 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
Tianrui Zhao6027d272022-12-13 20:50:16 +0800882 for (i = 0; i < num; i++) {
883 /* Connect pch_msi irqs to extioi */
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800884 qdev_connect_gpio_out(DEVICE(d), i,
Tianrui Zhao6027d272022-12-13 20:50:16 +0800885 qdev_get_gpio_in(extioi, i + start));
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800886 }
Xiaojuan Yangdc93b8d2022-06-06 20:43:27 +0800887
Song Gao572d45e2024-04-26 17:15:47 +0800888 /* Add PCH MSI node */
Bibo Maod804ad92024-05-08 11:11:07 +0800889 fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
Song Gao572d45e2024-04-26 17:15:47 +0800890
Bibo Maod804ad92024-05-08 11:11:07 +0800891 virt_devices_init(pch_pic, lvms, &pch_pic_phandle, &pch_msi_phandle);
Xiaojuan Yang69d9c742022-06-06 20:43:25 +0800892}
893
Bibo Maod804ad92024-05-08 11:11:07 +0800894static void virt_firmware_init(LoongArchVirtMachineState *lvms)
Xiaojuan Yang98afb0d2022-07-12 16:32:02 +0800895{
Bibo Maod804ad92024-05-08 11:11:07 +0800896 char *filename = MACHINE(lvms)->firmware;
Xiaojuan Yang98afb0d2022-07-12 16:32:02 +0800897 char *bios_name = NULL;
Xianglai Lic6e98472024-02-19 18:34:14 +0800898 int bios_size, i;
899 BlockBackend *pflash_blk0;
900 MemoryRegion *mr;
Xiaojuan Yang98afb0d2022-07-12 16:32:02 +0800901
Bibo Maod804ad92024-05-08 11:11:07 +0800902 lvms->bios_loaded = false;
Xiaojuan Yang288431a2022-11-07 10:09:47 +0800903
Xianglai Lic6e98472024-02-19 18:34:14 +0800904 /* Map legacy -drive if=pflash to machine properties */
Bibo Maod804ad92024-05-08 11:11:07 +0800905 for (i = 0; i < ARRAY_SIZE(lvms->flash); i++) {
906 pflash_cfi01_legacy_drive(lvms->flash[i],
Xianglai Lic6e98472024-02-19 18:34:14 +0800907 drive_get(IF_PFLASH, 0, i));
908 }
909
Bibo Maod804ad92024-05-08 11:11:07 +0800910 virt_flash_map(lvms, get_system_memory());
Xiaojuan Yang288431a2022-11-07 10:09:47 +0800911
Bibo Maod804ad92024-05-08 11:11:07 +0800912 pflash_blk0 = pflash_cfi01_get_blk(lvms->flash[0]);
Xianglai Lic6e98472024-02-19 18:34:14 +0800913
914 if (pflash_blk0) {
915 if (filename) {
916 error_report("cannot use both '-bios' and '-drive if=pflash'"
917 "options at once");
918 exit(1);
919 }
Bibo Maod804ad92024-05-08 11:11:07 +0800920 lvms->bios_loaded = true;
Xianglai Lic6e98472024-02-19 18:34:14 +0800921 return;
922 }
923
Xiaojuan Yang98afb0d2022-07-12 16:32:02 +0800924 if (filename) {
925 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename);
926 if (!bios_name) {
927 error_report("Could not find ROM image '%s'", filename);
928 exit(1);
929 }
930
Bibo Maod804ad92024-05-08 11:11:07 +0800931 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lvms->flash[0]), 0);
Xianglai Lic6e98472024-02-19 18:34:14 +0800932 bios_size = load_image_mr(bios_name, mr);
Xiaojuan Yang98afb0d2022-07-12 16:32:02 +0800933 if (bios_size < 0) {
934 error_report("Could not load ROM image '%s'", bios_name);
935 exit(1);
936 }
Xiaojuan Yang98afb0d2022-07-12 16:32:02 +0800937 g_free(bios_name);
Bibo Maod804ad92024-05-08 11:11:07 +0800938 lvms->bios_loaded = true;
Xiaojuan Yang98afb0d2022-07-12 16:32:02 +0800939 }
Xiaojuan Yang98afb0d2022-07-12 16:32:02 +0800940}
941
Song Gaof2e61ed2024-05-28 16:38:54 +0800942static MemTxResult virt_iocsr_misc_write(void *opaque, hwaddr addr,
943 uint64_t val, unsigned size,
944 MemTxAttrs attrs)
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800945{
Song Gao2b284fa2024-05-28 16:38:55 +0800946 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque);
947 uint64_t features;
948
949 switch (addr) {
950 case MISC_FUNC_REG:
951 if (!virt_is_veiointc_enabled(lvms)) {
952 return MEMTX_OK;
953 }
954
955 features = address_space_ldl(&lvms->as_iocsr,
956 EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG,
957 attrs, NULL);
958 if (val & BIT_ULL(IOCSRM_EXTIOI_EN)) {
959 features |= BIT(EXTIOI_ENABLE);
960 }
961 if (val & BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE)) {
962 features |= BIT(EXTIOI_ENABLE_INT_ENCODE);
963 }
964
965 address_space_stl(&lvms->as_iocsr,
966 EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG,
967 features, attrs, NULL);
968 break;
969 default:
970 g_assert_not_reached();
971 }
972
Song Gaof2e61ed2024-05-28 16:38:54 +0800973 return MEMTX_OK;
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800974}
975
Song Gaof2e61ed2024-05-28 16:38:54 +0800976static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr,
977 uint64_t *data,
978 unsigned size, MemTxAttrs attrs)
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800979{
Song Gao2b284fa2024-05-28 16:38:55 +0800980 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque);
Song Gaof2e61ed2024-05-28 16:38:54 +0800981 uint64_t ret = 0;
Song Gao2b284fa2024-05-28 16:38:55 +0800982 int features;
Bibo Maoa7701b62024-05-14 10:51:09 +0800983
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800984 switch (addr) {
985 case VERSION_REG:
Song Gaof2e61ed2024-05-28 16:38:54 +0800986 ret = 0x11ULL;
987 break;
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800988 case FEATURE_REG:
Bibo Maoa7701b62024-05-14 10:51:09 +0800989 ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI);
990 if (kvm_enabled()) {
991 ret |= BIT(IOCSRF_VM);
992 }
Song Gaof2e61ed2024-05-28 16:38:54 +0800993 break;
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800994 case VENDOR_REG:
Song Gaof2e61ed2024-05-28 16:38:54 +0800995 ret = 0x6e6f73676e6f6f4cULL; /* "Loongson" */
996 break;
Bibo Mao5e90b8d2023-12-13 12:13:14 +0800997 case CPUNAME_REG:
Song Gaof2e61ed2024-05-28 16:38:54 +0800998 ret = 0x303030354133ULL; /* "3A5000" */
999 break;
Bibo Mao5e90b8d2023-12-13 12:13:14 +08001000 case MISC_FUNC_REG:
Song Gao2b284fa2024-05-28 16:38:55 +08001001 if (!virt_is_veiointc_enabled(lvms)) {
1002 ret |= BIT_ULL(IOCSRM_EXTIOI_EN);
1003 break;
1004 }
1005
1006 features = address_space_ldl(&lvms->as_iocsr,
1007 EXTIOI_VIRT_BASE + EXTIOI_VIRT_CONFIG,
1008 attrs, NULL);
1009 if (features & BIT(EXTIOI_ENABLE)) {
1010 ret |= BIT_ULL(IOCSRM_EXTIOI_EN);
1011 }
1012 if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) {
1013 ret |= BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE);
1014 }
Song Gaof2e61ed2024-05-28 16:38:54 +08001015 break;
1016 default:
1017 g_assert_not_reached();
Bibo Mao5e90b8d2023-12-13 12:13:14 +08001018 }
Song Gaof2e61ed2024-05-28 16:38:54 +08001019
1020 *data = ret;
1021 return MEMTX_OK;
Bibo Mao5e90b8d2023-12-13 12:13:14 +08001022}
1023
Bibo Maod804ad92024-05-08 11:11:07 +08001024static const MemoryRegionOps virt_iocsr_misc_ops = {
Song Gaof2e61ed2024-05-28 16:38:54 +08001025 .read_with_attrs = virt_iocsr_misc_read,
1026 .write_with_attrs = virt_iocsr_misc_write,
Bibo Mao5e90b8d2023-12-13 12:13:14 +08001027 .endianness = DEVICE_LITTLE_ENDIAN,
1028 .valid = {
1029 .min_access_size = 4,
1030 .max_access_size = 8,
1031 },
1032 .impl = {
1033 .min_access_size = 8,
1034 .max_access_size = 8,
1035 },
1036};
1037
Bibo Mao3cc451c2024-05-15 17:39:24 +08001038static void fw_cfg_add_memory(MachineState *ms)
1039{
1040 hwaddr base, size, ram_size, gap;
1041 int nb_numa_nodes, nodes;
1042 NodeInfo *numa_info;
1043
1044 ram_size = ms->ram_size;
1045 base = VIRT_LOWMEM_BASE;
1046 gap = VIRT_LOWMEM_SIZE;
1047 nodes = nb_numa_nodes = ms->numa_state->num_nodes;
1048 numa_info = ms->numa_state->nodes;
1049 if (!nodes) {
1050 nodes = 1;
1051 }
1052
1053 /* add fw_cfg memory map of node0 */
1054 if (nb_numa_nodes) {
1055 size = numa_info[0].node_mem;
1056 } else {
1057 size = ram_size;
1058 }
1059
1060 if (size >= gap) {
1061 memmap_add_entry(base, gap, 1);
1062 size -= gap;
1063 base = VIRT_HIGHMEM_BASE;
Bibo Mao3cc451c2024-05-15 17:39:24 +08001064 }
1065
1066 if (size) {
1067 memmap_add_entry(base, size, 1);
1068 base += size;
1069 }
1070
1071 if (nodes < 2) {
1072 return;
1073 }
1074
1075 /* add fw_cfg memory map of other nodes */
Bibo Mao5efbc382024-06-12 11:36:37 +08001076 if (numa_info[0].node_mem < gap && ram_size > gap) {
Bibo Mao3cc451c2024-05-15 17:39:24 +08001077 /*
1078 * memory map for the maining nodes splited into two part
Bibo Mao5efbc382024-06-12 11:36:37 +08001079 * lowram: [base, +(gap - numa_info[0].node_mem))
1080 * highram: [VIRT_HIGHMEM_BASE, +(ram_size - gap))
Bibo Mao3cc451c2024-05-15 17:39:24 +08001081 */
Bibo Mao5efbc382024-06-12 11:36:37 +08001082 memmap_add_entry(base, gap - numa_info[0].node_mem, 1);
1083 size = ram_size - gap;
Bibo Mao3cc451c2024-05-15 17:39:24 +08001084 base = VIRT_HIGHMEM_BASE;
Bibo Mao5efbc382024-06-12 11:36:37 +08001085 } else {
1086 size = ram_size - numa_info[0].node_mem;
Bibo Mao3cc451c2024-05-15 17:39:24 +08001087 }
1088
1089 if (size)
1090 memmap_add_entry(base, size, 1);
1091}
1092
Bibo Maod804ad92024-05-08 11:11:07 +08001093static void virt_init(MachineState *machine)
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001094{
Xiaojuan Yangfb1cd3a2022-07-12 16:32:03 +08001095 LoongArchCPU *lacpu;
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001096 const char *cpu_model = machine->cpu_type;
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001097 MemoryRegion *address_space_mem = get_system_memory();
Bibo Maod804ad92024-05-08 11:11:07 +08001098 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine);
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001099 int i;
Bibo Mao8d967882024-05-15 17:39:25 +08001100 hwaddr base, size, ram_size = machine->ram_size;
Tianrui Zhao8f307712023-05-16 16:27:57 +08001101 const CPUArchIdList *possible_cpus;
1102 MachineClass *mc = MACHINE_GET_CLASS(machine);
1103 CPUState *cpu;
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001104
1105 if (!cpu_model) {
1106 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
1107 }
1108
Bibo Maod804ad92024-05-08 11:11:07 +08001109 create_fdt(lvms);
Tianrui Zhao8f307712023-05-16 16:27:57 +08001110
Bibo Mao5e90b8d2023-12-13 12:13:14 +08001111 /* Create IOCSR space */
Bibo Maod804ad92024-05-08 11:11:07 +08001112 memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL,
Bibo Mao5e90b8d2023-12-13 12:13:14 +08001113 machine, "iocsr", UINT64_MAX);
Bibo Maod804ad92024-05-08 11:11:07 +08001114 address_space_init(&lvms->as_iocsr, &lvms->system_iocsr, "IOCSR");
1115 memory_region_init_io(&lvms->iocsr_mem, OBJECT(machine),
1116 &virt_iocsr_misc_ops,
Bibo Mao5e90b8d2023-12-13 12:13:14 +08001117 machine, "iocsr_misc", 0x428);
Bibo Maod804ad92024-05-08 11:11:07 +08001118 memory_region_add_subregion(&lvms->system_iocsr, 0, &lvms->iocsr_mem);
Bibo Mao5e90b8d2023-12-13 12:13:14 +08001119
1120 /* Init CPUs */
Tianrui Zhao8f307712023-05-16 16:27:57 +08001121 possible_cpus = mc->possible_cpu_arch_ids(machine);
1122 for (i = 0; i < possible_cpus->len; i++) {
1123 cpu = cpu_create(machine->cpu_type);
1124 cpu->cpu_index = i;
Philippe Mathieu-Daudé97e03102024-01-29 17:44:44 +01001125 machine->possible_cpus->cpus[i].cpu = cpu;
Bibo Mao14f21f62023-08-24 08:50:07 +08001126 lacpu = LOONGARCH_CPU(cpu);
1127 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001128 }
Bibo Maod804ad92024-05-08 11:11:07 +08001129 fdt_add_cpu_nodes(lvms);
Bibo Mao09ec6572024-05-15 17:39:23 +08001130 fdt_add_memory_nodes(machine);
Bibo Mao3cc451c2024-05-15 17:39:24 +08001131 fw_cfg_add_memory(machine);
Tianrui Zhao0cf14782023-05-18 14:58:15 +08001132
1133 /* Node0 memory */
Bibo Mao8d967882024-05-15 17:39:25 +08001134 size = ram_size;
1135 base = VIRT_LOWMEM_BASE;
1136 if (size > VIRT_LOWMEM_SIZE) {
1137 size = VIRT_LOWMEM_SIZE;
Tianrui Zhao0cf14782023-05-18 14:58:15 +08001138 }
Tianrui Zhao0cf14782023-05-18 14:58:15 +08001139
Bibo Mao8d967882024-05-15 17:39:25 +08001140 memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.lowram",
1141 machine->ram, base, size);
1142 memory_region_add_subregion(address_space_mem, base, &lvms->lowmem);
1143 base += size;
1144 if (ram_size - size) {
1145 base = VIRT_HIGHMEM_BASE;
1146 memory_region_init_alias(&lvms->highmem, NULL, "loongarch.highram",
1147 machine->ram, VIRT_LOWMEM_BASE + size, ram_size - size);
1148 memory_region_add_subregion(address_space_mem, base, &lvms->highmem);
1149 base += ram_size - size;
Tianrui Zhao0cf14782023-05-18 14:58:15 +08001150 }
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001151
1152 /* initialize device memory address space */
1153 if (machine->ram_size < machine->maxram_size) {
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001154 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1155
1156 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1157 error_report("unsupported amount of memory slots: %"PRIu64,
1158 machine->ram_slots);
1159 exit(EXIT_FAILURE);
1160 }
1161
1162 if (QEMU_ALIGN_UP(machine->maxram_size,
1163 TARGET_PAGE_SIZE) != machine->maxram_size) {
1164 error_report("maximum memory size must by aligned to multiple of "
1165 "%d bytes", TARGET_PAGE_SIZE);
1166 exit(EXIT_FAILURE);
1167 }
Bibo Mao8d967882024-05-15 17:39:25 +08001168 machine_memory_devices_init(machine, base, device_mem_size);
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001169 }
1170
Xiaojuan Yang98afb0d2022-07-12 16:32:02 +08001171 /* load the BIOS image. */
Bibo Maod804ad92024-05-08 11:11:07 +08001172 virt_firmware_init(lvms);
Xiaojuan Yang98afb0d2022-07-12 16:32:02 +08001173
Xiaojuan Yang27ad7562022-07-12 16:32:01 +08001174 /* fw_cfg init */
Bibo Maod804ad92024-05-08 11:11:07 +08001175 lvms->fw_cfg = virt_fw_cfg_init(ram_size, machine);
1176 rom_set_fw(lvms->fw_cfg);
1177 if (lvms->fw_cfg != NULL) {
1178 fw_cfg_add_file(lvms->fw_cfg, "etc/memmap",
Xiaojuan Yang27ad7562022-07-12 16:32:01 +08001179 memmap_table,
1180 sizeof(struct memmap_entry) * (memmap_entries));
1181 }
Bibo Maod804ad92024-05-08 11:11:07 +08001182 fdt_add_fw_cfg_node(lvms);
1183 fdt_add_flash_node(lvms);
Song Gaod771ca12024-04-26 17:15:35 +08001184
Xiaojuan Yang69d9c742022-06-06 20:43:25 +08001185 /* Initialize the IO interrupt subsystem */
Bibo Maod804ad92024-05-08 11:11:07 +08001186 virt_irq_init(lvms);
Song Gao22126fd2024-04-26 17:15:49 +08001187 platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
Xiaojuan Yanga1f7d782022-08-10 15:50:35 +08001188 VIRT_PLATFORM_BUS_BASEADDRESS,
1189 VIRT_PLATFORM_BUS_SIZE,
1190 VIRT_PLATFORM_BUS_IRQ);
Bibo Maod804ad92024-05-08 11:11:07 +08001191 lvms->machine_done.notify = virt_done;
1192 qemu_add_machine_init_done_notifier(&lvms->machine_done);
Song Gao0d588c42023-01-10 11:29:16 +08001193 /* connect powerdown request */
Bibo Maod804ad92024-05-08 11:11:07 +08001194 lvms->powerdown_notifier.notify = virt_powerdown_req;
1195 qemu_register_powerdown_notifier(&lvms->powerdown_notifier);
Song Gao0d588c42023-01-10 11:29:16 +08001196
Xiaojuan Yang02183692022-10-28 09:40:05 +08001197 /*
Song Gao46b21de2022-11-09 10:04:49 +08001198 * Since lowmem region starts from 0 and Linux kernel legacy start address
1199 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
1200 * access. FDT size limit with 1 MiB.
Xiaojuan Yang02183692022-10-28 09:40:05 +08001201 * Put the FDT into the memory map as a ROM image: this will ensure
1202 * the FDT is copied again upon reset, even if addr points into RAM.
1203 */
Bibo Maod804ad92024-05-08 11:11:07 +08001204 qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size);
1205 rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE,
Song Gaod771ca12024-04-26 17:15:35 +08001206 &address_space_memory);
1207 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
Bibo Maod804ad92024-05-08 11:11:07 +08001208 rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size));
Song Gaod771ca12024-04-26 17:15:35 +08001209
Bibo Maod804ad92024-05-08 11:11:07 +08001210 lvms->bootinfo.ram_size = ram_size;
1211 loongarch_load_kernel(machine, &lvms->bootinfo);
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001212}
1213
Bibo Maod804ad92024-05-08 11:11:07 +08001214static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
1215 void *opaque, Error **errp)
Xiaojuan Yang735143f2022-07-12 16:32:05 +08001216{
Bibo Maod804ad92024-05-08 11:11:07 +08001217 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj);
1218 OnOffAuto acpi = lvms->acpi;
Xiaojuan Yang735143f2022-07-12 16:32:05 +08001219
1220 visit_type_OnOffAuto(v, name, &acpi, errp);
1221}
1222
Bibo Maod804ad92024-05-08 11:11:07 +08001223static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
Xiaojuan Yang735143f2022-07-12 16:32:05 +08001224 void *opaque, Error **errp)
1225{
Bibo Maod804ad92024-05-08 11:11:07 +08001226 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj);
Xiaojuan Yang735143f2022-07-12 16:32:05 +08001227
Bibo Maod804ad92024-05-08 11:11:07 +08001228 visit_type_OnOffAuto(v, name, &lvms->acpi, errp);
Xiaojuan Yang735143f2022-07-12 16:32:05 +08001229}
1230
Bibo Maod804ad92024-05-08 11:11:07 +08001231static void virt_initfn(Object *obj)
Xiaojuan Yang735143f2022-07-12 16:32:05 +08001232{
Bibo Maod804ad92024-05-08 11:11:07 +08001233 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj);
Xiaojuan Yang735143f2022-07-12 16:32:05 +08001234
Song Gao2b284fa2024-05-28 16:38:55 +08001235 if (tcg_enabled()) {
1236 lvms->veiointc = ON_OFF_AUTO_OFF;
1237 }
Bibo Maod804ad92024-05-08 11:11:07 +08001238 lvms->acpi = ON_OFF_AUTO_AUTO;
1239 lvms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
1240 lvms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
1241 virt_flash_create(lvms);
Xiaojuan Yang735143f2022-07-12 16:32:05 +08001242}
1243
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001244static bool memhp_type_supported(DeviceState *dev)
1245{
1246 /* we only support pc dimm now */
1247 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
1248 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1249}
1250
1251static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1252 Error **errp)
1253{
Philippe Mathieu-Daudéd4fdb052024-02-28 10:26:33 +01001254 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001255}
1256
Bibo Maod804ad92024-05-08 11:11:07 +08001257static void virt_device_pre_plug(HotplugHandler *hotplug_dev,
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001258 DeviceState *dev, Error **errp)
1259{
1260 if (memhp_type_supported(dev)) {
1261 virt_mem_pre_plug(hotplug_dev, dev, errp);
1262 }
1263}
1264
1265static void virt_mem_unplug_request(HotplugHandler *hotplug_dev,
1266 DeviceState *dev, Error **errp)
1267{
Bibo Maod804ad92024-05-08 11:11:07 +08001268 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev);
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001269
1270 /* the acpi ged is always exist */
Bibo Maod804ad92024-05-08 11:11:07 +08001271 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lvms->acpi_ged), dev,
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001272 errp);
1273}
1274
Bibo Maod804ad92024-05-08 11:11:07 +08001275static void virt_device_unplug_request(HotplugHandler *hotplug_dev,
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001276 DeviceState *dev, Error **errp)
1277{
1278 if (memhp_type_supported(dev)) {
1279 virt_mem_unplug_request(hotplug_dev, dev, errp);
1280 }
1281}
1282
1283static void virt_mem_unplug(HotplugHandler *hotplug_dev,
1284 DeviceState *dev, Error **errp)
1285{
Bibo Maod804ad92024-05-08 11:11:07 +08001286 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev);
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001287
Bibo Maod804ad92024-05-08 11:11:07 +08001288 hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->acpi_ged), dev, errp);
1289 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lvms));
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001290 qdev_unrealize(dev);
1291}
1292
Bibo Maod804ad92024-05-08 11:11:07 +08001293static void virt_device_unplug(HotplugHandler *hotplug_dev,
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001294 DeviceState *dev, Error **errp)
1295{
1296 if (memhp_type_supported(dev)) {
1297 virt_mem_unplug(hotplug_dev, dev, errp);
1298 }
1299}
1300
1301static void virt_mem_plug(HotplugHandler *hotplug_dev,
1302 DeviceState *dev, Error **errp)
1303{
Bibo Maod804ad92024-05-08 11:11:07 +08001304 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev);
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001305
Bibo Maod804ad92024-05-08 11:11:07 +08001306 pc_dimm_plug(PC_DIMM(dev), MACHINE(lvms));
1307 hotplug_handler_plug(HOTPLUG_HANDLER(lvms->acpi_ged),
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001308 dev, &error_abort);
1309}
1310
Bibo Maod804ad92024-05-08 11:11:07 +08001311static void virt_device_plug_cb(HotplugHandler *hotplug_dev,
Xiaojuan Yange27e5352022-08-10 16:37:21 +08001312 DeviceState *dev, Error **errp)
1313{
Bibo Maod804ad92024-05-08 11:11:07 +08001314 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev);
1315 MachineClass *mc = MACHINE_GET_CLASS(lvms);
1316 PlatformBusDevice *pbus;
Xiaojuan Yange27e5352022-08-10 16:37:21 +08001317
1318 if (device_is_dynamic_sysbus(mc, dev)) {
Bibo Maod804ad92024-05-08 11:11:07 +08001319 if (lvms->platform_bus_dev) {
1320 pbus = PLATFORM_BUS_DEVICE(lvms->platform_bus_dev);
1321 platform_bus_link_device(pbus, SYS_BUS_DEVICE(dev));
Xiaojuan Yange27e5352022-08-10 16:37:21 +08001322 }
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001323 } else if (memhp_type_supported(dev)) {
1324 virt_mem_plug(hotplug_dev, dev, errp);
Xiaojuan Yange27e5352022-08-10 16:37:21 +08001325 }
1326}
1327
Bibo Maod804ad92024-05-08 11:11:07 +08001328static HotplugHandler *virt_get_hotplug_handler(MachineState *machine,
1329 DeviceState *dev)
Xiaojuan Yange27e5352022-08-10 16:37:21 +08001330{
1331 MachineClass *mc = MACHINE_GET_CLASS(machine);
1332
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001333 if (device_is_dynamic_sysbus(mc, dev) ||
Bibo Maofe43cc52024-05-28 16:20:53 +08001334 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
Xiaojuan Yangc3da26f2022-08-25 11:36:59 +08001335 memhp_type_supported(dev)) {
Xiaojuan Yange27e5352022-08-10 16:37:21 +08001336 return HOTPLUG_HANDLER(machine);
1337 }
1338 return NULL;
1339}
1340
Tianrui Zhao8f307712023-05-16 16:27:57 +08001341static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
1342{
1343 int n;
1344 unsigned int max_cpus = ms->smp.max_cpus;
1345
1346 if (ms->possible_cpus) {
1347 assert(ms->possible_cpus->len == max_cpus);
1348 return ms->possible_cpus;
1349 }
1350
1351 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1352 sizeof(CPUArchId) * max_cpus);
1353 ms->possible_cpus->len = max_cpus;
1354 for (n = 0; n < ms->possible_cpus->len; n++) {
1355 ms->possible_cpus->cpus[n].type = ms->cpu_type;
1356 ms->possible_cpus->cpus[n].arch_id = n;
Tianrui Zhaof3323882023-06-13 19:37:36 +08001357
1358 ms->possible_cpus->cpus[n].props.has_socket_id = true;
1359 ms->possible_cpus->cpus[n].props.socket_id =
1360 n / (ms->smp.cores * ms->smp.threads);
Tianrui Zhao8f307712023-05-16 16:27:57 +08001361 ms->possible_cpus->cpus[n].props.has_core_id = true;
Tianrui Zhaof3323882023-06-13 19:37:36 +08001362 ms->possible_cpus->cpus[n].props.core_id =
1363 n / ms->smp.threads % ms->smp.cores;
1364 ms->possible_cpus->cpus[n].props.has_thread_id = true;
1365 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads;
Tianrui Zhao8f307712023-05-16 16:27:57 +08001366 }
1367 return ms->possible_cpus;
1368}
1369
Bibo Maod804ad92024-05-08 11:11:07 +08001370static CpuInstanceProperties virt_cpu_index_to_props(MachineState *ms,
1371 unsigned cpu_index)
Tianrui Zhao0cf14782023-05-18 14:58:15 +08001372{
1373 MachineClass *mc = MACHINE_GET_CLASS(ms);
1374 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1375
1376 assert(cpu_index < possible_cpus->len);
1377 return possible_cpus->cpus[cpu_index].props;
1378}
1379
1380static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
1381{
Bibo Maof532cf02024-03-19 10:26:06 +08001382 int64_t socket_id;
Tianrui Zhao0cf14782023-05-18 14:58:15 +08001383
1384 if (ms->numa_state->num_nodes) {
Bibo Maof532cf02024-03-19 10:26:06 +08001385 socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
1386 return socket_id % ms->numa_state->num_nodes;
1387 } else {
1388 return 0;
Tianrui Zhao0cf14782023-05-18 14:58:15 +08001389 }
Tianrui Zhao0cf14782023-05-18 14:58:15 +08001390}
1391
Bibo Maod804ad92024-05-08 11:11:07 +08001392static void virt_class_init(ObjectClass *oc, void *data)
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001393{
1394 MachineClass *mc = MACHINE_CLASS(oc);
Xiaojuan Yange27e5352022-08-10 16:37:21 +08001395 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001396
Bibo Maod804ad92024-05-08 11:11:07 +08001397 mc->init = virt_init;
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001398 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
1399 mc->default_ram_id = "loongarch.ram";
Song Gao646c39b2023-04-06 15:25:28 +08001400 mc->max_cpus = LOONGARCH_MAX_CPUS;
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001401 mc->is_default = 1;
1402 mc->default_kernel_irqchip_split = false;
1403 mc->block_default_type = IF_VIRTIO;
1404 mc->default_boot_order = "c";
1405 mc->no_cdrom = 1;
Tianrui Zhao8f307712023-05-16 16:27:57 +08001406 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
Tianrui Zhao0cf14782023-05-18 14:58:15 +08001407 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
1408 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
1409 mc->numa_mem_supported = true;
1410 mc->auto_enable_numa_with_memhp = true;
1411 mc->auto_enable_numa_with_memdev = true;
Bibo Maod804ad92024-05-08 11:11:07 +08001412 mc->get_hotplug_handler = virt_get_hotplug_handler;
Thomas Huth240294c2023-05-23 13:04:34 +02001413 mc->default_nic = "virtio-net-pci";
Bibo Maod804ad92024-05-08 11:11:07 +08001414 hc->plug = virt_device_plug_cb;
1415 hc->pre_plug = virt_device_pre_plug;
1416 hc->unplug_request = virt_device_unplug_request;
1417 hc->unplug = virt_device_unplug;
Xiaojuan Yang735143f2022-07-12 16:32:05 +08001418
1419 object_class_property_add(oc, "acpi", "OnOffAuto",
Bibo Maod804ad92024-05-08 11:11:07 +08001420 virt_get_acpi, virt_set_acpi,
Xiaojuan Yang735143f2022-07-12 16:32:05 +08001421 NULL, NULL);
1422 object_class_property_set_description(oc, "acpi",
1423 "Enable ACPI");
Song Gao2b284fa2024-05-28 16:38:55 +08001424 object_class_property_add(oc, "v-eiointc", "OnOffAuto",
1425 virt_get_veiointc, virt_set_veiointc,
1426 NULL, NULL);
1427 object_class_property_set_description(oc, "v-eiointc",
1428 "Enable Virt Extend I/O Interrupt Controller.");
Xiaojuan Yangf8ab9aa2022-08-10 16:41:52 +08001429 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
Xiaojuan Yang3dfbb6d2022-10-28 09:40:07 +08001430#ifdef CONFIG_TPM
1431 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
1432#endif
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001433}
1434
Bibo Maod804ad92024-05-08 11:11:07 +08001435static const TypeInfo virt_machine_types[] = {
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001436 {
Bibo Maodf0d93c2024-05-08 11:11:06 +08001437 .name = TYPE_LOONGARCH_VIRT_MACHINE,
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001438 .parent = TYPE_MACHINE,
Bibo Maod804ad92024-05-08 11:11:07 +08001439 .instance_size = sizeof(LoongArchVirtMachineState),
1440 .class_init = virt_class_init,
1441 .instance_init = virt_initfn,
Xiaojuan Yange27e5352022-08-10 16:37:21 +08001442 .interfaces = (InterfaceInfo[]) {
1443 { TYPE_HOTPLUG_HANDLER },
1444 { }
1445 },
Xiaojuan Yanga8a506c2022-06-06 20:43:20 +08001446 }
1447};
1448
Bibo Maod804ad92024-05-08 11:11:07 +08001449DEFINE_TYPES(virt_machine_types)