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ths5fafdf22007-09-16 21:08:06 +00001/*
pbrook20dcee92007-06-03 11:13:39 +00002 * ColdFire Interrupt Controller emulation.
3 *
4 * Copyright (c) 2007 CodeSourcery.
5 *
Matthew Fernandez8e31bf32011-06-26 12:21:35 +10006 * This code is licensed under the GPL
pbrook20dcee92007-06-03 11:13:39 +00007 */
Peter Maydelld8416662016-01-26 18:17:23 +00008#include "qemu/osdep.h"
Paolo Bonzini4771d752016-01-19 21:51:44 +01009#include "qemu-common.h"
10#include "cpu.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010011#include "hw/hw.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010012#include "hw/m68k/mcf.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010013#include "exec/address-spaces.h"
pbrook20dcee92007-06-03 11:13:39 +000014
15typedef struct {
Benoît Canet663d9442011-11-24 14:31:15 +010016 MemoryRegion iomem;
pbrook20dcee92007-06-03 11:13:39 +000017 uint64_t ipr;
18 uint64_t imr;
19 uint64_t ifr;
20 uint64_t enabled;
21 uint8_t icr[64];
Andreas Färber9a6ee9f2013-01-18 14:15:09 +010022 M68kCPU *cpu;
pbrook20dcee92007-06-03 11:13:39 +000023 int active_vector;
24} mcf_intc_state;
25
26static void mcf_intc_update(mcf_intc_state *s)
27{
28 uint64_t active;
29 int i;
30 int best;
31 int best_level;
32
33 active = (s->ipr | s->ifr) & s->enabled & ~s->imr;
34 best_level = 0;
35 best = 64;
36 if (active) {
37 for (i = 0; i < 64; i++) {
38 if ((active & 1) != 0 && s->icr[i] >= best_level) {
39 best_level = s->icr[i];
40 best = i;
41 }
42 active >>= 1;
43 }
44 }
45 s->active_vector = ((best == 64) ? 24 : (best + 64));
Andreas Färbercb3fb382013-01-18 14:20:52 +010046 m68k_set_irq_level(s->cpu, best_level, s->active_vector);
pbrook20dcee92007-06-03 11:13:39 +000047}
48
Avi Kivitya8170e52012-10-23 12:30:10 +020049static uint64_t mcf_intc_read(void *opaque, hwaddr addr,
Benoît Canet663d9442011-11-24 14:31:15 +010050 unsigned size)
pbrook20dcee92007-06-03 11:13:39 +000051{
52 int offset;
53 mcf_intc_state *s = (mcf_intc_state *)opaque;
54 offset = addr & 0xff;
55 if (offset >= 0x40 && offset < 0x80) {
56 return s->icr[offset - 0x40];
57 }
58 switch (offset) {
59 case 0x00:
60 return (uint32_t)(s->ipr >> 32);
61 case 0x04:
62 return (uint32_t)s->ipr;
63 case 0x08:
64 return (uint32_t)(s->imr >> 32);
65 case 0x0c:
66 return (uint32_t)s->imr;
67 case 0x10:
68 return (uint32_t)(s->ifr >> 32);
69 case 0x14:
70 return (uint32_t)s->ifr;
71 case 0xe0: /* SWIACK. */
72 return s->active_vector;
73 case 0xe1: case 0xe2: case 0xe3: case 0xe4:
74 case 0xe5: case 0xe6: case 0xe7:
75 /* LnIACK */
Paul Brook2ac71172009-05-08 02:35:15 +010076 hw_error("mcf_intc_read: LnIACK not implemented\n");
pbrook20dcee92007-06-03 11:13:39 +000077 default:
78 return 0;
79 }
80}
81
Avi Kivitya8170e52012-10-23 12:30:10 +020082static void mcf_intc_write(void *opaque, hwaddr addr,
Benoît Canet663d9442011-11-24 14:31:15 +010083 uint64_t val, unsigned size)
pbrook20dcee92007-06-03 11:13:39 +000084{
85 int offset;
86 mcf_intc_state *s = (mcf_intc_state *)opaque;
87 offset = addr & 0xff;
88 if (offset >= 0x40 && offset < 0x80) {
89 int n = offset - 0x40;
90 s->icr[n] = val;
91 if (val == 0)
92 s->enabled &= ~(1ull << n);
93 else
94 s->enabled |= (1ull << n);
95 mcf_intc_update(s);
96 return;
97 }
98 switch (offset) {
99 case 0x00: case 0x04:
100 /* Ignore IPR writes. */
101 return;
102 case 0x08:
103 s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32);
104 break;
105 case 0x0c:
106 s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
107 break;
Greg Ungerer8c52f0c2015-06-19 23:43:24 +1000108 case 0x1c:
109 if (val & 0x40) {
110 s->imr = ~0ull;
111 } else {
112 s->imr |= (0x1ull << (val & 0x3f));
113 }
114 break;
115 case 0x1d:
116 if (val & 0x40) {
117 s->imr = 0ull;
118 } else {
119 s->imr &= ~(0x1ull << (val & 0x3f));
120 }
121 break;
pbrook20dcee92007-06-03 11:13:39 +0000122 default:
Paul Brook2ac71172009-05-08 02:35:15 +0100123 hw_error("mcf_intc_write: Bad write offset %d\n", offset);
pbrook20dcee92007-06-03 11:13:39 +0000124 break;
125 }
126 mcf_intc_update(s);
127}
128
129static void mcf_intc_set_irq(void *opaque, int irq, int level)
130{
131 mcf_intc_state *s = (mcf_intc_state *)opaque;
132 if (irq >= 64)
133 return;
134 if (level)
135 s->ipr |= 1ull << irq;
136 else
137 s->ipr &= ~(1ull << irq);
138 mcf_intc_update(s);
139}
140
141static void mcf_intc_reset(mcf_intc_state *s)
142{
143 s->imr = ~0ull;
144 s->ipr = 0;
145 s->ifr = 0;
146 s->enabled = 0;
147 memset(s->icr, 0, 64);
148 s->active_vector = 24;
149}
150
Benoît Canet663d9442011-11-24 14:31:15 +0100151static const MemoryRegionOps mcf_intc_ops = {
152 .read = mcf_intc_read,
153 .write = mcf_intc_write,
154 .endianness = DEVICE_NATIVE_ENDIAN,
pbrook20dcee92007-06-03 11:13:39 +0000155};
156
Benoît Canet663d9442011-11-24 14:31:15 +0100157qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
Avi Kivitya8170e52012-10-23 12:30:10 +0200158 hwaddr base,
Andreas Färber9a6ee9f2013-01-18 14:15:09 +0100159 M68kCPU *cpu)
pbrook20dcee92007-06-03 11:13:39 +0000160{
161 mcf_intc_state *s;
pbrook20dcee92007-06-03 11:13:39 +0000162
Anthony Liguori7267c092011-08-20 22:09:37 -0500163 s = g_malloc0(sizeof(mcf_intc_state));
Andreas Färber9a6ee9f2013-01-18 14:15:09 +0100164 s->cpu = cpu;
pbrook20dcee92007-06-03 11:13:39 +0000165 mcf_intc_reset(s);
166
Paolo Bonzini2c9b15c2013-06-06 05:41:28 -0400167 memory_region_init_io(&s->iomem, NULL, &mcf_intc_ops, s, "mcf", 0x100);
Benoît Canet663d9442011-11-24 14:31:15 +0100168 memory_region_add_subregion(sysmem, base, &s->iomem);
pbrook20dcee92007-06-03 11:13:39 +0000169
170 return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
171}