blob: 58e7341cb7841e4cfadc70d8a7604214f337ac0f [file] [log] [blame]
Bharata B Rao3b542542016-06-10 06:29:01 +05301/*
2 * sPAPR CPU core device, acts as container of CPU thread devices.
3 *
4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
Markus Armbruster71e8a912019-08-12 07:23:38 +02009
Philippe Mathieu-Daudée9808d02017-10-17 13:43:53 -030010#include "qemu/osdep.h"
Bharata B Rao3b542542016-06-10 06:29:01 +053011#include "hw/cpu/core.h"
12#include "hw/ppc/spapr_cpu_core.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020013#include "hw/qdev-properties.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020014#include "migration/vmstate.h"
Thomas Huthfcf5ef22016-10-11 08:56:52 +020015#include "target/ppc/cpu.h"
Bharata B Rao3b542542016-06-10 06:29:01 +053016#include "hw/ppc/spapr.h"
Bharata B Rao3b542542016-06-10 06:29:01 +053017#include "qapi/error.h"
Markus Armbrustera9c94272016-06-22 19:11:19 +020018#include "sysemu/cpus.h"
David Gibsone57ca752017-02-23 11:39:18 +110019#include "sysemu/kvm.h"
Thomas Huthfcf5ef22016-10-11 08:56:52 +020020#include "target/ppc/kvm_ppc.h"
Bharata B Raoafd10a02016-06-10 06:29:02 +053021#include "hw/ppc/ppc.h"
Thomas Huthfcf5ef22016-10-11 08:56:52 +020022#include "target/ppc/mmu-hash64.h"
Markus Armbrustera9c94272016-06-22 19:11:19 +020023#include "sysemu/numa.h"
Markus Armbruster71e8a912019-08-12 07:23:38 +020024#include "sysemu/reset.h"
Greg Kurz1ec26c72017-09-25 13:00:02 +020025#include "sysemu/hw_accel.h"
David Gibsone57ca752017-02-23 11:39:18 +110026#include "qemu/error-report.h"
Bharata B Raoafd10a02016-06-10 06:29:02 +053027
Greg Kurzd1f2b462019-10-22 18:38:07 +020028static void spapr_reset_vcpu(PowerPCCPU *cpu)
Bharata B Raoafd10a02016-06-10 06:29:02 +053029{
Bharata B Raoafd10a02016-06-10 06:29:02 +053030 CPUState *cs = CPU(cpu);
31 CPUPPCState *env = &cpu->env;
Cédric Le Goaterd6322252017-11-24 08:05:49 +010032 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
David Gibsonce2918c2019-03-06 15:35:37 +110033 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
David Gibsonda20aed2018-04-05 16:02:51 +100034 target_ulong lpcr;
Cédric Le Goaterd49e8a92019-10-22 18:38:10 +020035 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
Bharata B Raoafd10a02016-06-10 06:29:02 +053036
37 cpu_reset(cs);
38
Bharata B Raoafd10a02016-06-10 06:29:02 +053039 env->spr[SPR_HIOR] = 0;
Cédric Le Goaterd6322252017-11-24 08:05:49 +010040
David Gibsonda20aed2018-04-05 16:02:51 +100041 lpcr = env->spr[SPR_LPCR];
42
43 /* Set emulated LPCR to not send interrupts to hypervisor. Note that
44 * under KVM, the actual HW LPCR will be set differently by KVM itself,
45 * the settings below ensure proper operations with TCG in absence of
46 * a real hypervisor.
47 *
David Gibson47a9b552018-04-05 16:27:18 +100048 * Disable Power-saving mode Exit Cause exceptions for the CPU, so
49 * we don't get spurious wakups before an RTAS start-cpu call.
Suraj Jitindar Singh70de0962019-05-16 10:57:44 +100050 * For the same reason, set PSSCR_EC.
David Gibsonda20aed2018-04-05 16:02:51 +100051 */
David Gibsone8b11442020-01-06 13:12:34 +110052 lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
David Gibsonda20aed2018-04-05 16:02:51 +100053 lpcr |= LPCR_LPES0 | LPCR_LPES1;
Suraj Jitindar Singh70de0962019-05-16 10:57:44 +100054 env->spr[SPR_PSSCR] |= PSSCR_EC;
David Gibsonda20aed2018-04-05 16:02:51 +100055
David Gibsonda20aed2018-04-05 16:02:51 +100056 ppc_store_lpcr(cpu, lpcr);
57
58 /* Set a full AMOR so guest can use the AMR as it sees fit */
59 env->spr[SPR_AMOR] = 0xffffffffffffffffull;
David Gibson7388efa2018-06-13 16:22:18 +100060
61 spapr_cpu->vpa_addr = 0;
62 spapr_cpu->slb_shadow_addr = 0;
63 spapr_cpu->slb_shadow_size = 0;
64 spapr_cpu->dtl_addr = 0;
65 spapr_cpu->dtl_size = 0;
David Gibsone2e4f642018-03-28 14:45:44 +110066
Cédric Le Goaterd49e8a92019-10-22 18:38:10 +020067 spapr_caps_cpu_apply(spapr, cpu);
David Gibsone5ca28e2018-04-16 16:19:52 +100068
69 kvm_check_mmu(cpu, &error_fatal);
Cédric Le Goaterd49e8a92019-10-22 18:38:10 +020070
71 spapr_irq_cpu_intc_reset(spapr, cpu);
Bharata B Raoafd10a02016-06-10 06:29:02 +053072}
73
Alexey Kardashevskiy395a20d2020-03-10 16:07:31 +110074void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
75 target_ulong r1, target_ulong r3,
76 target_ulong r4)
David Gibson84369f62018-05-01 16:22:49 +100077{
David Gibson47a9b552018-04-05 16:27:18 +100078 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
David Gibson84369f62018-05-01 16:22:49 +100079 CPUPPCState *env = &cpu->env;
80
81 env->nip = nip;
Alexey Kardashevskiy395a20d2020-03-10 16:07:31 +110082 env->gpr[1] = r1;
David Gibson84369f62018-05-01 16:22:49 +100083 env->gpr[3] = r3;
Alexey Kardashevskiy395a20d2020-03-10 16:07:31 +110084 env->gpr[4] = r4;
Nikunj A Dadhaniaa84f7172018-09-04 14:54:18 +053085 kvmppc_set_reg_ppc_online(cpu, 1);
David Gibson84369f62018-05-01 16:22:49 +100086 CPU(cpu)->halted = 0;
David Gibson47a9b552018-04-05 16:27:18 +100087 /* Enable Power-saving mode Exit Cause exceptions */
88 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
David Gibson84369f62018-05-01 16:22:49 +100089}
90
Bharata B Rao94a94e42016-06-10 06:29:03 +053091/*
92 * Return the sPAPR CPU core type for @model which essentially is the CPU
93 * model specified with -cpu cmdline option.
94 */
Igor Mammedov2e9c10e2017-10-09 21:51:05 +020095const char *spapr_get_cpu_core_type(const char *cpu_type)
Bharata B Rao94a94e42016-06-10 06:29:03 +053096{
Igor Mammedov2e9c10e2017-10-09 21:51:05 +020097 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
98 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
99 len, cpu_type);
100 ObjectClass *oc = object_class_by_name(core_type);
Bharata B Rao94a94e42016-06-10 06:29:03 +0530101
Igor Mammedov2e9c10e2017-10-09 21:51:05 +0200102 g_free(core_type);
103 if (!oc) {
104 return NULL;
Thomas Huth4babfaf2016-08-09 18:59:59 +0200105 }
106
Igor Mammedov2e9c10e2017-10-09 21:51:05 +0200107 return object_class_get_name(oc);
Bharata B Rao94a94e42016-06-10 06:29:03 +0530108}
109
Greg Kurz7f9fe3f2018-06-18 14:26:49 +0200110static bool slb_shadow_needed(void *opaque)
111{
David Gibsonce2918c2019-03-06 15:35:37 +1100112 SpaprCpuState *spapr_cpu = opaque;
Greg Kurz7f9fe3f2018-06-18 14:26:49 +0200113
114 return spapr_cpu->slb_shadow_addr != 0;
115}
116
117static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
118 .name = "spapr_cpu/vpa/slb_shadow",
119 .version_id = 1,
120 .minimum_version_id = 1,
121 .needed = slb_shadow_needed,
122 .fields = (VMStateField[]) {
David Gibsonce2918c2019-03-06 15:35:37 +1100123 VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
124 VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
Greg Kurz7f9fe3f2018-06-18 14:26:49 +0200125 VMSTATE_END_OF_LIST()
126 }
127};
128
129static bool dtl_needed(void *opaque)
130{
David Gibsonce2918c2019-03-06 15:35:37 +1100131 SpaprCpuState *spapr_cpu = opaque;
Greg Kurz7f9fe3f2018-06-18 14:26:49 +0200132
133 return spapr_cpu->dtl_addr != 0;
134}
135
136static const VMStateDescription vmstate_spapr_cpu_dtl = {
137 .name = "spapr_cpu/vpa/dtl",
138 .version_id = 1,
139 .minimum_version_id = 1,
140 .needed = dtl_needed,
141 .fields = (VMStateField[]) {
David Gibsonce2918c2019-03-06 15:35:37 +1100142 VMSTATE_UINT64(dtl_addr, SpaprCpuState),
143 VMSTATE_UINT64(dtl_size, SpaprCpuState),
Greg Kurz7f9fe3f2018-06-18 14:26:49 +0200144 VMSTATE_END_OF_LIST()
145 }
146};
147
148static bool vpa_needed(void *opaque)
149{
David Gibsonce2918c2019-03-06 15:35:37 +1100150 SpaprCpuState *spapr_cpu = opaque;
Greg Kurz7f9fe3f2018-06-18 14:26:49 +0200151
152 return spapr_cpu->vpa_addr != 0;
153}
154
155static const VMStateDescription vmstate_spapr_cpu_vpa = {
156 .name = "spapr_cpu/vpa",
157 .version_id = 1,
158 .minimum_version_id = 1,
159 .needed = vpa_needed,
160 .fields = (VMStateField[]) {
David Gibsonce2918c2019-03-06 15:35:37 +1100161 VMSTATE_UINT64(vpa_addr, SpaprCpuState),
Greg Kurz7f9fe3f2018-06-18 14:26:49 +0200162 VMSTATE_END_OF_LIST()
163 },
164 .subsections = (const VMStateDescription * []) {
165 &vmstate_spapr_cpu_slb_shadow,
166 &vmstate_spapr_cpu_dtl,
167 NULL
168 }
169};
170
Greg Kurzb9402022018-06-18 14:26:35 +0200171static const VMStateDescription vmstate_spapr_cpu_state = {
172 .name = "spapr_cpu",
173 .version_id = 1,
174 .minimum_version_id = 1,
175 .fields = (VMStateField[]) {
176 VMSTATE_END_OF_LIST()
177 },
Greg Kurz7f9fe3f2018-06-18 14:26:49 +0200178 .subsections = (const VMStateDescription * []) {
179 &vmstate_spapr_cpu_vpa,
180 NULL
181 }
Greg Kurzb9402022018-06-18 14:26:35 +0200182};
183
David Gibsonce2918c2019-03-06 15:35:37 +1100184static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
Bharata B Raocc71c772018-08-08 21:29:19 +0530185{
186 if (!sc->pre_3_0_migration) {
187 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
188 }
Greg Kurz0990ce62019-10-24 16:27:22 +0200189 spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu);
Greg Kurzf1023d22020-10-15 23:18:32 +0200190 qdev_unrealize(DEVICE(cpu));
Bharata B Raocc71c772018-08-08 21:29:19 +0530191}
192
Greg Kurzd1f2b462019-10-22 18:38:07 +0200193/*
194 * Called when CPUs are hot-plugged.
195 */
196static void spapr_cpu_core_reset(DeviceState *dev)
197{
198 CPUCore *cc = CPU_CORE(dev);
199 SpaprCpuCore *sc = SPAPR_CPU_CORE(dev);
200 int i;
201
202 for (i = 0; i < cc->nr_threads; i++) {
203 spapr_reset_vcpu(sc->threads[i]);
204 }
205}
206
207/*
208 * Called by the machine reset.
209 */
210static void spapr_cpu_core_reset_handler(void *opaque)
211{
212 spapr_cpu_core_reset(opaque);
213}
214
Greg Kurz96598cd2020-10-15 23:18:39 +0200215static void spapr_delete_vcpu(PowerPCCPU *cpu)
Greg Kurz90689a32020-10-15 23:18:25 +0200216{
217 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
218
219 cpu->machine_data = NULL;
220 g_free(spapr_cpu);
221 object_unparent(OBJECT(cpu));
222}
223
Markus Armbrusterb69c3c22020-05-05 17:29:24 +0200224static void spapr_cpu_core_unrealize(DeviceState *dev)
Bharata B Raocc71c772018-08-08 21:29:19 +0530225{
David Gibsonce2918c2019-03-06 15:35:37 +1100226 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
Bharata B Raocc71c772018-08-08 21:29:19 +0530227 CPUCore *cc = CPU_CORE(dev);
228 int i;
229
230 for (i = 0; i < cc->nr_threads; i++) {
Greg Kurz9370c282020-10-15 23:18:46 +0200231 if (sc->threads[i]) {
232 /*
233 * Since this we can get here from the error path of
234 * spapr_cpu_core_realize(), make sure we only unrealize
235 * vCPUs that have already been realized.
236 */
237 if (object_property_get_bool(OBJECT(sc->threads[i]), "realized",
238 &error_abort)) {
239 spapr_unrealize_vcpu(sc->threads[i], sc);
240 }
Greg Kurz9370c282020-10-15 23:18:46 +0200241 spapr_delete_vcpu(sc->threads[i]);
242 }
Greg Kurz90689a32020-10-15 23:18:25 +0200243 }
Bharata B Raocc71c772018-08-08 21:29:19 +0530244 g_free(sc->threads);
Greg Kurz9370c282020-10-15 23:18:46 +0200245 qemu_unregister_reset(spapr_cpu_core_reset_handler, sc);
Bharata B Raocc71c772018-08-08 21:29:19 +0530246}
247
Greg Kurza5af92e2020-09-14 14:35:01 +0200248static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
David Gibsonce2918c2019-03-06 15:35:37 +1100249 SpaprCpuCore *sc, Error **errp)
Bharata B Rao3b542542016-06-10 06:29:01 +0530250{
David Gibsonb1d40d62018-06-13 11:48:26 +1000251 CPUPPCState *env = &cpu->env;
Bharata B Raocc71c772018-08-08 21:29:19 +0530252 CPUState *cs = CPU(cpu);
Bharata B Rao3b542542016-06-10 06:29:01 +0530253
Markus Armbruster992861f2020-07-07 18:06:04 +0200254 if (!qdev_realize(DEVICE(cpu), NULL, errp)) {
Greg Kurza5af92e2020-09-14 14:35:01 +0200255 return false;
Bharata B Rao3b542542016-06-10 06:29:01 +0530256 }
257
David Gibsonb1d40d62018-06-13 11:48:26 +1000258 /* Set time-base frequency to 512 MHz */
259 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
Cédric Le Goater5bc8d262017-04-03 09:45:58 +0200260
David Gibsonb1d40d62018-06-13 11:48:26 +1000261 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
262 kvmppc_set_papr(cpu);
263
Greg Kurz9c4d1492020-09-14 14:34:51 +0200264 if (spapr_irq_cpu_intc_create(spapr, cpu, errp) < 0) {
Greg Kurzf1023d22020-10-15 23:18:32 +0200265 qdev_unrealize(DEVICE(cpu));
Greg Kurza5af92e2020-09-14 14:35:01 +0200266 return false;
Cédric Le Goater90f8db52019-10-22 18:38:06 +0200267 }
268
Bharata B Raocc71c772018-08-08 21:29:19 +0530269 if (!sc->pre_3_0_migration) {
270 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
271 cpu->machine_data);
272 }
Greg Kurza5af92e2020-09-14 14:35:01 +0200273 return true;
Bharata B Rao3b542542016-06-10 06:29:01 +0530274}
275
David Gibsonce2918c2019-03-06 15:35:37 +1100276static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
Greg Kurzd9f0e342018-06-14 23:50:57 +0200277{
David Gibsonce2918c2019-03-06 15:35:37 +1100278 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
Greg Kurzd9f0e342018-06-14 23:50:57 +0200279 CPUCore *cc = CPU_CORE(sc);
Daniel Henrique Barboza2a053502021-01-14 15:06:26 -0300280 g_autoptr(Object) obj = NULL;
281 g_autofree char *id = NULL;
Greg Kurzd9f0e342018-06-14 23:50:57 +0200282 CPUState *cs;
283 PowerPCCPU *cpu;
Greg Kurzd9f0e342018-06-14 23:50:57 +0200284
285 obj = object_new(scc->cpu_type);
286
287 cs = CPU(obj);
288 cpu = POWERPC_CPU(obj);
Thiago Jung Bauermann554c2162020-08-26 02:55:30 -0300289 /*
290 * All CPUs start halted. CPU0 is unhalted from the machine level reset code
291 * and the rest are explicitly started up by the guest using an RTAS call.
292 */
293 cs->start_powered_off = true;
Greg Kurzd9f0e342018-06-14 23:50:57 +0200294 cs->cpu_index = cc->core_id + i;
Greg Kurzcfdc5272020-09-14 14:35:00 +0200295 if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) {
Daniel Henrique Barboza2a053502021-01-14 15:06:26 -0300296 return NULL;
Greg Kurzd9f0e342018-06-14 23:50:57 +0200297 }
298
299 cpu->node_id = sc->node_id;
300
301 id = g_strdup_printf("thread[%d]", i);
Markus Armbrusterd2623122020-05-05 17:29:22 +0200302 object_property_add_child(OBJECT(sc), id, obj);
Greg Kurzd9f0e342018-06-14 23:50:57 +0200303
David Gibsonce2918c2019-03-06 15:35:37 +1100304 cpu->machine_data = g_new0(SpaprCpuState, 1);
David Gibson7388efa2018-06-13 16:22:18 +1000305
Greg Kurzd9f0e342018-06-14 23:50:57 +0200306 return cpu;
Greg Kurzd9f0e342018-06-14 23:50:57 +0200307}
308
Bharata B Rao3b542542016-06-10 06:29:01 +0530309static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
310{
Greg Kurze7cca3e2017-10-12 18:30:23 +0200311 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
312 * tries to add a sPAPR CPU core to a non-pseries machine.
313 */
David Gibsonce2918c2019-03-06 15:35:37 +1100314 SpaprMachineState *spapr =
315 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
Greg Kurze7cca3e2017-10-12 18:30:23 +0200316 TYPE_SPAPR_MACHINE);
David Gibsonce2918c2019-03-06 15:35:37 +1100317 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
Bharata B Rao3b542542016-06-10 06:29:01 +0530318 CPUCore *cc = CPU_CORE(OBJECT(dev));
Greg Kurz3cff86f2020-10-15 23:18:53 +0200319 int i;
Bharata B Rao3b542542016-06-10 06:29:01 +0530320
Greg Kurze7cca3e2017-10-12 18:30:23 +0200321 if (!spapr) {
322 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
Thomas Huth2363d5e2017-08-24 05:52:32 +0200323 return;
324 }
325
Greg Kurz9370c282020-10-15 23:18:46 +0200326 qemu_register_reset(spapr_cpu_core_reset_handler, sc);
327 sc->threads = g_new0(PowerPCCPU *, cc->nr_threads);
Bharata B Rao3b542542016-06-10 06:29:01 +0530328 for (i = 0; i < cc->nr_threads; i++) {
Greg Kurza5af92e2020-09-14 14:35:01 +0200329 sc->threads[i] = spapr_create_vcpu(sc, i, errp);
Greg Kurz3cff86f2020-10-15 23:18:53 +0200330 if (!sc->threads[i] ||
331 !spapr_realize_vcpu(sc->threads[i], spapr, sc, errp)) {
Greg Kurz9370c282020-10-15 23:18:46 +0200332 spapr_cpu_core_unrealize(dev);
333 return;
Bharata B Rao70936452016-07-01 10:44:39 +0530334 }
Bharata B Rao3b542542016-06-10 06:29:01 +0530335 }
Bharata B Rao3b542542016-06-10 06:29:01 +0530336}
337
Igor Mammedov0b8497f2017-05-10 13:29:46 +0200338static Property spapr_cpu_core_properties[] = {
David Gibsonce2918c2019-03-06 15:35:37 +1100339 DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
340 DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
Greg Kurzb9402022018-06-18 14:26:35 +0200341 false),
Igor Mammedov0b8497f2017-05-10 13:29:46 +0200342 DEFINE_PROP_END_OF_LIST()
343};
344
Igor Mammedov5bbb2642017-10-09 21:51:02 +0200345static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
Bharata B Rao3b542542016-06-10 06:29:01 +0530346{
Bharata B Rao7ebaf792016-09-12 13:27:20 +0530347 DeviceClass *dc = DEVICE_CLASS(oc);
David Gibsonce2918c2019-03-06 15:35:37 +1100348 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
Bharata B Rao3b542542016-06-10 06:29:01 +0530349
Bharata B Rao7ebaf792016-09-12 13:27:20 +0530350 dc->realize = spapr_cpu_core_realize;
David Gibsonb1d40d62018-06-13 11:48:26 +1000351 dc->unrealize = spapr_cpu_core_unrealize;
Greg Kurzd1f2b462019-10-22 18:38:07 +0200352 dc->reset = spapr_cpu_core_reset;
Marc-André Lureau4f67d302020-01-10 19:30:32 +0400353 device_class_set_props(dc, spapr_cpu_core_properties);
Igor Mammedovb51d3c82017-10-09 21:51:01 +0200354 scc->cpu_type = data;
Bharata B Rao3b542542016-06-10 06:29:01 +0530355}
356
Igor Mammedov44cd95e2017-10-09 21:51:00 +0200357#define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
358 { \
359 .parent = TYPE_SPAPR_CPU_CORE, \
Igor Mammedovb51d3c82017-10-09 21:51:01 +0200360 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
Igor Mammedov44cd95e2017-10-09 21:51:00 +0200361 .class_init = spapr_cpu_core_class_init, \
362 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \
363 }
364
365static const TypeInfo spapr_cpu_core_type_infos[] = {
366 {
367 .name = TYPE_SPAPR_CPU_CORE,
368 .parent = TYPE_CPU_CORE,
369 .abstract = true,
David Gibsonce2918c2019-03-06 15:35:37 +1100370 .instance_size = sizeof(SpaprCpuCore),
371 .class_size = sizeof(SpaprCpuCoreClass),
Igor Mammedov44cd95e2017-10-09 21:51:00 +0200372 },
373 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
374 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
375 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
376 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
377 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
378 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
379 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
380 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
381 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
382 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
383 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
Cédric Le Goater0bbf14a2020-05-07 09:38:55 +0200384 DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"),
Cédric Le Goater3ad21112021-09-01 11:41:47 +0200385 DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
Igor Mammedov5bbb2642017-10-09 21:51:02 +0200386#ifdef CONFIG_KVM
387 DEFINE_SPAPR_CPU_CORE_TYPE("host"),
388#endif
Bharata B Rao3b542542016-06-10 06:29:01 +0530389};
390
Igor Mammedov44cd95e2017-10-09 21:51:00 +0200391DEFINE_TYPES(spapr_cpu_core_type_infos)