Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 1 | /* |
| 2 | * sPAPR CPU core device, acts as container of CPU thread devices. |
| 3 | * |
| 4 | * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> |
| 5 | * |
| 6 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 7 | * See the COPYING file in the top-level directory. |
| 8 | */ |
Markus Armbruster | 71e8a91 | 2019-08-12 07:23:38 +0200 | [diff] [blame] | 9 | |
Philippe Mathieu-Daudé | e9808d0 | 2017-10-17 13:43:53 -0300 | [diff] [blame] | 10 | #include "qemu/osdep.h" |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 11 | #include "hw/cpu/core.h" |
| 12 | #include "hw/ppc/spapr_cpu_core.h" |
Markus Armbruster | a27bd6c | 2019-08-12 07:23:51 +0200 | [diff] [blame] | 13 | #include "hw/qdev-properties.h" |
Markus Armbruster | d645427 | 2019-08-12 07:23:45 +0200 | [diff] [blame] | 14 | #include "migration/vmstate.h" |
Thomas Huth | fcf5ef2 | 2016-10-11 08:56:52 +0200 | [diff] [blame] | 15 | #include "target/ppc/cpu.h" |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 16 | #include "hw/ppc/spapr.h" |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 17 | #include "qapi/error.h" |
Markus Armbruster | a9c9427 | 2016-06-22 19:11:19 +0200 | [diff] [blame] | 18 | #include "sysemu/cpus.h" |
David Gibson | e57ca75 | 2017-02-23 11:39:18 +1100 | [diff] [blame] | 19 | #include "sysemu/kvm.h" |
Thomas Huth | fcf5ef2 | 2016-10-11 08:56:52 +0200 | [diff] [blame] | 20 | #include "target/ppc/kvm_ppc.h" |
Bharata B Rao | afd10a0 | 2016-06-10 06:29:02 +0530 | [diff] [blame] | 21 | #include "hw/ppc/ppc.h" |
Thomas Huth | fcf5ef2 | 2016-10-11 08:56:52 +0200 | [diff] [blame] | 22 | #include "target/ppc/mmu-hash64.h" |
Markus Armbruster | a9c9427 | 2016-06-22 19:11:19 +0200 | [diff] [blame] | 23 | #include "sysemu/numa.h" |
Markus Armbruster | 71e8a91 | 2019-08-12 07:23:38 +0200 | [diff] [blame] | 24 | #include "sysemu/reset.h" |
Greg Kurz | 1ec26c7 | 2017-09-25 13:00:02 +0200 | [diff] [blame] | 25 | #include "sysemu/hw_accel.h" |
David Gibson | e57ca75 | 2017-02-23 11:39:18 +1100 | [diff] [blame] | 26 | #include "qemu/error-report.h" |
Bharata B Rao | afd10a0 | 2016-06-10 06:29:02 +0530 | [diff] [blame] | 27 | |
Greg Kurz | d1f2b46 | 2019-10-22 18:38:07 +0200 | [diff] [blame] | 28 | static void spapr_reset_vcpu(PowerPCCPU *cpu) |
Bharata B Rao | afd10a0 | 2016-06-10 06:29:02 +0530 | [diff] [blame] | 29 | { |
Bharata B Rao | afd10a0 | 2016-06-10 06:29:02 +0530 | [diff] [blame] | 30 | CPUState *cs = CPU(cpu); |
| 31 | CPUPPCState *env = &cpu->env; |
Cédric Le Goater | d632225 | 2017-11-24 08:05:49 +0100 | [diff] [blame] | 32 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 33 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
David Gibson | da20aed | 2018-04-05 16:02:51 +1000 | [diff] [blame] | 34 | target_ulong lpcr; |
Cédric Le Goater | d49e8a9 | 2019-10-22 18:38:10 +0200 | [diff] [blame] | 35 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
Bharata B Rao | afd10a0 | 2016-06-10 06:29:02 +0530 | [diff] [blame] | 36 | |
| 37 | cpu_reset(cs); |
| 38 | |
Bharata B Rao | afd10a0 | 2016-06-10 06:29:02 +0530 | [diff] [blame] | 39 | env->spr[SPR_HIOR] = 0; |
Cédric Le Goater | d632225 | 2017-11-24 08:05:49 +0100 | [diff] [blame] | 40 | |
David Gibson | da20aed | 2018-04-05 16:02:51 +1000 | [diff] [blame] | 41 | lpcr = env->spr[SPR_LPCR]; |
| 42 | |
| 43 | /* Set emulated LPCR to not send interrupts to hypervisor. Note that |
| 44 | * under KVM, the actual HW LPCR will be set differently by KVM itself, |
| 45 | * the settings below ensure proper operations with TCG in absence of |
| 46 | * a real hypervisor. |
| 47 | * |
David Gibson | 47a9b55 | 2018-04-05 16:27:18 +1000 | [diff] [blame] | 48 | * Disable Power-saving mode Exit Cause exceptions for the CPU, so |
| 49 | * we don't get spurious wakups before an RTAS start-cpu call. |
Suraj Jitindar Singh | 70de096 | 2019-05-16 10:57:44 +1000 | [diff] [blame] | 50 | * For the same reason, set PSSCR_EC. |
David Gibson | da20aed | 2018-04-05 16:02:51 +1000 | [diff] [blame] | 51 | */ |
David Gibson | e8b1144 | 2020-01-06 13:12:34 +1100 | [diff] [blame] | 52 | lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); |
David Gibson | da20aed | 2018-04-05 16:02:51 +1000 | [diff] [blame] | 53 | lpcr |= LPCR_LPES0 | LPCR_LPES1; |
Suraj Jitindar Singh | 70de096 | 2019-05-16 10:57:44 +1000 | [diff] [blame] | 54 | env->spr[SPR_PSSCR] |= PSSCR_EC; |
David Gibson | da20aed | 2018-04-05 16:02:51 +1000 | [diff] [blame] | 55 | |
David Gibson | da20aed | 2018-04-05 16:02:51 +1000 | [diff] [blame] | 56 | ppc_store_lpcr(cpu, lpcr); |
| 57 | |
| 58 | /* Set a full AMOR so guest can use the AMR as it sees fit */ |
| 59 | env->spr[SPR_AMOR] = 0xffffffffffffffffull; |
David Gibson | 7388efa | 2018-06-13 16:22:18 +1000 | [diff] [blame] | 60 | |
| 61 | spapr_cpu->vpa_addr = 0; |
| 62 | spapr_cpu->slb_shadow_addr = 0; |
| 63 | spapr_cpu->slb_shadow_size = 0; |
| 64 | spapr_cpu->dtl_addr = 0; |
| 65 | spapr_cpu->dtl_size = 0; |
David Gibson | e2e4f64 | 2018-03-28 14:45:44 +1100 | [diff] [blame] | 66 | |
Cédric Le Goater | d49e8a9 | 2019-10-22 18:38:10 +0200 | [diff] [blame] | 67 | spapr_caps_cpu_apply(spapr, cpu); |
David Gibson | e5ca28e | 2018-04-16 16:19:52 +1000 | [diff] [blame] | 68 | |
| 69 | kvm_check_mmu(cpu, &error_fatal); |
Cédric Le Goater | d49e8a9 | 2019-10-22 18:38:10 +0200 | [diff] [blame] | 70 | |
| 71 | spapr_irq_cpu_intc_reset(spapr, cpu); |
Bharata B Rao | afd10a0 | 2016-06-10 06:29:02 +0530 | [diff] [blame] | 72 | } |
| 73 | |
Alexey Kardashevskiy | 395a20d | 2020-03-10 16:07:31 +1100 | [diff] [blame] | 74 | void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, |
| 75 | target_ulong r1, target_ulong r3, |
| 76 | target_ulong r4) |
David Gibson | 84369f6 | 2018-05-01 16:22:49 +1000 | [diff] [blame] | 77 | { |
David Gibson | 47a9b55 | 2018-04-05 16:27:18 +1000 | [diff] [blame] | 78 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
David Gibson | 84369f6 | 2018-05-01 16:22:49 +1000 | [diff] [blame] | 79 | CPUPPCState *env = &cpu->env; |
| 80 | |
| 81 | env->nip = nip; |
Alexey Kardashevskiy | 395a20d | 2020-03-10 16:07:31 +1100 | [diff] [blame] | 82 | env->gpr[1] = r1; |
David Gibson | 84369f6 | 2018-05-01 16:22:49 +1000 | [diff] [blame] | 83 | env->gpr[3] = r3; |
Alexey Kardashevskiy | 395a20d | 2020-03-10 16:07:31 +1100 | [diff] [blame] | 84 | env->gpr[4] = r4; |
Nikunj A Dadhania | a84f717 | 2018-09-04 14:54:18 +0530 | [diff] [blame] | 85 | kvmppc_set_reg_ppc_online(cpu, 1); |
David Gibson | 84369f6 | 2018-05-01 16:22:49 +1000 | [diff] [blame] | 86 | CPU(cpu)->halted = 0; |
David Gibson | 47a9b55 | 2018-04-05 16:27:18 +1000 | [diff] [blame] | 87 | /* Enable Power-saving mode Exit Cause exceptions */ |
| 88 | ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); |
David Gibson | 84369f6 | 2018-05-01 16:22:49 +1000 | [diff] [blame] | 89 | } |
| 90 | |
Bharata B Rao | 94a94e4 | 2016-06-10 06:29:03 +0530 | [diff] [blame] | 91 | /* |
| 92 | * Return the sPAPR CPU core type for @model which essentially is the CPU |
| 93 | * model specified with -cpu cmdline option. |
| 94 | */ |
Igor Mammedov | 2e9c10e | 2017-10-09 21:51:05 +0200 | [diff] [blame] | 95 | const char *spapr_get_cpu_core_type(const char *cpu_type) |
Bharata B Rao | 94a94e4 | 2016-06-10 06:29:03 +0530 | [diff] [blame] | 96 | { |
Igor Mammedov | 2e9c10e | 2017-10-09 21:51:05 +0200 | [diff] [blame] | 97 | int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); |
| 98 | char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), |
| 99 | len, cpu_type); |
| 100 | ObjectClass *oc = object_class_by_name(core_type); |
Bharata B Rao | 94a94e4 | 2016-06-10 06:29:03 +0530 | [diff] [blame] | 101 | |
Igor Mammedov | 2e9c10e | 2017-10-09 21:51:05 +0200 | [diff] [blame] | 102 | g_free(core_type); |
| 103 | if (!oc) { |
| 104 | return NULL; |
Thomas Huth | 4babfaf | 2016-08-09 18:59:59 +0200 | [diff] [blame] | 105 | } |
| 106 | |
Igor Mammedov | 2e9c10e | 2017-10-09 21:51:05 +0200 | [diff] [blame] | 107 | return object_class_get_name(oc); |
Bharata B Rao | 94a94e4 | 2016-06-10 06:29:03 +0530 | [diff] [blame] | 108 | } |
| 109 | |
Greg Kurz | 7f9fe3f | 2018-06-18 14:26:49 +0200 | [diff] [blame] | 110 | static bool slb_shadow_needed(void *opaque) |
| 111 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 112 | SpaprCpuState *spapr_cpu = opaque; |
Greg Kurz | 7f9fe3f | 2018-06-18 14:26:49 +0200 | [diff] [blame] | 113 | |
| 114 | return spapr_cpu->slb_shadow_addr != 0; |
| 115 | } |
| 116 | |
| 117 | static const VMStateDescription vmstate_spapr_cpu_slb_shadow = { |
| 118 | .name = "spapr_cpu/vpa/slb_shadow", |
| 119 | .version_id = 1, |
| 120 | .minimum_version_id = 1, |
| 121 | .needed = slb_shadow_needed, |
| 122 | .fields = (VMStateField[]) { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 123 | VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState), |
| 124 | VMSTATE_UINT64(slb_shadow_size, SpaprCpuState), |
Greg Kurz | 7f9fe3f | 2018-06-18 14:26:49 +0200 | [diff] [blame] | 125 | VMSTATE_END_OF_LIST() |
| 126 | } |
| 127 | }; |
| 128 | |
| 129 | static bool dtl_needed(void *opaque) |
| 130 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 131 | SpaprCpuState *spapr_cpu = opaque; |
Greg Kurz | 7f9fe3f | 2018-06-18 14:26:49 +0200 | [diff] [blame] | 132 | |
| 133 | return spapr_cpu->dtl_addr != 0; |
| 134 | } |
| 135 | |
| 136 | static const VMStateDescription vmstate_spapr_cpu_dtl = { |
| 137 | .name = "spapr_cpu/vpa/dtl", |
| 138 | .version_id = 1, |
| 139 | .minimum_version_id = 1, |
| 140 | .needed = dtl_needed, |
| 141 | .fields = (VMStateField[]) { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 142 | VMSTATE_UINT64(dtl_addr, SpaprCpuState), |
| 143 | VMSTATE_UINT64(dtl_size, SpaprCpuState), |
Greg Kurz | 7f9fe3f | 2018-06-18 14:26:49 +0200 | [diff] [blame] | 144 | VMSTATE_END_OF_LIST() |
| 145 | } |
| 146 | }; |
| 147 | |
| 148 | static bool vpa_needed(void *opaque) |
| 149 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 150 | SpaprCpuState *spapr_cpu = opaque; |
Greg Kurz | 7f9fe3f | 2018-06-18 14:26:49 +0200 | [diff] [blame] | 151 | |
| 152 | return spapr_cpu->vpa_addr != 0; |
| 153 | } |
| 154 | |
| 155 | static const VMStateDescription vmstate_spapr_cpu_vpa = { |
| 156 | .name = "spapr_cpu/vpa", |
| 157 | .version_id = 1, |
| 158 | .minimum_version_id = 1, |
| 159 | .needed = vpa_needed, |
| 160 | .fields = (VMStateField[]) { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 161 | VMSTATE_UINT64(vpa_addr, SpaprCpuState), |
Greg Kurz | 7f9fe3f | 2018-06-18 14:26:49 +0200 | [diff] [blame] | 162 | VMSTATE_END_OF_LIST() |
| 163 | }, |
| 164 | .subsections = (const VMStateDescription * []) { |
| 165 | &vmstate_spapr_cpu_slb_shadow, |
| 166 | &vmstate_spapr_cpu_dtl, |
| 167 | NULL |
| 168 | } |
| 169 | }; |
| 170 | |
Greg Kurz | b940202 | 2018-06-18 14:26:35 +0200 | [diff] [blame] | 171 | static const VMStateDescription vmstate_spapr_cpu_state = { |
| 172 | .name = "spapr_cpu", |
| 173 | .version_id = 1, |
| 174 | .minimum_version_id = 1, |
| 175 | .fields = (VMStateField[]) { |
| 176 | VMSTATE_END_OF_LIST() |
| 177 | }, |
Greg Kurz | 7f9fe3f | 2018-06-18 14:26:49 +0200 | [diff] [blame] | 178 | .subsections = (const VMStateDescription * []) { |
| 179 | &vmstate_spapr_cpu_vpa, |
| 180 | NULL |
| 181 | } |
Greg Kurz | b940202 | 2018-06-18 14:26:35 +0200 | [diff] [blame] | 182 | }; |
| 183 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 184 | static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) |
Bharata B Rao | cc71c77 | 2018-08-08 21:29:19 +0530 | [diff] [blame] | 185 | { |
| 186 | if (!sc->pre_3_0_migration) { |
| 187 | vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); |
| 188 | } |
Greg Kurz | 0990ce6 | 2019-10-24 16:27:22 +0200 | [diff] [blame] | 189 | spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu); |
Greg Kurz | f1023d2 | 2020-10-15 23:18:32 +0200 | [diff] [blame] | 190 | qdev_unrealize(DEVICE(cpu)); |
Bharata B Rao | cc71c77 | 2018-08-08 21:29:19 +0530 | [diff] [blame] | 191 | } |
| 192 | |
Greg Kurz | d1f2b46 | 2019-10-22 18:38:07 +0200 | [diff] [blame] | 193 | /* |
| 194 | * Called when CPUs are hot-plugged. |
| 195 | */ |
| 196 | static void spapr_cpu_core_reset(DeviceState *dev) |
| 197 | { |
| 198 | CPUCore *cc = CPU_CORE(dev); |
| 199 | SpaprCpuCore *sc = SPAPR_CPU_CORE(dev); |
| 200 | int i; |
| 201 | |
| 202 | for (i = 0; i < cc->nr_threads; i++) { |
| 203 | spapr_reset_vcpu(sc->threads[i]); |
| 204 | } |
| 205 | } |
| 206 | |
| 207 | /* |
| 208 | * Called by the machine reset. |
| 209 | */ |
| 210 | static void spapr_cpu_core_reset_handler(void *opaque) |
| 211 | { |
| 212 | spapr_cpu_core_reset(opaque); |
| 213 | } |
| 214 | |
Greg Kurz | 96598cd | 2020-10-15 23:18:39 +0200 | [diff] [blame] | 215 | static void spapr_delete_vcpu(PowerPCCPU *cpu) |
Greg Kurz | 90689a3 | 2020-10-15 23:18:25 +0200 | [diff] [blame] | 216 | { |
| 217 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
| 218 | |
| 219 | cpu->machine_data = NULL; |
| 220 | g_free(spapr_cpu); |
| 221 | object_unparent(OBJECT(cpu)); |
| 222 | } |
| 223 | |
Markus Armbruster | b69c3c2 | 2020-05-05 17:29:24 +0200 | [diff] [blame] | 224 | static void spapr_cpu_core_unrealize(DeviceState *dev) |
Bharata B Rao | cc71c77 | 2018-08-08 21:29:19 +0530 | [diff] [blame] | 225 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 226 | SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); |
Bharata B Rao | cc71c77 | 2018-08-08 21:29:19 +0530 | [diff] [blame] | 227 | CPUCore *cc = CPU_CORE(dev); |
| 228 | int i; |
| 229 | |
| 230 | for (i = 0; i < cc->nr_threads; i++) { |
Greg Kurz | 9370c28 | 2020-10-15 23:18:46 +0200 | [diff] [blame] | 231 | if (sc->threads[i]) { |
| 232 | /* |
| 233 | * Since this we can get here from the error path of |
| 234 | * spapr_cpu_core_realize(), make sure we only unrealize |
| 235 | * vCPUs that have already been realized. |
| 236 | */ |
| 237 | if (object_property_get_bool(OBJECT(sc->threads[i]), "realized", |
| 238 | &error_abort)) { |
| 239 | spapr_unrealize_vcpu(sc->threads[i], sc); |
| 240 | } |
Greg Kurz | 9370c28 | 2020-10-15 23:18:46 +0200 | [diff] [blame] | 241 | spapr_delete_vcpu(sc->threads[i]); |
| 242 | } |
Greg Kurz | 90689a3 | 2020-10-15 23:18:25 +0200 | [diff] [blame] | 243 | } |
Bharata B Rao | cc71c77 | 2018-08-08 21:29:19 +0530 | [diff] [blame] | 244 | g_free(sc->threads); |
Greg Kurz | 9370c28 | 2020-10-15 23:18:46 +0200 | [diff] [blame] | 245 | qemu_unregister_reset(spapr_cpu_core_reset_handler, sc); |
Bharata B Rao | cc71c77 | 2018-08-08 21:29:19 +0530 | [diff] [blame] | 246 | } |
| 247 | |
Greg Kurz | a5af92e | 2020-09-14 14:35:01 +0200 | [diff] [blame] | 248 | static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 249 | SpaprCpuCore *sc, Error **errp) |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 250 | { |
David Gibson | b1d40d6 | 2018-06-13 11:48:26 +1000 | [diff] [blame] | 251 | CPUPPCState *env = &cpu->env; |
Bharata B Rao | cc71c77 | 2018-08-08 21:29:19 +0530 | [diff] [blame] | 252 | CPUState *cs = CPU(cpu); |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 253 | |
Markus Armbruster | 992861f | 2020-07-07 18:06:04 +0200 | [diff] [blame] | 254 | if (!qdev_realize(DEVICE(cpu), NULL, errp)) { |
Greg Kurz | a5af92e | 2020-09-14 14:35:01 +0200 | [diff] [blame] | 255 | return false; |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 256 | } |
| 257 | |
David Gibson | b1d40d6 | 2018-06-13 11:48:26 +1000 | [diff] [blame] | 258 | /* Set time-base frequency to 512 MHz */ |
| 259 | cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); |
Cédric Le Goater | 5bc8d26 | 2017-04-03 09:45:58 +0200 | [diff] [blame] | 260 | |
David Gibson | b1d40d6 | 2018-06-13 11:48:26 +1000 | [diff] [blame] | 261 | cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); |
| 262 | kvmppc_set_papr(cpu); |
| 263 | |
Greg Kurz | 9c4d149 | 2020-09-14 14:34:51 +0200 | [diff] [blame] | 264 | if (spapr_irq_cpu_intc_create(spapr, cpu, errp) < 0) { |
Greg Kurz | f1023d2 | 2020-10-15 23:18:32 +0200 | [diff] [blame] | 265 | qdev_unrealize(DEVICE(cpu)); |
Greg Kurz | a5af92e | 2020-09-14 14:35:01 +0200 | [diff] [blame] | 266 | return false; |
Cédric Le Goater | 90f8db5 | 2019-10-22 18:38:06 +0200 | [diff] [blame] | 267 | } |
| 268 | |
Bharata B Rao | cc71c77 | 2018-08-08 21:29:19 +0530 | [diff] [blame] | 269 | if (!sc->pre_3_0_migration) { |
| 270 | vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, |
| 271 | cpu->machine_data); |
| 272 | } |
Greg Kurz | a5af92e | 2020-09-14 14:35:01 +0200 | [diff] [blame] | 273 | return true; |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 274 | } |
| 275 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 276 | static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp) |
Greg Kurz | d9f0e34 | 2018-06-14 23:50:57 +0200 | [diff] [blame] | 277 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 278 | SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc); |
Greg Kurz | d9f0e34 | 2018-06-14 23:50:57 +0200 | [diff] [blame] | 279 | CPUCore *cc = CPU_CORE(sc); |
Daniel Henrique Barboza | 2a05350 | 2021-01-14 15:06:26 -0300 | [diff] [blame] | 280 | g_autoptr(Object) obj = NULL; |
| 281 | g_autofree char *id = NULL; |
Greg Kurz | d9f0e34 | 2018-06-14 23:50:57 +0200 | [diff] [blame] | 282 | CPUState *cs; |
| 283 | PowerPCCPU *cpu; |
Greg Kurz | d9f0e34 | 2018-06-14 23:50:57 +0200 | [diff] [blame] | 284 | |
| 285 | obj = object_new(scc->cpu_type); |
| 286 | |
| 287 | cs = CPU(obj); |
| 288 | cpu = POWERPC_CPU(obj); |
Thiago Jung Bauermann | 554c216 | 2020-08-26 02:55:30 -0300 | [diff] [blame] | 289 | /* |
| 290 | * All CPUs start halted. CPU0 is unhalted from the machine level reset code |
| 291 | * and the rest are explicitly started up by the guest using an RTAS call. |
| 292 | */ |
| 293 | cs->start_powered_off = true; |
Greg Kurz | d9f0e34 | 2018-06-14 23:50:57 +0200 | [diff] [blame] | 294 | cs->cpu_index = cc->core_id + i; |
Greg Kurz | cfdc527 | 2020-09-14 14:35:00 +0200 | [diff] [blame] | 295 | if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) { |
Daniel Henrique Barboza | 2a05350 | 2021-01-14 15:06:26 -0300 | [diff] [blame] | 296 | return NULL; |
Greg Kurz | d9f0e34 | 2018-06-14 23:50:57 +0200 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | cpu->node_id = sc->node_id; |
| 300 | |
| 301 | id = g_strdup_printf("thread[%d]", i); |
Markus Armbruster | d262312 | 2020-05-05 17:29:22 +0200 | [diff] [blame] | 302 | object_property_add_child(OBJECT(sc), id, obj); |
Greg Kurz | d9f0e34 | 2018-06-14 23:50:57 +0200 | [diff] [blame] | 303 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 304 | cpu->machine_data = g_new0(SpaprCpuState, 1); |
David Gibson | 7388efa | 2018-06-13 16:22:18 +1000 | [diff] [blame] | 305 | |
Greg Kurz | d9f0e34 | 2018-06-14 23:50:57 +0200 | [diff] [blame] | 306 | return cpu; |
Greg Kurz | d9f0e34 | 2018-06-14 23:50:57 +0200 | [diff] [blame] | 307 | } |
| 308 | |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 309 | static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) |
| 310 | { |
Greg Kurz | e7cca3e | 2017-10-12 18:30:23 +0200 | [diff] [blame] | 311 | /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user |
| 312 | * tries to add a sPAPR CPU core to a non-pseries machine. |
| 313 | */ |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 314 | SpaprMachineState *spapr = |
| 315 | (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), |
Greg Kurz | e7cca3e | 2017-10-12 18:30:23 +0200 | [diff] [blame] | 316 | TYPE_SPAPR_MACHINE); |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 317 | SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 318 | CPUCore *cc = CPU_CORE(OBJECT(dev)); |
Greg Kurz | 3cff86f | 2020-10-15 23:18:53 +0200 | [diff] [blame] | 319 | int i; |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 320 | |
Greg Kurz | e7cca3e | 2017-10-12 18:30:23 +0200 | [diff] [blame] | 321 | if (!spapr) { |
| 322 | error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); |
Thomas Huth | 2363d5e | 2017-08-24 05:52:32 +0200 | [diff] [blame] | 323 | return; |
| 324 | } |
| 325 | |
Greg Kurz | 9370c28 | 2020-10-15 23:18:46 +0200 | [diff] [blame] | 326 | qemu_register_reset(spapr_cpu_core_reset_handler, sc); |
| 327 | sc->threads = g_new0(PowerPCCPU *, cc->nr_threads); |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 328 | for (i = 0; i < cc->nr_threads; i++) { |
Greg Kurz | a5af92e | 2020-09-14 14:35:01 +0200 | [diff] [blame] | 329 | sc->threads[i] = spapr_create_vcpu(sc, i, errp); |
Greg Kurz | 3cff86f | 2020-10-15 23:18:53 +0200 | [diff] [blame] | 330 | if (!sc->threads[i] || |
| 331 | !spapr_realize_vcpu(sc->threads[i], spapr, sc, errp)) { |
Greg Kurz | 9370c28 | 2020-10-15 23:18:46 +0200 | [diff] [blame] | 332 | spapr_cpu_core_unrealize(dev); |
| 333 | return; |
Bharata B Rao | 7093645 | 2016-07-01 10:44:39 +0530 | [diff] [blame] | 334 | } |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 335 | } |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 336 | } |
| 337 | |
Igor Mammedov | 0b8497f | 2017-05-10 13:29:46 +0200 | [diff] [blame] | 338 | static Property spapr_cpu_core_properties[] = { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 339 | DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID), |
| 340 | DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration, |
Greg Kurz | b940202 | 2018-06-18 14:26:35 +0200 | [diff] [blame] | 341 | false), |
Igor Mammedov | 0b8497f | 2017-05-10 13:29:46 +0200 | [diff] [blame] | 342 | DEFINE_PROP_END_OF_LIST() |
| 343 | }; |
| 344 | |
Igor Mammedov | 5bbb264 | 2017-10-09 21:51:02 +0200 | [diff] [blame] | 345 | static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 346 | { |
Bharata B Rao | 7ebaf79 | 2016-09-12 13:27:20 +0530 | [diff] [blame] | 347 | DeviceClass *dc = DEVICE_CLASS(oc); |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 348 | SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 349 | |
Bharata B Rao | 7ebaf79 | 2016-09-12 13:27:20 +0530 | [diff] [blame] | 350 | dc->realize = spapr_cpu_core_realize; |
David Gibson | b1d40d6 | 2018-06-13 11:48:26 +1000 | [diff] [blame] | 351 | dc->unrealize = spapr_cpu_core_unrealize; |
Greg Kurz | d1f2b46 | 2019-10-22 18:38:07 +0200 | [diff] [blame] | 352 | dc->reset = spapr_cpu_core_reset; |
Marc-André Lureau | 4f67d30 | 2020-01-10 19:30:32 +0400 | [diff] [blame] | 353 | device_class_set_props(dc, spapr_cpu_core_properties); |
Igor Mammedov | b51d3c8 | 2017-10-09 21:51:01 +0200 | [diff] [blame] | 354 | scc->cpu_type = data; |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 355 | } |
| 356 | |
Igor Mammedov | 44cd95e | 2017-10-09 21:51:00 +0200 | [diff] [blame] | 357 | #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ |
| 358 | { \ |
| 359 | .parent = TYPE_SPAPR_CPU_CORE, \ |
Igor Mammedov | b51d3c8 | 2017-10-09 21:51:01 +0200 | [diff] [blame] | 360 | .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ |
Igor Mammedov | 44cd95e | 2017-10-09 21:51:00 +0200 | [diff] [blame] | 361 | .class_init = spapr_cpu_core_class_init, \ |
| 362 | .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ |
| 363 | } |
| 364 | |
| 365 | static const TypeInfo spapr_cpu_core_type_infos[] = { |
| 366 | { |
| 367 | .name = TYPE_SPAPR_CPU_CORE, |
| 368 | .parent = TYPE_CPU_CORE, |
| 369 | .abstract = true, |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 370 | .instance_size = sizeof(SpaprCpuCore), |
| 371 | .class_size = sizeof(SpaprCpuCoreClass), |
Igor Mammedov | 44cd95e | 2017-10-09 21:51:00 +0200 | [diff] [blame] | 372 | }, |
| 373 | DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), |
| 374 | DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), |
| 375 | DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), |
| 376 | DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), |
| 377 | DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), |
| 378 | DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), |
| 379 | DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), |
| 380 | DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), |
| 381 | DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), |
| 382 | DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), |
| 383 | DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), |
Cédric Le Goater | 0bbf14a | 2020-05-07 09:38:55 +0200 | [diff] [blame] | 384 | DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"), |
Cédric Le Goater | 3ad2111 | 2021-09-01 11:41:47 +0200 | [diff] [blame] | 385 | DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), |
Igor Mammedov | 5bbb264 | 2017-10-09 21:51:02 +0200 | [diff] [blame] | 386 | #ifdef CONFIG_KVM |
| 387 | DEFINE_SPAPR_CPU_CORE_TYPE("host"), |
| 388 | #endif |
Bharata B Rao | 3b54254 | 2016-06-10 06:29:01 +0530 | [diff] [blame] | 389 | }; |
| 390 | |
Igor Mammedov | 44cd95e | 2017-10-09 21:51:00 +0200 | [diff] [blame] | 391 | DEFINE_TYPES(spapr_cpu_core_type_infos) |