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Peter Maydelldd750742021-02-19 14:46:16 +00001Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``)
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Peter Maydellba7912a2020-05-07 16:18:18 +01003
4These board models all use Arm M-profile CPUs.
5
Peter Maydellced8bb02021-02-15 11:51:37 +00006The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
7bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
8FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash).
9
10Since the CPU itself and most of the devices are in the FPGA, the
11details of the board as seen by the guest depend significantly on the
12FPGA image.
Peter Maydellba7912a2020-05-07 16:18:18 +010013
14QEMU models the following FPGA images:
15
16``mps2-an385``
Peter Maydell99dfb042020-09-03 21:20:48 +010017 Cortex-M3 as documented in Arm Application Note AN385
Peter Maydell897d2722020-09-03 21:20:46 +010018``mps2-an386``
Peter Maydell99dfb042020-09-03 21:20:48 +010019 Cortex-M4 as documented in Arm Application Note AN386
Peter Maydell6d4811c2020-09-03 21:20:47 +010020``mps2-an500``
Peter Maydell99dfb042020-09-03 21:20:48 +010021 Cortex-M7 as documented in Arm Application Note AN500
Peter Maydellba7912a2020-05-07 16:18:18 +010022``mps2-an505``
Peter Maydell99dfb042020-09-03 21:20:48 +010023 Cortex-M33 as documented in Arm Application Note AN505
24``mps2-an511``
25 Cortex-M3 'DesignStart' as documented in Arm Application Note AN511
Peter Maydellba7912a2020-05-07 16:18:18 +010026``mps2-an521``
Peter Maydell99dfb042020-09-03 21:20:48 +010027 Dual Cortex-M33 as documented in Arm Application Note AN521
Peter Maydellced8bb02021-02-15 11:51:37 +000028``mps3-an524``
29 Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524
Peter Maydelldd750742021-02-19 14:46:16 +000030``mps3-an547``
31 Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
Peter Maydellba7912a2020-05-07 16:18:18 +010032
33Differences between QEMU and real hardware:
34
Peter Maydell897d2722020-09-03 21:20:46 +010035- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
Peter Maydellba7912a2020-05-07 16:18:18 +010036 block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as
37 if zbt_boot_ctrl is always zero)
Peter Maydellced8bb02021-02-15 11:51:37 +000038- AN524 remapping of low memory to either BRAM or to QSPI flash is
39 unimplemented (QEMU always maps this to BRAM, ignoring the
40 SCC CFG_REG0 memory-remap bit)
Peter Maydellba7912a2020-05-07 16:18:18 +010041- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest
42 visible difference is that the LAN9118 doesn't support checksum
43 offloading
Peter Maydellced8bb02021-02-15 11:51:37 +000044- QEMU does not model the QSPI flash in MPS3 boards as real QSPI
45 flash, but only as simple ROM, so attempting to rewrite the flash
46 from the guest will fail
47- QEMU does not model the USB controller in MPS3 boards
Peter Maydellf1dfab02021-05-04 13:09:12 +010048
49Machine-specific options
50""""""""""""""""""""""""
51
52The following machine-specific options are supported:
53
54remap
55 Supported for ``mps3-an524`` only.
56 Set ``BRAM``/``QSPI`` to select the initial memory mapping. The
57 default is ``BRAM``.