bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1 | /* |
| 2 | * internal execution defines for qemu |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 18 | */ |
| 19 | |
aliguori | 875cdcf | 2008-10-23 13:52:00 +0000 | [diff] [blame] | 20 | #ifndef _EXEC_ALL_H_ |
| 21 | #define _EXEC_ALL_H_ |
blueswir1 | 7d99a00 | 2009-01-14 19:00:36 +0000 | [diff] [blame] | 22 | |
| 23 | #include "qemu-common.h" |
| 24 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 25 | /* allow to see translation results - the slowdown should be negligible, so we leave it */ |
aurel32 | de9a95f | 2008-11-11 13:41:01 +0000 | [diff] [blame] | 26 | #define DEBUG_DISAS |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 27 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 28 | /* Page tracking code uses ram addresses in system mode, and virtual |
| 29 | addresses in userspace mode. Define tb_page_addr_t to be an appropriate |
| 30 | type. */ |
| 31 | #if defined(CONFIG_USER_ONLY) |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 32 | typedef abi_ulong tb_page_addr_t; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 33 | #else |
| 34 | typedef ram_addr_t tb_page_addr_t; |
| 35 | #endif |
| 36 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 37 | /* is_jmp field values */ |
| 38 | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
| 39 | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
| 40 | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
| 41 | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
| 42 | |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 43 | struct TranslationBlock; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 44 | typedef struct TranslationBlock TranslationBlock; |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 45 | |
| 46 | /* XXX: make safe guess about sizes */ |
Peter Maydell | 5b620fb | 2011-06-22 15:16:32 +0100 | [diff] [blame] | 47 | #define MAX_OP_PER_INSTR 208 |
Stuart Brady | 4d0e4ac | 2010-04-27 22:23:35 +0100 | [diff] [blame] | 48 | |
| 49 | #if HOST_LONG_BITS == 32 |
| 50 | #define MAX_OPC_PARAM_PER_ARG 2 |
| 51 | #else |
| 52 | #define MAX_OPC_PARAM_PER_ARG 1 |
| 53 | #endif |
| 54 | #define MAX_OPC_PARAM_IARGS 4 |
| 55 | #define MAX_OPC_PARAM_OARGS 1 |
| 56 | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) |
| 57 | |
| 58 | /* A Call op needs up to 4 + 2N parameters on 32-bit archs, |
| 59 | * and up to 4 + N parameters on 64-bit archs |
| 60 | * (N = number of input arguments + output arguments). */ |
| 61 | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) |
Aurelien Jarno | 6db7350 | 2009-09-22 23:31:04 +0200 | [diff] [blame] | 62 | #define OPC_BUF_SIZE 640 |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 63 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) |
| 64 | |
pbrook | a208e54 | 2008-03-31 17:07:36 +0000 | [diff] [blame] | 65 | /* Maximum size a TCG op can expand to. This is complicated because a |
Aurelien Jarno | 0cbfcd2 | 2009-10-22 02:36:27 +0200 | [diff] [blame] | 66 | single op may require several host instructions and register reloads. |
| 67 | For now take a wild guess at 192 bytes, which should allow at least |
pbrook | a208e54 | 2008-03-31 17:07:36 +0000 | [diff] [blame] | 68 | a couple of fixup instructions per argument. */ |
Aurelien Jarno | 0cbfcd2 | 2009-10-22 02:36:27 +0200 | [diff] [blame] | 69 | #define TCG_MAX_OP_SIZE 192 |
pbrook | a208e54 | 2008-03-31 17:07:36 +0000 | [diff] [blame] | 70 | |
pbrook | 0115be3 | 2008-02-03 17:35:41 +0000 | [diff] [blame] | 71 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 72 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 73 | extern target_ulong gen_opc_pc[OPC_BUF_SIZE]; |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 74 | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 75 | extern uint16_t gen_opc_icount[OPC_BUF_SIZE]; |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 76 | |
blueswir1 | 79383c9 | 2008-08-30 09:51:20 +0000 | [diff] [blame] | 77 | #include "qemu-log.h" |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 78 | |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 79 | void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
| 80 | void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
Stefan Weil | e87b7cb | 2011-04-18 06:39:52 +0000 | [diff] [blame] | 81 | void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb, |
| 82 | int pc_pos); |
aurel32 | d2856f1 | 2008-04-28 00:32:32 +0000 | [diff] [blame] | 83 | |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 84 | void cpu_gen_init(void); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 85 | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
blueswir1 | d07bde8 | 2007-12-11 19:35:45 +0000 | [diff] [blame] | 86 | int *gen_code_size_ptr); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 87 | int cpu_restore_state(struct TranslationBlock *tb, |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 88 | CPUState *env, unsigned long searched_pc); |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 89 | void cpu_resume_from_signal(CPUState *env1, void *puc); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 90 | void cpu_io_recompile(CPUState *env, void *retaddr); |
| 91 | TranslationBlock *tb_gen_code(CPUState *env, |
| 92 | target_ulong pc, target_ulong cs_base, int flags, |
| 93 | int cflags); |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 94 | void cpu_exec_init(CPUState *env); |
Blue Swirl | 1162c04 | 2011-05-14 12:52:35 +0000 | [diff] [blame] | 95 | void QEMU_NORETURN cpu_loop_exit(CPUState *env1); |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 96 | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 97 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 98 | int is_cpu_write_access); |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 99 | void tlb_flush_page(CPUState *env, target_ulong addr); |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 100 | void tlb_flush(CPUState *env, int flush_global); |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 101 | #if !defined(CONFIG_USER_ONLY) |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 102 | void tlb_set_page(CPUState *env, target_ulong vaddr, |
| 103 | target_phys_addr_t paddr, int prot, |
| 104 | int mmu_idx, target_ulong size); |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 105 | #endif |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 106 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 107 | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
| 108 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 109 | #define CODE_GEN_PHYS_HASH_BITS 15 |
| 110 | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
| 111 | |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 112 | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 113 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 114 | /* estimated block size for TB allocation */ |
| 115 | /* XXX: use a per code average code fragment size and modulate it |
| 116 | according to the host CPU */ |
| 117 | #if defined(CONFIG_SOFTMMU) |
| 118 | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
| 119 | #else |
| 120 | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
| 121 | #endif |
| 122 | |
Filip Navara | a8cd70f | 2009-07-27 10:02:07 -0500 | [diff] [blame] | 123 | #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 124 | #define USE_DIRECT_JUMP |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 125 | #elif defined(CONFIG_TCG_INTERPRETER) |
| 126 | #define USE_DIRECT_JUMP |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 127 | #endif |
| 128 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 129 | struct TranslationBlock { |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 130 | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
| 131 | target_ulong cs_base; /* CS base for this block */ |
j_mayer | c068688 | 2007-09-20 22:47:42 +0000 | [diff] [blame] | 132 | uint64_t flags; /* flags defining in which context the code was generated */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 133 | uint16_t size; /* size of target code for this block (1 <= |
| 134 | size <= TARGET_PAGE_SIZE) */ |
bellard | 58fe2f1 | 2004-02-16 22:11:32 +0000 | [diff] [blame] | 135 | uint16_t cflags; /* compile flags */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 136 | #define CF_COUNT_MASK 0x7fff |
| 137 | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ |
bellard | 58fe2f1 | 2004-02-16 22:11:32 +0000 | [diff] [blame] | 138 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 139 | uint8_t *tc_ptr; /* pointer to the translated code */ |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 140 | /* next matching tb for physical address. */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 141 | struct TranslationBlock *phys_hash_next; |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 142 | /* first and second physical page containing code. The lower bit |
| 143 | of the pointer tells the index in page_next[] */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 144 | struct TranslationBlock *page_next[2]; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 145 | tb_page_addr_t page_addr[2]; |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 146 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 147 | /* the following data are used to directly call another TB from |
| 148 | the code of this one. */ |
| 149 | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
| 150 | #ifdef USE_DIRECT_JUMP |
Filip Navara | efc0a51 | 2010-03-26 16:06:28 +0000 | [diff] [blame] | 151 | uint16_t tb_jmp_offset[2]; /* offset of jump instruction */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 152 | #else |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 153 | unsigned long tb_next[2]; /* address of jump generated code */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 154 | #endif |
| 155 | /* list of TBs jumping to this one. This is a circular list using |
| 156 | the two least significant bits of the pointers to tell what is |
| 157 | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = |
| 158 | jmp_first */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 159 | struct TranslationBlock *jmp_next[2]; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 160 | struct TranslationBlock *jmp_first; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 161 | uint32_t icount; |
| 162 | }; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 163 | |
pbrook | b362e5e | 2006-11-12 20:40:55 +0000 | [diff] [blame] | 164 | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
| 165 | { |
| 166 | target_ulong tmp; |
| 167 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
edgar_igl | b5e19d4 | 2008-05-06 08:38:22 +0000 | [diff] [blame] | 168 | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK; |
pbrook | b362e5e | 2006-11-12 20:40:55 +0000 | [diff] [blame] | 169 | } |
| 170 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 171 | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 172 | { |
pbrook | b362e5e | 2006-11-12 20:40:55 +0000 | [diff] [blame] | 173 | target_ulong tmp; |
| 174 | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
edgar_igl | b5e19d4 | 2008-05-06 08:38:22 +0000 | [diff] [blame] | 175 | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK) |
| 176 | | (tmp & TB_JMP_ADDR_MASK)); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 177 | } |
| 178 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 179 | static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 180 | { |
Aurelien Jarno | f96a383 | 2010-12-28 17:46:59 +0100 | [diff] [blame] | 181 | return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1); |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 182 | } |
| 183 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 184 | void tb_free(TranslationBlock *tb); |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 185 | void tb_flush(CPUState *env); |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 186 | void tb_link_page(TranslationBlock *tb, |
| 187 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2); |
| 188 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 189 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 190 | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 191 | |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 192 | #if defined(USE_DIRECT_JUMP) |
| 193 | |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 194 | #if defined(CONFIG_TCG_INTERPRETER) |
| 195 | static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) |
| 196 | { |
| 197 | /* patch the branch destination */ |
| 198 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); |
| 199 | /* no need to flush icache explicitly */ |
| 200 | } |
| 201 | #elif defined(_ARCH_PPC) |
Blue Swirl | 64b85a8 | 2011-01-23 16:21:20 +0000 | [diff] [blame] | 202 | void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr); |
malc | 810260a | 2008-07-23 19:17:46 +0000 | [diff] [blame] | 203 | #define tb_set_jmp_target1 ppc_tb_set_jmp_target |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 204 | #elif defined(__i386__) || defined(__x86_64__) |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 205 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
| 206 | { |
| 207 | /* patch the branch destination */ |
| 208 | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); |
ths | 1235fc0 | 2008-06-03 19:51:57 +0000 | [diff] [blame] | 209 | /* no need to flush icache explicitly */ |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 210 | } |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 211 | #elif defined(__arm__) |
| 212 | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
| 213 | { |
Aurelien Jarno | 4a1e19a | 2010-12-21 19:32:49 +0100 | [diff] [blame] | 214 | #if !QEMU_GNUC_PREREQ(4, 1) |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 215 | register unsigned long _beg __asm ("a1"); |
| 216 | register unsigned long _end __asm ("a2"); |
| 217 | register unsigned long _flg __asm ("a3"); |
balrog | 3233f0d | 2008-12-01 02:02:37 +0000 | [diff] [blame] | 218 | #endif |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 219 | |
| 220 | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ |
Laurent Desnogues | 87b78ad | 2009-09-21 14:27:59 +0200 | [diff] [blame] | 221 | *(uint32_t *)jmp_addr = |
| 222 | (*(uint32_t *)jmp_addr & ~0xffffff) |
| 223 | | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 224 | |
balrog | 3233f0d | 2008-12-01 02:02:37 +0000 | [diff] [blame] | 225 | #if QEMU_GNUC_PREREQ(4, 1) |
Aurelien Jarno | 4a1e19a | 2010-12-21 19:32:49 +0100 | [diff] [blame] | 226 | __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); |
balrog | 3233f0d | 2008-12-01 02:02:37 +0000 | [diff] [blame] | 227 | #else |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 228 | /* flush icache */ |
| 229 | _beg = jmp_addr; |
| 230 | _end = jmp_addr + 4; |
| 231 | _flg = 0; |
| 232 | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
balrog | 3233f0d | 2008-12-01 02:02:37 +0000 | [diff] [blame] | 233 | #endif |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 234 | } |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 235 | #else |
| 236 | #error tb_set_jmp_target1 is missing |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 237 | #endif |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 238 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 239 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 240 | int n, unsigned long addr) |
| 241 | { |
| 242 | unsigned long offset; |
| 243 | |
| 244 | offset = tb->tb_jmp_offset[n]; |
| 245 | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
bellard | 4cbb86e | 2003-09-17 22:53:29 +0000 | [diff] [blame] | 246 | } |
| 247 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 248 | #else |
| 249 | |
| 250 | /* set the jump target */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 251 | static inline void tb_set_jmp_target(TranslationBlock *tb, |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 252 | int n, unsigned long addr) |
| 253 | { |
bellard | 95f7652 | 2003-06-05 00:54:44 +0000 | [diff] [blame] | 254 | tb->tb_next[n] = addr; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | #endif |
| 258 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 259 | static inline void tb_add_jump(TranslationBlock *tb, int n, |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 260 | TranslationBlock *tb_next) |
| 261 | { |
bellard | cf25629 | 2003-05-25 19:20:31 +0000 | [diff] [blame] | 262 | /* NOTE: this test is only needed for thread safety */ |
| 263 | if (!tb->jmp_next[n]) { |
| 264 | /* patch the native jump address */ |
| 265 | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 266 | |
bellard | cf25629 | 2003-05-25 19:20:31 +0000 | [diff] [blame] | 267 | /* add in TB jmp circular list */ |
| 268 | tb->jmp_next[n] = tb_next->jmp_first; |
| 269 | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n)); |
| 270 | } |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 271 | } |
| 272 | |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 273 | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
| 274 | |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 275 | #include "qemu-lock.h" |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 276 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 277 | extern spinlock_t tb_lock; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 278 | |
bellard | 36bdbe5 | 2003-11-19 22:12:02 +0000 | [diff] [blame] | 279 | extern int tb_invalidated_flag; |
bellard | 6e59c1d | 2003-10-27 21:24:54 +0000 | [diff] [blame] | 280 | |
Blue Swirl | 3917149 | 2011-09-21 18:13:16 +0000 | [diff] [blame] | 281 | /* The return address may point to the start of the next instruction. |
| 282 | Subtracting one gets us the call instruction itself. */ |
Stefan Weil | 7316329 | 2011-10-05 20:03:02 +0200 | [diff] [blame] | 283 | #if defined(CONFIG_TCG_INTERPRETER) |
| 284 | /* Alpha and SH4 user mode emulations and Softmmu call GETPC(). |
| 285 | For all others, GETPC remains undefined (which makes TCI a little faster. */ |
| 286 | # if defined(CONFIG_SOFTMMU) || defined(TARGET_ALPHA) || defined(TARGET_SH4) |
| 287 | extern void *tci_tb_ptr; |
| 288 | # define GETPC() tci_tb_ptr |
| 289 | # endif |
| 290 | #elif defined(__s390__) && !defined(__s390x__) |
Blue Swirl | 3917149 | 2011-09-21 18:13:16 +0000 | [diff] [blame] | 291 | # define GETPC() ((void*)(((unsigned long)__builtin_return_address(0) & 0x7fffffffUL) - 1)) |
| 292 | #elif defined(__arm__) |
| 293 | /* Thumb return addresses have the low bit set, so we need to subtract two. |
| 294 | This is still safe in ARM mode because instructions are 4 bytes. */ |
| 295 | # define GETPC() ((void *)((unsigned long)__builtin_return_address(0) - 2)) |
| 296 | #else |
| 297 | # define GETPC() ((void *)((unsigned long)__builtin_return_address(0) - 1)) |
| 298 | #endif |
| 299 | |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 300 | #if !defined(CONFIG_USER_ONLY) |
bellard | 6e59c1d | 2003-10-27 21:24:54 +0000 | [diff] [blame] | 301 | |
Avi Kivity | 37ec01d | 2012-03-08 18:08:35 +0200 | [diff] [blame] | 302 | struct MemoryRegion *iotlb_to_region(target_phys_addr_t index); |
| 303 | uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr, |
| 304 | unsigned size); |
| 305 | void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr, |
| 306 | uint64_t value, unsigned size); |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 307 | |
Blue Swirl | bccd9ec | 2011-07-04 20:57:05 +0000 | [diff] [blame] | 308 | void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx, |
bellard | 6e59c1d | 2003-10-27 21:24:54 +0000 | [diff] [blame] | 309 | void *retaddr); |
| 310 | |
blueswir1 | 79383c9 | 2008-08-30 09:51:20 +0000 | [diff] [blame] | 311 | #include "softmmu_defs.h" |
| 312 | |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 313 | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
bellard | 6e59c1d | 2003-10-27 21:24:54 +0000 | [diff] [blame] | 314 | #define MEMSUFFIX _code |
| 315 | #define env cpu_single_env |
| 316 | |
| 317 | #define DATA_SIZE 1 |
| 318 | #include "softmmu_header.h" |
| 319 | |
| 320 | #define DATA_SIZE 2 |
| 321 | #include "softmmu_header.h" |
| 322 | |
| 323 | #define DATA_SIZE 4 |
| 324 | #include "softmmu_header.h" |
| 325 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 326 | #define DATA_SIZE 8 |
| 327 | #include "softmmu_header.h" |
| 328 | |
bellard | 6e59c1d | 2003-10-27 21:24:54 +0000 | [diff] [blame] | 329 | #undef ACCESS_TYPE |
| 330 | #undef MEMSUFFIX |
| 331 | #undef env |
| 332 | |
| 333 | #endif |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 334 | |
| 335 | #if defined(CONFIG_USER_ONLY) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 336 | static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr) |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 337 | { |
| 338 | return addr; |
| 339 | } |
| 340 | #else |
Avi Kivity | d39e822 | 2012-01-01 23:35:10 +0200 | [diff] [blame] | 341 | tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr); |
bellard | 4390df5 | 2004-01-04 18:03:10 +0000 | [diff] [blame] | 342 | #endif |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 343 | |
aliguori | dde2367 | 2008-11-18 20:50:36 +0000 | [diff] [blame] | 344 | typedef void (CPUDebugExcpHandler)(CPUState *env); |
| 345 | |
| 346 | CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler); |
aurel32 | 1b530a6 | 2009-04-05 20:08:59 +0000 | [diff] [blame] | 347 | |
| 348 | /* vl.c */ |
| 349 | extern int singlestep; |
| 350 | |
Marcelo Tosatti | 1a28cac | 2010-05-04 09:45:20 -0300 | [diff] [blame] | 351 | /* cpu-exec.c */ |
| 352 | extern volatile sig_atomic_t exit_request; |
| 353 | |
Paolo Bonzini | 946fb27 | 2011-09-12 13:57:37 +0200 | [diff] [blame] | 354 | /* Deterministic execution requires that IO only be performed on the last |
| 355 | instruction of a TB so that interrupts take effect immediately. */ |
| 356 | static inline int can_do_io(CPUState *env) |
| 357 | { |
| 358 | if (!use_icount) { |
| 359 | return 1; |
| 360 | } |
| 361 | /* If not executing code then assume we are ok. */ |
| 362 | if (!env->current_tb) { |
| 363 | return 1; |
| 364 | } |
| 365 | return env->can_do_io != 0; |
| 366 | } |
| 367 | |
aliguori | 875cdcf | 2008-10-23 13:52:00 +0000 | [diff] [blame] | 368 | #endif |