blob: 3ec60a2c492890f922fd5f225828cc5c05396e0e [file] [log] [blame]
bellardd4e81642003-05-25 16:46:15 +00001/*
2 * internal execution defines for qemu
ths5fafdf22007-09-16 21:08:06 +00003 *
bellardd4e81642003-05-25 16:46:15 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellardd4e81642003-05-25 16:46:15 +000018 */
19
aliguori875cdcf2008-10-23 13:52:00 +000020#ifndef _EXEC_ALL_H_
21#define _EXEC_ALL_H_
blueswir17d99a002009-01-14 19:00:36 +000022
23#include "qemu-common.h"
24
bellardb346ff42003-06-15 20:05:50 +000025/* allow to see translation results - the slowdown should be negligible, so we leave it */
aurel32de9a95f2008-11-11 13:41:01 +000026#define DEBUG_DISAS
bellardb346ff42003-06-15 20:05:50 +000027
Paul Brook41c1b1c2010-03-12 16:54:58 +000028/* Page tracking code uses ram addresses in system mode, and virtual
29 addresses in userspace mode. Define tb_page_addr_t to be an appropriate
30 type. */
31#if defined(CONFIG_USER_ONLY)
Paul Brookb480d9b2010-03-12 23:23:29 +000032typedef abi_ulong tb_page_addr_t;
Paul Brook41c1b1c2010-03-12 16:54:58 +000033#else
34typedef ram_addr_t tb_page_addr_t;
35#endif
36
bellardb346ff42003-06-15 20:05:50 +000037/* is_jmp field values */
38#define DISAS_NEXT 0 /* next instruction can be analyzed */
39#define DISAS_JUMP 1 /* only pc was modified dynamically */
40#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
41#define DISAS_TB_JUMP 3 /* only pc was modified statically */
42
Blue Swirlf081c762011-05-21 07:10:23 +000043struct TranslationBlock;
pbrook2e70f6e2008-06-29 01:03:05 +000044typedef struct TranslationBlock TranslationBlock;
bellardb346ff42003-06-15 20:05:50 +000045
46/* XXX: make safe guess about sizes */
Peter Maydell5b620fb2011-06-22 15:16:32 +010047#define MAX_OP_PER_INSTR 208
Stuart Brady4d0e4ac2010-04-27 22:23:35 +010048
49#if HOST_LONG_BITS == 32
50#define MAX_OPC_PARAM_PER_ARG 2
51#else
52#define MAX_OPC_PARAM_PER_ARG 1
53#endif
54#define MAX_OPC_PARAM_IARGS 4
55#define MAX_OPC_PARAM_OARGS 1
56#define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
57
58/* A Call op needs up to 4 + 2N parameters on 32-bit archs,
59 * and up to 4 + N parameters on 64-bit archs
60 * (N = number of input arguments + output arguments). */
61#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
Aurelien Jarno6db73502009-09-22 23:31:04 +020062#define OPC_BUF_SIZE 640
bellardb346ff42003-06-15 20:05:50 +000063#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
64
pbrooka208e542008-03-31 17:07:36 +000065/* Maximum size a TCG op can expand to. This is complicated because a
Aurelien Jarno0cbfcd22009-10-22 02:36:27 +020066 single op may require several host instructions and register reloads.
67 For now take a wild guess at 192 bytes, which should allow at least
pbrooka208e542008-03-31 17:07:36 +000068 a couple of fixup instructions per argument. */
Aurelien Jarno0cbfcd22009-10-22 02:36:27 +020069#define TCG_MAX_OP_SIZE 192
pbrooka208e542008-03-31 17:07:36 +000070
pbrook0115be32008-02-03 17:35:41 +000071#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
bellardb346ff42003-06-15 20:05:50 +000072
bellardc27004e2005-01-03 23:35:10 +000073extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
bellardb346ff42003-06-15 20:05:50 +000074extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
pbrook2e70f6e2008-06-29 01:03:05 +000075extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
bellardb346ff42003-06-15 20:05:50 +000076
blueswir179383c92008-08-30 09:51:20 +000077#include "qemu-log.h"
bellardb346ff42003-06-15 20:05:50 +000078
ths2cfc5f12008-07-18 18:01:29 +000079void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
80void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
Stefan Weile87b7cb2011-04-18 06:39:52 +000081void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb,
82 int pc_pos);
aurel32d2856f12008-04-28 00:32:32 +000083
bellard57fec1f2008-02-01 10:50:11 +000084void cpu_gen_init(void);
bellard4c3a88a2003-07-26 12:06:08 +000085int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
blueswir1d07bde82007-12-11 19:35:45 +000086 int *gen_code_size_ptr);
ths5fafdf22007-09-16 21:08:06 +000087int cpu_restore_state(struct TranslationBlock *tb,
Stefan Weil618ba8e2011-04-18 06:39:53 +000088 CPUState *env, unsigned long searched_pc);
bellard2e126692004-04-25 21:28:44 +000089void cpu_resume_from_signal(CPUState *env1, void *puc);
pbrook2e70f6e2008-06-29 01:03:05 +000090void cpu_io_recompile(CPUState *env, void *retaddr);
91TranslationBlock *tb_gen_code(CPUState *env,
92 target_ulong pc, target_ulong cs_base, int flags,
93 int cflags);
bellard6a00d602005-11-21 23:25:50 +000094void cpu_exec_init(CPUState *env);
Blue Swirl1162c042011-05-14 12:52:35 +000095void QEMU_NORETURN cpu_loop_exit(CPUState *env1);
pbrook53a59602006-03-25 19:31:22 +000096int page_unprotect(target_ulong address, unsigned long pc, void *puc);
Paul Brook41c1b1c2010-03-12 16:54:58 +000097void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
bellard2e126692004-04-25 21:28:44 +000098 int is_cpu_write_access);
bellard2e126692004-04-25 21:28:44 +000099void tlb_flush_page(CPUState *env, target_ulong addr);
bellardee8b7022004-02-03 23:35:10 +0000100void tlb_flush(CPUState *env, int flush_global);
Paul Brookc527ee82010-03-01 03:31:14 +0000101#if !defined(CONFIG_USER_ONLY)
Paul Brookd4c430a2010-03-17 02:14:28 +0000102void tlb_set_page(CPUState *env, target_ulong vaddr,
103 target_phys_addr_t paddr, int prot,
104 int mmu_idx, target_ulong size);
Paul Brookc527ee82010-03-01 03:31:14 +0000105#endif
bellardd4e81642003-05-25 16:46:15 +0000106
bellardd4e81642003-05-25 16:46:15 +0000107#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
108
bellard4390df52004-01-04 18:03:10 +0000109#define CODE_GEN_PHYS_HASH_BITS 15
110#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
111
bellard26a5f132008-05-28 12:30:31 +0000112#define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
bellardd4e81642003-05-25 16:46:15 +0000113
bellard4390df52004-01-04 18:03:10 +0000114/* estimated block size for TB allocation */
115/* XXX: use a per code average code fragment size and modulate it
116 according to the host CPU */
117#if defined(CONFIG_SOFTMMU)
118#define CODE_GEN_AVG_BLOCK_SIZE 128
119#else
120#define CODE_GEN_AVG_BLOCK_SIZE 64
121#endif
122
Filip Navaraa8cd70f2009-07-27 10:02:07 -0500123#if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
bellardd4e81642003-05-25 16:46:15 +0000124#define USE_DIRECT_JUMP
Stefan Weil73163292011-10-05 20:03:02 +0200125#elif defined(CONFIG_TCG_INTERPRETER)
126#define USE_DIRECT_JUMP
bellardd4e81642003-05-25 16:46:15 +0000127#endif
128
pbrook2e70f6e2008-06-29 01:03:05 +0000129struct TranslationBlock {
bellard2e126692004-04-25 21:28:44 +0000130 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
131 target_ulong cs_base; /* CS base for this block */
j_mayerc0686882007-09-20 22:47:42 +0000132 uint64_t flags; /* flags defining in which context the code was generated */
bellardd4e81642003-05-25 16:46:15 +0000133 uint16_t size; /* size of target code for this block (1 <=
134 size <= TARGET_PAGE_SIZE) */
bellard58fe2f12004-02-16 22:11:32 +0000135 uint16_t cflags; /* compile flags */
pbrook2e70f6e2008-06-29 01:03:05 +0000136#define CF_COUNT_MASK 0x7fff
137#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
bellard58fe2f12004-02-16 22:11:32 +0000138
bellardd4e81642003-05-25 16:46:15 +0000139 uint8_t *tc_ptr; /* pointer to the translated code */
bellard4390df52004-01-04 18:03:10 +0000140 /* next matching tb for physical address. */
ths5fafdf22007-09-16 21:08:06 +0000141 struct TranslationBlock *phys_hash_next;
bellard4390df52004-01-04 18:03:10 +0000142 /* first and second physical page containing code. The lower bit
143 of the pointer tells the index in page_next[] */
ths5fafdf22007-09-16 21:08:06 +0000144 struct TranslationBlock *page_next[2];
Paul Brook41c1b1c2010-03-12 16:54:58 +0000145 tb_page_addr_t page_addr[2];
bellard4390df52004-01-04 18:03:10 +0000146
bellardd4e81642003-05-25 16:46:15 +0000147 /* the following data are used to directly call another TB from
148 the code of this one. */
149 uint16_t tb_next_offset[2]; /* offset of original jump target */
150#ifdef USE_DIRECT_JUMP
Filip Navaraefc0a512010-03-26 16:06:28 +0000151 uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
bellardd4e81642003-05-25 16:46:15 +0000152#else
bellard57fec1f2008-02-01 10:50:11 +0000153 unsigned long tb_next[2]; /* address of jump generated code */
bellardd4e81642003-05-25 16:46:15 +0000154#endif
155 /* list of TBs jumping to this one. This is a circular list using
156 the two least significant bits of the pointers to tell what is
157 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
158 jmp_first */
ths5fafdf22007-09-16 21:08:06 +0000159 struct TranslationBlock *jmp_next[2];
bellardd4e81642003-05-25 16:46:15 +0000160 struct TranslationBlock *jmp_first;
pbrook2e70f6e2008-06-29 01:03:05 +0000161 uint32_t icount;
162};
bellardd4e81642003-05-25 16:46:15 +0000163
pbrookb362e5e2006-11-12 20:40:55 +0000164static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
165{
166 target_ulong tmp;
167 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
edgar_iglb5e19d42008-05-06 08:38:22 +0000168 return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
pbrookb362e5e2006-11-12 20:40:55 +0000169}
170
bellard8a40a182005-11-20 10:35:40 +0000171static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
bellardd4e81642003-05-25 16:46:15 +0000172{
pbrookb362e5e2006-11-12 20:40:55 +0000173 target_ulong tmp;
174 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
edgar_iglb5e19d42008-05-06 08:38:22 +0000175 return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
176 | (tmp & TB_JMP_ADDR_MASK));
bellardd4e81642003-05-25 16:46:15 +0000177}
178
Paul Brook41c1b1c2010-03-12 16:54:58 +0000179static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
bellard4390df52004-01-04 18:03:10 +0000180{
Aurelien Jarnof96a3832010-12-28 17:46:59 +0100181 return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
bellard4390df52004-01-04 18:03:10 +0000182}
183
pbrook2e70f6e2008-06-29 01:03:05 +0000184void tb_free(TranslationBlock *tb);
bellard01243112004-01-04 15:48:17 +0000185void tb_flush(CPUState *env);
Paul Brook41c1b1c2010-03-12 16:54:58 +0000186void tb_link_page(TranslationBlock *tb,
187 tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
188void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
bellardd4e81642003-05-25 16:46:15 +0000189
bellard4390df52004-01-04 18:03:10 +0000190extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
bellardd4e81642003-05-25 16:46:15 +0000191
bellard4390df52004-01-04 18:03:10 +0000192#if defined(USE_DIRECT_JUMP)
193
Stefan Weil73163292011-10-05 20:03:02 +0200194#if defined(CONFIG_TCG_INTERPRETER)
195static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
196{
197 /* patch the branch destination */
198 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
199 /* no need to flush icache explicitly */
200}
201#elif defined(_ARCH_PPC)
Blue Swirl64b85a82011-01-23 16:21:20 +0000202void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
malc810260a2008-07-23 19:17:46 +0000203#define tb_set_jmp_target1 ppc_tb_set_jmp_target
bellard57fec1f2008-02-01 10:50:11 +0000204#elif defined(__i386__) || defined(__x86_64__)
bellard4390df52004-01-04 18:03:10 +0000205static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
206{
207 /* patch the branch destination */
208 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
ths1235fc02008-06-03 19:51:57 +0000209 /* no need to flush icache explicitly */
bellard4390df52004-01-04 18:03:10 +0000210}
balrog811d4cf2008-05-19 23:59:38 +0000211#elif defined(__arm__)
212static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
213{
Aurelien Jarno4a1e19a2010-12-21 19:32:49 +0100214#if !QEMU_GNUC_PREREQ(4, 1)
balrog811d4cf2008-05-19 23:59:38 +0000215 register unsigned long _beg __asm ("a1");
216 register unsigned long _end __asm ("a2");
217 register unsigned long _flg __asm ("a3");
balrog3233f0d2008-12-01 02:02:37 +0000218#endif
balrog811d4cf2008-05-19 23:59:38 +0000219
220 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
Laurent Desnogues87b78ad2009-09-21 14:27:59 +0200221 *(uint32_t *)jmp_addr =
222 (*(uint32_t *)jmp_addr & ~0xffffff)
223 | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
balrog811d4cf2008-05-19 23:59:38 +0000224
balrog3233f0d2008-12-01 02:02:37 +0000225#if QEMU_GNUC_PREREQ(4, 1)
Aurelien Jarno4a1e19a2010-12-21 19:32:49 +0100226 __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
balrog3233f0d2008-12-01 02:02:37 +0000227#else
balrog811d4cf2008-05-19 23:59:38 +0000228 /* flush icache */
229 _beg = jmp_addr;
230 _end = jmp_addr + 4;
231 _flg = 0;
232 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
balrog3233f0d2008-12-01 02:02:37 +0000233#endif
balrog811d4cf2008-05-19 23:59:38 +0000234}
Stefan Weil73163292011-10-05 20:03:02 +0200235#else
236#error tb_set_jmp_target1 is missing
bellard4390df52004-01-04 18:03:10 +0000237#endif
bellardd4e81642003-05-25 16:46:15 +0000238
ths5fafdf22007-09-16 21:08:06 +0000239static inline void tb_set_jmp_target(TranslationBlock *tb,
bellard4cbb86e2003-09-17 22:53:29 +0000240 int n, unsigned long addr)
241{
242 unsigned long offset;
243
244 offset = tb->tb_jmp_offset[n];
245 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
bellard4cbb86e2003-09-17 22:53:29 +0000246}
247
bellardd4e81642003-05-25 16:46:15 +0000248#else
249
250/* set the jump target */
ths5fafdf22007-09-16 21:08:06 +0000251static inline void tb_set_jmp_target(TranslationBlock *tb,
bellardd4e81642003-05-25 16:46:15 +0000252 int n, unsigned long addr)
253{
bellard95f76522003-06-05 00:54:44 +0000254 tb->tb_next[n] = addr;
bellardd4e81642003-05-25 16:46:15 +0000255}
256
257#endif
258
ths5fafdf22007-09-16 21:08:06 +0000259static inline void tb_add_jump(TranslationBlock *tb, int n,
bellardd4e81642003-05-25 16:46:15 +0000260 TranslationBlock *tb_next)
261{
bellardcf256292003-05-25 19:20:31 +0000262 /* NOTE: this test is only needed for thread safety */
263 if (!tb->jmp_next[n]) {
264 /* patch the native jump address */
265 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
ths3b46e622007-09-17 08:09:54 +0000266
bellardcf256292003-05-25 19:20:31 +0000267 /* add in TB jmp circular list */
268 tb->jmp_next[n] = tb_next->jmp_first;
269 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
270 }
bellardd4e81642003-05-25 16:46:15 +0000271}
272
bellarda513fe12003-05-27 23:29:48 +0000273TranslationBlock *tb_find_pc(unsigned long pc_ptr);
274
pbrookd5975362008-06-07 20:50:51 +0000275#include "qemu-lock.h"
bellardd4e81642003-05-25 16:46:15 +0000276
Anthony Liguoric227f092009-10-01 16:12:16 -0500277extern spinlock_t tb_lock;
bellardd4e81642003-05-25 16:46:15 +0000278
bellard36bdbe52003-11-19 22:12:02 +0000279extern int tb_invalidated_flag;
bellard6e59c1d2003-10-27 21:24:54 +0000280
Blue Swirl39171492011-09-21 18:13:16 +0000281/* The return address may point to the start of the next instruction.
282 Subtracting one gets us the call instruction itself. */
Stefan Weil73163292011-10-05 20:03:02 +0200283#if defined(CONFIG_TCG_INTERPRETER)
284/* Alpha and SH4 user mode emulations and Softmmu call GETPC().
285 For all others, GETPC remains undefined (which makes TCI a little faster. */
286# if defined(CONFIG_SOFTMMU) || defined(TARGET_ALPHA) || defined(TARGET_SH4)
287extern void *tci_tb_ptr;
288# define GETPC() tci_tb_ptr
289# endif
290#elif defined(__s390__) && !defined(__s390x__)
Blue Swirl39171492011-09-21 18:13:16 +0000291# define GETPC() ((void*)(((unsigned long)__builtin_return_address(0) & 0x7fffffffUL) - 1))
292#elif defined(__arm__)
293/* Thumb return addresses have the low bit set, so we need to subtract two.
294 This is still safe in ARM mode because instructions are 4 bytes. */
295# define GETPC() ((void *)((unsigned long)__builtin_return_address(0) - 2))
296#else
297# define GETPC() ((void *)((unsigned long)__builtin_return_address(0) - 1))
298#endif
299
bellarde95c8d52004-09-30 22:22:08 +0000300#if !defined(CONFIG_USER_ONLY)
bellard6e59c1d2003-10-27 21:24:54 +0000301
Avi Kivity37ec01d2012-03-08 18:08:35 +0200302struct MemoryRegion *iotlb_to_region(target_phys_addr_t index);
303uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr,
304 unsigned size);
305void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr,
306 uint64_t value, unsigned size);
Paul Brookb3755a92010-03-12 16:54:58 +0000307
Blue Swirlbccd9ec2011-07-04 20:57:05 +0000308void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
bellard6e59c1d2003-10-27 21:24:54 +0000309 void *retaddr);
310
blueswir179383c92008-08-30 09:51:20 +0000311#include "softmmu_defs.h"
312
j_mayer6ebbf392007-10-14 07:07:08 +0000313#define ACCESS_TYPE (NB_MMU_MODES + 1)
bellard6e59c1d2003-10-27 21:24:54 +0000314#define MEMSUFFIX _code
315#define env cpu_single_env
316
317#define DATA_SIZE 1
318#include "softmmu_header.h"
319
320#define DATA_SIZE 2
321#include "softmmu_header.h"
322
323#define DATA_SIZE 4
324#include "softmmu_header.h"
325
bellardc27004e2005-01-03 23:35:10 +0000326#define DATA_SIZE 8
327#include "softmmu_header.h"
328
bellard6e59c1d2003-10-27 21:24:54 +0000329#undef ACCESS_TYPE
330#undef MEMSUFFIX
331#undef env
332
333#endif
bellard4390df52004-01-04 18:03:10 +0000334
335#if defined(CONFIG_USER_ONLY)
Paul Brook41c1b1c2010-03-12 16:54:58 +0000336static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
bellard4390df52004-01-04 18:03:10 +0000337{
338 return addr;
339}
340#else
Avi Kivityd39e8222012-01-01 23:35:10 +0200341tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr);
bellard4390df52004-01-04 18:03:10 +0000342#endif
bellard9df217a2005-02-10 22:05:51 +0000343
aliguoridde23672008-11-18 20:50:36 +0000344typedef void (CPUDebugExcpHandler)(CPUState *env);
345
346CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
aurel321b530a62009-04-05 20:08:59 +0000347
348/* vl.c */
349extern int singlestep;
350
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300351/* cpu-exec.c */
352extern volatile sig_atomic_t exit_request;
353
Paolo Bonzini946fb272011-09-12 13:57:37 +0200354/* Deterministic execution requires that IO only be performed on the last
355 instruction of a TB so that interrupts take effect immediately. */
356static inline int can_do_io(CPUState *env)
357{
358 if (!use_icount) {
359 return 1;
360 }
361 /* If not executing code then assume we are ok. */
362 if (!env->current_tb) {
363 return 1;
364 }
365 return env->can_do_io != 0;
366}
367
aliguori875cdcf2008-10-23 13:52:00 +0000368#endif