blob: e226d7b56381105e177cfcb8f112127f58af1ad8 [file] [log] [blame]
aurel32b7169912009-03-02 16:42:04 +00001#if !defined(__OPENPIC_H__)
2#define __OPENPIC_H__
3
4/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
5enum {
6 OPENPIC_OUTPUT_INT = 0, /* IRQ */
7 OPENPIC_OUTPUT_CINT, /* critical IRQ */
8 OPENPIC_OUTPUT_MCK, /* Machine check event */
9 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
10 OPENPIC_OUTPUT_RESET, /* Core reset event */
11 OPENPIC_OUTPUT_NB,
12};
13
Alexander Grafd0b72632012-12-08 05:17:14 +010014#define OPENPIC_MODEL_RAVEN 0
15#define OPENPIC_MODEL_FSL_MPIC_20 1
Alexander Graf5861a332012-12-07 23:51:09 +010016
aurel32b7169912009-03-02 16:42:04 +000017#endif /* __OPENPIC_H__ */