blob: 254f7353701c788727af9faedce3ad7697519c95 [file] [log] [blame]
Paulo Alcantara45dcdb92015-06-28 14:58:57 -03001/*
2 * QEMU ICH9 TCO emulation tests
3 *
4 * Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
Markus Armbruster452fcdb2018-02-01 12:18:39 +01009
Peter Maydell681c28a2016-02-08 18:08:51 +000010#include "qemu/osdep.h"
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030011
12#include "libqtest.h"
13#include "libqos/pci.h"
14#include "libqos/pci-pc.h"
Markus Armbruster452fcdb2018-02-01 12:18:39 +010015#include "qapi/qmp/qdict.h"
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030016#include "hw/pci/pci_regs.h"
17#include "hw/i386/ich9.h"
18#include "hw/acpi/ich9.h"
19#include "hw/acpi/tco.h"
20
21#define RCBA_BASE_ADDR 0xfed1c000
22#define PM_IO_BASE_ADDR 0xb000
23
24enum {
25 TCO_RLD_DEFAULT = 0x0000,
26 TCO_DAT_IN_DEFAULT = 0x00,
27 TCO_DAT_OUT_DEFAULT = 0x00,
28 TCO1_STS_DEFAULT = 0x0000,
29 TCO2_STS_DEFAULT = 0x0000,
30 TCO1_CNT_DEFAULT = 0x0000,
31 TCO2_CNT_DEFAULT = 0x0008,
32 TCO_MESSAGE1_DEFAULT = 0x00,
33 TCO_MESSAGE2_DEFAULT = 0x00,
34 TCO_WDCNT_DEFAULT = 0x00,
35 TCO_TMR_DEFAULT = 0x0004,
36 SW_IRQ_GEN_DEFAULT = 0x03,
37};
38
39#define TCO_SECS_TO_TICKS(secs) (((secs) * 10) / 6)
40#define TCO_TICKS_TO_SECS(ticks) (((ticks) * 6) / 10)
41
42typedef struct {
43 const char *args;
Paulo Alcantara5add35b2015-06-28 14:58:58 -030044 bool noreboot;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030045 QPCIDevice *dev;
David Gibsonb4ba67d2016-10-24 15:52:06 +110046 QPCIBar tco_io_bar;
Marc-André Lureau34779e82017-02-05 20:47:24 +000047 QPCIBus *bus;
Thomas Huth6bb58d22019-04-09 10:52:41 +020048 QTestState *qts;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030049} TestData;
50
Marc-André Lureau34779e82017-02-05 20:47:24 +000051static void test_end(TestData *d)
52{
53 g_free(d->dev);
54 qpci_free_pc(d->bus);
Thomas Huth6bb58d22019-04-09 10:52:41 +020055 qtest_quit(d->qts);
Marc-André Lureau34779e82017-02-05 20:47:24 +000056}
57
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030058static void test_init(TestData *d)
59{
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030060 QTestState *qs;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030061
Markus Armbruster88b988c2018-08-06 08:53:43 +020062 qs = qtest_initf("-machine q35 %s %s",
63 d->noreboot ? "" : "-global ICH9-LPC.noreboot=false",
64 !d->args ? "" : d->args);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030065 qtest_irq_intercept_in(qs, "ioapic");
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030066
Emanuele Giuseppe Esposito143e6db2018-07-19 13:50:27 +020067 d->bus = qpci_new_pc(qs, NULL);
Marc-André Lureau34779e82017-02-05 20:47:24 +000068 d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030069 g_assert(d->dev != NULL);
70
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030071 qpci_device_enable(d->dev);
72
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030073 /* set ACPI PM I/O space base address */
Michael S. Tsirkinc4fc82b2015-07-08 10:06:15 +030074 qpci_config_writel(d->dev, ICH9_LPC_PMBASE, PM_IO_BASE_ADDR | 0x1);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030075 /* enable ACPI I/O */
Michael S. Tsirkinc4fc82b2015-07-08 10:06:15 +030076 qpci_config_writeb(d->dev, ICH9_LPC_ACPI_CTRL, 0x80);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030077 /* set Root Complex BAR */
Michael S. Tsirkinc4fc82b2015-07-08 10:06:15 +030078 qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030079
David Gibsonb4ba67d2016-10-24 15:52:06 +110080 d->tco_io_bar = qpci_legacy_iomap(d->dev, PM_IO_BASE_ADDR + 0x60);
Thomas Huth6bb58d22019-04-09 10:52:41 +020081 d->qts = qs;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030082}
83
84static void stop_tco(const TestData *d)
85{
86 uint32_t val;
87
David Gibsonb4ba67d2016-10-24 15:52:06 +110088 val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030089 val |= TCO_TMR_HLT;
David Gibsonb4ba67d2016-10-24 15:52:06 +110090 qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030091}
92
93static void start_tco(const TestData *d)
94{
95 uint32_t val;
96
David Gibsonb4ba67d2016-10-24 15:52:06 +110097 val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -030098 val &= ~TCO_TMR_HLT;
David Gibsonb4ba67d2016-10-24 15:52:06 +110099 qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300100}
101
102static void load_tco(const TestData *d)
103{
David Gibsonb4ba67d2016-10-24 15:52:06 +1100104 qpci_io_writew(d->dev, d->tco_io_bar, TCO_RLD, 4);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300105}
106
107static void set_tco_timeout(const TestData *d, uint16_t ticks)
108{
David Gibsonb4ba67d2016-10-24 15:52:06 +1100109 qpci_io_writew(d->dev, d->tco_io_bar, TCO_TMR, ticks);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300110}
111
112static void clear_tco_status(const TestData *d)
113{
David Gibsonb4ba67d2016-10-24 15:52:06 +1100114 qpci_io_writew(d->dev, d->tco_io_bar, TCO1_STS, 0x0008);
115 qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0002);
116 qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0004);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300117}
118
Thomas Huth6bb58d22019-04-09 10:52:41 +0200119static void reset_on_second_timeout(const TestData *td, bool enable)
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300120{
121 uint32_t val;
122
Thomas Huth6bb58d22019-04-09 10:52:41 +0200123 val = qtest_readl(td->qts, RCBA_BASE_ADDR + ICH9_CC_GCS);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300124 if (enable) {
125 val &= ~ICH9_CC_GCS_NO_REBOOT;
126 } else {
127 val |= ICH9_CC_GCS_NO_REBOOT;
128 }
Thomas Huth6bb58d22019-04-09 10:52:41 +0200129 qtest_writel(td->qts, RCBA_BASE_ADDR + ICH9_CC_GCS, val);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300130}
131
132static void test_tco_defaults(void)
133{
134 TestData d;
135
136 d.args = NULL;
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300137 d.noreboot = true;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300138 test_init(&d);
David Gibsonb4ba67d2016-10-24 15:52:06 +1100139 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD), ==,
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300140 TCO_RLD_DEFAULT);
141 /* TCO_DAT_IN & TCO_DAT_OUT */
David Gibsonb4ba67d2016-10-24 15:52:06 +1100142 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_DAT_IN), ==,
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300143 (TCO_DAT_OUT_DEFAULT << 8) | TCO_DAT_IN_DEFAULT);
144 /* TCO1_STS & TCO2_STS */
David Gibsonb4ba67d2016-10-24 15:52:06 +1100145 g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_STS), ==,
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300146 (TCO2_STS_DEFAULT << 16) | TCO1_STS_DEFAULT);
147 /* TCO1_CNT & TCO2_CNT */
David Gibsonb4ba67d2016-10-24 15:52:06 +1100148 g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_CNT), ==,
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300149 (TCO2_CNT_DEFAULT << 16) | TCO1_CNT_DEFAULT);
150 /* TCO_MESSAGE1 & TCO_MESSAGE2 */
David Gibsonb4ba67d2016-10-24 15:52:06 +1100151 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_MESSAGE1), ==,
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300152 (TCO_MESSAGE2_DEFAULT << 8) | TCO_MESSAGE1_DEFAULT);
David Gibsonb4ba67d2016-10-24 15:52:06 +1100153 g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, TCO_WDCNT), ==,
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300154 TCO_WDCNT_DEFAULT);
David Gibsonb4ba67d2016-10-24 15:52:06 +1100155 g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, SW_IRQ_GEN), ==,
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300156 SW_IRQ_GEN_DEFAULT);
David Gibsonb4ba67d2016-10-24 15:52:06 +1100157 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_TMR), ==,
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300158 TCO_TMR_DEFAULT);
Marc-André Lureau34779e82017-02-05 20:47:24 +0000159 test_end(&d);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300160}
161
162static void test_tco_timeout(void)
163{
164 TestData d;
165 const uint16_t ticks = TCO_SECS_TO_TICKS(4);
166 uint32_t val;
167 int ret;
168
169 d.args = NULL;
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300170 d.noreboot = true;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300171 test_init(&d);
172
173 stop_tco(&d);
174 clear_tco_status(&d);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200175 reset_on_second_timeout(&d, false);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300176 set_tco_timeout(&d, ticks);
177 load_tco(&d);
178 start_tco(&d);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200179 qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300180
181 /* test first timeout */
David Gibsonb4ba67d2016-10-24 15:52:06 +1100182 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300183 ret = val & TCO_TIMEOUT ? 1 : 0;
184 g_assert(ret == 1);
185
186 /* test clearing timeout bit */
187 val |= TCO_TIMEOUT;
David Gibsonb4ba67d2016-10-24 15:52:06 +1100188 qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
189 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300190 ret = val & TCO_TIMEOUT ? 1 : 0;
191 g_assert(ret == 0);
192
193 /* test second timeout */
Thomas Huth6bb58d22019-04-09 10:52:41 +0200194 qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC);
David Gibsonb4ba67d2016-10-24 15:52:06 +1100195 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300196 ret = val & TCO_TIMEOUT ? 1 : 0;
197 g_assert(ret == 1);
David Gibsonb4ba67d2016-10-24 15:52:06 +1100198 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300199 ret = val & TCO_SECOND_TO_STS ? 1 : 0;
200 g_assert(ret == 1);
201
202 stop_tco(&d);
Marc-André Lureau34779e82017-02-05 20:47:24 +0000203 test_end(&d);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300204}
205
206static void test_tco_max_timeout(void)
207{
208 TestData d;
209 const uint16_t ticks = 0xffff;
210 uint32_t val;
211 int ret;
212
213 d.args = NULL;
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300214 d.noreboot = true;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300215 test_init(&d);
216
217 stop_tco(&d);
218 clear_tco_status(&d);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200219 reset_on_second_timeout(&d, false);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300220 set_tco_timeout(&d, ticks);
221 load_tco(&d);
222 start_tco(&d);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200223 qtest_clock_step(d.qts, ((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300224
David Gibsonb4ba67d2016-10-24 15:52:06 +1100225 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300226 g_assert_cmpint(val & TCO_RLD_MASK, ==, 1);
David Gibsonb4ba67d2016-10-24 15:52:06 +1100227 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300228 ret = val & TCO_TIMEOUT ? 1 : 0;
229 g_assert(ret == 0);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200230 qtest_clock_step(d.qts, TCO_TICK_NSEC);
David Gibsonb4ba67d2016-10-24 15:52:06 +1100231 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300232 ret = val & TCO_TIMEOUT ? 1 : 0;
233 g_assert(ret == 1);
234
235 stop_tco(&d);
Marc-André Lureau34779e82017-02-05 20:47:24 +0000236 test_end(&d);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300237}
238
Thomas Huth6bb58d22019-04-09 10:52:41 +0200239static QDict *get_watchdog_action(const TestData *td)
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300240{
Thomas Huth6bb58d22019-04-09 10:52:41 +0200241 QDict *ev = qtest_qmp_eventwait_ref(td->qts, "WATCHDOG");
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300242 QDict *data;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300243
244 data = qdict_get_qdict(ev, "data");
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +0200245 qobject_ref(data);
246 qobject_unref(ev);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300247 return data;
248}
249
250static void test_tco_second_timeout_pause(void)
251{
252 TestData td;
253 const uint16_t ticks = TCO_SECS_TO_TICKS(32);
254 QDict *ad;
255
256 td.args = "-watchdog-action pause";
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300257 td.noreboot = false;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300258 test_init(&td);
259
260 stop_tco(&td);
261 clear_tco_status(&td);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200262 reset_on_second_timeout(&td, true);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300263 set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
264 load_tco(&td);
265 start_tco(&td);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200266 qtest_clock_step(td.qts, ticks * TCO_TICK_NSEC * 2);
267 ad = get_watchdog_action(&td);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300268 g_assert(!strcmp(qdict_get_str(ad, "action"), "pause"));
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +0200269 qobject_unref(ad);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300270
271 stop_tco(&td);
Marc-André Lureau34779e82017-02-05 20:47:24 +0000272 test_end(&td);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300273}
274
275static void test_tco_second_timeout_reset(void)
276{
277 TestData td;
278 const uint16_t ticks = TCO_SECS_TO_TICKS(16);
279 QDict *ad;
280
281 td.args = "-watchdog-action reset";
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300282 td.noreboot = false;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300283 test_init(&td);
284
285 stop_tco(&td);
286 clear_tco_status(&td);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200287 reset_on_second_timeout(&td, true);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300288 set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
289 load_tco(&td);
290 start_tco(&td);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200291 qtest_clock_step(td.qts, ticks * TCO_TICK_NSEC * 2);
292 ad = get_watchdog_action(&td);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300293 g_assert(!strcmp(qdict_get_str(ad, "action"), "reset"));
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +0200294 qobject_unref(ad);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300295
296 stop_tco(&td);
Marc-André Lureau34779e82017-02-05 20:47:24 +0000297 test_end(&td);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300298}
299
300static void test_tco_second_timeout_shutdown(void)
301{
302 TestData td;
303 const uint16_t ticks = TCO_SECS_TO_TICKS(128);
304 QDict *ad;
305
306 td.args = "-watchdog-action shutdown";
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300307 td.noreboot = false;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300308 test_init(&td);
309
310 stop_tco(&td);
311 clear_tco_status(&td);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200312 reset_on_second_timeout(&td, true);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300313 set_tco_timeout(&td, ticks);
314 load_tco(&td);
315 start_tco(&td);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200316 qtest_clock_step(td.qts, ticks * TCO_TICK_NSEC * 2);
317 ad = get_watchdog_action(&td);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300318 g_assert(!strcmp(qdict_get_str(ad, "action"), "shutdown"));
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +0200319 qobject_unref(ad);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300320
321 stop_tco(&td);
Marc-André Lureau34779e82017-02-05 20:47:24 +0000322 test_end(&td);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300323}
324
325static void test_tco_second_timeout_none(void)
326{
327 TestData td;
328 const uint16_t ticks = TCO_SECS_TO_TICKS(256);
329 QDict *ad;
330
331 td.args = "-watchdog-action none";
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300332 td.noreboot = false;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300333 test_init(&td);
334
335 stop_tco(&td);
336 clear_tco_status(&td);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200337 reset_on_second_timeout(&td, true);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300338 set_tco_timeout(&td, ticks);
339 load_tco(&td);
340 start_tco(&td);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200341 qtest_clock_step(td.qts, ticks * TCO_TICK_NSEC * 2);
342 ad = get_watchdog_action(&td);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300343 g_assert(!strcmp(qdict_get_str(ad, "action"), "none"));
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +0200344 qobject_unref(ad);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300345
346 stop_tco(&td);
Marc-André Lureau34779e82017-02-05 20:47:24 +0000347 test_end(&td);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300348}
349
350static void test_tco_ticks_counter(void)
351{
352 TestData d;
353 uint16_t ticks = TCO_SECS_TO_TICKS(8);
354 uint16_t rld;
355
356 d.args = NULL;
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300357 d.noreboot = true;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300358 test_init(&d);
359
360 stop_tco(&d);
361 clear_tco_status(&d);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200362 reset_on_second_timeout(&d, false);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300363 set_tco_timeout(&d, ticks);
364 load_tco(&d);
365 start_tco(&d);
366
367 do {
David Gibsonb4ba67d2016-10-24 15:52:06 +1100368 rld = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD) & TCO_RLD_MASK;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300369 g_assert_cmpint(rld, ==, ticks);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200370 qtest_clock_step(d.qts, TCO_TICK_NSEC);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300371 ticks--;
David Gibsonb4ba67d2016-10-24 15:52:06 +1100372 } while (!(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS) & TCO_TIMEOUT));
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300373
374 stop_tco(&d);
Marc-André Lureau34779e82017-02-05 20:47:24 +0000375 test_end(&d);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300376}
377
378static void test_tco1_control_bits(void)
379{
380 TestData d;
381 uint16_t val;
382
383 d.args = NULL;
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300384 d.noreboot = true;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300385 test_init(&d);
386
387 val = TCO_LOCK;
David Gibsonb4ba67d2016-10-24 15:52:06 +1100388 qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300389 val &= ~TCO_LOCK;
David Gibsonb4ba67d2016-10-24 15:52:06 +1100390 qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
391 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_CNT), ==,
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300392 TCO_LOCK);
Marc-André Lureau34779e82017-02-05 20:47:24 +0000393 test_end(&d);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300394}
395
396static void test_tco1_status_bits(void)
397{
398 TestData d;
399 uint16_t ticks = 8;
400 uint16_t val;
401 int ret;
402
403 d.args = NULL;
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300404 d.noreboot = true;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300405 test_init(&d);
406
407 stop_tco(&d);
408 clear_tco_status(&d);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200409 reset_on_second_timeout(&d, false);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300410 set_tco_timeout(&d, ticks);
411 load_tco(&d);
412 start_tco(&d);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200413 qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300414
David Gibsonb4ba67d2016-10-24 15:52:06 +1100415 qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_IN, 0);
416 qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_OUT, 0);
417 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300418 ret = val & (TCO_TIMEOUT | SW_TCO_SMI | TCO_INT_STS) ? 1 : 0;
419 g_assert(ret == 1);
David Gibsonb4ba67d2016-10-24 15:52:06 +1100420 qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
421 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS), ==, 0);
Marc-André Lureau34779e82017-02-05 20:47:24 +0000422 test_end(&d);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300423}
424
425static void test_tco2_status_bits(void)
426{
427 TestData d;
428 uint16_t ticks = 8;
429 uint16_t val;
430 int ret;
431
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300432 d.args = NULL;
433 d.noreboot = true;
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300434 test_init(&d);
435
436 stop_tco(&d);
437 clear_tco_status(&d);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200438 reset_on_second_timeout(&d, true);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300439 set_tco_timeout(&d, ticks);
440 load_tco(&d);
441 start_tco(&d);
Thomas Huth6bb58d22019-04-09 10:52:41 +0200442 qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC * 2);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300443
David Gibsonb4ba67d2016-10-24 15:52:06 +1100444 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300445 ret = val & (TCO_SECOND_TO_STS | TCO_BOOT_STS) ? 1 : 0;
446 g_assert(ret == 1);
David Gibsonb4ba67d2016-10-24 15:52:06 +1100447 qpci_io_writew(d.dev, d.tco_io_bar, TCO2_STS, val);
448 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS), ==, 0);
Marc-André Lureau34779e82017-02-05 20:47:24 +0000449 test_end(&d);
Paulo Alcantara45dcdb92015-06-28 14:58:57 -0300450}
451
452int main(int argc, char **argv)
453{
454 g_test_init(&argc, &argv, NULL);
455
456 qtest_add_func("tco/defaults", test_tco_defaults);
457 qtest_add_func("tco/timeout/no_action", test_tco_timeout);
458 qtest_add_func("tco/timeout/no_action/max", test_tco_max_timeout);
459 qtest_add_func("tco/second_timeout/pause", test_tco_second_timeout_pause);
460 qtest_add_func("tco/second_timeout/reset", test_tco_second_timeout_reset);
461 qtest_add_func("tco/second_timeout/shutdown",
462 test_tco_second_timeout_shutdown);
463 qtest_add_func("tco/second_timeout/none", test_tco_second_timeout_none);
464 qtest_add_func("tco/counter", test_tco_ticks_counter);
465 qtest_add_func("tco/tco1_control/bits", test_tco1_control_bits);
466 qtest_add_func("tco/tco1_status/bits", test_tco1_status_bits);
467 qtest_add_func("tco/tco2_status/bits", test_tco2_status_bits);
468 return g_test_run();
469}