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ths81fdc5f2007-10-08 13:04:02 +00001/*
2 * CRIS virtual CPU header
3 *
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
ths81fdc5f2007-10-08 13:04:02 +000019 */
20#ifndef CPU_CRIS_H
21#define CPU_CRIS_H
22
Stefan Weil7ad757b2012-02-01 20:53:33 +010023#include "config.h"
24#include "qemu-common.h"
25
ths81fdc5f2007-10-08 13:04:02 +000026#define TARGET_LONG_BITS 32
27
Andreas Färber9349b4f2012-03-14 01:38:32 +010028#define CPUArchState struct CPUCRISState
pbrookc2764712009-03-07 15:24:59 +000029
ths81fdc5f2007-10-08 13:04:02 +000030#include "cpu-defs.h"
31
ths81fdc5f2007-10-08 13:04:02 +000032#define TARGET_HAS_ICE 1
33
34#define ELF_MACHINE EM_CRIS
35
edgar_igl1b1a38b2008-06-09 23:18:06 +000036#define EXCP_NMI 1
37#define EXCP_GURU 2
38#define EXCP_BUSFAULT 3
39#define EXCP_IRQ 4
40#define EXCP_BREAK 5
ths81fdc5f2007-10-08 13:04:02 +000041
Richard Henderson85097db2011-05-04 13:34:31 -070042/* CRIS-specific interrupt pending bits. */
43#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
44
edgar_iglb41f7df2008-05-02 22:16:17 +000045/* Register aliases. R0 - R15 */
46#define R_FP 8
47#define R_SP 14
48#define R_ACR 15
49
50/* Support regs, P0 - P15 */
51#define PR_BZ 0
52#define PR_VR 1
53#define PR_PID 2
54#define PR_SRS 3
55#define PR_WZ 4
56#define PR_EXS 5
57#define PR_EDA 6
Edgar E. Iglesiasfb9fb692010-02-15 11:17:33 +010058#define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
edgar_iglb41f7df2008-05-02 22:16:17 +000059#define PR_MOF 7
60#define PR_DZ 8
61#define PR_EBP 9
62#define PR_ERP 10
63#define PR_SRP 11
edgar_igl1b1a38b2008-06-09 23:18:06 +000064#define PR_NRP 12
edgar_iglb41f7df2008-05-02 22:16:17 +000065#define PR_CCS 13
66#define PR_USP 14
67#define PR_SPC 15
68
ths81fdc5f2007-10-08 13:04:02 +000069/* CPU flags. */
edgar_igl1b1a38b2008-06-09 23:18:06 +000070#define Q_FLAG 0x80000000
71#define M_FLAG 0x40000000
Edgar E. Iglesiasfb9fb692010-02-15 11:17:33 +010072#define PFIX_FLAG 0x800 /* CRISv10 Only. */
Stefan Sandstrom774d5c52011-12-12 11:38:31 +010073#define F_FLAG_V10 0x400
74#define P_FLAG_V10 0x200
ths81fdc5f2007-10-08 13:04:02 +000075#define S_FLAG 0x200
76#define R_FLAG 0x100
77#define P_FLAG 0x80
78#define U_FLAG 0x40
ths81fdc5f2007-10-08 13:04:02 +000079#define I_FLAG 0x20
80#define X_FLAG 0x10
81#define N_FLAG 0x08
82#define Z_FLAG 0x04
83#define V_FLAG 0x02
84#define C_FLAG 0x01
85#define ALU_FLAGS 0x1F
86
87/* Condition codes. */
88#define CC_CC 0
89#define CC_CS 1
90#define CC_NE 2
91#define CC_EQ 3
92#define CC_VC 4
93#define CC_VS 5
94#define CC_PL 6
95#define CC_MI 7
96#define CC_LS 8
97#define CC_HI 9
98#define CC_GE 10
99#define CC_LT 11
100#define CC_GT 12
101#define CC_LE 13
102#define CC_A 14
103#define CC_P 15
104
j_mayer6ebbf392007-10-14 07:07:08 +0000105#define NB_MMU_MODES 2
106
ths81fdc5f2007-10-08 13:04:02 +0000107typedef struct CPUCRISState {
ths81fdc5f2007-10-08 13:04:02 +0000108 uint32_t regs[16];
edgar_iglb41f7df2008-05-02 22:16:17 +0000109 /* P0 - P15 are referred to as special registers in the docs. */
ths81fdc5f2007-10-08 13:04:02 +0000110 uint32_t pregs[16];
edgar_iglb41f7df2008-05-02 22:16:17 +0000111
Stefan Weil64c7b9d2011-04-28 17:20:27 +0200112 /* Pseudo register for the PC. Not directly accessible on CRIS. */
ths81fdc5f2007-10-08 13:04:02 +0000113 uint32_t pc;
ths81fdc5f2007-10-08 13:04:02 +0000114
edgar_iglb41f7df2008-05-02 22:16:17 +0000115 /* Pseudo register for the kernel stack. */
116 uint32_t ksp;
117
edgar_iglcf1d97f2008-05-13 10:59:14 +0000118 /* Branch. */
119 int dslot;
ths81fdc5f2007-10-08 13:04:02 +0000120 int btaken;
edgar_iglcf1d97f2008-05-13 10:59:14 +0000121 uint32_t btarget;
ths81fdc5f2007-10-08 13:04:02 +0000122
ths81fdc5f2007-10-08 13:04:02 +0000123 /* Condition flag tracking. */
124 uint32_t cc_op;
125 uint32_t cc_mask;
126 uint32_t cc_dest;
127 uint32_t cc_src;
128 uint32_t cc_result;
ths81fdc5f2007-10-08 13:04:02 +0000129 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
130 int cc_size;
edgar_igl30abcfc2008-05-27 21:10:56 +0000131 /* X flag at the time of cc snapshot. */
ths81fdc5f2007-10-08 13:04:02 +0000132 int cc_x;
133
Edgar E. Iglesiasfb9fb692010-02-15 11:17:33 +0100134 /* CRIS has certain insns that lockout interrupts. */
135 int locked_irq;
edgar_igl786c02f2008-03-14 01:08:09 +0000136 int interrupt_vector;
137 int fault_vector;
138 int trap_vector;
139
edgar_iglb41f7df2008-05-02 22:16:17 +0000140 /* FIXME: add a check in the translator to avoid writing to support
141 register sets beyond the 4th. The ISA allows up to 256! but in
142 practice there is no core that implements more than 4.
143
144 Support function registers are used to control units close to the
145 core. Accesses do not pass down the normal hierarchy.
146 */
147 uint32_t sregs[4][16];
148
edgar_igl44cd42e2008-05-11 14:28:14 +0000149 /* Linear feedback shift reg in the mmu. Used to provide pseudo
150 randomness for the 'hint' the mmu gives to sw for chosing valid
151 sets on TLB refills. */
152 uint32_t mmu_rand_lfsr;
153
edgar_iglb41f7df2008-05-02 22:16:17 +0000154 /*
155 * We just store the stores to the tlbset here for later evaluation
156 * when the hw needs access to them.
157 *
158 * One for I and another for D.
159 */
160 struct
161 {
162 uint32_t hi;
163 uint32_t lo;
164 } tlbsets[2][4][16];
165
ths81fdc5f2007-10-08 13:04:02 +0000166 CPU_COMMON
Edgar E. Iglesiasebab1722010-09-19 00:30:25 +0200167
168 /* Members after CPU_COMMON are preserved across resets. */
169 void *load_info;
ths81fdc5f2007-10-08 13:04:02 +0000170} CPUCRISState;
171
bellardaaed9092007-11-10 15:15:54 +0000172CPUCRISState *cpu_cris_init(const char *cpu_model);
ths81fdc5f2007-10-08 13:04:02 +0000173int cpu_cris_exec(CPUCRISState *s);
174void cpu_cris_close(CPUCRISState *s);
175void do_interrupt(CPUCRISState *env);
176/* you can call this signal handler from your SIGBUS and SIGSEGV
177 signal handlers to inform the virtual CPU of exceptions. non zero
178 is returned if the signal was handled by the virtual CPU. */
179int cpu_cris_signal_handler(int host_signum, void *pinfo,
180 void *puc);
ths81fdc5f2007-10-08 13:04:02 +0000181
182enum {
183 CC_OP_DYNAMIC, /* Use env->cc_op */
184 CC_OP_FLAGS,
ths81fdc5f2007-10-08 13:04:02 +0000185 CC_OP_CMP,
186 CC_OP_MOVE,
ths81fdc5f2007-10-08 13:04:02 +0000187 CC_OP_ADD,
188 CC_OP_ADDC,
189 CC_OP_MCP,
190 CC_OP_ADDU,
191 CC_OP_SUB,
192 CC_OP_SUBU,
193 CC_OP_NEG,
194 CC_OP_BTST,
195 CC_OP_MULS,
196 CC_OP_MULU,
197 CC_OP_DSTEP,
Edgar E. Iglesiasfb9fb692010-02-15 11:17:33 +0100198 CC_OP_MSTEP,
ths81fdc5f2007-10-08 13:04:02 +0000199 CC_OP_BOUND,
200
201 CC_OP_OR,
202 CC_OP_AND,
203 CC_OP_XOR,
204 CC_OP_LSL,
205 CC_OP_LSR,
206 CC_OP_ASR,
207 CC_OP_LZ
208};
209
ths81fdc5f2007-10-08 13:04:02 +0000210/* CRIS uses 8k pages. */
211#define TARGET_PAGE_BITS 13
pbrookbb7ec042008-03-25 22:28:25 +0000212#define MMAP_SHIFT TARGET_PAGE_BITS
ths81fdc5f2007-10-08 13:04:02 +0000213
Richard Henderson52705892010-03-10 14:33:23 -0800214#define TARGET_PHYS_ADDR_SPACE_BITS 32
215#define TARGET_VIRT_ADDR_SPACE_BITS 32
216
ths81fdc5f2007-10-08 13:04:02 +0000217#define cpu_init cpu_cris_init
218#define cpu_exec cpu_cris_exec
219#define cpu_gen_code cpu_cris_gen_code
220#define cpu_signal_handler cpu_cris_signal_handler
221
pbrookb3c77242008-06-30 16:31:04 +0000222#define CPU_SAVE_VERSION 1
223
j_mayer6ebbf392007-10-14 07:07:08 +0000224/* MMU modes definitions */
225#define MMU_MODE0_SUFFIX _kernel
226#define MMU_MODE1_SUFFIX _user
227#define MMU_USER_IDX 1
Andreas Färbera1170bf2012-03-14 01:38:21 +0100228static inline int cpu_mmu_index (CPUCRISState *env)
j_mayer6ebbf392007-10-14 07:07:08 +0000229{
edgar_iglb41f7df2008-05-02 22:16:17 +0000230 return !!(env->pregs[PR_CCS] & U_FLAG);
j_mayer6ebbf392007-10-14 07:07:08 +0000231}
232
Andreas Färbera1170bf2012-03-14 01:38:21 +0100233int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
Blue Swirl97b348e2011-08-01 16:12:17 +0000234 int mmu_idx);
Nathan Froyd0b5c1ce2009-08-10 13:37:36 -0700235#define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
edgar_iglcc53adb2009-02-22 11:59:59 +0000236
pbrook6e68e072008-05-30 17:22:15 +0000237#if defined(CONFIG_USER_ONLY)
Andreas Färbera1170bf2012-03-14 01:38:21 +0100238static inline void cpu_clone_regs(CPUCRISState *env, target_ulong newsp)
pbrook6e68e072008-05-30 17:22:15 +0000239{
pbrookf8ed7072008-05-30 17:54:15 +0000240 if (newsp)
pbrook6e68e072008-05-30 17:22:15 +0000241 env->regs[14] = newsp;
242 env->regs[10] = 0;
243}
244#endif
245
edgar_iglef967792009-01-07 14:19:38 +0000246static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
247{
248 env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
249}
250
edgar_igl90046272008-02-28 08:28:32 +0000251/* Support function regs. */
ths81fdc5f2007-10-08 13:04:02 +0000252#define SFR_RW_GC_CFG 0][0
edgar_iglb41f7df2008-05-02 22:16:17 +0000253#define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
254#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
255#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
256#define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
257#define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
258#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
259#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
ths81fdc5f2007-10-08 13:04:02 +0000260
edgar_iglb41f7df2008-05-02 22:16:17 +0000261#include "cpu-all.h"
aliguori622ed362008-11-18 19:36:03 +0000262
Andreas Färbera1170bf2012-03-14 01:38:21 +0100263static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
aliguori6b917542008-11-18 19:46:41 +0000264 target_ulong *cs_base, int *flags)
265{
266 *pc = env->pc;
267 *cs_base = 0;
268 *flags = env->dslot |
Edgar E. Iglesiasfb9fb692010-02-15 11:17:33 +0100269 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
270 | X_FLAG | PFIX_FLAG));
aliguori6b917542008-11-18 19:46:41 +0000271}
272
Edgar E. Iglesias40e9edd2010-02-15 12:18:57 +0100273#define cpu_list cris_cpu_list
Stefan Weil9a78eea2010-10-22 23:03:33 +0200274void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
Edgar E. Iglesias40e9edd2010-02-15 12:18:57 +0100275
Andreas Färbera1170bf2012-03-14 01:38:21 +0100276static inline bool cpu_has_work(CPUCRISState *env)
Blue Swirlf081c762011-05-21 07:10:23 +0000277{
278 return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
279}
280
281#include "exec-all.h"
282
Andreas Färbera1170bf2012-03-14 01:38:21 +0100283static inline void cpu_pc_from_tb(CPUCRISState *env, TranslationBlock *tb)
Blue Swirlf081c762011-05-21 07:10:23 +0000284{
285 env->pc = tb->pc;
286}
ths81fdc5f2007-10-08 13:04:02 +0000287#endif