Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Channel subsystem structures and definitions. |
| 3 | * |
| 4 | * Copyright 2012 IBM Corp. |
| 5 | * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> |
| 6 | * |
| 7 | * This work is licensed under the terms of the GNU GPL, version 2 or (at |
| 8 | * your option) any later version. See the COPYING file in the top-level |
| 9 | * directory. |
| 10 | */ |
| 11 | |
| 12 | #ifndef CSS_H |
| 13 | #define CSS_H |
| 14 | |
Yi Min Zhao | a28d839 | 2016-01-27 16:05:26 +0800 | [diff] [blame] | 15 | #include "hw/s390x/adapter.h" |
| 16 | #include "hw/s390x/s390_flic.h" |
Paolo Bonzini | bd3f16a | 2015-12-04 12:06:26 +0100 | [diff] [blame] | 17 | #include "hw/s390x/ioinst.h" |
David Hildenbrand | f16bbb9 | 2017-08-18 13:43:52 +0200 | [diff] [blame] | 18 | #include "sysemu/kvm.h" |
Markus Armbruster | ec150c7 | 2019-08-12 07:23:31 +0200 | [diff] [blame] | 19 | #include "target/s390x/cpu-qom.h" |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 20 | |
| 21 | /* Channel subsystem constants. */ |
Sascha Silbe | cf24993 | 2016-06-15 17:16:05 +0200 | [diff] [blame] | 22 | #define MAX_DEVNO 65535 |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 23 | #define MAX_SCHID 65535 |
| 24 | #define MAX_SSID 3 |
Cornelia Huck | 882b3b9 | 2016-08-15 11:10:28 +0200 | [diff] [blame] | 25 | #define MAX_CSSID 255 |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 26 | #define MAX_CHPID 255 |
| 27 | |
Fei Li | dde522b | 2016-11-24 11:10:39 +0100 | [diff] [blame] | 28 | #define MAX_ISC 7 |
| 29 | |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 30 | #define MAX_CIWS 62 |
| 31 | |
Sascha Silbe | cf24993 | 2016-06-15 17:16:05 +0200 | [diff] [blame] | 32 | #define VIRTUAL_CSSID 0xfe |
Jing Liu | 6c15e9b | 2016-09-19 09:10:43 +0200 | [diff] [blame] | 33 | #define VIRTIO_CCW_CHPID 0 /* used by convention */ |
Sascha Silbe | cf24993 | 2016-06-15 17:16:05 +0200 | [diff] [blame] | 34 | |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 35 | typedef struct CIW { |
| 36 | uint8_t type; |
| 37 | uint8_t command; |
| 38 | uint16_t count; |
| 39 | } QEMU_PACKED CIW; |
| 40 | |
| 41 | typedef struct SenseId { |
| 42 | /* common part */ |
| 43 | uint8_t reserved; /* always 0x'FF' */ |
| 44 | uint16_t cu_type; /* control unit type */ |
| 45 | uint8_t cu_model; /* control unit model */ |
| 46 | uint16_t dev_type; /* device type */ |
| 47 | uint8_t dev_model; /* device model */ |
| 48 | uint8_t unused; /* padding byte */ |
| 49 | /* extended part */ |
| 50 | CIW ciw[MAX_CIWS]; /* variable # of CIWs */ |
Thomas Huth | 729315e | 2018-09-27 10:23:34 +0200 | [diff] [blame] | 51 | } SenseId; /* Note: No QEMU_PACKED due to unaligned members */ |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 52 | |
| 53 | /* Channel measurements, from linux/drivers/s390/cio/cmf.c. */ |
| 54 | typedef struct CMB { |
| 55 | uint16_t ssch_rsch_count; |
| 56 | uint16_t sample_count; |
| 57 | uint32_t device_connect_time; |
| 58 | uint32_t function_pending_time; |
| 59 | uint32_t device_disconnect_time; |
| 60 | uint32_t control_unit_queuing_time; |
| 61 | uint32_t device_active_only_time; |
| 62 | uint32_t reserved[2]; |
| 63 | } QEMU_PACKED CMB; |
| 64 | |
| 65 | typedef struct CMBE { |
| 66 | uint32_t ssch_rsch_count; |
| 67 | uint32_t sample_count; |
| 68 | uint32_t device_connect_time; |
| 69 | uint32_t function_pending_time; |
| 70 | uint32_t device_disconnect_time; |
| 71 | uint32_t control_unit_queuing_time; |
| 72 | uint32_t device_active_only_time; |
| 73 | uint32_t device_busy_time; |
| 74 | uint32_t initial_command_response_time; |
| 75 | uint32_t reserved[7]; |
| 76 | } QEMU_PACKED CMBE; |
| 77 | |
Halil Pasic | 57065a7 | 2017-09-21 20:08:37 +0200 | [diff] [blame] | 78 | typedef enum CcwDataStreamOp { |
| 79 | CDS_OP_R = 0, /* read, false when used as is_write */ |
| 80 | CDS_OP_W = 1, /* write, true when used as is_write */ |
| 81 | CDS_OP_A = 2 /* advance, should not be used as is_write */ |
| 82 | } CcwDataStreamOp; |
| 83 | |
| 84 | /* normal usage is via SuchchDev.cds instead of instantiating */ |
| 85 | typedef struct CcwDataStream { |
| 86 | #define CDS_F_IDA 0x01 |
| 87 | #define CDS_F_MIDA 0x02 |
| 88 | #define CDS_F_I2K 0x04 |
| 89 | #define CDS_F_C64 0x08 |
Halil Pasic | 62a2554 | 2017-09-21 20:08:40 +0200 | [diff] [blame] | 90 | #define CDS_F_FMT 0x10 /* CCW format-1 */ |
Halil Pasic | 57065a7 | 2017-09-21 20:08:37 +0200 | [diff] [blame] | 91 | #define CDS_F_STREAM_BROKEN 0x80 |
| 92 | uint8_t flags; |
| 93 | uint8_t at_idaw; |
| 94 | uint16_t at_byte; |
| 95 | uint16_t count; |
| 96 | uint32_t cda_orig; |
| 97 | int (*op_handler)(struct CcwDataStream *cds, void *buff, int len, |
| 98 | CcwDataStreamOp op); |
| 99 | hwaddr cda; |
Cornelia Huck | 85fa94e | 2019-05-06 19:11:48 +0200 | [diff] [blame] | 100 | bool do_skip; |
Halil Pasic | 57065a7 | 2017-09-21 20:08:37 +0200 | [diff] [blame] | 101 | } CcwDataStream; |
| 102 | |
Halil Pasic | e443ef9 | 2017-10-17 16:04:48 +0200 | [diff] [blame] | 103 | /* |
| 104 | * IO instructions conclude according to this. Currently we have only |
| 105 | * cc codes. Valid values are 0, 1, 2, 3 and the generic semantic for |
| 106 | * IO instructions is described briefly. For more details consult the PoP. |
| 107 | */ |
| 108 | typedef enum IOInstEnding { |
| 109 | /* produced expected result */ |
| 110 | IOINST_CC_EXPECTED = 0, |
| 111 | /* status conditions were present or produced alternate result */ |
| 112 | IOINST_CC_STATUS_PRESENT = 1, |
| 113 | /* inst. ineffective because busy with previously initiated function */ |
| 114 | IOINST_CC_BUSY = 2, |
| 115 | /* inst. ineffective because not operational */ |
| 116 | IOINST_CC_NOT_OPERATIONAL = 3 |
| 117 | } IOInstEnding; |
| 118 | |
Paolo Bonzini | bd3f16a | 2015-12-04 12:06:26 +0100 | [diff] [blame] | 119 | typedef struct SubchDev SubchDev; |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 120 | struct SubchDev { |
| 121 | /* channel-subsystem related things: */ |
Thomas Huth | cb89b34 | 2018-09-27 10:23:35 +0200 | [diff] [blame] | 122 | SCHIB curr_status; /* Needs alignment and thus must come first */ |
| 123 | ORB orb; |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 124 | uint8_t cssid; |
| 125 | uint8_t ssid; |
| 126 | uint16_t schid; |
| 127 | uint16_t devno; |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 128 | uint8_t sense_data[32]; |
| 129 | hwaddr channel_prog; |
| 130 | CCW1 last_cmd; |
| 131 | bool last_cmd_valid; |
Cornelia Huck | a327c92 | 2014-09-05 09:33:17 +0200 | [diff] [blame] | 132 | bool ccw_fmt_1; |
Cornelia Huck | 7e74946 | 2013-02-06 10:31:37 +0100 | [diff] [blame] | 133 | bool thinint_active; |
Cornelia Huck | e8601dd | 2014-09-05 09:33:18 +0200 | [diff] [blame] | 134 | uint8_t ccw_no_data_cnt; |
Michael Tokarev | cba42d6 | 2021-03-09 14:15:10 +0300 | [diff] [blame] | 135 | uint16_t migrated_schid; /* used for mismatch detection */ |
Halil Pasic | 57065a7 | 2017-09-21 20:08:37 +0200 | [diff] [blame] | 136 | CcwDataStream cds; |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 137 | /* transport-provided data: */ |
| 138 | int (*ccw_cb) (SubchDev *, CCW1); |
Thomas Huth | 62ac4a5 | 2014-12-11 14:25:11 +0100 | [diff] [blame] | 139 | void (*disable_cb)(SubchDev *); |
Halil Pasic | 66dc50f | 2017-10-17 16:04:49 +0200 | [diff] [blame] | 140 | IOInstEnding (*do_subchannel_work) (SubchDev *); |
Eric Farman | 0599a04 | 2021-06-18 01:25:36 +0200 | [diff] [blame] | 141 | void (*irb_cb)(SubchDev *, IRB *); |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 142 | SenseId id; |
| 143 | void *driver_data; |
Eric Farman | c626710 | 2021-06-18 01:25:37 +0200 | [diff] [blame] | 144 | ESW esw; |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 145 | }; |
| 146 | |
Halil Pasic | 66dc50f | 2017-10-17 16:04:49 +0200 | [diff] [blame] | 147 | static inline void sch_gen_unit_exception(SubchDev *sch) |
| 148 | { |
Cornelia Huck | 89c6722 | 2021-07-05 18:39:52 +0200 | [diff] [blame] | 149 | sch->curr_status.scsw.ctrl &= ~(SCSW_ACTL_DEVICE_ACTIVE | |
| 150 | SCSW_ACTL_SUBCH_ACTIVE); |
Halil Pasic | 66dc50f | 2017-10-17 16:04:49 +0200 | [diff] [blame] | 151 | sch->curr_status.scsw.ctrl |= SCSW_STCTL_PRIMARY | |
| 152 | SCSW_STCTL_SECONDARY | |
| 153 | SCSW_STCTL_ALERT | |
| 154 | SCSW_STCTL_STATUS_PEND; |
| 155 | sch->curr_status.scsw.cpa = sch->channel_prog + 8; |
| 156 | sch->curr_status.scsw.dstat = SCSW_DSTAT_UNIT_EXCEP; |
| 157 | } |
| 158 | |
Halil Pasic | 517ff12 | 2017-07-03 23:34:14 +0200 | [diff] [blame] | 159 | extern const VMStateDescription vmstate_subch_dev; |
| 160 | |
Xiao Feng Ren | 8f3cf01 | 2017-05-17 02:48:04 +0200 | [diff] [blame] | 161 | /* |
| 162 | * Identify a device within the channel subsystem. |
| 163 | * Note that this can be used to identify either the subchannel or |
| 164 | * the attached I/O device, as there's always one I/O device per |
| 165 | * subchannel. |
| 166 | */ |
| 167 | typedef struct CssDevId { |
| 168 | uint8_t cssid; |
| 169 | uint8_t ssid; |
| 170 | uint16_t devid; |
| 171 | bool valid; |
| 172 | } CssDevId; |
| 173 | |
Fam Zheng | 1b6b7d1 | 2017-07-14 10:14:54 +0800 | [diff] [blame] | 174 | extern const PropertyInfo css_devid_propinfo; |
Xiao Feng Ren | 8f3cf01 | 2017-05-17 02:48:04 +0200 | [diff] [blame] | 175 | |
| 176 | #define DEFINE_PROP_CSS_DEV_ID(_n, _s, _f) \ |
| 177 | DEFINE_PROP(_n, _s, _f, css_devid_propinfo, CssDevId) |
| 178 | |
Yi Min Zhao | a28d839 | 2016-01-27 16:05:26 +0800 | [diff] [blame] | 179 | typedef struct IndAddr { |
| 180 | hwaddr addr; |
| 181 | uint64_t map; |
| 182 | unsigned long refcnt; |
Halil Pasic | 517ff12 | 2017-07-03 23:34:14 +0200 | [diff] [blame] | 183 | int32_t len; |
Yi Min Zhao | a28d839 | 2016-01-27 16:05:26 +0800 | [diff] [blame] | 184 | QTAILQ_ENTRY(IndAddr) sibling; |
| 185 | } IndAddr; |
| 186 | |
Halil Pasic | 517ff12 | 2017-07-03 23:34:14 +0200 | [diff] [blame] | 187 | extern const VMStateDescription vmstate_ind_addr; |
| 188 | |
| 189 | #define VMSTATE_PTR_TO_IND_ADDR(_f, _s) \ |
| 190 | VMSTATE_STRUCT(_f, _s, 1, vmstate_ind_addr, IndAddr*) |
| 191 | |
Yi Min Zhao | a28d839 | 2016-01-27 16:05:26 +0800 | [diff] [blame] | 192 | IndAddr *get_indicator(hwaddr ind_addr, int len); |
| 193 | void release_indicator(AdapterInfo *adapter, IndAddr *indicator); |
| 194 | int map_indicator(AdapterInfo *adapter, IndAddr *indicator); |
| 195 | |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 196 | typedef SubchDev *(*css_subch_cb_func)(uint8_t m, uint8_t cssid, uint8_t ssid, |
| 197 | uint16_t schid); |
| 198 | int css_create_css_image(uint8_t cssid, bool default_image); |
| 199 | bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno); |
| 200 | void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid, |
| 201 | uint16_t devno, SubchDev *sch); |
| 202 | void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type); |
Xiao Feng Ren | 8f3cf01 | 2017-05-17 02:48:04 +0200 | [diff] [blame] | 203 | int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id); |
Jing Liu | 6c15e9b | 2016-09-19 09:10:43 +0200 | [diff] [blame] | 204 | unsigned int css_find_free_chpid(uint8_t cssid); |
Cornelia Huck | b4436a0 | 2013-02-15 10:18:43 +0100 | [diff] [blame] | 205 | uint16_t css_build_subchannel_id(SubchDev *sch); |
Xiao Feng Ren | 8ca2b37 | 2017-05-17 02:48:10 +0200 | [diff] [blame] | 206 | void copy_scsw_to_guest(SCSW *dest, const SCSW *src); |
Eric Farman | c626710 | 2021-06-18 01:25:37 +0200 | [diff] [blame] | 207 | void copy_esw_to_guest(ESW *dest, const ESW *src); |
Xiao Feng Ren | 8ca2b37 | 2017-05-17 02:48:10 +0200 | [diff] [blame] | 208 | void css_inject_io_interrupt(SubchDev *sch); |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 209 | void css_reset(void); |
| 210 | void css_reset_sch(SubchDev *sch); |
Eric Farman | f6dde1b | 2020-05-05 14:57:56 +0200 | [diff] [blame] | 211 | void css_crw_add_to_queue(CRW crw); |
Dong Jia Shi | 5c8d6f0 | 2017-08-03 02:35:27 +0200 | [diff] [blame] | 212 | void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited, |
| 213 | int chain, uint16_t rsid); |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 214 | void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid, |
| 215 | int hotplugged, int add); |
| 216 | void css_generate_chp_crws(uint8_t cssid, uint8_t chpid); |
Frank Blaschka | 8cba80c | 2015-01-09 09:04:38 +0100 | [diff] [blame] | 217 | void css_generate_css_crws(uint8_t cssid); |
Song Shan Gong | c81b4f8 | 2016-01-19 02:55:00 +0100 | [diff] [blame] | 218 | void css_clear_sei_pending(void); |
Halil Pasic | 66dc50f | 2017-10-17 16:04:49 +0200 | [diff] [blame] | 219 | IOInstEnding s390_ccw_cmd_request(SubchDev *sch); |
| 220 | IOInstEnding do_subchannel_work_virtual(SubchDev *sub); |
| 221 | IOInstEnding do_subchannel_work_passthrough(SubchDev *sub); |
Eric Farman | c626710 | 2021-06-18 01:25:37 +0200 | [diff] [blame] | 222 | void build_irb_passthrough(SubchDev *sch, IRB *irb); |
Eric Farman | 0599a04 | 2021-06-18 01:25:36 +0200 | [diff] [blame] | 223 | void build_irb_virtual(SubchDev *sch, IRB *irb); |
Cornelia Huck | 03cf077 | 2013-07-15 17:45:03 +0200 | [diff] [blame] | 224 | |
Cornelia Huck | 8fadea2 | 2019-05-07 17:47:33 +0200 | [diff] [blame] | 225 | int s390_ccw_halt(SubchDev *sch); |
| 226 | int s390_ccw_clear(SubchDev *sch); |
Farhan Ali | 46ea384 | 2020-05-05 14:57:54 +0200 | [diff] [blame] | 227 | IOInstEnding s390_ccw_store(SubchDev *sch); |
Cornelia Huck | 8fadea2 | 2019-05-07 17:47:33 +0200 | [diff] [blame] | 228 | |
Fei Li | 5b00bef | 2016-11-25 07:45:14 +0100 | [diff] [blame] | 229 | typedef enum { |
| 230 | CSS_IO_ADAPTER_VIRTIO = 0, |
| 231 | CSS_IO_ADAPTER_PCI = 1, |
| 232 | CSS_IO_ADAPTER_TYPE_NUMS, |
| 233 | } CssIoAdapterType; |
| 234 | |
Yi Min Zhao | 25a08b8 | 2017-02-17 15:26:48 +0800 | [diff] [blame] | 235 | void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc); |
Philippe Mathieu-Daudé | 6233759 | 2023-11-05 19:22:57 +0100 | [diff] [blame] | 236 | int css_do_sic(S390CPU *cpu, uint8_t isc, uint16_t mode); |
Fei Li | dde522b | 2016-11-24 11:10:39 +0100 | [diff] [blame] | 237 | uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc); |
| 238 | void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable, |
Fei Li | 1497c16 | 2017-03-07 04:07:44 +0100 | [diff] [blame] | 239 | uint8_t flags, Error **errp); |
| 240 | |
Paolo Bonzini | bd3f16a | 2015-12-04 12:06:26 +0100 | [diff] [blame] | 241 | #ifndef CONFIG_USER_ONLY |
| 242 | SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, |
| 243 | uint16_t schid); |
| 244 | bool css_subch_visible(SubchDev *sch); |
| 245 | void css_conditional_io_interrupt(SubchDev *sch); |
Farhan Ali | 46ea384 | 2020-05-05 14:57:54 +0200 | [diff] [blame] | 246 | IOInstEnding css_do_stsch(SubchDev *sch, SCHIB *schib); |
Paolo Bonzini | bd3f16a | 2015-12-04 12:06:26 +0100 | [diff] [blame] | 247 | bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid); |
Halil Pasic | 6bb6f19 | 2017-10-17 16:04:53 +0200 | [diff] [blame] | 248 | IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *schib); |
Halil Pasic | 9637640 | 2017-10-17 16:04:50 +0200 | [diff] [blame] | 249 | IOInstEnding css_do_xsch(SubchDev *sch); |
Halil Pasic | 7733144 | 2017-10-17 16:04:51 +0200 | [diff] [blame] | 250 | IOInstEnding css_do_csch(SubchDev *sch); |
Halil Pasic | ae9f1be | 2017-10-17 16:04:52 +0200 | [diff] [blame] | 251 | IOInstEnding css_do_hsch(SubchDev *sch); |
Halil Pasic | 66dc50f | 2017-10-17 16:04:49 +0200 | [diff] [blame] | 252 | IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb); |
Paolo Bonzini | bd3f16a | 2015-12-04 12:06:26 +0100 | [diff] [blame] | 253 | int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len); |
| 254 | void css_do_tsch_update_subch(SubchDev *sch); |
| 255 | int css_do_stcrw(CRW *crw); |
| 256 | void css_undo_stcrw(CRW *crw); |
Paolo Bonzini | bd3f16a | 2015-12-04 12:06:26 +0100 | [diff] [blame] | 257 | int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, |
| 258 | int rfmt, void *buf); |
| 259 | void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo); |
| 260 | int css_enable_mcsse(void); |
| 261 | int css_enable_mss(void); |
Halil Pasic | 66dc50f | 2017-10-17 16:04:49 +0200 | [diff] [blame] | 262 | IOInstEnding css_do_rsch(SubchDev *sch); |
Paolo Bonzini | bd3f16a | 2015-12-04 12:06:26 +0100 | [diff] [blame] | 263 | int css_do_rchp(uint8_t cssid, uint8_t chpid); |
| 264 | bool css_present(uint8_t cssid); |
| 265 | #endif |
| 266 | |
Fam Zheng | 1b6b7d1 | 2017-07-14 10:14:54 +0800 | [diff] [blame] | 267 | extern const PropertyInfo css_devid_ro_propinfo; |
Dong Jia Shi | c35fc6a | 2017-02-14 04:04:02 +0100 | [diff] [blame] | 268 | |
| 269 | #define DEFINE_PROP_CSS_DEV_ID_RO(_n, _s, _f) \ |
| 270 | DEFINE_PROP(_n, _s, _f, css_devid_ro_propinfo, CssDevId) |
| 271 | |
Sascha Silbe | cf24993 | 2016-06-15 17:16:05 +0200 | [diff] [blame] | 272 | /** |
| 273 | * Create a subchannel for the given bus id. |
| 274 | * |
Cornelia Huck | 36699ab | 2018-07-23 18:32:21 +0200 | [diff] [blame] | 275 | * If @p bus_id is valid, verify that it is not already in use, and find a |
| 276 | * free devno for it. |
Halil Pasic | 99577c4 | 2017-12-06 15:44:37 +0100 | [diff] [blame] | 277 | * If @p bus_id is not valid find a free subchannel id and device number |
| 278 | * across all subchannel sets and all css images starting from the default |
| 279 | * css image. |
Dong Jia Shi | 817d4a6 | 2017-05-17 02:48:05 +0200 | [diff] [blame] | 280 | * |
| 281 | * If either of the former actions succeed, allocate a subchannel structure, |
| 282 | * initialise it with the bus id, subchannel id and device number, register |
| 283 | * it with the CSS and return it. Otherwise return NULL. |
Sascha Silbe | cf24993 | 2016-06-15 17:16:05 +0200 | [diff] [blame] | 284 | * |
| 285 | * The caller becomes owner of the returned subchannel structure and |
| 286 | * is responsible for unregistering and freeing it. |
| 287 | */ |
Cornelia Huck | 36699ab | 2018-07-23 18:32:21 +0200 | [diff] [blame] | 288 | SubchDev *css_create_sch(CssDevId bus_id, Error **errp); |
Halil Pasic | e996583 | 2017-07-11 16:54:40 +0200 | [diff] [blame] | 289 | |
| 290 | /** Turn on css migration */ |
| 291 | void css_register_vmstate(void); |
| 292 | |
Halil Pasic | 57065a7 | 2017-09-21 20:08:37 +0200 | [diff] [blame] | 293 | |
| 294 | void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb); |
| 295 | |
| 296 | static inline void ccw_dstream_rewind(CcwDataStream *cds) |
| 297 | { |
| 298 | cds->at_byte = 0; |
| 299 | cds->at_idaw = 0; |
| 300 | cds->cda = cds->cda_orig; |
| 301 | } |
| 302 | |
| 303 | static inline bool ccw_dstream_good(CcwDataStream *cds) |
| 304 | { |
| 305 | return !(cds->flags & CDS_F_STREAM_BROKEN); |
| 306 | } |
| 307 | |
| 308 | static inline uint16_t ccw_dstream_residual_count(CcwDataStream *cds) |
| 309 | { |
| 310 | return cds->count - cds->at_byte; |
| 311 | } |
| 312 | |
| 313 | static inline uint16_t ccw_dstream_avail(CcwDataStream *cds) |
| 314 | { |
| 315 | return ccw_dstream_good(cds) ? ccw_dstream_residual_count(cds) : 0; |
| 316 | } |
| 317 | |
| 318 | static inline int ccw_dstream_advance(CcwDataStream *cds, int len) |
| 319 | { |
| 320 | return cds->op_handler(cds, NULL, len, CDS_OP_A); |
| 321 | } |
| 322 | |
| 323 | static inline int ccw_dstream_write_buf(CcwDataStream *cds, void *buff, int len) |
| 324 | { |
| 325 | return cds->op_handler(cds, buff, len, CDS_OP_W); |
| 326 | } |
| 327 | |
| 328 | static inline int ccw_dstream_read_buf(CcwDataStream *cds, void *buff, int len) |
| 329 | { |
| 330 | return cds->op_handler(cds, buff, len, CDS_OP_R); |
| 331 | } |
| 332 | |
| 333 | #define ccw_dstream_read(cds, v) ccw_dstream_read_buf((cds), &(v), sizeof(v)) |
| 334 | #define ccw_dstream_write(cds, v) ccw_dstream_write_buf((cds), &(v), sizeof(v)) |
| 335 | |
Paolo Bonzini | a55ae46 | 2024-05-09 19:00:34 +0200 | [diff] [blame] | 336 | /** |
| 337 | * true if (vmstate based) migration of the channel subsystem |
| 338 | * is enabled, false if it is disabled. |
| 339 | */ |
| 340 | extern bool css_migration_enabled; |
| 341 | |
Cornelia Huck | df1fe5b | 2013-01-24 02:28:06 +0000 | [diff] [blame] | 342 | #endif |