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j_mayer008ff9d2007-10-07 14:21:26 +00001/*
2 * QEMU PowerPC 4xx emulation shared definitions
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#if !defined(PPC_4XX_H)
26#define PPC_4XX_H
27
aurel32825bb582008-12-02 23:53:50 +000028#include "pci.h"
29
j_mayer008ff9d2007-10-07 14:21:26 +000030/* PowerPC 4xx core initialization */
blueswir1b55266b2008-09-20 08:07:15 +000031CPUState *ppc4xx_init (const char *cpu_model,
Anthony Liguoric227f092009-10-01 16:12:16 -050032 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
j_mayer008ff9d2007-10-07 14:21:26 +000033 uint32_t sysclk);
34
j_mayer008ff9d2007-10-07 14:21:26 +000035/* PowerPC 4xx universal interrupt controller */
36enum {
37 PPCUIC_OUTPUT_INT = 0,
38 PPCUIC_OUTPUT_CINT = 1,
39 PPCUIC_OUTPUT_NB,
40};
41qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
42 uint32_t dcr_base, int has_ssr, int has_vr);
43
Anthony Liguoric227f092009-10-01 16:12:16 -050044ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
45 target_phys_addr_t ram_bases[],
46 target_phys_addr_t ram_sizes[],
aurel32b7da58f2008-12-15 23:15:56 +000047 const unsigned int sdram_bank_sizes[]);
48
aurel3280e8bd22008-12-15 22:59:45 +000049void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
Anthony Liguoric227f092009-10-01 16:12:16 -050050 target_phys_addr_t *ram_bases,
51 target_phys_addr_t *ram_sizes,
aurel3261b24402008-12-15 22:59:34 +000052 int do_init);
53
aurel32825bb582008-12-02 23:53:50 +000054PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
Anthony Liguoric227f092009-10-01 16:12:16 -050055 target_phys_addr_t config_space,
56 target_phys_addr_t int_ack,
57 target_phys_addr_t special_cycle,
58 target_phys_addr_t registers);
aurel32825bb582008-12-02 23:53:50 +000059
j_mayer008ff9d2007-10-07 14:21:26 +000060#endif /* !defined(PPC_4XX_H) */