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Paolo Bonzinicb9c3772012-12-06 12:15:58 +01001#ifndef HW_PCNET_H
2#define HW_PCNET_H 1
3
Gerd Hoffmann94e1a912009-10-21 15:25:33 +02004#define PCNET_IOPORT_SIZE 0x20
5#define PCNET_PNPMMIO_SIZE 0x20
6
7#define PCNET_LOOPTEST_CRC 1
8#define PCNET_LOOPTEST_NOCRC 2
9
Paolo Bonzini022c62c2012-12-17 18:19:49 +010010#include "exec/memory.h"
Gerd Hoffmann94e1a912009-10-21 15:25:33 +020011
Jan Kiszka488a1a52011-09-26 19:01:44 +020012/* BUS CONFIGURATION REGISTERS */
13#define BCR_MSRDA 0
14#define BCR_MSWRA 1
15#define BCR_MC 2
16#define BCR_LNKST 4
17#define BCR_LED1 5
18#define BCR_LED2 6
19#define BCR_LED3 7
20#define BCR_FDC 9
21#define BCR_BSBC 18
22#define BCR_EECAS 19
23#define BCR_SWS 20
24#define BCR_PLAT 22
25
Jan Kiszkaef45c912012-02-29 15:37:43 +010026#define BCR_TMAULOOP(S) !!((S)->bcr[BCR_MC ] & 0x4000)
Jan Kiszka488a1a52011-09-26 19:01:44 +020027#define BCR_APROMWE(S) !!((S)->bcr[BCR_MC ] & 0x0100)
28#define BCR_DWIO(S) !!((S)->bcr[BCR_BSBC] & 0x0080)
29#define BCR_SSIZE32(S) !!((S)->bcr[BCR_SWS ] & 0x0100)
30#define BCR_SWSTYLE(S) ((S)->bcr[BCR_SWS ] & 0x00FF)
31
Gerd Hoffmann94e1a912009-10-21 15:25:33 +020032typedef struct PCNetState_st PCNetState;
33
34struct PCNetState_st {
Mark McLoughlin1fa51482009-11-25 18:49:15 +000035 NICState *nic;
Gerd Hoffmann94e1a912009-10-21 15:25:33 +020036 NICConf conf;
37 QEMUTimer *poll_timer;
38 int rap, isr, lnkst;
39 uint32_t rdra, tdra;
40 uint8_t prom[16];
41 uint16_t csr[128];
42 uint16_t bcr[32];
Blue Swirlfe87aa82011-08-07 19:38:49 +000043 int xmit_pos;
Gerd Hoffmann94e1a912009-10-21 15:25:33 +020044 uint64_t timer;
Avi Kivitybd8d6f72011-08-08 16:09:19 +030045 MemoryRegion mmio;
Gerd Hoffmann94e1a912009-10-21 15:25:33 +020046 uint8_t buffer[4096];
Gerd Hoffmann94e1a912009-10-21 15:25:33 +020047 qemu_irq irq;
Avi Kivitya8170e52012-10-23 12:30:10 +020048 void (*phys_mem_read)(void *dma_opaque, hwaddr addr,
Gerd Hoffmann94e1a912009-10-21 15:25:33 +020049 uint8_t *buf, int len, int do_bswap);
Avi Kivitya8170e52012-10-23 12:30:10 +020050 void (*phys_mem_write)(void *dma_opaque, hwaddr addr,
Gerd Hoffmann94e1a912009-10-21 15:25:33 +020051 uint8_t *buf, int len, int do_bswap);
52 void *dma_opaque;
Blue Swirlfe87aa82011-08-07 19:38:49 +000053 int tx_busy;
Gerd Hoffmann94e1a912009-10-21 15:25:33 +020054 int looptest;
55};
56
57void pcnet_h_reset(void *opaque);
58void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val);
59uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr);
Paul Brooka4c75a22010-11-27 11:23:34 +000060void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val);
61uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr);
62uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap);
Stefan Hajnoczi4e68f7a2012-07-24 16:35:13 +010063int pcnet_can_receive(NetClientState *nc);
64ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_);
65void pcnet_set_link_status(NetClientState *nc);
Mark McLoughlin1fa51482009-11-25 18:49:15 +000066int pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info);
Juan Quintela3d865052009-10-19 18:02:13 +020067extern const VMStateDescription vmstate_pcnet;
Paolo Bonzinicb9c3772012-12-06 12:15:58 +010068#endif