bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Tiny Code Generator for QEMU |
| 3 | * |
| 4 | * Copyright (c) 2008 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | #include "tcg.h" |
| 25 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 26 | int gen_new_label(void); |
| 27 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 28 | static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 29 | { |
| 30 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 31 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 32 | } |
| 33 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 34 | static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 35 | { |
| 36 | *gen_opc_ptr++ = opc; |
| 37 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 38 | } |
| 39 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 40 | static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 41 | { |
| 42 | *gen_opc_ptr++ = opc; |
| 43 | *gen_opparam_ptr++ = arg1; |
| 44 | } |
| 45 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 46 | static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 47 | { |
| 48 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 49 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 50 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 51 | } |
| 52 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 53 | static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 54 | { |
| 55 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 56 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 57 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 58 | } |
| 59 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 60 | static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 61 | { |
| 62 | *gen_opc_ptr++ = opc; |
| 63 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 64 | *gen_opparam_ptr++ = arg2; |
| 65 | } |
| 66 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 67 | static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 68 | { |
| 69 | *gen_opc_ptr++ = opc; |
| 70 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 71 | *gen_opparam_ptr++ = arg2; |
| 72 | } |
| 73 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 74 | static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2) |
pbrook | bcb0126 | 2008-05-24 02:24:25 +0000 | [diff] [blame] | 75 | { |
| 76 | *gen_opc_ptr++ = opc; |
| 77 | *gen_opparam_ptr++ = arg1; |
| 78 | *gen_opparam_ptr++ = arg2; |
| 79 | } |
| 80 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 81 | static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 82 | TCGv_i32 arg3) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 83 | { |
| 84 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 85 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 86 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 87 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 88 | } |
| 89 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 90 | static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 91 | TCGv_i64 arg3) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 92 | { |
| 93 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 94 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 95 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 96 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 97 | } |
| 98 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 99 | static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1, |
| 100 | TCGv_i32 arg2, TCGArg arg3) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 101 | { |
| 102 | *gen_opc_ptr++ = opc; |
| 103 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 104 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 105 | *gen_opparam_ptr++ = arg3; |
| 106 | } |
| 107 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 108 | static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1, |
| 109 | TCGv_i64 arg2, TCGArg arg3) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 110 | { |
| 111 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 112 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 113 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 114 | *gen_opparam_ptr++ = arg3; |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 115 | } |
| 116 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 117 | static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
| 118 | TCGv_ptr base, TCGArg offset) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 119 | { |
| 120 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 121 | *gen_opparam_ptr++ = GET_TCGV_I32(val); |
| 122 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); |
| 123 | *gen_opparam_ptr++ = offset; |
| 124 | } |
| 125 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 126 | static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
| 127 | TCGv_ptr base, TCGArg offset) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 128 | { |
| 129 | *gen_opc_ptr++ = opc; |
blueswir1 | a810a2d | 2008-12-07 17:16:42 +0000 | [diff] [blame] | 130 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 131 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); |
| 132 | *gen_opparam_ptr++ = offset; |
| 133 | } |
| 134 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 135 | static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val, |
| 136 | TCGv_i32 addr, TCGArg mem_index) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 137 | { |
| 138 | *gen_opc_ptr++ = opc; |
| 139 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
| 140 | *gen_opparam_ptr++ = GET_TCGV_I32(addr); |
| 141 | *gen_opparam_ptr++ = mem_index; |
| 142 | } |
| 143 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 144 | static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val, |
| 145 | TCGv_i64 addr, TCGArg mem_index) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 146 | { |
| 147 | *gen_opc_ptr++ = opc; |
| 148 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
| 149 | *gen_opparam_ptr++ = GET_TCGV_I64(addr); |
| 150 | *gen_opparam_ptr++ = mem_index; |
| 151 | } |
| 152 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 153 | static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 154 | TCGv_i32 arg3, TCGv_i32 arg4) |
| 155 | { |
| 156 | *gen_opc_ptr++ = opc; |
| 157 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 158 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 159 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 160 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
| 161 | } |
| 162 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 163 | static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
blueswir1 | a810a2d | 2008-12-07 17:16:42 +0000 | [diff] [blame] | 164 | TCGv_i64 arg3, TCGv_i64 arg4) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 165 | { |
| 166 | *gen_opc_ptr++ = opc; |
| 167 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 168 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 169 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 170 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
| 171 | } |
| 172 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 173 | static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 174 | TCGv_i32 arg3, TCGArg arg4) |
| 175 | { |
| 176 | *gen_opc_ptr++ = opc; |
| 177 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 178 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 179 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 180 | *gen_opparam_ptr++ = arg4; |
| 181 | } |
| 182 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 183 | static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 184 | TCGv_i64 arg3, TCGArg arg4) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 185 | { |
| 186 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 187 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 188 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 189 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 190 | *gen_opparam_ptr++ = arg4; |
| 191 | } |
| 192 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 193 | static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 194 | TCGArg arg3, TCGArg arg4) |
| 195 | { |
| 196 | *gen_opc_ptr++ = opc; |
| 197 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 198 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 199 | *gen_opparam_ptr++ = arg3; |
| 200 | *gen_opparam_ptr++ = arg4; |
| 201 | } |
| 202 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 203 | static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 204 | TCGArg arg3, TCGArg arg4) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 205 | { |
| 206 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 207 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 208 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 209 | *gen_opparam_ptr++ = arg3; |
| 210 | *gen_opparam_ptr++ = arg4; |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 211 | } |
| 212 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 213 | static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 214 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 215 | { |
| 216 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 217 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 218 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 219 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 220 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
| 221 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
| 222 | } |
| 223 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 224 | static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 225 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) |
| 226 | { |
| 227 | *gen_opc_ptr++ = opc; |
| 228 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 229 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 230 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 231 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
| 232 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
| 233 | } |
| 234 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 235 | static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 236 | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) |
| 237 | { |
| 238 | *gen_opc_ptr++ = opc; |
| 239 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 240 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 241 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 242 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 243 | *gen_opparam_ptr++ = arg5; |
| 244 | } |
| 245 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 246 | static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 247 | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 248 | { |
| 249 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 250 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 251 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 252 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 253 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
| 254 | *gen_opparam_ptr++ = arg5; |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 255 | } |
| 256 | |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 257 | static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1, |
| 258 | TCGv_i32 arg2, TCGv_i32 arg3, |
| 259 | TCGArg arg4, TCGArg arg5) |
| 260 | { |
| 261 | *gen_opc_ptr++ = opc; |
| 262 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 263 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 264 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 265 | *gen_opparam_ptr++ = arg4; |
| 266 | *gen_opparam_ptr++ = arg5; |
| 267 | } |
| 268 | |
| 269 | static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1, |
| 270 | TCGv_i64 arg2, TCGv_i64 arg3, |
| 271 | TCGArg arg4, TCGArg arg5) |
| 272 | { |
| 273 | *gen_opc_ptr++ = opc; |
| 274 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 275 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 276 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 277 | *gen_opparam_ptr++ = arg4; |
| 278 | *gen_opparam_ptr++ = arg5; |
| 279 | } |
| 280 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 281 | static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 282 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, |
| 283 | TCGv_i32 arg6) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 284 | { |
| 285 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 286 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 287 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 288 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 289 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
| 290 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
| 291 | *gen_opparam_ptr++ = GET_TCGV_I32(arg6); |
| 292 | } |
| 293 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 294 | static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 295 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, |
| 296 | TCGv_i64 arg6) |
| 297 | { |
| 298 | *gen_opc_ptr++ = opc; |
| 299 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 300 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 301 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 302 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
| 303 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
| 304 | *gen_opparam_ptr++ = GET_TCGV_I64(arg6); |
| 305 | } |
| 306 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 307 | static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 308 | TCGv_i32 arg3, TCGv_i32 arg4, |
| 309 | TCGv_i32 arg5, TCGArg arg6) |
| 310 | { |
| 311 | *gen_opc_ptr++ = opc; |
| 312 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 313 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 314 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 315 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
| 316 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
| 317 | *gen_opparam_ptr++ = arg6; |
| 318 | } |
| 319 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 320 | static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 321 | TCGv_i64 arg3, TCGv_i64 arg4, |
| 322 | TCGv_i64 arg5, TCGArg arg6) |
| 323 | { |
| 324 | *gen_opc_ptr++ = opc; |
| 325 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 326 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 327 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 328 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
| 329 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
| 330 | *gen_opparam_ptr++ = arg6; |
| 331 | } |
| 332 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 333 | static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1, |
| 334 | TCGv_i32 arg2, TCGv_i32 arg3, |
| 335 | TCGv_i32 arg4, TCGArg arg5, TCGArg arg6) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 336 | { |
| 337 | *gen_opc_ptr++ = opc; |
| 338 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 339 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 340 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 341 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
| 342 | *gen_opparam_ptr++ = arg5; |
| 343 | *gen_opparam_ptr++ = arg6; |
| 344 | } |
| 345 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 346 | static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1, |
| 347 | TCGv_i64 arg2, TCGv_i64 arg3, |
| 348 | TCGv_i64 arg4, TCGArg arg5, TCGArg arg6) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 349 | { |
| 350 | *gen_opc_ptr++ = opc; |
| 351 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 352 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 353 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 354 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 355 | *gen_opparam_ptr++ = arg5; |
| 356 | *gen_opparam_ptr++ = arg6; |
| 357 | } |
| 358 | |
| 359 | static inline void gen_set_label(int n) |
| 360 | { |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 361 | tcg_gen_op1i(INDEX_op_set_label, n); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 362 | } |
| 363 | |
blueswir1 | fb50d41 | 2008-03-21 17:58:45 +0000 | [diff] [blame] | 364 | static inline void tcg_gen_br(int label) |
| 365 | { |
| 366 | tcg_gen_op1i(INDEX_op_br, label); |
| 367 | } |
| 368 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 369 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 370 | { |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 371 | if (!TCGV_EQUAL_I32(ret, arg)) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 372 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 373 | } |
| 374 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 375 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 376 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 377 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 378 | } |
| 379 | |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 380 | /* A version of dh_sizemask from def-helper.h that doesn't rely on |
| 381 | preprocessor magic. */ |
| 382 | static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed) |
| 383 | { |
| 384 | return (is_64bit << n*2) | (is_signed << (n*2 + 1)); |
| 385 | } |
| 386 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 387 | /* helper calls */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 388 | static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
| 389 | TCGArg ret, int nargs, TCGArg *args) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 390 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 391 | TCGv_ptr fn; |
Peter Maydell | 73f5e31 | 2011-12-10 16:35:31 +0000 | [diff] [blame] | 392 | fn = tcg_const_ptr(func); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 393 | tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, |
| 394 | nargs, args); |
| 395 | tcg_temp_free_ptr(fn); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 396 | } |
| 397 | |
Aurelien Jarno | dbfff4d | 2010-03-14 23:01:01 +0100 | [diff] [blame] | 398 | /* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently |
| 399 | reserved for helpers in tcg-runtime.c. These helpers are all const |
| 400 | and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST | |
| 401 | TCG_CALL_PURE. This may need to be adjusted if these functions |
| 402 | start to be used with other helpers. */ |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 403 | static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret, |
Aurelien Jarno | 31d6655 | 2010-03-02 23:16:36 +0100 | [diff] [blame] | 404 | TCGv_i32 a, TCGv_i32 b) |
| 405 | { |
| 406 | TCGv_ptr fn; |
| 407 | TCGArg args[2]; |
Peter Maydell | 73f5e31 | 2011-12-10 16:35:31 +0000 | [diff] [blame] | 408 | fn = tcg_const_ptr(func); |
Aurelien Jarno | 31d6655 | 2010-03-02 23:16:36 +0100 | [diff] [blame] | 409 | args[0] = GET_TCGV_I32(a); |
| 410 | args[1] = GET_TCGV_I32(b); |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 411 | tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask, |
| 412 | GET_TCGV_I32(ret), 2, args); |
Aurelien Jarno | 31d6655 | 2010-03-02 23:16:36 +0100 | [diff] [blame] | 413 | tcg_temp_free_ptr(fn); |
| 414 | } |
| 415 | |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 416 | static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 417 | TCGv_i64 a, TCGv_i64 b) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 418 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 419 | TCGv_ptr fn; |
| 420 | TCGArg args[2]; |
Peter Maydell | 73f5e31 | 2011-12-10 16:35:31 +0000 | [diff] [blame] | 421 | fn = tcg_const_ptr(func); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 422 | args[0] = GET_TCGV_I64(a); |
| 423 | args[1] = GET_TCGV_I64(b); |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 424 | tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask, |
| 425 | GET_TCGV_I64(ret), 2, args); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 426 | tcg_temp_free_ptr(fn); |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 427 | } |
| 428 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 429 | /* 32 bit ops */ |
| 430 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 431 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 432 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 433 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 434 | } |
| 435 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 436 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 437 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 438 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 439 | } |
| 440 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 441 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 442 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 443 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 444 | } |
| 445 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 446 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 447 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 448 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 449 | } |
| 450 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 451 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 452 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 453 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 454 | } |
| 455 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 456 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 457 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 458 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 459 | } |
| 460 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 461 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 462 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 463 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 464 | } |
| 465 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 466 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 467 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 468 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 469 | } |
| 470 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 471 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 472 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 473 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 474 | } |
| 475 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 476 | static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 477 | { |
blueswir1 | 7089442 | 2008-02-20 18:01:23 +0000 | [diff] [blame] | 478 | /* some cases can be optimized here */ |
| 479 | if (arg2 == 0) { |
| 480 | tcg_gen_mov_i32(ret, arg1); |
| 481 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 482 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 483 | tcg_gen_add_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 484 | tcg_temp_free_i32(t0); |
blueswir1 | 7089442 | 2008-02-20 18:01:23 +0000 | [diff] [blame] | 485 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 486 | } |
| 487 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 488 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 489 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 490 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 491 | } |
| 492 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 493 | static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 494 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 495 | TCGv_i32 t0 = tcg_const_i32(arg1); |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 496 | tcg_gen_sub_i32(ret, t0, arg2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 497 | tcg_temp_free_i32(t0); |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 498 | } |
| 499 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 500 | static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 501 | { |
blueswir1 | 7089442 | 2008-02-20 18:01:23 +0000 | [diff] [blame] | 502 | /* some cases can be optimized here */ |
| 503 | if (arg2 == 0) { |
| 504 | tcg_gen_mov_i32(ret, arg1); |
| 505 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 506 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 507 | tcg_gen_sub_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 508 | tcg_temp_free_i32(t0); |
blueswir1 | 7089442 | 2008-02-20 18:01:23 +0000 | [diff] [blame] | 509 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 510 | } |
| 511 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 512 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 513 | { |
aurel32 | 7fc8105 | 2009-03-10 19:37:39 +0000 | [diff] [blame] | 514 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
| 515 | tcg_gen_mov_i32(ret, arg1); |
| 516 | } else { |
| 517 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); |
| 518 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 519 | } |
| 520 | |
Richard Henderson | 42ce3e2 | 2012-09-21 17:18:10 -0700 | [diff] [blame] | 521 | static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 522 | { |
Richard Henderson | 42ce3e2 | 2012-09-21 17:18:10 -0700 | [diff] [blame] | 523 | TCGv_i32 t0; |
| 524 | /* Some cases can be optimized here. */ |
| 525 | switch (arg2) { |
| 526 | case 0: |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 527 | tcg_gen_movi_i32(ret, 0); |
Richard Henderson | 42ce3e2 | 2012-09-21 17:18:10 -0700 | [diff] [blame] | 528 | return; |
| 529 | case 0xffffffffu: |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 530 | tcg_gen_mov_i32(ret, arg1); |
Richard Henderson | 42ce3e2 | 2012-09-21 17:18:10 -0700 | [diff] [blame] | 531 | return; |
| 532 | case 0xffu: |
| 533 | /* Don't recurse with tcg_gen_ext8u_i32. */ |
| 534 | if (TCG_TARGET_HAS_ext8u_i32) { |
| 535 | tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1); |
| 536 | return; |
| 537 | } |
| 538 | break; |
| 539 | case 0xffffu: |
| 540 | if (TCG_TARGET_HAS_ext16u_i32) { |
| 541 | tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1); |
| 542 | return; |
| 543 | } |
| 544 | break; |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 545 | } |
Richard Henderson | 42ce3e2 | 2012-09-21 17:18:10 -0700 | [diff] [blame] | 546 | t0 = tcg_const_i32(arg2); |
| 547 | tcg_gen_and_i32(ret, arg1, t0); |
| 548 | tcg_temp_free_i32(t0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 549 | } |
| 550 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 551 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 552 | { |
aurel32 | 7fc8105 | 2009-03-10 19:37:39 +0000 | [diff] [blame] | 553 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
| 554 | tcg_gen_mov_i32(ret, arg1); |
| 555 | } else { |
| 556 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); |
| 557 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 558 | } |
| 559 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 560 | static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 561 | { |
Richard Henderson | d81ada7 | 2012-09-21 17:18:11 -0700 | [diff] [blame] | 562 | /* Some cases can be optimized here. */ |
| 563 | if (arg2 == -1) { |
| 564 | tcg_gen_movi_i32(ret, -1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 565 | } else if (arg2 == 0) { |
| 566 | tcg_gen_mov_i32(ret, arg1); |
| 567 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 568 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 569 | tcg_gen_or_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 570 | tcg_temp_free_i32(t0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 571 | } |
| 572 | } |
| 573 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 574 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 575 | { |
aurel32 | 7fc8105 | 2009-03-10 19:37:39 +0000 | [diff] [blame] | 576 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
| 577 | tcg_gen_movi_i32(ret, 0); |
| 578 | } else { |
| 579 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); |
| 580 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 581 | } |
| 582 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 583 | static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 584 | { |
Richard Henderson | 6f3bb33 | 2012-09-21 17:18:12 -0700 | [diff] [blame] | 585 | /* Some cases can be optimized here. */ |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 586 | if (arg2 == 0) { |
| 587 | tcg_gen_mov_i32(ret, arg1); |
Richard Henderson | 6f3bb33 | 2012-09-21 17:18:12 -0700 | [diff] [blame] | 588 | } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) { |
| 589 | /* Don't recurse with tcg_gen_not_i32. */ |
| 590 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 591 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 592 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 593 | tcg_gen_xor_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 594 | tcg_temp_free_i32(t0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 595 | } |
| 596 | } |
| 597 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 598 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 599 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 600 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 601 | } |
| 602 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 603 | static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 604 | { |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 605 | if (arg2 == 0) { |
| 606 | tcg_gen_mov_i32(ret, arg1); |
| 607 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 608 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 609 | tcg_gen_shl_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 610 | tcg_temp_free_i32(t0); |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 611 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 612 | } |
| 613 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 614 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 615 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 616 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 617 | } |
| 618 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 619 | static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 620 | { |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 621 | if (arg2 == 0) { |
| 622 | tcg_gen_mov_i32(ret, arg1); |
| 623 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 624 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 625 | tcg_gen_shr_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 626 | tcg_temp_free_i32(t0); |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 627 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 628 | } |
| 629 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 630 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 631 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 632 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 633 | } |
| 634 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 635 | static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 636 | { |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 637 | if (arg2 == 0) { |
| 638 | tcg_gen_mov_i32(ret, arg1); |
| 639 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 640 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 641 | tcg_gen_sar_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 642 | tcg_temp_free_i32(t0); |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 643 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 644 | } |
| 645 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 646 | static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, |
| 647 | TCGv_i32 arg2, int label_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 648 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 649 | tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 650 | } |
| 651 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 652 | static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, |
| 653 | int32_t arg2, int label_index) |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 654 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 655 | TCGv_i32 t0 = tcg_const_i32(arg2); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 656 | tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 657 | tcg_temp_free_i32(t0); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 658 | } |
| 659 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 660 | static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, |
Aurelien Jarno | 5105c55 | 2010-02-08 12:10:15 +0100 | [diff] [blame] | 661 | TCGv_i32 arg1, TCGv_i32 arg2) |
| 662 | { |
| 663 | tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); |
| 664 | } |
| 665 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 666 | static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, |
| 667 | TCGv_i32 arg1, int32_t arg2) |
Aurelien Jarno | 5105c55 | 2010-02-08 12:10:15 +0100 | [diff] [blame] | 668 | { |
| 669 | TCGv_i32 t0 = tcg_const_i32(arg2); |
| 670 | tcg_gen_setcond_i32(cond, ret, arg1, t0); |
| 671 | tcg_temp_free_i32(t0); |
| 672 | } |
| 673 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 674 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 675 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 676 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 677 | } |
| 678 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 679 | static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 680 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 681 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 682 | tcg_gen_mul_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 683 | tcg_temp_free_i32(t0); |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 684 | } |
| 685 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 686 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 687 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 688 | if (TCG_TARGET_HAS_div_i32) { |
| 689 | tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); |
| 690 | } else if (TCG_TARGET_HAS_div2_i32) { |
| 691 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 692 | tcg_gen_sari_i32(t0, arg1, 31); |
| 693 | tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
| 694 | tcg_temp_free_i32(t0); |
| 695 | } else { |
| 696 | int sizemask = 0; |
| 697 | /* Return value and both arguments are 32-bit and signed. */ |
| 698 | sizemask |= tcg_gen_sizemask(0, 0, 1); |
| 699 | sizemask |= tcg_gen_sizemask(1, 0, 1); |
| 700 | sizemask |= tcg_gen_sizemask(2, 0, 1); |
| 701 | tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2); |
| 702 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 703 | } |
| 704 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 705 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 706 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 707 | if (TCG_TARGET_HAS_div_i32) { |
| 708 | tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); |
| 709 | } else if (TCG_TARGET_HAS_div2_i32) { |
| 710 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 711 | tcg_gen_sari_i32(t0, arg1, 31); |
| 712 | tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
| 713 | tcg_temp_free_i32(t0); |
| 714 | } else { |
| 715 | int sizemask = 0; |
| 716 | /* Return value and both arguments are 32-bit and signed. */ |
| 717 | sizemask |= tcg_gen_sizemask(0, 0, 1); |
| 718 | sizemask |= tcg_gen_sizemask(1, 0, 1); |
| 719 | sizemask |= tcg_gen_sizemask(2, 0, 1); |
| 720 | tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2); |
| 721 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 722 | } |
| 723 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 724 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 725 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 726 | if (TCG_TARGET_HAS_div_i32) { |
| 727 | tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); |
| 728 | } else if (TCG_TARGET_HAS_div2_i32) { |
| 729 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 730 | tcg_gen_movi_i32(t0, 0); |
| 731 | tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
| 732 | tcg_temp_free_i32(t0); |
| 733 | } else { |
| 734 | int sizemask = 0; |
| 735 | /* Return value and both arguments are 32-bit and unsigned. */ |
| 736 | sizemask |= tcg_gen_sizemask(0, 0, 0); |
| 737 | sizemask |= tcg_gen_sizemask(1, 0, 0); |
| 738 | sizemask |= tcg_gen_sizemask(2, 0, 0); |
| 739 | tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2); |
| 740 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 741 | } |
| 742 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 743 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 744 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 745 | if (TCG_TARGET_HAS_div_i32) { |
| 746 | tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); |
| 747 | } else if (TCG_TARGET_HAS_div2_i32) { |
| 748 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 749 | tcg_gen_movi_i32(t0, 0); |
| 750 | tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
| 751 | tcg_temp_free_i32(t0); |
| 752 | } else { |
| 753 | int sizemask = 0; |
| 754 | /* Return value and both arguments are 32-bit and unsigned. */ |
| 755 | sizemask |= tcg_gen_sizemask(0, 0, 0); |
| 756 | sizemask |= tcg_gen_sizemask(1, 0, 0); |
| 757 | sizemask |= tcg_gen_sizemask(2, 0, 0); |
| 758 | tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2); |
| 759 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 760 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 761 | |
| 762 | #if TCG_TARGET_REG_BITS == 32 |
| 763 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 764 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 765 | { |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 766 | if (!TCGV_EQUAL_I64(ret, arg)) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 767 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
blueswir1 | 4d07272 | 2008-05-03 20:52:26 +0000 | [diff] [blame] | 768 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
| 769 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 770 | } |
| 771 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 772 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 773 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 774 | tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 775 | tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 776 | } |
| 777 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 778 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 779 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 780 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 781 | tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 782 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 783 | } |
| 784 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 785 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 786 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 787 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 788 | tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
| 789 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 790 | } |
| 791 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 792 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 793 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 794 | { |
aurel32 | a747723 | 2009-02-09 20:43:53 +0000 | [diff] [blame] | 795 | tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 796 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 797 | } |
| 798 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 799 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 800 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 801 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 802 | tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
| 803 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 804 | } |
| 805 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 806 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 807 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 808 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 809 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 810 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 811 | } |
| 812 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 813 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 814 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 815 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 816 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
| 817 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 818 | } |
| 819 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 820 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 821 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 822 | { |
| 823 | /* since arg2 and ret have different types, they cannot be the |
| 824 | same temporary */ |
| 825 | #ifdef TCG_TARGET_WORDS_BIGENDIAN |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 826 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 827 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 828 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 829 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 830 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 831 | #endif |
| 832 | } |
| 833 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 834 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 835 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 836 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 837 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 838 | } |
| 839 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 840 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 841 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 842 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 843 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 844 | } |
| 845 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 846 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 847 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 848 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 849 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 850 | } |
| 851 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 852 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 853 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 854 | { |
| 855 | #ifdef TCG_TARGET_WORDS_BIGENDIAN |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 856 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 857 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 858 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 859 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 860 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 861 | #endif |
| 862 | } |
| 863 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 864 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 865 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 866 | tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
| 867 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
| 868 | TCGV_HIGH(arg2)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 869 | } |
| 870 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 871 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 872 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 873 | tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
| 874 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
| 875 | TCGV_HIGH(arg2)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 876 | } |
| 877 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 878 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 879 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 880 | tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 881 | tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 882 | } |
| 883 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 884 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 885 | { |
aurel32 | e510508 | 2009-03-11 02:57:30 +0000 | [diff] [blame] | 886 | tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
| 887 | tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 888 | } |
| 889 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 890 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 891 | { |
aurel32 | e510508 | 2009-03-11 02:57:30 +0000 | [diff] [blame] | 892 | tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 893 | tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 894 | } |
| 895 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 896 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 897 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 898 | tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 899 | tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 900 | } |
| 901 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 902 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 903 | { |
aurel32 | e510508 | 2009-03-11 02:57:30 +0000 | [diff] [blame] | 904 | tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 905 | tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 906 | } |
| 907 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 908 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 909 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 910 | tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 911 | tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 912 | } |
| 913 | |
| 914 | /* XXX: use generic code when basic block handling is OK or CPU |
| 915 | specific code (x86) */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 916 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 917 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 918 | int sizemask = 0; |
| 919 | /* Return value and both arguments are 64-bit and signed. */ |
| 920 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 921 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 922 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 923 | |
| 924 | tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 925 | } |
| 926 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 927 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 928 | { |
| 929 | tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
| 930 | } |
| 931 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 932 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 933 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 934 | int sizemask = 0; |
| 935 | /* Return value and both arguments are 64-bit and signed. */ |
| 936 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 937 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 938 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 939 | |
| 940 | tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 941 | } |
| 942 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 943 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 944 | { |
| 945 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
| 946 | } |
| 947 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 948 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 949 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 950 | int sizemask = 0; |
| 951 | /* Return value and both arguments are 64-bit and signed. */ |
| 952 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 953 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 954 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 955 | |
| 956 | tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 957 | } |
| 958 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 959 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 960 | { |
| 961 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
| 962 | } |
| 963 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 964 | static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
| 965 | TCGv_i64 arg2, int label_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 966 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 967 | tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, |
| 968 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
| 969 | TCGV_HIGH(arg2), cond, label_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 970 | } |
| 971 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 972 | static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
Aurelien Jarno | 5105c55 | 2010-02-08 12:10:15 +0100 | [diff] [blame] | 973 | TCGv_i64 arg1, TCGv_i64 arg2) |
| 974 | { |
| 975 | tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), |
| 976 | TCGV_LOW(arg1), TCGV_HIGH(arg1), |
| 977 | TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); |
| 978 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
| 979 | } |
| 980 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 981 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 982 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 983 | TCGv_i64 t0; |
| 984 | TCGv_i32 t1; |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 985 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 986 | t0 = tcg_temp_new_i64(); |
| 987 | t1 = tcg_temp_new_i32(); |
| 988 | |
| 989 | tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), |
| 990 | TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 991 | |
| 992 | tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 993 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 994 | tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 995 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 996 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 997 | tcg_gen_mov_i64(ret, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 998 | tcg_temp_free_i64(t0); |
| 999 | tcg_temp_free_i32(t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1000 | } |
| 1001 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1002 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1003 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 1004 | int sizemask = 0; |
| 1005 | /* Return value and both arguments are 64-bit and signed. */ |
| 1006 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 1007 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 1008 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 1009 | |
| 1010 | tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1011 | } |
| 1012 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1013 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1014 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 1015 | int sizemask = 0; |
| 1016 | /* Return value and both arguments are 64-bit and signed. */ |
| 1017 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 1018 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 1019 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 1020 | |
| 1021 | tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1022 | } |
| 1023 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1024 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1025 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 1026 | int sizemask = 0; |
| 1027 | /* Return value and both arguments are 64-bit and unsigned. */ |
| 1028 | sizemask |= tcg_gen_sizemask(0, 1, 0); |
| 1029 | sizemask |= tcg_gen_sizemask(1, 1, 0); |
| 1030 | sizemask |= tcg_gen_sizemask(2, 1, 0); |
| 1031 | |
| 1032 | tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1033 | } |
| 1034 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1035 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1036 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 1037 | int sizemask = 0; |
| 1038 | /* Return value and both arguments are 64-bit and unsigned. */ |
| 1039 | sizemask |= tcg_gen_sizemask(0, 1, 0); |
| 1040 | sizemask |= tcg_gen_sizemask(1, 1, 0); |
| 1041 | sizemask |= tcg_gen_sizemask(2, 1, 0); |
| 1042 | |
| 1043 | tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1044 | } |
| 1045 | |
| 1046 | #else |
| 1047 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1048 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1049 | { |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 1050 | if (!TCGV_EQUAL_I64(ret, arg)) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1051 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1052 | } |
| 1053 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1054 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1055 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1056 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1057 | } |
| 1058 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1059 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1060 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1061 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1062 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1063 | } |
| 1064 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1065 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1066 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1067 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1068 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1069 | } |
| 1070 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1071 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1072 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1073 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1074 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1075 | } |
| 1076 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1077 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1078 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1079 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1080 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1081 | } |
| 1082 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1083 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1084 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1085 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1086 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1087 | } |
| 1088 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1089 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1090 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1091 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1092 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1093 | } |
| 1094 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1095 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1096 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1097 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1098 | } |
| 1099 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1100 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1101 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1102 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1103 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1104 | } |
| 1105 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1106 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1107 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1108 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1109 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1110 | } |
| 1111 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1112 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1113 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1114 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1115 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1116 | } |
| 1117 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1118 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1119 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1120 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1121 | } |
| 1122 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1123 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1124 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1125 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1126 | } |
| 1127 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1128 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1129 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1130 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1131 | } |
| 1132 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1133 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1134 | { |
aurel32 | 7fc8105 | 2009-03-10 19:37:39 +0000 | [diff] [blame] | 1135 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
| 1136 | tcg_gen_mov_i64(ret, arg1); |
| 1137 | } else { |
| 1138 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); |
| 1139 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1140 | } |
| 1141 | |
Richard Henderson | 42ce3e2 | 2012-09-21 17:18:10 -0700 | [diff] [blame] | 1142 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1143 | { |
Richard Henderson | 42ce3e2 | 2012-09-21 17:18:10 -0700 | [diff] [blame] | 1144 | TCGv_i64 t0; |
| 1145 | /* Some cases can be optimized here. */ |
| 1146 | switch (arg2) { |
| 1147 | case 0: |
| 1148 | tcg_gen_movi_i64(ret, 0); |
| 1149 | return; |
| 1150 | case 0xffffffffffffffffull: |
| 1151 | tcg_gen_mov_i64(ret, arg1); |
| 1152 | return; |
| 1153 | case 0xffull: |
| 1154 | /* Don't recurse with tcg_gen_ext8u_i32. */ |
| 1155 | if (TCG_TARGET_HAS_ext8u_i64) { |
| 1156 | tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1); |
| 1157 | return; |
| 1158 | } |
| 1159 | break; |
| 1160 | case 0xffffu: |
| 1161 | if (TCG_TARGET_HAS_ext16u_i64) { |
| 1162 | tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1); |
| 1163 | return; |
| 1164 | } |
| 1165 | break; |
| 1166 | case 0xffffffffull: |
| 1167 | if (TCG_TARGET_HAS_ext32u_i64) { |
| 1168 | tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1); |
| 1169 | return; |
| 1170 | } |
| 1171 | break; |
| 1172 | } |
| 1173 | t0 = tcg_const_i64(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 1174 | tcg_gen_and_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1175 | tcg_temp_free_i64(t0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1176 | } |
| 1177 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1178 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1179 | { |
aurel32 | 7fc8105 | 2009-03-10 19:37:39 +0000 | [diff] [blame] | 1180 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
| 1181 | tcg_gen_mov_i64(ret, arg1); |
| 1182 | } else { |
| 1183 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); |
| 1184 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1185 | } |
| 1186 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1187 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1188 | { |
Richard Henderson | d81ada7 | 2012-09-21 17:18:11 -0700 | [diff] [blame] | 1189 | /* Some cases can be optimized here. */ |
| 1190 | if (arg2 == -1) { |
| 1191 | tcg_gen_movi_i64(ret, -1); |
| 1192 | } else if (arg2 == 0) { |
| 1193 | tcg_gen_mov_i64(ret, arg1); |
| 1194 | } else { |
| 1195 | TCGv_i64 t0 = tcg_const_i64(arg2); |
| 1196 | tcg_gen_or_i64(ret, arg1, t0); |
| 1197 | tcg_temp_free_i64(t0); |
| 1198 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1199 | } |
| 1200 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1201 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1202 | { |
aurel32 | 7fc8105 | 2009-03-10 19:37:39 +0000 | [diff] [blame] | 1203 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
| 1204 | tcg_gen_movi_i64(ret, 0); |
| 1205 | } else { |
| 1206 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); |
| 1207 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1208 | } |
| 1209 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1210 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1211 | { |
Richard Henderson | 6f3bb33 | 2012-09-21 17:18:12 -0700 | [diff] [blame] | 1212 | /* Some cases can be optimized here. */ |
| 1213 | if (arg2 == 0) { |
| 1214 | tcg_gen_mov_i64(ret, arg1); |
| 1215 | } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) { |
| 1216 | /* Don't recurse with tcg_gen_not_i64. */ |
| 1217 | tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1); |
| 1218 | } else { |
| 1219 | TCGv_i64 t0 = tcg_const_i64(arg2); |
| 1220 | tcg_gen_xor_i64(ret, arg1, t0); |
| 1221 | tcg_temp_free_i64(t0); |
| 1222 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1223 | } |
| 1224 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1225 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1226 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1227 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1228 | } |
| 1229 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1230 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1231 | { |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 1232 | if (arg2 == 0) { |
| 1233 | tcg_gen_mov_i64(ret, arg1); |
| 1234 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1235 | TCGv_i64 t0 = tcg_const_i64(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 1236 | tcg_gen_shl_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1237 | tcg_temp_free_i64(t0); |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 1238 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1239 | } |
| 1240 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1241 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1242 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1243 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1244 | } |
| 1245 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1246 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1247 | { |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 1248 | if (arg2 == 0) { |
| 1249 | tcg_gen_mov_i64(ret, arg1); |
| 1250 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1251 | TCGv_i64 t0 = tcg_const_i64(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 1252 | tcg_gen_shr_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1253 | tcg_temp_free_i64(t0); |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 1254 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1255 | } |
| 1256 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1257 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1258 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1259 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1260 | } |
| 1261 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1262 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1263 | { |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 1264 | if (arg2 == 0) { |
| 1265 | tcg_gen_mov_i64(ret, arg1); |
| 1266 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1267 | TCGv_i64 t0 = tcg_const_i64(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 1268 | tcg_gen_sar_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1269 | tcg_temp_free_i64(t0); |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 1270 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1271 | } |
| 1272 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 1273 | static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
| 1274 | TCGv_i64 arg2, int label_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1275 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1276 | tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1277 | } |
| 1278 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 1279 | static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
Aurelien Jarno | 5105c55 | 2010-02-08 12:10:15 +0100 | [diff] [blame] | 1280 | TCGv_i64 arg1, TCGv_i64 arg2) |
| 1281 | { |
| 1282 | tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); |
| 1283 | } |
| 1284 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1285 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1286 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1287 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1288 | } |
| 1289 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1290 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1291 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1292 | if (TCG_TARGET_HAS_div_i64) { |
| 1293 | tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); |
| 1294 | } else if (TCG_TARGET_HAS_div2_i64) { |
| 1295 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1296 | tcg_gen_sari_i64(t0, arg1, 63); |
| 1297 | tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
| 1298 | tcg_temp_free_i64(t0); |
| 1299 | } else { |
| 1300 | int sizemask = 0; |
| 1301 | /* Return value and both arguments are 64-bit and signed. */ |
| 1302 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 1303 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 1304 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 1305 | tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2); |
| 1306 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1307 | } |
| 1308 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1309 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1310 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1311 | if (TCG_TARGET_HAS_div_i64) { |
| 1312 | tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); |
| 1313 | } else if (TCG_TARGET_HAS_div2_i64) { |
| 1314 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1315 | tcg_gen_sari_i64(t0, arg1, 63); |
| 1316 | tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
| 1317 | tcg_temp_free_i64(t0); |
| 1318 | } else { |
| 1319 | int sizemask = 0; |
| 1320 | /* Return value and both arguments are 64-bit and signed. */ |
| 1321 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 1322 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 1323 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 1324 | tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2); |
| 1325 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1326 | } |
| 1327 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1328 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1329 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1330 | if (TCG_TARGET_HAS_div_i64) { |
| 1331 | tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); |
| 1332 | } else if (TCG_TARGET_HAS_div2_i64) { |
| 1333 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1334 | tcg_gen_movi_i64(t0, 0); |
| 1335 | tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
| 1336 | tcg_temp_free_i64(t0); |
| 1337 | } else { |
| 1338 | int sizemask = 0; |
| 1339 | /* Return value and both arguments are 64-bit and unsigned. */ |
| 1340 | sizemask |= tcg_gen_sizemask(0, 1, 0); |
| 1341 | sizemask |= tcg_gen_sizemask(1, 1, 0); |
| 1342 | sizemask |= tcg_gen_sizemask(2, 1, 0); |
| 1343 | tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2); |
| 1344 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1345 | } |
| 1346 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1347 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1348 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1349 | if (TCG_TARGET_HAS_div_i64) { |
| 1350 | tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); |
| 1351 | } else if (TCG_TARGET_HAS_div2_i64) { |
| 1352 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1353 | tcg_gen_movi_i64(t0, 0); |
| 1354 | tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
| 1355 | tcg_temp_free_i64(t0); |
| 1356 | } else { |
| 1357 | int sizemask = 0; |
| 1358 | /* Return value and both arguments are 64-bit and unsigned. */ |
| 1359 | sizemask |= tcg_gen_sizemask(0, 1, 0); |
| 1360 | sizemask |= tcg_gen_sizemask(1, 1, 0); |
| 1361 | sizemask |= tcg_gen_sizemask(2, 1, 0); |
| 1362 | tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2); |
| 1363 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1364 | } |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1365 | #endif /* TCG_TARGET_REG_BITS == 32 */ |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1366 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1367 | static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1368 | { |
| 1369 | /* some cases can be optimized here */ |
| 1370 | if (arg2 == 0) { |
| 1371 | tcg_gen_mov_i64(ret, arg1); |
| 1372 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1373 | TCGv_i64 t0 = tcg_const_i64(arg2); |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1374 | tcg_gen_add_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1375 | tcg_temp_free_i64(t0); |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1376 | } |
| 1377 | } |
| 1378 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1379 | static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 1380 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1381 | TCGv_i64 t0 = tcg_const_i64(arg1); |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 1382 | tcg_gen_sub_i64(ret, t0, arg2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1383 | tcg_temp_free_i64(t0); |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 1384 | } |
| 1385 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1386 | static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1387 | { |
| 1388 | /* some cases can be optimized here */ |
| 1389 | if (arg2 == 0) { |
| 1390 | tcg_gen_mov_i64(ret, arg1); |
| 1391 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1392 | TCGv_i64 t0 = tcg_const_i64(arg2); |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1393 | tcg_gen_sub_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1394 | tcg_temp_free_i64(t0); |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1395 | } |
| 1396 | } |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 1397 | static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, |
| 1398 | int64_t arg2, int label_index) |
aurel32 | f02bb95 | 2008-11-03 07:08:26 +0000 | [diff] [blame] | 1399 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1400 | TCGv_i64 t0 = tcg_const_i64(arg2); |
aurel32 | f02bb95 | 2008-11-03 07:08:26 +0000 | [diff] [blame] | 1401 | tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1402 | tcg_temp_free_i64(t0); |
aurel32 | f02bb95 | 2008-11-03 07:08:26 +0000 | [diff] [blame] | 1403 | } |
| 1404 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 1405 | static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, |
| 1406 | TCGv_i64 arg1, int64_t arg2) |
Aurelien Jarno | 5105c55 | 2010-02-08 12:10:15 +0100 | [diff] [blame] | 1407 | { |
| 1408 | TCGv_i64 t0 = tcg_const_i64(arg2); |
| 1409 | tcg_gen_setcond_i64(cond, ret, arg1, t0); |
| 1410 | tcg_temp_free_i64(t0); |
| 1411 | } |
| 1412 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1413 | static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
aurel32 | f02bb95 | 2008-11-03 07:08:26 +0000 | [diff] [blame] | 1414 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1415 | TCGv_i64 t0 = tcg_const_i64(arg2); |
aurel32 | f02bb95 | 2008-11-03 07:08:26 +0000 | [diff] [blame] | 1416 | tcg_gen_mul_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1417 | tcg_temp_free_i64(t0); |
aurel32 | f02bb95 | 2008-11-03 07:08:26 +0000 | [diff] [blame] | 1418 | } |
| 1419 | |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1420 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1421 | /***************************************/ |
| 1422 | /* optional operations */ |
| 1423 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1424 | static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1425 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1426 | if (TCG_TARGET_HAS_ext8s_i32) { |
| 1427 | tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); |
| 1428 | } else { |
| 1429 | tcg_gen_shli_i32(ret, arg, 24); |
| 1430 | tcg_gen_sari_i32(ret, ret, 24); |
| 1431 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1432 | } |
| 1433 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1434 | static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1435 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1436 | if (TCG_TARGET_HAS_ext16s_i32) { |
| 1437 | tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); |
| 1438 | } else { |
| 1439 | tcg_gen_shli_i32(ret, arg, 16); |
| 1440 | tcg_gen_sari_i32(ret, ret, 16); |
| 1441 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1442 | } |
| 1443 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1444 | static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1445 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1446 | if (TCG_TARGET_HAS_ext8u_i32) { |
| 1447 | tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); |
| 1448 | } else { |
| 1449 | tcg_gen_andi_i32(ret, arg, 0xffu); |
| 1450 | } |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1451 | } |
| 1452 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1453 | static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1454 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1455 | if (TCG_TARGET_HAS_ext16u_i32) { |
| 1456 | tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); |
| 1457 | } else { |
| 1458 | tcg_gen_andi_i32(ret, arg, 0xffffu); |
| 1459 | } |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1460 | } |
| 1461 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1462 | /* Note: we assume the two high bytes are set to zero */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1463 | static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1464 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1465 | if (TCG_TARGET_HAS_bswap16_i32) { |
| 1466 | tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); |
| 1467 | } else { |
| 1468 | TCGv_i32 t0 = tcg_temp_new_i32(); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1469 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1470 | tcg_gen_ext8u_i32(t0, arg); |
| 1471 | tcg_gen_shli_i32(t0, t0, 8); |
| 1472 | tcg_gen_shri_i32(ret, arg, 8); |
| 1473 | tcg_gen_or_i32(ret, ret, t0); |
| 1474 | tcg_temp_free_i32(t0); |
| 1475 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1476 | } |
| 1477 | |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 1478 | static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1479 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1480 | if (TCG_TARGET_HAS_bswap32_i32) { |
| 1481 | tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); |
| 1482 | } else { |
| 1483 | TCGv_i32 t0, t1; |
| 1484 | t0 = tcg_temp_new_i32(); |
| 1485 | t1 = tcg_temp_new_i32(); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1486 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1487 | tcg_gen_shli_i32(t0, arg, 24); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1488 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1489 | tcg_gen_andi_i32(t1, arg, 0x0000ff00); |
| 1490 | tcg_gen_shli_i32(t1, t1, 8); |
| 1491 | tcg_gen_or_i32(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1492 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1493 | tcg_gen_shri_i32(t1, arg, 8); |
| 1494 | tcg_gen_andi_i32(t1, t1, 0x0000ff00); |
| 1495 | tcg_gen_or_i32(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1496 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1497 | tcg_gen_shri_i32(t1, arg, 24); |
| 1498 | tcg_gen_or_i32(ret, t0, t1); |
| 1499 | tcg_temp_free_i32(t0); |
| 1500 | tcg_temp_free_i32(t1); |
| 1501 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1502 | } |
| 1503 | |
| 1504 | #if TCG_TARGET_REG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1505 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1506 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1507 | tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
| 1508 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1509 | } |
| 1510 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1511 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1512 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1513 | tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
| 1514 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1515 | } |
| 1516 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1517 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1518 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1519 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
| 1520 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1521 | } |
| 1522 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1523 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1524 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1525 | tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1526 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
| 1527 | } |
| 1528 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1529 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1530 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1531 | tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1532 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
| 1533 | } |
| 1534 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1535 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1536 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1537 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1538 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
| 1539 | } |
| 1540 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1541 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1542 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1543 | tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1544 | } |
| 1545 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1546 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1547 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1548 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1549 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1550 | } |
| 1551 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1552 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1553 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1554 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
| 1555 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1556 | } |
| 1557 | |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1558 | /* Note: we assume the six high bytes are set to zero */ |
| 1559 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
| 1560 | { |
| 1561 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
| 1562 | tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
| 1563 | } |
| 1564 | |
| 1565 | /* Note: we assume the four high bytes are set to zero */ |
| 1566 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
| 1567 | { |
| 1568 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
| 1569 | tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
| 1570 | } |
| 1571 | |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 1572 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1573 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1574 | TCGv_i32 t0, t1; |
| 1575 | t0 = tcg_temp_new_i32(); |
| 1576 | t1 = tcg_temp_new_i32(); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1577 | |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 1578 | tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
| 1579 | tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1580 | tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1581 | tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1582 | tcg_temp_free_i32(t0); |
| 1583 | tcg_temp_free_i32(t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1584 | } |
| 1585 | #else |
| 1586 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1587 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1588 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1589 | if (TCG_TARGET_HAS_ext8s_i64) { |
| 1590 | tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); |
| 1591 | } else { |
| 1592 | tcg_gen_shli_i64(ret, arg, 56); |
| 1593 | tcg_gen_sari_i64(ret, ret, 56); |
| 1594 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1595 | } |
| 1596 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1597 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1598 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1599 | if (TCG_TARGET_HAS_ext16s_i64) { |
| 1600 | tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); |
| 1601 | } else { |
| 1602 | tcg_gen_shli_i64(ret, arg, 48); |
| 1603 | tcg_gen_sari_i64(ret, ret, 48); |
| 1604 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1605 | } |
| 1606 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1607 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1608 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1609 | if (TCG_TARGET_HAS_ext32s_i64) { |
| 1610 | tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); |
| 1611 | } else { |
| 1612 | tcg_gen_shli_i64(ret, arg, 32); |
| 1613 | tcg_gen_sari_i64(ret, ret, 32); |
| 1614 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1615 | } |
| 1616 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1617 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1618 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1619 | if (TCG_TARGET_HAS_ext8u_i64) { |
| 1620 | tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); |
| 1621 | } else { |
| 1622 | tcg_gen_andi_i64(ret, arg, 0xffu); |
| 1623 | } |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1624 | } |
| 1625 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1626 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1627 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1628 | if (TCG_TARGET_HAS_ext16u_i64) { |
| 1629 | tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); |
| 1630 | } else { |
| 1631 | tcg_gen_andi_i64(ret, arg, 0xffffu); |
| 1632 | } |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1633 | } |
| 1634 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1635 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1636 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1637 | if (TCG_TARGET_HAS_ext32u_i64) { |
| 1638 | tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); |
| 1639 | } else { |
| 1640 | tcg_gen_andi_i64(ret, arg, 0xffffffffu); |
| 1641 | } |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1642 | } |
| 1643 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1644 | /* Note: we assume the target supports move between 32 and 64 bit |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1645 | registers. This will probably break MIPS64 targets. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1646 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1647 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1648 | tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1649 | } |
| 1650 | |
| 1651 | /* Note: we assume the target supports move between 32 and 64 bit |
| 1652 | registers */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1653 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1654 | { |
Aurelien Jarno | cfc8698 | 2009-09-30 23:09:35 +0200 | [diff] [blame] | 1655 | tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1656 | } |
| 1657 | |
| 1658 | /* Note: we assume the target supports move between 32 and 64 bit |
| 1659 | registers */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1660 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1661 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1662 | tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1663 | } |
| 1664 | |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1665 | /* Note: we assume the six high bytes are set to zero */ |
| 1666 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
| 1667 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1668 | if (TCG_TARGET_HAS_bswap16_i64) { |
| 1669 | tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); |
| 1670 | } else { |
| 1671 | TCGv_i64 t0 = tcg_temp_new_i64(); |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1672 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1673 | tcg_gen_ext8u_i64(t0, arg); |
| 1674 | tcg_gen_shli_i64(t0, t0, 8); |
| 1675 | tcg_gen_shri_i64(ret, arg, 8); |
| 1676 | tcg_gen_or_i64(ret, ret, t0); |
| 1677 | tcg_temp_free_i64(t0); |
| 1678 | } |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1679 | } |
| 1680 | |
| 1681 | /* Note: we assume the four high bytes are set to zero */ |
| 1682 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
| 1683 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1684 | if (TCG_TARGET_HAS_bswap32_i64) { |
| 1685 | tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); |
| 1686 | } else { |
| 1687 | TCGv_i64 t0, t1; |
| 1688 | t0 = tcg_temp_new_i64(); |
| 1689 | t1 = tcg_temp_new_i64(); |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1690 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1691 | tcg_gen_shli_i64(t0, arg, 24); |
| 1692 | tcg_gen_ext32u_i64(t0, t0); |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1693 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1694 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); |
| 1695 | tcg_gen_shli_i64(t1, t1, 8); |
| 1696 | tcg_gen_or_i64(t0, t0, t1); |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1697 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1698 | tcg_gen_shri_i64(t1, arg, 8); |
| 1699 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); |
| 1700 | tcg_gen_or_i64(t0, t0, t1); |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1701 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1702 | tcg_gen_shri_i64(t1, arg, 24); |
| 1703 | tcg_gen_or_i64(ret, t0, t1); |
| 1704 | tcg_temp_free_i64(t0); |
| 1705 | tcg_temp_free_i64(t1); |
| 1706 | } |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1707 | } |
| 1708 | |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 1709 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1710 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1711 | if (TCG_TARGET_HAS_bswap64_i64) { |
| 1712 | tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); |
| 1713 | } else { |
| 1714 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1715 | TCGv_i64 t1 = tcg_temp_new_i64(); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1716 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1717 | tcg_gen_shli_i64(t0, arg, 56); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1718 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1719 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); |
| 1720 | tcg_gen_shli_i64(t1, t1, 40); |
| 1721 | tcg_gen_or_i64(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1722 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1723 | tcg_gen_andi_i64(t1, arg, 0x00ff0000); |
| 1724 | tcg_gen_shli_i64(t1, t1, 24); |
| 1725 | tcg_gen_or_i64(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1726 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1727 | tcg_gen_andi_i64(t1, arg, 0xff000000); |
| 1728 | tcg_gen_shli_i64(t1, t1, 8); |
| 1729 | tcg_gen_or_i64(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1730 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1731 | tcg_gen_shri_i64(t1, arg, 8); |
| 1732 | tcg_gen_andi_i64(t1, t1, 0xff000000); |
| 1733 | tcg_gen_or_i64(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1734 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1735 | tcg_gen_shri_i64(t1, arg, 24); |
| 1736 | tcg_gen_andi_i64(t1, t1, 0x00ff0000); |
| 1737 | tcg_gen_or_i64(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1738 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1739 | tcg_gen_shri_i64(t1, arg, 40); |
| 1740 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); |
| 1741 | tcg_gen_or_i64(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1742 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1743 | tcg_gen_shri_i64(t1, arg, 56); |
| 1744 | tcg_gen_or_i64(ret, t0, t1); |
| 1745 | tcg_temp_free_i64(t0); |
| 1746 | tcg_temp_free_i64(t1); |
| 1747 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1748 | } |
| 1749 | |
| 1750 | #endif |
| 1751 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1752 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 1753 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1754 | if (TCG_TARGET_HAS_neg_i32) { |
| 1755 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
| 1756 | } else { |
| 1757 | TCGv_i32 t0 = tcg_const_i32(0); |
| 1758 | tcg_gen_sub_i32(ret, t0, arg); |
| 1759 | tcg_temp_free_i32(t0); |
| 1760 | } |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 1761 | } |
| 1762 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1763 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 1764 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1765 | if (TCG_TARGET_HAS_neg_i64) { |
| 1766 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
| 1767 | } else { |
| 1768 | TCGv_i64 t0 = tcg_const_i64(0); |
| 1769 | tcg_gen_sub_i64(ret, t0, arg); |
| 1770 | tcg_temp_free_i64(t0); |
| 1771 | } |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 1772 | } |
| 1773 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1774 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 1775 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1776 | if (TCG_TARGET_HAS_not_i32) { |
| 1777 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); |
| 1778 | } else { |
| 1779 | tcg_gen_xori_i32(ret, arg, -1); |
| 1780 | } |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 1781 | } |
| 1782 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1783 | static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 1784 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1785 | #if TCG_TARGET_REG_BITS == 64 |
| 1786 | if (TCG_TARGET_HAS_not_i64) { |
| 1787 | tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); |
| 1788 | } else { |
| 1789 | tcg_gen_xori_i64(ret, arg, -1); |
| 1790 | } |
| 1791 | #else |
Richard Henderson | a10f9f4 | 2010-03-19 12:44:47 -0700 | [diff] [blame] | 1792 | tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
| 1793 | tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
aurel32 | d260428 | 2009-03-09 22:35:13 +0000 | [diff] [blame] | 1794 | #endif |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 1795 | } |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1796 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1797 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1798 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1799 | tcg_gen_op1_i32(INDEX_op_discard, arg); |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1800 | } |
| 1801 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1802 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1803 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1804 | #if TCG_TARGET_REG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1805 | tcg_gen_discard_i32(TCGV_LOW(arg)); |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1806 | tcg_gen_discard_i32(TCGV_HIGH(arg)); |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1807 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1808 | tcg_gen_op1_i64(INDEX_op_discard, arg); |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1809 | #endif |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1810 | } |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1811 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1812 | static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1813 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1814 | if (TCG_TARGET_HAS_andc_i32) { |
| 1815 | tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); |
| 1816 | } else { |
| 1817 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 1818 | tcg_gen_not_i32(t0, arg2); |
| 1819 | tcg_gen_and_i32(ret, arg1, t0); |
| 1820 | tcg_temp_free_i32(t0); |
| 1821 | } |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1822 | } |
| 1823 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1824 | static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1825 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1826 | #if TCG_TARGET_REG_BITS == 64 |
| 1827 | if (TCG_TARGET_HAS_andc_i64) { |
| 1828 | tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); |
| 1829 | } else { |
| 1830 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1831 | tcg_gen_not_i64(t0, arg2); |
| 1832 | tcg_gen_and_i64(ret, arg1, t0); |
| 1833 | tcg_temp_free_i64(t0); |
| 1834 | } |
| 1835 | #else |
Richard Henderson | 241cbed | 2010-02-16 14:10:13 -0800 | [diff] [blame] | 1836 | tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 1837 | tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
Richard Henderson | 241cbed | 2010-02-16 14:10:13 -0800 | [diff] [blame] | 1838 | #endif |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1839 | } |
| 1840 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1841 | static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1842 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1843 | if (TCG_TARGET_HAS_eqv_i32) { |
| 1844 | tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2); |
| 1845 | } else { |
| 1846 | tcg_gen_xor_i32(ret, arg1, arg2); |
| 1847 | tcg_gen_not_i32(ret, ret); |
| 1848 | } |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1849 | } |
| 1850 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1851 | static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1852 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1853 | #if TCG_TARGET_REG_BITS == 64 |
| 1854 | if (TCG_TARGET_HAS_eqv_i64) { |
| 1855 | tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2); |
| 1856 | } else { |
| 1857 | tcg_gen_xor_i64(ret, arg1, arg2); |
| 1858 | tcg_gen_not_i64(ret, ret); |
| 1859 | } |
| 1860 | #else |
Richard Henderson | 8d625cf | 2010-03-19 13:02:02 -0700 | [diff] [blame] | 1861 | tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 1862 | tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
Richard Henderson | 8d625cf | 2010-03-19 13:02:02 -0700 | [diff] [blame] | 1863 | #endif |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1864 | } |
| 1865 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1866 | static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1867 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1868 | if (TCG_TARGET_HAS_nand_i32) { |
| 1869 | tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2); |
| 1870 | } else { |
| 1871 | tcg_gen_and_i32(ret, arg1, arg2); |
| 1872 | tcg_gen_not_i32(ret, ret); |
| 1873 | } |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1874 | } |
| 1875 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1876 | static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1877 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1878 | #if TCG_TARGET_REG_BITS == 64 |
| 1879 | if (TCG_TARGET_HAS_nand_i64) { |
| 1880 | tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2); |
| 1881 | } else { |
| 1882 | tcg_gen_and_i64(ret, arg1, arg2); |
| 1883 | tcg_gen_not_i64(ret, ret); |
| 1884 | } |
| 1885 | #else |
Richard Henderson | 9940a96 | 2010-03-19 13:03:58 -0700 | [diff] [blame] | 1886 | tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 1887 | tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
Richard Henderson | 9940a96 | 2010-03-19 13:03:58 -0700 | [diff] [blame] | 1888 | #endif |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1889 | } |
| 1890 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1891 | static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1892 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1893 | if (TCG_TARGET_HAS_nor_i32) { |
| 1894 | tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2); |
| 1895 | } else { |
| 1896 | tcg_gen_or_i32(ret, arg1, arg2); |
| 1897 | tcg_gen_not_i32(ret, ret); |
| 1898 | } |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1899 | } |
| 1900 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1901 | static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1902 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1903 | #if TCG_TARGET_REG_BITS == 64 |
| 1904 | if (TCG_TARGET_HAS_nor_i64) { |
| 1905 | tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2); |
| 1906 | } else { |
| 1907 | tcg_gen_or_i64(ret, arg1, arg2); |
| 1908 | tcg_gen_not_i64(ret, ret); |
| 1909 | } |
| 1910 | #else |
Richard Henderson | 32d98fb | 2010-03-19 13:08:56 -0700 | [diff] [blame] | 1911 | tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 1912 | tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
Richard Henderson | 32d98fb | 2010-03-19 13:08:56 -0700 | [diff] [blame] | 1913 | #endif |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1914 | } |
| 1915 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1916 | static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1917 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1918 | if (TCG_TARGET_HAS_orc_i32) { |
| 1919 | tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); |
| 1920 | } else { |
| 1921 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 1922 | tcg_gen_not_i32(t0, arg2); |
| 1923 | tcg_gen_or_i32(ret, arg1, t0); |
| 1924 | tcg_temp_free_i32(t0); |
| 1925 | } |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1926 | } |
| 1927 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1928 | static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1929 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1930 | #if TCG_TARGET_REG_BITS == 64 |
| 1931 | if (TCG_TARGET_HAS_orc_i64) { |
| 1932 | tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2); |
| 1933 | } else { |
| 1934 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1935 | tcg_gen_not_i64(t0, arg2); |
| 1936 | tcg_gen_or_i64(ret, arg1, t0); |
| 1937 | tcg_temp_free_i64(t0); |
| 1938 | } |
| 1939 | #else |
Richard Henderson | 791d126 | 2010-02-16 14:15:28 -0800 | [diff] [blame] | 1940 | tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 1941 | tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
Richard Henderson | 791d126 | 2010-02-16 14:15:28 -0800 | [diff] [blame] | 1942 | #endif |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1943 | } |
| 1944 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1945 | static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1946 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1947 | if (TCG_TARGET_HAS_rot_i32) { |
| 1948 | tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); |
| 1949 | } else { |
| 1950 | TCGv_i32 t0, t1; |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1951 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1952 | t0 = tcg_temp_new_i32(); |
| 1953 | t1 = tcg_temp_new_i32(); |
| 1954 | tcg_gen_shl_i32(t0, arg1, arg2); |
| 1955 | tcg_gen_subfi_i32(t1, 32, arg2); |
| 1956 | tcg_gen_shr_i32(t1, arg1, t1); |
| 1957 | tcg_gen_or_i32(ret, t0, t1); |
| 1958 | tcg_temp_free_i32(t0); |
| 1959 | tcg_temp_free_i32(t1); |
| 1960 | } |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1961 | } |
| 1962 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1963 | static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1964 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1965 | if (TCG_TARGET_HAS_rot_i64) { |
| 1966 | tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); |
| 1967 | } else { |
| 1968 | TCGv_i64 t0, t1; |
| 1969 | t0 = tcg_temp_new_i64(); |
| 1970 | t1 = tcg_temp_new_i64(); |
| 1971 | tcg_gen_shl_i64(t0, arg1, arg2); |
| 1972 | tcg_gen_subfi_i64(t1, 64, arg2); |
| 1973 | tcg_gen_shr_i64(t1, arg1, t1); |
| 1974 | tcg_gen_or_i64(ret, t0, t1); |
| 1975 | tcg_temp_free_i64(t0); |
| 1976 | tcg_temp_free_i64(t1); |
| 1977 | } |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1978 | } |
| 1979 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1980 | static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1981 | { |
| 1982 | /* some cases can be optimized here */ |
| 1983 | if (arg2 == 0) { |
| 1984 | tcg_gen_mov_i32(ret, arg1); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1985 | } else if (TCG_TARGET_HAS_rot_i32) { |
aurel32 | d42f183 | 2009-03-09 18:50:53 +0000 | [diff] [blame] | 1986 | TCGv_i32 t0 = tcg_const_i32(arg2); |
| 1987 | tcg_gen_rotl_i32(ret, arg1, t0); |
| 1988 | tcg_temp_free_i32(t0); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1989 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1990 | TCGv_i32 t0, t1; |
| 1991 | t0 = tcg_temp_new_i32(); |
| 1992 | t1 = tcg_temp_new_i32(); |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1993 | tcg_gen_shli_i32(t0, arg1, arg2); |
| 1994 | tcg_gen_shri_i32(t1, arg1, 32 - arg2); |
| 1995 | tcg_gen_or_i32(ret, t0, t1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1996 | tcg_temp_free_i32(t0); |
| 1997 | tcg_temp_free_i32(t1); |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1998 | } |
| 1999 | } |
| 2000 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2001 | static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2002 | { |
| 2003 | /* some cases can be optimized here */ |
| 2004 | if (arg2 == 0) { |
| 2005 | tcg_gen_mov_i64(ret, arg1); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2006 | } else if (TCG_TARGET_HAS_rot_i64) { |
aurel32 | d42f183 | 2009-03-09 18:50:53 +0000 | [diff] [blame] | 2007 | TCGv_i64 t0 = tcg_const_i64(arg2); |
| 2008 | tcg_gen_rotl_i64(ret, arg1, t0); |
| 2009 | tcg_temp_free_i64(t0); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2010 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2011 | TCGv_i64 t0, t1; |
| 2012 | t0 = tcg_temp_new_i64(); |
| 2013 | t1 = tcg_temp_new_i64(); |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2014 | tcg_gen_shli_i64(t0, arg1, arg2); |
| 2015 | tcg_gen_shri_i64(t1, arg1, 64 - arg2); |
| 2016 | tcg_gen_or_i64(ret, t0, t1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2017 | tcg_temp_free_i64(t0); |
| 2018 | tcg_temp_free_i64(t1); |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2019 | } |
| 2020 | } |
| 2021 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2022 | static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2023 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2024 | if (TCG_TARGET_HAS_rot_i32) { |
| 2025 | tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); |
| 2026 | } else { |
| 2027 | TCGv_i32 t0, t1; |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2028 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2029 | t0 = tcg_temp_new_i32(); |
| 2030 | t1 = tcg_temp_new_i32(); |
| 2031 | tcg_gen_shr_i32(t0, arg1, arg2); |
| 2032 | tcg_gen_subfi_i32(t1, 32, arg2); |
| 2033 | tcg_gen_shl_i32(t1, arg1, t1); |
| 2034 | tcg_gen_or_i32(ret, t0, t1); |
| 2035 | tcg_temp_free_i32(t0); |
| 2036 | tcg_temp_free_i32(t1); |
| 2037 | } |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2038 | } |
| 2039 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2040 | static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2041 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2042 | if (TCG_TARGET_HAS_rot_i64) { |
| 2043 | tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); |
| 2044 | } else { |
| 2045 | TCGv_i64 t0, t1; |
| 2046 | t0 = tcg_temp_new_i64(); |
| 2047 | t1 = tcg_temp_new_i64(); |
| 2048 | tcg_gen_shr_i64(t0, arg1, arg2); |
| 2049 | tcg_gen_subfi_i64(t1, 64, arg2); |
| 2050 | tcg_gen_shl_i64(t1, arg1, t1); |
| 2051 | tcg_gen_or_i64(ret, t0, t1); |
| 2052 | tcg_temp_free_i64(t0); |
| 2053 | tcg_temp_free_i64(t1); |
| 2054 | } |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2055 | } |
| 2056 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2057 | static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2058 | { |
| 2059 | /* some cases can be optimized here */ |
| 2060 | if (arg2 == 0) { |
| 2061 | tcg_gen_mov_i32(ret, arg1); |
| 2062 | } else { |
| 2063 | tcg_gen_rotli_i32(ret, arg1, 32 - arg2); |
| 2064 | } |
| 2065 | } |
| 2066 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2067 | static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2068 | { |
| 2069 | /* some cases can be optimized here */ |
| 2070 | if (arg2 == 0) { |
pbrook | de3526b | 2008-11-03 13:30:50 +0000 | [diff] [blame] | 2071 | tcg_gen_mov_i64(ret, arg1); |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2072 | } else { |
| 2073 | tcg_gen_rotli_i64(ret, arg1, 64 - arg2); |
| 2074 | } |
| 2075 | } |
| 2076 | |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2077 | static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, |
Richard Henderson | 0756e71 | 2011-11-01 15:06:43 -0700 | [diff] [blame] | 2078 | TCGv_i32 arg2, unsigned int ofs, |
| 2079 | unsigned int len) |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2080 | { |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2081 | uint32_t mask; |
| 2082 | TCGv_i32 t1; |
| 2083 | |
Richard Henderson | 717e703 | 2012-09-21 17:18:15 -0700 | [diff] [blame] | 2084 | tcg_debug_assert(ofs < 32); |
| 2085 | tcg_debug_assert(len <= 32); |
| 2086 | tcg_debug_assert(ofs + len <= 32); |
| 2087 | |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2088 | if (ofs == 0 && len == 32) { |
| 2089 | tcg_gen_mov_i32(ret, arg2); |
| 2090 | return; |
| 2091 | } |
Jan Kiszka | a477332 | 2011-09-29 18:52:11 +0200 | [diff] [blame] | 2092 | if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2093 | tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2094 | return; |
| 2095 | } |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2096 | |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2097 | mask = (1u << len) - 1; |
| 2098 | t1 = tcg_temp_new_i32(); |
| 2099 | |
| 2100 | if (ofs + len < 32) { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2101 | tcg_gen_andi_i32(t1, arg2, mask); |
| 2102 | tcg_gen_shli_i32(t1, t1, ofs); |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2103 | } else { |
| 2104 | tcg_gen_shli_i32(t1, arg2, ofs); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2105 | } |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2106 | tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); |
| 2107 | tcg_gen_or_i32(ret, ret, t1); |
| 2108 | |
| 2109 | tcg_temp_free_i32(t1); |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2110 | } |
| 2111 | |
| 2112 | static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, |
Richard Henderson | 0756e71 | 2011-11-01 15:06:43 -0700 | [diff] [blame] | 2113 | TCGv_i64 arg2, unsigned int ofs, |
| 2114 | unsigned int len) |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2115 | { |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2116 | uint64_t mask; |
| 2117 | TCGv_i64 t1; |
| 2118 | |
Richard Henderson | 717e703 | 2012-09-21 17:18:15 -0700 | [diff] [blame] | 2119 | tcg_debug_assert(ofs < 64); |
| 2120 | tcg_debug_assert(len <= 64); |
| 2121 | tcg_debug_assert(ofs + len <= 64); |
| 2122 | |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2123 | if (ofs == 0 && len == 64) { |
| 2124 | tcg_gen_mov_i64(ret, arg2); |
| 2125 | return; |
| 2126 | } |
Jan Kiszka | a477332 | 2011-09-29 18:52:11 +0200 | [diff] [blame] | 2127 | if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2128 | tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len); |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2129 | return; |
| 2130 | } |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2131 | |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2132 | #if TCG_TARGET_REG_BITS == 32 |
| 2133 | if (ofs >= 32) { |
Richard Henderson | 2f98c9d | 2011-11-01 15:06:42 -0700 | [diff] [blame] | 2134 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2135 | tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), |
| 2136 | TCGV_LOW(arg2), ofs - 32, len); |
| 2137 | return; |
| 2138 | } |
| 2139 | if (ofs + len <= 32) { |
| 2140 | tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), |
| 2141 | TCGV_LOW(arg2), ofs, len); |
Richard Henderson | 2f98c9d | 2011-11-01 15:06:42 -0700 | [diff] [blame] | 2142 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2143 | return; |
| 2144 | } |
| 2145 | #endif |
| 2146 | |
| 2147 | mask = (1ull << len) - 1; |
| 2148 | t1 = tcg_temp_new_i64(); |
| 2149 | |
| 2150 | if (ofs + len < 64) { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2151 | tcg_gen_andi_i64(t1, arg2, mask); |
| 2152 | tcg_gen_shli_i64(t1, t1, ofs); |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2153 | } else { |
| 2154 | tcg_gen_shli_i64(t1, arg2, ofs); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2155 | } |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2156 | tcg_gen_andi_i64(ret, arg1, ~(mask << ofs)); |
| 2157 | tcg_gen_or_i64(ret, ret, t1); |
| 2158 | |
| 2159 | tcg_temp_free_i64(t1); |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2160 | } |
| 2161 | |
Richard Henderson | 77276f6 | 2012-09-21 17:18:13 -0700 | [diff] [blame] | 2162 | static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, |
| 2163 | TCGv_i32 high) |
| 2164 | { |
| 2165 | #if TCG_TARGET_REG_BITS == 32 |
| 2166 | tcg_gen_mov_i32(TCGV_LOW(dest), low); |
| 2167 | tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
| 2168 | #else |
| 2169 | TCGv_i64 tmp = tcg_temp_new_i64(); |
| 2170 | /* These extensions are only needed for type correctness. |
| 2171 | We may be able to do better given target specific information. */ |
| 2172 | tcg_gen_extu_i32_i64(tmp, high); |
| 2173 | tcg_gen_extu_i32_i64(dest, low); |
| 2174 | /* If deposit is available, use it. Otherwise use the extra |
| 2175 | knowledge that we have of the zero-extensions above. */ |
| 2176 | if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) { |
| 2177 | tcg_gen_deposit_i64(dest, dest, tmp, 32, 32); |
| 2178 | } else { |
| 2179 | tcg_gen_shli_i64(tmp, tmp, 32); |
| 2180 | tcg_gen_or_i64(dest, dest, tmp); |
| 2181 | } |
| 2182 | tcg_temp_free_i64(tmp); |
| 2183 | #endif |
| 2184 | } |
| 2185 | |
| 2186 | static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, |
| 2187 | TCGv_i64 high) |
| 2188 | { |
| 2189 | tcg_gen_deposit_i64(dest, low, high, 32, 32); |
| 2190 | } |
| 2191 | |
Richard Henderson | ffc5ea0 | 2012-09-21 10:13:34 -0700 | [diff] [blame] | 2192 | static inline void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, |
| 2193 | TCGv_i32 c1, TCGv_i32 c2, |
| 2194 | TCGv_i32 v1, TCGv_i32 v2) |
| 2195 | { |
| 2196 | if (TCG_TARGET_HAS_movcond_i32) { |
| 2197 | tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond); |
| 2198 | } else { |
| 2199 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 2200 | TCGv_i32 t1 = tcg_temp_new_i32(); |
| 2201 | tcg_gen_setcond_i32(cond, t0, c1, c2); |
| 2202 | tcg_gen_neg_i32(t0, t0); |
| 2203 | tcg_gen_and_i32(t1, v1, t0); |
| 2204 | tcg_gen_andc_i32(ret, v2, t0); |
| 2205 | tcg_gen_or_i32(ret, ret, t1); |
| 2206 | tcg_temp_free_i32(t0); |
| 2207 | tcg_temp_free_i32(t1); |
| 2208 | } |
| 2209 | } |
| 2210 | |
| 2211 | static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, |
| 2212 | TCGv_i64 c1, TCGv_i64 c2, |
| 2213 | TCGv_i64 v1, TCGv_i64 v2) |
| 2214 | { |
Richard Henderson | a463133 | 2012-09-24 13:44:59 -0700 | [diff] [blame] | 2215 | #if TCG_TARGET_REG_BITS == 32 |
| 2216 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 2217 | TCGv_i32 t1 = tcg_temp_new_i32(); |
| 2218 | tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, |
| 2219 | TCGV_LOW(c1), TCGV_HIGH(c1), |
| 2220 | TCGV_LOW(c2), TCGV_HIGH(c2), cond); |
Richard Henderson | a463133 | 2012-09-24 13:44:59 -0700 | [diff] [blame] | 2221 | |
Richard Henderson | a80a6b6 | 2012-09-24 13:45:00 -0700 | [diff] [blame] | 2222 | if (TCG_TARGET_HAS_movcond_i32) { |
| 2223 | tcg_gen_movi_i32(t1, 0); |
| 2224 | tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1, |
| 2225 | TCGV_LOW(v1), TCGV_LOW(v2)); |
| 2226 | tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1, |
| 2227 | TCGV_HIGH(v1), TCGV_HIGH(v2)); |
| 2228 | } else { |
| 2229 | tcg_gen_neg_i32(t0, t0); |
Richard Henderson | a463133 | 2012-09-24 13:44:59 -0700 | [diff] [blame] | 2230 | |
Richard Henderson | a80a6b6 | 2012-09-24 13:45:00 -0700 | [diff] [blame] | 2231 | tcg_gen_and_i32(t1, TCGV_LOW(v1), t0); |
| 2232 | tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0); |
| 2233 | tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1); |
Richard Henderson | a463133 | 2012-09-24 13:44:59 -0700 | [diff] [blame] | 2234 | |
Richard Henderson | a80a6b6 | 2012-09-24 13:45:00 -0700 | [diff] [blame] | 2235 | tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0); |
| 2236 | tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0); |
| 2237 | tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1); |
| 2238 | } |
Richard Henderson | a463133 | 2012-09-24 13:44:59 -0700 | [diff] [blame] | 2239 | tcg_temp_free_i32(t0); |
| 2240 | tcg_temp_free_i32(t1); |
| 2241 | #else |
Richard Henderson | ffc5ea0 | 2012-09-21 10:13:34 -0700 | [diff] [blame] | 2242 | if (TCG_TARGET_HAS_movcond_i64) { |
| 2243 | tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond); |
| 2244 | } else { |
| 2245 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 2246 | TCGv_i64 t1 = tcg_temp_new_i64(); |
| 2247 | tcg_gen_setcond_i64(cond, t0, c1, c2); |
| 2248 | tcg_gen_neg_i64(t0, t0); |
| 2249 | tcg_gen_and_i64(t1, v1, t0); |
| 2250 | tcg_gen_andc_i64(ret, v2, t0); |
| 2251 | tcg_gen_or_i64(ret, ret, t1); |
| 2252 | tcg_temp_free_i64(t0); |
| 2253 | tcg_temp_free_i64(t1); |
| 2254 | } |
Richard Henderson | a463133 | 2012-09-24 13:44:59 -0700 | [diff] [blame] | 2255 | #endif |
Richard Henderson | ffc5ea0 | 2012-09-21 10:13:34 -0700 | [diff] [blame] | 2256 | } |
| 2257 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2258 | /***************************************/ |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2259 | /* QEMU specific operations. Their type depend on the QEMU CPU |
| 2260 | type. */ |
| 2261 | #ifndef TARGET_LONG_BITS |
| 2262 | #error must include QEMU headers |
| 2263 | #endif |
| 2264 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2265 | #if TARGET_LONG_BITS == 32 |
| 2266 | #define TCGv TCGv_i32 |
| 2267 | #define tcg_temp_new() tcg_temp_new_i32() |
| 2268 | #define tcg_global_reg_new tcg_global_reg_new_i32 |
| 2269 | #define tcg_global_mem_new tcg_global_mem_new_i32 |
aurel32 | df9247b | 2009-01-01 14:09:05 +0000 | [diff] [blame] | 2270 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2271 | #define tcg_temp_free tcg_temp_free_i32 |
| 2272 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32 |
| 2273 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32 |
| 2274 | #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 2275 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2276 | #else |
| 2277 | #define TCGv TCGv_i64 |
| 2278 | #define tcg_temp_new() tcg_temp_new_i64() |
| 2279 | #define tcg_global_reg_new tcg_global_reg_new_i64 |
| 2280 | #define tcg_global_mem_new tcg_global_mem_new_i64 |
aurel32 | df9247b | 2009-01-01 14:09:05 +0000 | [diff] [blame] | 2281 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2282 | #define tcg_temp_free tcg_temp_free_i64 |
| 2283 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64 |
| 2284 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64 |
| 2285 | #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 2286 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2287 | #endif |
| 2288 | |
bellard | 7e4597d | 2008-05-22 16:56:05 +0000 | [diff] [blame] | 2289 | /* debug info: write the PC of the corresponding QEMU CPU instruction */ |
| 2290 | static inline void tcg_gen_debug_insn_start(uint64_t pc) |
| 2291 | { |
| 2292 | /* XXX: must really use a 32 bit size for TCGArg in all cases */ |
| 2293 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS |
pbrook | bcb0126 | 2008-05-24 02:24:25 +0000 | [diff] [blame] | 2294 | tcg_gen_op2ii(INDEX_op_debug_insn_start, |
| 2295 | (uint32_t)(pc), (uint32_t)(pc >> 32)); |
bellard | 7e4597d | 2008-05-22 16:56:05 +0000 | [diff] [blame] | 2296 | #else |
| 2297 | tcg_gen_op1i(INDEX_op_debug_insn_start, pc); |
| 2298 | #endif |
| 2299 | } |
| 2300 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2301 | static inline void tcg_gen_exit_tb(tcg_target_long val) |
| 2302 | { |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2303 | tcg_gen_op1i(INDEX_op_exit_tb, val); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2304 | } |
| 2305 | |
Richard Henderson | 0a209d4 | 2012-09-21 17:18:16 -0700 | [diff] [blame] | 2306 | static inline void tcg_gen_goto_tb(unsigned idx) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2307 | { |
Richard Henderson | 0a209d4 | 2012-09-21 17:18:16 -0700 | [diff] [blame] | 2308 | /* We only support two chained exits. */ |
| 2309 | tcg_debug_assert(idx <= 1); |
| 2310 | #ifdef CONFIG_DEBUG_TCG |
| 2311 | /* Verify that we havn't seen this numbered exit before. */ |
| 2312 | tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0); |
| 2313 | tcg_ctx.goto_tb_issue_mask |= 1 << idx; |
| 2314 | #endif |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2315 | tcg_gen_op1i(INDEX_op_goto_tb, idx); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2316 | } |
| 2317 | |
| 2318 | #if TCG_TARGET_REG_BITS == 32 |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2319 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2320 | { |
| 2321 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2322 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2323 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2324 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
| 2325 | TCGV_HIGH(addr), mem_index); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2326 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2327 | #endif |
| 2328 | } |
| 2329 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2330 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2331 | { |
| 2332 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2333 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2334 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2335 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
| 2336 | TCGV_HIGH(addr), mem_index); |
| 2337 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2338 | #endif |
| 2339 | } |
| 2340 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2341 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2342 | { |
| 2343 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2344 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2345 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2346 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
| 2347 | TCGV_HIGH(addr), mem_index); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2348 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2349 | #endif |
| 2350 | } |
| 2351 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2352 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2353 | { |
| 2354 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2355 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2356 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2357 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
| 2358 | TCGV_HIGH(addr), mem_index); |
| 2359 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2360 | #endif |
| 2361 | } |
| 2362 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2363 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2364 | { |
| 2365 | #if TARGET_LONG_BITS == 32 |
Richard Henderson | 86feb1c | 2010-03-19 12:00:26 -0700 | [diff] [blame] | 2366 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2367 | #else |
Richard Henderson | 86feb1c | 2010-03-19 12:00:26 -0700 | [diff] [blame] | 2368 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr), |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2369 | TCGV_HIGH(addr), mem_index); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2370 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2371 | #endif |
| 2372 | } |
| 2373 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2374 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2375 | { |
| 2376 | #if TARGET_LONG_BITS == 32 |
Richard Henderson | 86feb1c | 2010-03-19 12:00:26 -0700 | [diff] [blame] | 2377 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2378 | #else |
Richard Henderson | 86feb1c | 2010-03-19 12:00:26 -0700 | [diff] [blame] | 2379 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr), |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2380 | TCGV_HIGH(addr), mem_index); |
| 2381 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2382 | #endif |
| 2383 | } |
| 2384 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2385 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2386 | { |
| 2387 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2388 | tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2389 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2390 | tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
| 2391 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2392 | #endif |
| 2393 | } |
| 2394 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2395 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2396 | { |
| 2397 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2398 | tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2399 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2400 | tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
| 2401 | TCGV_HIGH(addr), mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2402 | #endif |
| 2403 | } |
| 2404 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2405 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2406 | { |
| 2407 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2408 | tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2409 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2410 | tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
| 2411 | TCGV_HIGH(addr), mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2412 | #endif |
| 2413 | } |
| 2414 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2415 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2416 | { |
| 2417 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2418 | tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2419 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2420 | tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
| 2421 | TCGV_HIGH(addr), mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2422 | #endif |
| 2423 | } |
| 2424 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2425 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2426 | { |
| 2427 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2428 | tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
| 2429 | mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2430 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2431 | tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
| 2432 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2433 | #endif |
| 2434 | } |
| 2435 | |
Peter Maydell | ebecf36 | 2011-05-27 13:12:13 +0100 | [diff] [blame] | 2436 | #define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O)) |
| 2437 | #define tcg_gen_discard_ptr(A) tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A)) |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2438 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2439 | #else /* TCG_TARGET_REG_BITS == 32 */ |
| 2440 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2441 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2442 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2443 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2444 | } |
| 2445 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2446 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2447 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2448 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2449 | } |
| 2450 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2451 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2452 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2453 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2454 | } |
| 2455 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2456 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2457 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2458 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2459 | } |
| 2460 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2461 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2462 | { |
Richard Henderson | 3e1dbad | 2010-05-03 16:30:48 -0700 | [diff] [blame] | 2463 | #if TARGET_LONG_BITS == 32 |
| 2464 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index); |
| 2465 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2466 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
Richard Henderson | 3e1dbad | 2010-05-03 16:30:48 -0700 | [diff] [blame] | 2467 | #endif |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2468 | } |
| 2469 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2470 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2471 | { |
Richard Henderson | 3e1dbad | 2010-05-03 16:30:48 -0700 | [diff] [blame] | 2472 | #if TARGET_LONG_BITS == 32 |
| 2473 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index); |
| 2474 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2475 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
Richard Henderson | 3e1dbad | 2010-05-03 16:30:48 -0700 | [diff] [blame] | 2476 | #endif |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2477 | } |
| 2478 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2479 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2480 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2481 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2482 | } |
| 2483 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2484 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2485 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2486 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2487 | } |
| 2488 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2489 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2490 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2491 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2492 | } |
| 2493 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2494 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2495 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2496 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2497 | } |
| 2498 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2499 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2500 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2501 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2502 | } |
| 2503 | |
Peter Maydell | ebecf36 | 2011-05-27 13:12:13 +0100 | [diff] [blame] | 2504 | #define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O)) |
| 2505 | #define tcg_gen_discard_ptr(A) tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A)) |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2506 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2507 | #endif /* TCG_TARGET_REG_BITS != 32 */ |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2508 | |
| 2509 | #if TARGET_LONG_BITS == 64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2510 | #define tcg_gen_movi_tl tcg_gen_movi_i64 |
| 2511 | #define tcg_gen_mov_tl tcg_gen_mov_i64 |
| 2512 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 |
| 2513 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 |
| 2514 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 |
| 2515 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 |
| 2516 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 |
| 2517 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 |
| 2518 | #define tcg_gen_ld_tl tcg_gen_ld_i64 |
| 2519 | #define tcg_gen_st8_tl tcg_gen_st8_i64 |
| 2520 | #define tcg_gen_st16_tl tcg_gen_st16_i64 |
| 2521 | #define tcg_gen_st32_tl tcg_gen_st32_i64 |
| 2522 | #define tcg_gen_st_tl tcg_gen_st_i64 |
| 2523 | #define tcg_gen_add_tl tcg_gen_add_i64 |
| 2524 | #define tcg_gen_addi_tl tcg_gen_addi_i64 |
| 2525 | #define tcg_gen_sub_tl tcg_gen_sub_i64 |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 2526 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
pbrook | 10460c8 | 2008-11-02 13:26:16 +0000 | [diff] [blame] | 2527 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2528 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
| 2529 | #define tcg_gen_and_tl tcg_gen_and_i64 |
| 2530 | #define tcg_gen_andi_tl tcg_gen_andi_i64 |
| 2531 | #define tcg_gen_or_tl tcg_gen_or_i64 |
| 2532 | #define tcg_gen_ori_tl tcg_gen_ori_i64 |
| 2533 | #define tcg_gen_xor_tl tcg_gen_xor_i64 |
| 2534 | #define tcg_gen_xori_tl tcg_gen_xori_i64 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 2535 | #define tcg_gen_not_tl tcg_gen_not_i64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2536 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
| 2537 | #define tcg_gen_shli_tl tcg_gen_shli_i64 |
| 2538 | #define tcg_gen_shr_tl tcg_gen_shr_i64 |
| 2539 | #define tcg_gen_shri_tl tcg_gen_shri_i64 |
| 2540 | #define tcg_gen_sar_tl tcg_gen_sar_i64 |
| 2541 | #define tcg_gen_sari_tl tcg_gen_sari_i64 |
blueswir1 | 0cf767d | 2008-03-02 18:20:59 +0000 | [diff] [blame] | 2542 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 2543 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 2544 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
Aurelien Jarno | add1e7e | 2010-02-08 12:06:05 +0100 | [diff] [blame] | 2545 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 2546 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
| 2547 | #define tcg_gen_muli_tl tcg_gen_muli_i64 |
aurel32 | ab36421 | 2009-03-29 01:19:22 +0000 | [diff] [blame] | 2548 | #define tcg_gen_div_tl tcg_gen_div_i64 |
| 2549 | #define tcg_gen_rem_tl tcg_gen_rem_i64 |
aurel32 | 864951a | 2009-03-29 14:08:54 +0000 | [diff] [blame] | 2550 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
| 2551 | #define tcg_gen_remu_tl tcg_gen_remu_i64 |
blueswir1 | a768e4b | 2008-03-16 19:16:37 +0000 | [diff] [blame] | 2552 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
blueswir1 | e429073 | 2008-03-22 08:39:04 +0000 | [diff] [blame] | 2553 | #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32 |
| 2554 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 |
| 2555 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 |
| 2556 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 |
| 2557 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 |
| 2558 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 2559 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
| 2560 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 |
| 2561 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 |
| 2562 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 |
| 2563 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 |
| 2564 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 |
aurel32 | 911d79b | 2009-03-13 09:35:19 +0000 | [diff] [blame] | 2565 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
| 2566 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 |
| 2567 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 |
blueswir1 | 945ca82 | 2008-09-21 18:32:28 +0000 | [diff] [blame] | 2568 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 2569 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
| 2570 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 |
| 2571 | #define tcg_gen_nand_tl tcg_gen_nand_i64 |
| 2572 | #define tcg_gen_nor_tl tcg_gen_nor_i64 |
| 2573 | #define tcg_gen_orc_tl tcg_gen_orc_i64 |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2574 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
| 2575 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 |
| 2576 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 |
| 2577 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2578 | #define tcg_gen_deposit_tl tcg_gen_deposit_i64 |
blueswir1 | a98824a | 2008-03-13 20:46:42 +0000 | [diff] [blame] | 2579 | #define tcg_const_tl tcg_const_i64 |
aurel32 | bdffd4a | 2008-10-21 11:30:45 +0000 | [diff] [blame] | 2580 | #define tcg_const_local_tl tcg_const_local_i64 |
Richard Henderson | ffc5ea0 | 2012-09-21 10:13:34 -0700 | [diff] [blame] | 2581 | #define tcg_gen_movcond_tl tcg_gen_movcond_i64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2582 | #else |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2583 | #define tcg_gen_movi_tl tcg_gen_movi_i32 |
| 2584 | #define tcg_gen_mov_tl tcg_gen_mov_i32 |
| 2585 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 |
| 2586 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 |
| 2587 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 |
| 2588 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 |
| 2589 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 |
| 2590 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 |
| 2591 | #define tcg_gen_ld_tl tcg_gen_ld_i32 |
| 2592 | #define tcg_gen_st8_tl tcg_gen_st8_i32 |
| 2593 | #define tcg_gen_st16_tl tcg_gen_st16_i32 |
| 2594 | #define tcg_gen_st32_tl tcg_gen_st_i32 |
| 2595 | #define tcg_gen_st_tl tcg_gen_st_i32 |
| 2596 | #define tcg_gen_add_tl tcg_gen_add_i32 |
| 2597 | #define tcg_gen_addi_tl tcg_gen_addi_i32 |
| 2598 | #define tcg_gen_sub_tl tcg_gen_sub_i32 |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 2599 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 2600 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2601 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
| 2602 | #define tcg_gen_and_tl tcg_gen_and_i32 |
| 2603 | #define tcg_gen_andi_tl tcg_gen_andi_i32 |
| 2604 | #define tcg_gen_or_tl tcg_gen_or_i32 |
| 2605 | #define tcg_gen_ori_tl tcg_gen_ori_i32 |
| 2606 | #define tcg_gen_xor_tl tcg_gen_xor_i32 |
| 2607 | #define tcg_gen_xori_tl tcg_gen_xori_i32 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 2608 | #define tcg_gen_not_tl tcg_gen_not_i32 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2609 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
| 2610 | #define tcg_gen_shli_tl tcg_gen_shli_i32 |
| 2611 | #define tcg_gen_shr_tl tcg_gen_shr_i32 |
| 2612 | #define tcg_gen_shri_tl tcg_gen_shri_i32 |
| 2613 | #define tcg_gen_sar_tl tcg_gen_sar_i32 |
| 2614 | #define tcg_gen_sari_tl tcg_gen_sari_i32 |
blueswir1 | 0cf767d | 2008-03-02 18:20:59 +0000 | [diff] [blame] | 2615 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 2616 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 2617 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
Aurelien Jarno | add1e7e | 2010-02-08 12:06:05 +0100 | [diff] [blame] | 2618 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 2619 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
| 2620 | #define tcg_gen_muli_tl tcg_gen_muli_i32 |
aurel32 | ab36421 | 2009-03-29 01:19:22 +0000 | [diff] [blame] | 2621 | #define tcg_gen_div_tl tcg_gen_div_i32 |
| 2622 | #define tcg_gen_rem_tl tcg_gen_rem_i32 |
aurel32 | 864951a | 2009-03-29 14:08:54 +0000 | [diff] [blame] | 2623 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
| 2624 | #define tcg_gen_remu_tl tcg_gen_remu_i32 |
blueswir1 | a768e4b | 2008-03-16 19:16:37 +0000 | [diff] [blame] | 2625 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
blueswir1 | e429073 | 2008-03-22 08:39:04 +0000 | [diff] [blame] | 2626 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
| 2627 | #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32 |
| 2628 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 |
| 2629 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 |
| 2630 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 |
| 2631 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 2632 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
| 2633 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 |
| 2634 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 |
| 2635 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 |
| 2636 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 |
| 2637 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 |
aurel32 | 911d79b | 2009-03-13 09:35:19 +0000 | [diff] [blame] | 2638 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
| 2639 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 |
blueswir1 | 945ca82 | 2008-09-21 18:32:28 +0000 | [diff] [blame] | 2640 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 2641 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
| 2642 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 |
| 2643 | #define tcg_gen_nand_tl tcg_gen_nand_i32 |
| 2644 | #define tcg_gen_nor_tl tcg_gen_nor_i32 |
| 2645 | #define tcg_gen_orc_tl tcg_gen_orc_i32 |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2646 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
| 2647 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 |
| 2648 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 |
| 2649 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2650 | #define tcg_gen_deposit_tl tcg_gen_deposit_i32 |
blueswir1 | a98824a | 2008-03-13 20:46:42 +0000 | [diff] [blame] | 2651 | #define tcg_const_tl tcg_const_i32 |
aurel32 | bdffd4a | 2008-10-21 11:30:45 +0000 | [diff] [blame] | 2652 | #define tcg_const_local_tl tcg_const_local_i32 |
Richard Henderson | ffc5ea0 | 2012-09-21 10:13:34 -0700 | [diff] [blame] | 2653 | #define tcg_gen_movcond_tl tcg_gen_movcond_i32 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2654 | #endif |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 2655 | |
| 2656 | #if TCG_TARGET_REG_BITS == 32 |
Peter Maydell | ebecf36 | 2011-05-27 13:12:13 +0100 | [diff] [blame] | 2657 | #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \ |
| 2658 | TCGV_PTR_TO_NAT(A), \ |
| 2659 | TCGV_PTR_TO_NAT(B)) |
| 2660 | #define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), \ |
| 2661 | TCGV_PTR_TO_NAT(A), (B)) |
| 2662 | #define tcg_gen_ext_i32_ptr(R, A) tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A)) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 2663 | #else /* TCG_TARGET_REG_BITS == 32 */ |
Peter Maydell | ebecf36 | 2011-05-27 13:12:13 +0100 | [diff] [blame] | 2664 | #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), \ |
| 2665 | TCGV_PTR_TO_NAT(A), \ |
| 2666 | TCGV_PTR_TO_NAT(B)) |
| 2667 | #define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), \ |
| 2668 | TCGV_PTR_TO_NAT(A), (B)) |
| 2669 | #define tcg_gen_ext_i32_ptr(R, A) tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A)) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 2670 | #endif /* TCG_TARGET_REG_BITS != 32 */ |