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bellardc896fe22008-02-01 10:05:41 +00001/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include "tcg.h"
25
bellardc896fe22008-02-01 10:05:41 +000026int gen_new_label(void);
27
Richard Hendersona9751602010-03-19 11:12:29 -070028static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1)
pbrookac56dd42008-02-03 19:56:33 +000029{
30 *gen_opc_ptr++ = opc;
pbrooka7812ae2008-11-17 14:43:54 +000031 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
32}
33
Richard Hendersona9751602010-03-19 11:12:29 -070034static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1)
pbrooka7812ae2008-11-17 14:43:54 +000035{
36 *gen_opc_ptr++ = opc;
37 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
pbrookac56dd42008-02-03 19:56:33 +000038}
39
Richard Hendersona9751602010-03-19 11:12:29 -070040static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1)
bellardc896fe22008-02-01 10:05:41 +000041{
42 *gen_opc_ptr++ = opc;
43 *gen_opparam_ptr++ = arg1;
44}
45
Richard Hendersona9751602010-03-19 11:12:29 -070046static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +000047{
48 *gen_opc_ptr++ = opc;
pbrooka7812ae2008-11-17 14:43:54 +000049 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
50 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
pbrookac56dd42008-02-03 19:56:33 +000051}
52
Richard Hendersona9751602010-03-19 11:12:29 -070053static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2)
pbrookac56dd42008-02-03 19:56:33 +000054{
55 *gen_opc_ptr++ = opc;
pbrooka7812ae2008-11-17 14:43:54 +000056 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
57 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
58}
59
Richard Hendersona9751602010-03-19 11:12:29 -070060static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2)
pbrooka7812ae2008-11-17 14:43:54 +000061{
62 *gen_opc_ptr++ = opc;
63 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
64 *gen_opparam_ptr++ = arg2;
65}
66
Richard Hendersona9751602010-03-19 11:12:29 -070067static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2)
pbrooka7812ae2008-11-17 14:43:54 +000068{
69 *gen_opc_ptr++ = opc;
70 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
bellardc896fe22008-02-01 10:05:41 +000071 *gen_opparam_ptr++ = arg2;
72}
73
Richard Hendersona9751602010-03-19 11:12:29 -070074static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2)
pbrookbcb01262008-05-24 02:24:25 +000075{
76 *gen_opc_ptr++ = opc;
77 *gen_opparam_ptr++ = arg1;
78 *gen_opparam_ptr++ = arg2;
79}
80
Richard Hendersona9751602010-03-19 11:12:29 -070081static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
pbrooka7812ae2008-11-17 14:43:54 +000082 TCGv_i32 arg3)
bellardc896fe22008-02-01 10:05:41 +000083{
84 *gen_opc_ptr++ = opc;
pbrooka7812ae2008-11-17 14:43:54 +000085 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
86 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
87 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
pbrookac56dd42008-02-03 19:56:33 +000088}
89
Richard Hendersona9751602010-03-19 11:12:29 -070090static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
pbrooka7812ae2008-11-17 14:43:54 +000091 TCGv_i64 arg3)
pbrookac56dd42008-02-03 19:56:33 +000092{
93 *gen_opc_ptr++ = opc;
pbrooka7812ae2008-11-17 14:43:54 +000094 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
95 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
96 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
97}
98
Richard Hendersona9751602010-03-19 11:12:29 -070099static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1,
100 TCGv_i32 arg2, TCGArg arg3)
pbrooka7812ae2008-11-17 14:43:54 +0000101{
102 *gen_opc_ptr++ = opc;
103 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
104 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
bellardc896fe22008-02-01 10:05:41 +0000105 *gen_opparam_ptr++ = arg3;
106}
107
Richard Hendersona9751602010-03-19 11:12:29 -0700108static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1,
109 TCGv_i64 arg2, TCGArg arg3)
bellardc896fe22008-02-01 10:05:41 +0000110{
111 *gen_opc_ptr++ = opc;
pbrooka7812ae2008-11-17 14:43:54 +0000112 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
113 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
114 *gen_opparam_ptr++ = arg3;
pbrookac56dd42008-02-03 19:56:33 +0000115}
116
Richard Hendersona9751602010-03-19 11:12:29 -0700117static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
118 TCGv_ptr base, TCGArg offset)
pbrookac56dd42008-02-03 19:56:33 +0000119{
120 *gen_opc_ptr++ = opc;
pbrooka7812ae2008-11-17 14:43:54 +0000121 *gen_opparam_ptr++ = GET_TCGV_I32(val);
122 *gen_opparam_ptr++ = GET_TCGV_PTR(base);
123 *gen_opparam_ptr++ = offset;
124}
125
Richard Hendersona9751602010-03-19 11:12:29 -0700126static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
127 TCGv_ptr base, TCGArg offset)
pbrooka7812ae2008-11-17 14:43:54 +0000128{
129 *gen_opc_ptr++ = opc;
blueswir1a810a2d2008-12-07 17:16:42 +0000130 *gen_opparam_ptr++ = GET_TCGV_I64(val);
pbrooka7812ae2008-11-17 14:43:54 +0000131 *gen_opparam_ptr++ = GET_TCGV_PTR(base);
132 *gen_opparam_ptr++ = offset;
133}
134
Richard Hendersona9751602010-03-19 11:12:29 -0700135static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val,
136 TCGv_i32 addr, TCGArg mem_index)
pbrooka7812ae2008-11-17 14:43:54 +0000137{
138 *gen_opc_ptr++ = opc;
139 *gen_opparam_ptr++ = GET_TCGV_I64(val);
140 *gen_opparam_ptr++ = GET_TCGV_I32(addr);
141 *gen_opparam_ptr++ = mem_index;
142}
143
Richard Hendersona9751602010-03-19 11:12:29 -0700144static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
145 TCGv_i64 addr, TCGArg mem_index)
pbrooka7812ae2008-11-17 14:43:54 +0000146{
147 *gen_opc_ptr++ = opc;
148 *gen_opparam_ptr++ = GET_TCGV_I64(val);
149 *gen_opparam_ptr++ = GET_TCGV_I64(addr);
150 *gen_opparam_ptr++ = mem_index;
151}
152
Richard Hendersona9751602010-03-19 11:12:29 -0700153static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
pbrooka7812ae2008-11-17 14:43:54 +0000154 TCGv_i32 arg3, TCGv_i32 arg4)
155{
156 *gen_opc_ptr++ = opc;
157 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
158 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
159 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
160 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
161}
162
Richard Hendersona9751602010-03-19 11:12:29 -0700163static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
blueswir1a810a2d2008-12-07 17:16:42 +0000164 TCGv_i64 arg3, TCGv_i64 arg4)
pbrooka7812ae2008-11-17 14:43:54 +0000165{
166 *gen_opc_ptr++ = opc;
167 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
168 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
169 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
170 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
171}
172
Richard Hendersona9751602010-03-19 11:12:29 -0700173static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
pbrooka7812ae2008-11-17 14:43:54 +0000174 TCGv_i32 arg3, TCGArg arg4)
175{
176 *gen_opc_ptr++ = opc;
177 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
178 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
179 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
pbrookac56dd42008-02-03 19:56:33 +0000180 *gen_opparam_ptr++ = arg4;
181}
182
Richard Hendersona9751602010-03-19 11:12:29 -0700183static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
pbrooka7812ae2008-11-17 14:43:54 +0000184 TCGv_i64 arg3, TCGArg arg4)
pbrookac56dd42008-02-03 19:56:33 +0000185{
186 *gen_opc_ptr++ = opc;
pbrooka7812ae2008-11-17 14:43:54 +0000187 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
188 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
189 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
190 *gen_opparam_ptr++ = arg4;
191}
192
Richard Hendersona9751602010-03-19 11:12:29 -0700193static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
pbrooka7812ae2008-11-17 14:43:54 +0000194 TCGArg arg3, TCGArg arg4)
195{
196 *gen_opc_ptr++ = opc;
197 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
198 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
bellardc896fe22008-02-01 10:05:41 +0000199 *gen_opparam_ptr++ = arg3;
200 *gen_opparam_ptr++ = arg4;
201}
202
Richard Hendersona9751602010-03-19 11:12:29 -0700203static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
pbrooka7812ae2008-11-17 14:43:54 +0000204 TCGArg arg3, TCGArg arg4)
bellardc896fe22008-02-01 10:05:41 +0000205{
206 *gen_opc_ptr++ = opc;
pbrooka7812ae2008-11-17 14:43:54 +0000207 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
208 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
209 *gen_opparam_ptr++ = arg3;
210 *gen_opparam_ptr++ = arg4;
pbrookac56dd42008-02-03 19:56:33 +0000211}
212
Richard Hendersona9751602010-03-19 11:12:29 -0700213static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
pbrooka7812ae2008-11-17 14:43:54 +0000214 TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
pbrookac56dd42008-02-03 19:56:33 +0000215{
216 *gen_opc_ptr++ = opc;
pbrooka7812ae2008-11-17 14:43:54 +0000217 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
218 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
219 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
220 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
221 *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
222}
223
Richard Hendersona9751602010-03-19 11:12:29 -0700224static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
pbrooka7812ae2008-11-17 14:43:54 +0000225 TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
226{
227 *gen_opc_ptr++ = opc;
228 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
229 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
230 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
231 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
232 *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
233}
234
Richard Hendersona9751602010-03-19 11:12:29 -0700235static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
pbrooka7812ae2008-11-17 14:43:54 +0000236 TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
237{
238 *gen_opc_ptr++ = opc;
239 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
240 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
241 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
242 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
bellardc896fe22008-02-01 10:05:41 +0000243 *gen_opparam_ptr++ = arg5;
244}
245
Richard Hendersona9751602010-03-19 11:12:29 -0700246static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
pbrooka7812ae2008-11-17 14:43:54 +0000247 TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
bellardc896fe22008-02-01 10:05:41 +0000248{
249 *gen_opc_ptr++ = opc;
pbrooka7812ae2008-11-17 14:43:54 +0000250 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
251 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
252 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
253 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
254 *gen_opparam_ptr++ = arg5;
pbrookac56dd42008-02-03 19:56:33 +0000255}
256
Richard Hendersonb7767f02011-01-10 19:23:42 -0800257static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
258 TCGv_i32 arg2, TCGv_i32 arg3,
259 TCGArg arg4, TCGArg arg5)
260{
261 *gen_opc_ptr++ = opc;
262 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
263 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
264 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
265 *gen_opparam_ptr++ = arg4;
266 *gen_opparam_ptr++ = arg5;
267}
268
269static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
270 TCGv_i64 arg2, TCGv_i64 arg3,
271 TCGArg arg4, TCGArg arg5)
272{
273 *gen_opc_ptr++ = opc;
274 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
275 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
276 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
277 *gen_opparam_ptr++ = arg4;
278 *gen_opparam_ptr++ = arg5;
279}
280
Richard Hendersona9751602010-03-19 11:12:29 -0700281static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
pbrooka7812ae2008-11-17 14:43:54 +0000282 TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
283 TCGv_i32 arg6)
pbrookac56dd42008-02-03 19:56:33 +0000284{
285 *gen_opc_ptr++ = opc;
pbrooka7812ae2008-11-17 14:43:54 +0000286 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
287 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
288 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
289 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
290 *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
291 *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
292}
293
Richard Hendersona9751602010-03-19 11:12:29 -0700294static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
pbrooka7812ae2008-11-17 14:43:54 +0000295 TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
296 TCGv_i64 arg6)
297{
298 *gen_opc_ptr++ = opc;
299 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
300 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
301 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
302 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
303 *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
304 *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
305}
306
Richard Hendersona9751602010-03-19 11:12:29 -0700307static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800308 TCGv_i32 arg3, TCGv_i32 arg4,
309 TCGv_i32 arg5, TCGArg arg6)
310{
311 *gen_opc_ptr++ = opc;
312 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
313 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
314 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
315 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
316 *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
317 *gen_opparam_ptr++ = arg6;
318}
319
Richard Hendersona9751602010-03-19 11:12:29 -0700320static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800321 TCGv_i64 arg3, TCGv_i64 arg4,
322 TCGv_i64 arg5, TCGArg arg6)
323{
324 *gen_opc_ptr++ = opc;
325 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
326 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
327 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
328 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
329 *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
330 *gen_opparam_ptr++ = arg6;
331}
332
Richard Hendersona9751602010-03-19 11:12:29 -0700333static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1,
334 TCGv_i32 arg2, TCGv_i32 arg3,
335 TCGv_i32 arg4, TCGArg arg5, TCGArg arg6)
pbrooka7812ae2008-11-17 14:43:54 +0000336{
337 *gen_opc_ptr++ = opc;
338 *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
339 *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
340 *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
341 *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
342 *gen_opparam_ptr++ = arg5;
343 *gen_opparam_ptr++ = arg6;
344}
345
Richard Hendersona9751602010-03-19 11:12:29 -0700346static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1,
347 TCGv_i64 arg2, TCGv_i64 arg3,
348 TCGv_i64 arg4, TCGArg arg5, TCGArg arg6)
pbrooka7812ae2008-11-17 14:43:54 +0000349{
350 *gen_opc_ptr++ = opc;
351 *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
352 *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
353 *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
354 *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
bellardc896fe22008-02-01 10:05:41 +0000355 *gen_opparam_ptr++ = arg5;
356 *gen_opparam_ptr++ = arg6;
357}
358
359static inline void gen_set_label(int n)
360{
pbrookac56dd42008-02-03 19:56:33 +0000361 tcg_gen_op1i(INDEX_op_set_label, n);
bellardc896fe22008-02-01 10:05:41 +0000362}
363
blueswir1fb50d412008-03-21 17:58:45 +0000364static inline void tcg_gen_br(int label)
365{
366 tcg_gen_op1i(INDEX_op_br, label);
367}
368
pbrooka7812ae2008-11-17 14:43:54 +0000369static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +0000370{
aurel32fe75bcf2009-03-10 08:57:16 +0000371 if (!TCGV_EQUAL_I32(ret, arg))
pbrooka7812ae2008-11-17 14:43:54 +0000372 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
bellardc896fe22008-02-01 10:05:41 +0000373}
374
pbrooka7812ae2008-11-17 14:43:54 +0000375static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
bellardc896fe22008-02-01 10:05:41 +0000376{
pbrooka7812ae2008-11-17 14:43:54 +0000377 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
bellardc896fe22008-02-01 10:05:41 +0000378}
379
Richard Henderson2bece2c2010-06-14 17:35:27 -0700380/* A version of dh_sizemask from def-helper.h that doesn't rely on
381 preprocessor magic. */
382static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed)
383{
384 return (is_64bit << n*2) | (is_signed << (n*2 + 1));
385}
386
bellardc896fe22008-02-01 10:05:41 +0000387/* helper calls */
pbrooka7812ae2008-11-17 14:43:54 +0000388static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
389 TCGArg ret, int nargs, TCGArg *args)
bellardc896fe22008-02-01 10:05:41 +0000390{
pbrooka7812ae2008-11-17 14:43:54 +0000391 TCGv_ptr fn;
Peter Maydell73f5e312011-12-10 16:35:31 +0000392 fn = tcg_const_ptr(func);
pbrooka7812ae2008-11-17 14:43:54 +0000393 tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
394 nargs, args);
395 tcg_temp_free_ptr(fn);
bellardc896fe22008-02-01 10:05:41 +0000396}
397
Aurelien Jarnodbfff4d2010-03-14 23:01:01 +0100398/* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
399 reserved for helpers in tcg-runtime.c. These helpers are all const
400 and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
401 TCG_CALL_PURE. This may need to be adjusted if these functions
402 start to be used with other helpers. */
Richard Henderson2bece2c2010-06-14 17:35:27 -0700403static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret,
Aurelien Jarno31d66552010-03-02 23:16:36 +0100404 TCGv_i32 a, TCGv_i32 b)
405{
406 TCGv_ptr fn;
407 TCGArg args[2];
Peter Maydell73f5e312011-12-10 16:35:31 +0000408 fn = tcg_const_ptr(func);
Aurelien Jarno31d66552010-03-02 23:16:36 +0100409 args[0] = GET_TCGV_I32(a);
410 args[1] = GET_TCGV_I32(b);
Richard Henderson2bece2c2010-06-14 17:35:27 -0700411 tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
412 GET_TCGV_I32(ret), 2, args);
Aurelien Jarno31d66552010-03-02 23:16:36 +0100413 tcg_temp_free_ptr(fn);
414}
415
Richard Henderson2bece2c2010-06-14 17:35:27 -0700416static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret,
pbrooka7812ae2008-11-17 14:43:54 +0000417 TCGv_i64 a, TCGv_i64 b)
bellardc896fe22008-02-01 10:05:41 +0000418{
pbrooka7812ae2008-11-17 14:43:54 +0000419 TCGv_ptr fn;
420 TCGArg args[2];
Peter Maydell73f5e312011-12-10 16:35:31 +0000421 fn = tcg_const_ptr(func);
pbrooka7812ae2008-11-17 14:43:54 +0000422 args[0] = GET_TCGV_I64(a);
423 args[1] = GET_TCGV_I64(b);
Richard Henderson2bece2c2010-06-14 17:35:27 -0700424 tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
425 GET_TCGV_I64(ret), 2, args);
pbrooka7812ae2008-11-17 14:43:54 +0000426 tcg_temp_free_ptr(fn);
blueswir1f8422f52008-02-24 07:45:43 +0000427}
428
bellardc896fe22008-02-01 10:05:41 +0000429/* 32 bit ops */
430
pbrooka7812ae2008-11-17 14:43:54 +0000431static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000432{
pbrooka7812ae2008-11-17 14:43:54 +0000433 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000434}
435
pbrooka7812ae2008-11-17 14:43:54 +0000436static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000437{
pbrooka7812ae2008-11-17 14:43:54 +0000438 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000439}
440
pbrooka7812ae2008-11-17 14:43:54 +0000441static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000442{
pbrooka7812ae2008-11-17 14:43:54 +0000443 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000444}
445
pbrooka7812ae2008-11-17 14:43:54 +0000446static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000447{
pbrooka7812ae2008-11-17 14:43:54 +0000448 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000449}
450
pbrooka7812ae2008-11-17 14:43:54 +0000451static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000452{
pbrooka7812ae2008-11-17 14:43:54 +0000453 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000454}
455
pbrooka7812ae2008-11-17 14:43:54 +0000456static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000457{
pbrooka7812ae2008-11-17 14:43:54 +0000458 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000459}
460
pbrooka7812ae2008-11-17 14:43:54 +0000461static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000462{
pbrooka7812ae2008-11-17 14:43:54 +0000463 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000464}
465
pbrooka7812ae2008-11-17 14:43:54 +0000466static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000467{
pbrooka7812ae2008-11-17 14:43:54 +0000468 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000469}
470
pbrooka7812ae2008-11-17 14:43:54 +0000471static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000472{
pbrooka7812ae2008-11-17 14:43:54 +0000473 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000474}
475
pbrooka7812ae2008-11-17 14:43:54 +0000476static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000477{
blueswir170894422008-02-20 18:01:23 +0000478 /* some cases can be optimized here */
479 if (arg2 == 0) {
480 tcg_gen_mov_i32(ret, arg1);
481 } else {
pbrooka7812ae2008-11-17 14:43:54 +0000482 TCGv_i32 t0 = tcg_const_i32(arg2);
bellarde8996ee2008-05-23 17:33:39 +0000483 tcg_gen_add_i32(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +0000484 tcg_temp_free_i32(t0);
blueswir170894422008-02-20 18:01:23 +0000485 }
bellardc896fe22008-02-01 10:05:41 +0000486}
487
pbrooka7812ae2008-11-17 14:43:54 +0000488static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000489{
pbrooka7812ae2008-11-17 14:43:54 +0000490 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000491}
492
pbrooka7812ae2008-11-17 14:43:54 +0000493static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
aurel3200457342008-11-02 08:23:04 +0000494{
pbrooka7812ae2008-11-17 14:43:54 +0000495 TCGv_i32 t0 = tcg_const_i32(arg1);
aurel3200457342008-11-02 08:23:04 +0000496 tcg_gen_sub_i32(ret, t0, arg2);
pbrooka7812ae2008-11-17 14:43:54 +0000497 tcg_temp_free_i32(t0);
aurel3200457342008-11-02 08:23:04 +0000498}
499
pbrooka7812ae2008-11-17 14:43:54 +0000500static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000501{
blueswir170894422008-02-20 18:01:23 +0000502 /* some cases can be optimized here */
503 if (arg2 == 0) {
504 tcg_gen_mov_i32(ret, arg1);
505 } else {
pbrooka7812ae2008-11-17 14:43:54 +0000506 TCGv_i32 t0 = tcg_const_i32(arg2);
bellarde8996ee2008-05-23 17:33:39 +0000507 tcg_gen_sub_i32(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +0000508 tcg_temp_free_i32(t0);
blueswir170894422008-02-20 18:01:23 +0000509 }
bellardc896fe22008-02-01 10:05:41 +0000510}
511
pbrooka7812ae2008-11-17 14:43:54 +0000512static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000513{
aurel327fc81052009-03-10 19:37:39 +0000514 if (TCGV_EQUAL_I32(arg1, arg2)) {
515 tcg_gen_mov_i32(ret, arg1);
516 } else {
517 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
518 }
bellardc896fe22008-02-01 10:05:41 +0000519}
520
Richard Henderson42ce3e22012-09-21 17:18:10 -0700521static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000522{
Richard Henderson42ce3e22012-09-21 17:18:10 -0700523 TCGv_i32 t0;
524 /* Some cases can be optimized here. */
525 switch (arg2) {
526 case 0:
bellardc896fe22008-02-01 10:05:41 +0000527 tcg_gen_movi_i32(ret, 0);
Richard Henderson42ce3e22012-09-21 17:18:10 -0700528 return;
529 case 0xffffffffu:
bellardc896fe22008-02-01 10:05:41 +0000530 tcg_gen_mov_i32(ret, arg1);
Richard Henderson42ce3e22012-09-21 17:18:10 -0700531 return;
532 case 0xffu:
533 /* Don't recurse with tcg_gen_ext8u_i32. */
534 if (TCG_TARGET_HAS_ext8u_i32) {
535 tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1);
536 return;
537 }
538 break;
539 case 0xffffu:
540 if (TCG_TARGET_HAS_ext16u_i32) {
541 tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1);
542 return;
543 }
544 break;
bellardc896fe22008-02-01 10:05:41 +0000545 }
Richard Henderson42ce3e22012-09-21 17:18:10 -0700546 t0 = tcg_const_i32(arg2);
547 tcg_gen_and_i32(ret, arg1, t0);
548 tcg_temp_free_i32(t0);
bellardc896fe22008-02-01 10:05:41 +0000549}
550
pbrooka7812ae2008-11-17 14:43:54 +0000551static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000552{
aurel327fc81052009-03-10 19:37:39 +0000553 if (TCGV_EQUAL_I32(arg1, arg2)) {
554 tcg_gen_mov_i32(ret, arg1);
555 } else {
556 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
557 }
bellardc896fe22008-02-01 10:05:41 +0000558}
559
pbrooka7812ae2008-11-17 14:43:54 +0000560static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000561{
Richard Hendersond81ada72012-09-21 17:18:11 -0700562 /* Some cases can be optimized here. */
563 if (arg2 == -1) {
564 tcg_gen_movi_i32(ret, -1);
bellardc896fe22008-02-01 10:05:41 +0000565 } else if (arg2 == 0) {
566 tcg_gen_mov_i32(ret, arg1);
567 } else {
pbrooka7812ae2008-11-17 14:43:54 +0000568 TCGv_i32 t0 = tcg_const_i32(arg2);
bellarde8996ee2008-05-23 17:33:39 +0000569 tcg_gen_or_i32(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +0000570 tcg_temp_free_i32(t0);
bellardc896fe22008-02-01 10:05:41 +0000571 }
572}
573
pbrooka7812ae2008-11-17 14:43:54 +0000574static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000575{
aurel327fc81052009-03-10 19:37:39 +0000576 if (TCGV_EQUAL_I32(arg1, arg2)) {
577 tcg_gen_movi_i32(ret, 0);
578 } else {
579 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
580 }
bellardc896fe22008-02-01 10:05:41 +0000581}
582
pbrooka7812ae2008-11-17 14:43:54 +0000583static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000584{
Richard Henderson6f3bb332012-09-21 17:18:12 -0700585 /* Some cases can be optimized here. */
bellardc896fe22008-02-01 10:05:41 +0000586 if (arg2 == 0) {
587 tcg_gen_mov_i32(ret, arg1);
Richard Henderson6f3bb332012-09-21 17:18:12 -0700588 } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) {
589 /* Don't recurse with tcg_gen_not_i32. */
590 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1);
bellardc896fe22008-02-01 10:05:41 +0000591 } else {
pbrooka7812ae2008-11-17 14:43:54 +0000592 TCGv_i32 t0 = tcg_const_i32(arg2);
bellarde8996ee2008-05-23 17:33:39 +0000593 tcg_gen_xor_i32(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +0000594 tcg_temp_free_i32(t0);
bellardc896fe22008-02-01 10:05:41 +0000595 }
596}
597
pbrooka7812ae2008-11-17 14:43:54 +0000598static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000599{
pbrooka7812ae2008-11-17 14:43:54 +0000600 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000601}
602
pbrooka7812ae2008-11-17 14:43:54 +0000603static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000604{
bellard34151a22008-05-22 13:25:14 +0000605 if (arg2 == 0) {
606 tcg_gen_mov_i32(ret, arg1);
607 } else {
pbrooka7812ae2008-11-17 14:43:54 +0000608 TCGv_i32 t0 = tcg_const_i32(arg2);
bellarde8996ee2008-05-23 17:33:39 +0000609 tcg_gen_shl_i32(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +0000610 tcg_temp_free_i32(t0);
bellard34151a22008-05-22 13:25:14 +0000611 }
bellardc896fe22008-02-01 10:05:41 +0000612}
613
pbrooka7812ae2008-11-17 14:43:54 +0000614static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000615{
pbrooka7812ae2008-11-17 14:43:54 +0000616 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000617}
618
pbrooka7812ae2008-11-17 14:43:54 +0000619static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000620{
bellard34151a22008-05-22 13:25:14 +0000621 if (arg2 == 0) {
622 tcg_gen_mov_i32(ret, arg1);
623 } else {
pbrooka7812ae2008-11-17 14:43:54 +0000624 TCGv_i32 t0 = tcg_const_i32(arg2);
bellarde8996ee2008-05-23 17:33:39 +0000625 tcg_gen_shr_i32(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +0000626 tcg_temp_free_i32(t0);
bellard34151a22008-05-22 13:25:14 +0000627 }
bellardc896fe22008-02-01 10:05:41 +0000628}
629
pbrooka7812ae2008-11-17 14:43:54 +0000630static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000631{
pbrooka7812ae2008-11-17 14:43:54 +0000632 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000633}
634
pbrooka7812ae2008-11-17 14:43:54 +0000635static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000636{
bellard34151a22008-05-22 13:25:14 +0000637 if (arg2 == 0) {
638 tcg_gen_mov_i32(ret, arg1);
639 } else {
pbrooka7812ae2008-11-17 14:43:54 +0000640 TCGv_i32 t0 = tcg_const_i32(arg2);
bellarde8996ee2008-05-23 17:33:39 +0000641 tcg_gen_sar_i32(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +0000642 tcg_temp_free_i32(t0);
bellard34151a22008-05-22 13:25:14 +0000643 }
bellardc896fe22008-02-01 10:05:41 +0000644}
645
Richard Henderson8a56e842010-03-19 11:26:05 -0700646static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1,
647 TCGv_i32 arg2, int label_index)
bellardc896fe22008-02-01 10:05:41 +0000648{
pbrooka7812ae2008-11-17 14:43:54 +0000649 tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
bellardc896fe22008-02-01 10:05:41 +0000650}
651
Richard Henderson8a56e842010-03-19 11:26:05 -0700652static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1,
653 int32_t arg2, int label_index)
pbrookcb636692008-05-24 02:22:00 +0000654{
pbrooka7812ae2008-11-17 14:43:54 +0000655 TCGv_i32 t0 = tcg_const_i32(arg2);
pbrookcb636692008-05-24 02:22:00 +0000656 tcg_gen_brcond_i32(cond, arg1, t0, label_index);
pbrooka7812ae2008-11-17 14:43:54 +0000657 tcg_temp_free_i32(t0);
pbrookcb636692008-05-24 02:22:00 +0000658}
659
Richard Henderson8a56e842010-03-19 11:26:05 -0700660static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
Aurelien Jarno5105c552010-02-08 12:10:15 +0100661 TCGv_i32 arg1, TCGv_i32 arg2)
662{
663 tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
664}
665
Richard Henderson8a56e842010-03-19 11:26:05 -0700666static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
667 TCGv_i32 arg1, int32_t arg2)
Aurelien Jarno5105c552010-02-08 12:10:15 +0100668{
669 TCGv_i32 t0 = tcg_const_i32(arg2);
670 tcg_gen_setcond_i32(cond, ret, arg1, t0);
671 tcg_temp_free_i32(t0);
672}
673
pbrooka7812ae2008-11-17 14:43:54 +0000674static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000675{
pbrooka7812ae2008-11-17 14:43:54 +0000676 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000677}
678
pbrooka7812ae2008-11-17 14:43:54 +0000679static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
thsf730fd22008-05-04 08:14:08 +0000680{
pbrooka7812ae2008-11-17 14:43:54 +0000681 TCGv_i32 t0 = tcg_const_i32(arg2);
bellarde8996ee2008-05-23 17:33:39 +0000682 tcg_gen_mul_i32(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +0000683 tcg_temp_free_i32(t0);
thsf730fd22008-05-04 08:14:08 +0000684}
685
pbrooka7812ae2008-11-17 14:43:54 +0000686static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000687{
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700688 if (TCG_TARGET_HAS_div_i32) {
689 tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
690 } else if (TCG_TARGET_HAS_div2_i32) {
691 TCGv_i32 t0 = tcg_temp_new_i32();
692 tcg_gen_sari_i32(t0, arg1, 31);
693 tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
694 tcg_temp_free_i32(t0);
695 } else {
696 int sizemask = 0;
697 /* Return value and both arguments are 32-bit and signed. */
698 sizemask |= tcg_gen_sizemask(0, 0, 1);
699 sizemask |= tcg_gen_sizemask(1, 0, 1);
700 sizemask |= tcg_gen_sizemask(2, 0, 1);
701 tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2);
702 }
bellardc896fe22008-02-01 10:05:41 +0000703}
704
pbrooka7812ae2008-11-17 14:43:54 +0000705static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000706{
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700707 if (TCG_TARGET_HAS_div_i32) {
708 tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
709 } else if (TCG_TARGET_HAS_div2_i32) {
710 TCGv_i32 t0 = tcg_temp_new_i32();
711 tcg_gen_sari_i32(t0, arg1, 31);
712 tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
713 tcg_temp_free_i32(t0);
714 } else {
715 int sizemask = 0;
716 /* Return value and both arguments are 32-bit and signed. */
717 sizemask |= tcg_gen_sizemask(0, 0, 1);
718 sizemask |= tcg_gen_sizemask(1, 0, 1);
719 sizemask |= tcg_gen_sizemask(2, 0, 1);
720 tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2);
721 }
bellardc896fe22008-02-01 10:05:41 +0000722}
723
pbrooka7812ae2008-11-17 14:43:54 +0000724static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000725{
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700726 if (TCG_TARGET_HAS_div_i32) {
727 tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
728 } else if (TCG_TARGET_HAS_div2_i32) {
729 TCGv_i32 t0 = tcg_temp_new_i32();
730 tcg_gen_movi_i32(t0, 0);
731 tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
732 tcg_temp_free_i32(t0);
733 } else {
734 int sizemask = 0;
735 /* Return value and both arguments are 32-bit and unsigned. */
736 sizemask |= tcg_gen_sizemask(0, 0, 0);
737 sizemask |= tcg_gen_sizemask(1, 0, 0);
738 sizemask |= tcg_gen_sizemask(2, 0, 0);
739 tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2);
740 }
bellardc896fe22008-02-01 10:05:41 +0000741}
742
pbrooka7812ae2008-11-17 14:43:54 +0000743static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000744{
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700745 if (TCG_TARGET_HAS_div_i32) {
746 tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
747 } else if (TCG_TARGET_HAS_div2_i32) {
748 TCGv_i32 t0 = tcg_temp_new_i32();
749 tcg_gen_movi_i32(t0, 0);
750 tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
751 tcg_temp_free_i32(t0);
752 } else {
753 int sizemask = 0;
754 /* Return value and both arguments are 32-bit and unsigned. */
755 sizemask |= tcg_gen_sizemask(0, 0, 0);
756 sizemask |= tcg_gen_sizemask(1, 0, 0);
757 sizemask |= tcg_gen_sizemask(2, 0, 0);
758 tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2);
759 }
bellardc896fe22008-02-01 10:05:41 +0000760}
bellardc896fe22008-02-01 10:05:41 +0000761
762#if TCG_TARGET_REG_BITS == 32
763
pbrooka7812ae2008-11-17 14:43:54 +0000764static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +0000765{
aurel32fe75bcf2009-03-10 08:57:16 +0000766 if (!TCGV_EQUAL_I64(ret, arg)) {
pbrooka7812ae2008-11-17 14:43:54 +0000767 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
blueswir14d072722008-05-03 20:52:26 +0000768 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
769 }
bellardc896fe22008-02-01 10:05:41 +0000770}
771
pbrooka7812ae2008-11-17 14:43:54 +0000772static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
bellardc896fe22008-02-01 10:05:41 +0000773{
pbrooka7812ae2008-11-17 14:43:54 +0000774 tcg_gen_movi_i32(TCGV_LOW(ret), arg);
pbrookac56dd42008-02-03 19:56:33 +0000775 tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
bellardc896fe22008-02-01 10:05:41 +0000776}
777
pbrooka7812ae2008-11-17 14:43:54 +0000778static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
779 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000780{
pbrooka7812ae2008-11-17 14:43:54 +0000781 tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
pbrookac56dd42008-02-03 19:56:33 +0000782 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
bellardc896fe22008-02-01 10:05:41 +0000783}
784
pbrooka7812ae2008-11-17 14:43:54 +0000785static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
786 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000787{
pbrooka7812ae2008-11-17 14:43:54 +0000788 tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
789 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
bellardc896fe22008-02-01 10:05:41 +0000790}
791
pbrooka7812ae2008-11-17 14:43:54 +0000792static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
793 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000794{
aurel32a7477232009-02-09 20:43:53 +0000795 tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
pbrookac56dd42008-02-03 19:56:33 +0000796 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
bellardc896fe22008-02-01 10:05:41 +0000797}
798
pbrooka7812ae2008-11-17 14:43:54 +0000799static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
800 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000801{
pbrooka7812ae2008-11-17 14:43:54 +0000802 tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
803 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
bellardc896fe22008-02-01 10:05:41 +0000804}
805
pbrooka7812ae2008-11-17 14:43:54 +0000806static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
807 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000808{
pbrooka7812ae2008-11-17 14:43:54 +0000809 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
pbrookac56dd42008-02-03 19:56:33 +0000810 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
bellardc896fe22008-02-01 10:05:41 +0000811}
812
pbrooka7812ae2008-11-17 14:43:54 +0000813static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
814 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000815{
pbrooka7812ae2008-11-17 14:43:54 +0000816 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
817 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
bellardc896fe22008-02-01 10:05:41 +0000818}
819
pbrooka7812ae2008-11-17 14:43:54 +0000820static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
821 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000822{
823 /* since arg2 and ret have different types, they cannot be the
824 same temporary */
825#ifdef TCG_TARGET_WORDS_BIGENDIAN
pbrookac56dd42008-02-03 19:56:33 +0000826 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
pbrooka7812ae2008-11-17 14:43:54 +0000827 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
bellardc896fe22008-02-01 10:05:41 +0000828#else
pbrooka7812ae2008-11-17 14:43:54 +0000829 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
pbrookac56dd42008-02-03 19:56:33 +0000830 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
bellardc896fe22008-02-01 10:05:41 +0000831#endif
832}
833
pbrooka7812ae2008-11-17 14:43:54 +0000834static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
835 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000836{
pbrooka7812ae2008-11-17 14:43:54 +0000837 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000838}
839
pbrooka7812ae2008-11-17 14:43:54 +0000840static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
841 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000842{
pbrooka7812ae2008-11-17 14:43:54 +0000843 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000844}
845
pbrooka7812ae2008-11-17 14:43:54 +0000846static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
847 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000848{
pbrooka7812ae2008-11-17 14:43:54 +0000849 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000850}
851
pbrooka7812ae2008-11-17 14:43:54 +0000852static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
853 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000854{
855#ifdef TCG_TARGET_WORDS_BIGENDIAN
pbrookac56dd42008-02-03 19:56:33 +0000856 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
pbrooka7812ae2008-11-17 14:43:54 +0000857 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
bellardc896fe22008-02-01 10:05:41 +0000858#else
pbrooka7812ae2008-11-17 14:43:54 +0000859 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
pbrookac56dd42008-02-03 19:56:33 +0000860 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
bellardc896fe22008-02-01 10:05:41 +0000861#endif
862}
863
pbrooka7812ae2008-11-17 14:43:54 +0000864static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000865{
pbrooka7812ae2008-11-17 14:43:54 +0000866 tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
867 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
868 TCGV_HIGH(arg2));
bellardc896fe22008-02-01 10:05:41 +0000869}
870
pbrooka7812ae2008-11-17 14:43:54 +0000871static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000872{
pbrooka7812ae2008-11-17 14:43:54 +0000873 tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
874 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
875 TCGV_HIGH(arg2));
bellardc896fe22008-02-01 10:05:41 +0000876}
877
pbrooka7812ae2008-11-17 14:43:54 +0000878static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000879{
pbrooka7812ae2008-11-17 14:43:54 +0000880 tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
pbrookac56dd42008-02-03 19:56:33 +0000881 tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
bellardc896fe22008-02-01 10:05:41 +0000882}
883
pbrooka7812ae2008-11-17 14:43:54 +0000884static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000885{
aurel32e5105082009-03-11 02:57:30 +0000886 tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
887 tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
bellardc896fe22008-02-01 10:05:41 +0000888}
889
pbrooka7812ae2008-11-17 14:43:54 +0000890static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000891{
aurel32e5105082009-03-11 02:57:30 +0000892 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
893 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
bellardc896fe22008-02-01 10:05:41 +0000894}
895
pbrooka7812ae2008-11-17 14:43:54 +0000896static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000897{
pbrooka7812ae2008-11-17 14:43:54 +0000898 tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
pbrookac56dd42008-02-03 19:56:33 +0000899 tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
bellardc896fe22008-02-01 10:05:41 +0000900}
901
pbrooka7812ae2008-11-17 14:43:54 +0000902static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000903{
aurel32e5105082009-03-11 02:57:30 +0000904 tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
905 tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
bellardc896fe22008-02-01 10:05:41 +0000906}
907
pbrooka7812ae2008-11-17 14:43:54 +0000908static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000909{
pbrooka7812ae2008-11-17 14:43:54 +0000910 tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
pbrookac56dd42008-02-03 19:56:33 +0000911 tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
bellardc896fe22008-02-01 10:05:41 +0000912}
913
914/* XXX: use generic code when basic block handling is OK or CPU
915 specific code (x86) */
pbrooka7812ae2008-11-17 14:43:54 +0000916static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000917{
Richard Henderson2bece2c2010-06-14 17:35:27 -0700918 int sizemask = 0;
919 /* Return value and both arguments are 64-bit and signed. */
920 sizemask |= tcg_gen_sizemask(0, 1, 1);
921 sizemask |= tcg_gen_sizemask(1, 1, 1);
922 sizemask |= tcg_gen_sizemask(2, 1, 1);
923
924 tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000925}
926
pbrooka7812ae2008-11-17 14:43:54 +0000927static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000928{
929 tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
930}
931
pbrooka7812ae2008-11-17 14:43:54 +0000932static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000933{
Richard Henderson2bece2c2010-06-14 17:35:27 -0700934 int sizemask = 0;
935 /* Return value and both arguments are 64-bit and signed. */
936 sizemask |= tcg_gen_sizemask(0, 1, 1);
937 sizemask |= tcg_gen_sizemask(1, 1, 1);
938 sizemask |= tcg_gen_sizemask(2, 1, 1);
939
940 tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000941}
942
pbrooka7812ae2008-11-17 14:43:54 +0000943static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000944{
945 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
946}
947
pbrooka7812ae2008-11-17 14:43:54 +0000948static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000949{
Richard Henderson2bece2c2010-06-14 17:35:27 -0700950 int sizemask = 0;
951 /* Return value and both arguments are 64-bit and signed. */
952 sizemask |= tcg_gen_sizemask(0, 1, 1);
953 sizemask |= tcg_gen_sizemask(1, 1, 1);
954 sizemask |= tcg_gen_sizemask(2, 1, 1);
955
956 tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000957}
958
pbrooka7812ae2008-11-17 14:43:54 +0000959static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
bellardc896fe22008-02-01 10:05:41 +0000960{
961 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
962}
963
Richard Henderson8a56e842010-03-19 11:26:05 -0700964static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
965 TCGv_i64 arg2, int label_index)
bellardc896fe22008-02-01 10:05:41 +0000966{
pbrooka7812ae2008-11-17 14:43:54 +0000967 tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
968 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
969 TCGV_HIGH(arg2), cond, label_index);
bellardc896fe22008-02-01 10:05:41 +0000970}
971
Richard Henderson8a56e842010-03-19 11:26:05 -0700972static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
Aurelien Jarno5105c552010-02-08 12:10:15 +0100973 TCGv_i64 arg1, TCGv_i64 arg2)
974{
975 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
976 TCGV_LOW(arg1), TCGV_HIGH(arg1),
977 TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
978 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
979}
980
pbrooka7812ae2008-11-17 14:43:54 +0000981static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000982{
pbrooka7812ae2008-11-17 14:43:54 +0000983 TCGv_i64 t0;
984 TCGv_i32 t1;
bellardc896fe22008-02-01 10:05:41 +0000985
pbrooka7812ae2008-11-17 14:43:54 +0000986 t0 = tcg_temp_new_i64();
987 t1 = tcg_temp_new_i32();
988
989 tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
990 TCGV_LOW(arg1), TCGV_LOW(arg2));
991
992 tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
pbrookac56dd42008-02-03 19:56:33 +0000993 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
pbrooka7812ae2008-11-17 14:43:54 +0000994 tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
pbrookac56dd42008-02-03 19:56:33 +0000995 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
pbrooka7812ae2008-11-17 14:43:54 +0000996
bellardc896fe22008-02-01 10:05:41 +0000997 tcg_gen_mov_i64(ret, t0);
pbrooka7812ae2008-11-17 14:43:54 +0000998 tcg_temp_free_i64(t0);
999 tcg_temp_free_i32(t1);
bellardc896fe22008-02-01 10:05:41 +00001000}
1001
pbrooka7812ae2008-11-17 14:43:54 +00001002static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001003{
Richard Henderson2bece2c2010-06-14 17:35:27 -07001004 int sizemask = 0;
1005 /* Return value and both arguments are 64-bit and signed. */
1006 sizemask |= tcg_gen_sizemask(0, 1, 1);
1007 sizemask |= tcg_gen_sizemask(1, 1, 1);
1008 sizemask |= tcg_gen_sizemask(2, 1, 1);
1009
1010 tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +00001011}
1012
pbrooka7812ae2008-11-17 14:43:54 +00001013static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001014{
Richard Henderson2bece2c2010-06-14 17:35:27 -07001015 int sizemask = 0;
1016 /* Return value and both arguments are 64-bit and signed. */
1017 sizemask |= tcg_gen_sizemask(0, 1, 1);
1018 sizemask |= tcg_gen_sizemask(1, 1, 1);
1019 sizemask |= tcg_gen_sizemask(2, 1, 1);
1020
1021 tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +00001022}
1023
pbrooka7812ae2008-11-17 14:43:54 +00001024static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001025{
Richard Henderson2bece2c2010-06-14 17:35:27 -07001026 int sizemask = 0;
1027 /* Return value and both arguments are 64-bit and unsigned. */
1028 sizemask |= tcg_gen_sizemask(0, 1, 0);
1029 sizemask |= tcg_gen_sizemask(1, 1, 0);
1030 sizemask |= tcg_gen_sizemask(2, 1, 0);
1031
1032 tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +00001033}
1034
pbrooka7812ae2008-11-17 14:43:54 +00001035static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001036{
Richard Henderson2bece2c2010-06-14 17:35:27 -07001037 int sizemask = 0;
1038 /* Return value and both arguments are 64-bit and unsigned. */
1039 sizemask |= tcg_gen_sizemask(0, 1, 0);
1040 sizemask |= tcg_gen_sizemask(1, 1, 0);
1041 sizemask |= tcg_gen_sizemask(2, 1, 0);
1042
1043 tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +00001044}
1045
1046#else
1047
pbrooka7812ae2008-11-17 14:43:54 +00001048static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +00001049{
aurel32fe75bcf2009-03-10 08:57:16 +00001050 if (!TCGV_EQUAL_I64(ret, arg))
pbrooka7812ae2008-11-17 14:43:54 +00001051 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
bellardc896fe22008-02-01 10:05:41 +00001052}
1053
pbrooka7812ae2008-11-17 14:43:54 +00001054static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
bellardc896fe22008-02-01 10:05:41 +00001055{
pbrooka7812ae2008-11-17 14:43:54 +00001056 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
bellardc896fe22008-02-01 10:05:41 +00001057}
1058
Peter Maydell6bd4b082011-05-27 13:12:12 +01001059static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +00001060 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +00001061{
pbrooka7812ae2008-11-17 14:43:54 +00001062 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +00001063}
1064
Peter Maydell6bd4b082011-05-27 13:12:12 +01001065static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +00001066 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +00001067{
pbrooka7812ae2008-11-17 14:43:54 +00001068 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +00001069}
1070
Peter Maydell6bd4b082011-05-27 13:12:12 +01001071static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +00001072 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +00001073{
pbrooka7812ae2008-11-17 14:43:54 +00001074 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +00001075}
1076
Peter Maydell6bd4b082011-05-27 13:12:12 +01001077static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +00001078 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +00001079{
pbrooka7812ae2008-11-17 14:43:54 +00001080 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +00001081}
1082
Peter Maydell6bd4b082011-05-27 13:12:12 +01001083static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +00001084 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +00001085{
pbrooka7812ae2008-11-17 14:43:54 +00001086 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +00001087}
1088
Peter Maydell6bd4b082011-05-27 13:12:12 +01001089static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +00001090 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +00001091{
pbrooka7812ae2008-11-17 14:43:54 +00001092 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +00001093}
1094
Peter Maydell6bd4b082011-05-27 13:12:12 +01001095static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +00001096{
pbrooka7812ae2008-11-17 14:43:54 +00001097 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +00001098}
1099
Peter Maydell6bd4b082011-05-27 13:12:12 +01001100static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +00001101 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +00001102{
pbrooka7812ae2008-11-17 14:43:54 +00001103 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +00001104}
1105
Peter Maydell6bd4b082011-05-27 13:12:12 +01001106static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +00001107 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +00001108{
pbrooka7812ae2008-11-17 14:43:54 +00001109 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +00001110}
1111
Peter Maydell6bd4b082011-05-27 13:12:12 +01001112static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +00001113 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +00001114{
pbrooka7812ae2008-11-17 14:43:54 +00001115 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +00001116}
1117
Peter Maydell6bd4b082011-05-27 13:12:12 +01001118static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +00001119{
pbrooka7812ae2008-11-17 14:43:54 +00001120 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +00001121}
1122
pbrooka7812ae2008-11-17 14:43:54 +00001123static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001124{
pbrooka7812ae2008-11-17 14:43:54 +00001125 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +00001126}
1127
pbrooka7812ae2008-11-17 14:43:54 +00001128static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001129{
pbrooka7812ae2008-11-17 14:43:54 +00001130 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +00001131}
1132
pbrooka7812ae2008-11-17 14:43:54 +00001133static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001134{
aurel327fc81052009-03-10 19:37:39 +00001135 if (TCGV_EQUAL_I64(arg1, arg2)) {
1136 tcg_gen_mov_i64(ret, arg1);
1137 } else {
1138 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
1139 }
bellardc896fe22008-02-01 10:05:41 +00001140}
1141
Richard Henderson42ce3e22012-09-21 17:18:10 -07001142static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
bellardc896fe22008-02-01 10:05:41 +00001143{
Richard Henderson42ce3e22012-09-21 17:18:10 -07001144 TCGv_i64 t0;
1145 /* Some cases can be optimized here. */
1146 switch (arg2) {
1147 case 0:
1148 tcg_gen_movi_i64(ret, 0);
1149 return;
1150 case 0xffffffffffffffffull:
1151 tcg_gen_mov_i64(ret, arg1);
1152 return;
1153 case 0xffull:
1154 /* Don't recurse with tcg_gen_ext8u_i32. */
1155 if (TCG_TARGET_HAS_ext8u_i64) {
1156 tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1);
1157 return;
1158 }
1159 break;
1160 case 0xffffu:
1161 if (TCG_TARGET_HAS_ext16u_i64) {
1162 tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1);
1163 return;
1164 }
1165 break;
1166 case 0xffffffffull:
1167 if (TCG_TARGET_HAS_ext32u_i64) {
1168 tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1);
1169 return;
1170 }
1171 break;
1172 }
1173 t0 = tcg_const_i64(arg2);
bellarde8996ee2008-05-23 17:33:39 +00001174 tcg_gen_and_i64(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +00001175 tcg_temp_free_i64(t0);
bellardc896fe22008-02-01 10:05:41 +00001176}
1177
pbrooka7812ae2008-11-17 14:43:54 +00001178static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001179{
aurel327fc81052009-03-10 19:37:39 +00001180 if (TCGV_EQUAL_I64(arg1, arg2)) {
1181 tcg_gen_mov_i64(ret, arg1);
1182 } else {
1183 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
1184 }
bellardc896fe22008-02-01 10:05:41 +00001185}
1186
pbrooka7812ae2008-11-17 14:43:54 +00001187static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
bellardc896fe22008-02-01 10:05:41 +00001188{
Richard Hendersond81ada72012-09-21 17:18:11 -07001189 /* Some cases can be optimized here. */
1190 if (arg2 == -1) {
1191 tcg_gen_movi_i64(ret, -1);
1192 } else if (arg2 == 0) {
1193 tcg_gen_mov_i64(ret, arg1);
1194 } else {
1195 TCGv_i64 t0 = tcg_const_i64(arg2);
1196 tcg_gen_or_i64(ret, arg1, t0);
1197 tcg_temp_free_i64(t0);
1198 }
bellardc896fe22008-02-01 10:05:41 +00001199}
1200
pbrooka7812ae2008-11-17 14:43:54 +00001201static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001202{
aurel327fc81052009-03-10 19:37:39 +00001203 if (TCGV_EQUAL_I64(arg1, arg2)) {
1204 tcg_gen_movi_i64(ret, 0);
1205 } else {
1206 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
1207 }
bellardc896fe22008-02-01 10:05:41 +00001208}
1209
pbrooka7812ae2008-11-17 14:43:54 +00001210static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
bellardc896fe22008-02-01 10:05:41 +00001211{
Richard Henderson6f3bb332012-09-21 17:18:12 -07001212 /* Some cases can be optimized here. */
1213 if (arg2 == 0) {
1214 tcg_gen_mov_i64(ret, arg1);
1215 } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) {
1216 /* Don't recurse with tcg_gen_not_i64. */
1217 tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1);
1218 } else {
1219 TCGv_i64 t0 = tcg_const_i64(arg2);
1220 tcg_gen_xor_i64(ret, arg1, t0);
1221 tcg_temp_free_i64(t0);
1222 }
bellardc896fe22008-02-01 10:05:41 +00001223}
1224
pbrooka7812ae2008-11-17 14:43:54 +00001225static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001226{
pbrooka7812ae2008-11-17 14:43:54 +00001227 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +00001228}
1229
pbrooka7812ae2008-11-17 14:43:54 +00001230static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
bellardc896fe22008-02-01 10:05:41 +00001231{
bellard34151a22008-05-22 13:25:14 +00001232 if (arg2 == 0) {
1233 tcg_gen_mov_i64(ret, arg1);
1234 } else {
pbrooka7812ae2008-11-17 14:43:54 +00001235 TCGv_i64 t0 = tcg_const_i64(arg2);
bellarde8996ee2008-05-23 17:33:39 +00001236 tcg_gen_shl_i64(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +00001237 tcg_temp_free_i64(t0);
bellard34151a22008-05-22 13:25:14 +00001238 }
bellardc896fe22008-02-01 10:05:41 +00001239}
1240
pbrooka7812ae2008-11-17 14:43:54 +00001241static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001242{
pbrooka7812ae2008-11-17 14:43:54 +00001243 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +00001244}
1245
pbrooka7812ae2008-11-17 14:43:54 +00001246static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
bellardc896fe22008-02-01 10:05:41 +00001247{
bellard34151a22008-05-22 13:25:14 +00001248 if (arg2 == 0) {
1249 tcg_gen_mov_i64(ret, arg1);
1250 } else {
pbrooka7812ae2008-11-17 14:43:54 +00001251 TCGv_i64 t0 = tcg_const_i64(arg2);
bellarde8996ee2008-05-23 17:33:39 +00001252 tcg_gen_shr_i64(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +00001253 tcg_temp_free_i64(t0);
bellard34151a22008-05-22 13:25:14 +00001254 }
bellardc896fe22008-02-01 10:05:41 +00001255}
1256
pbrooka7812ae2008-11-17 14:43:54 +00001257static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001258{
pbrooka7812ae2008-11-17 14:43:54 +00001259 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +00001260}
1261
pbrooka7812ae2008-11-17 14:43:54 +00001262static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
bellardc896fe22008-02-01 10:05:41 +00001263{
bellard34151a22008-05-22 13:25:14 +00001264 if (arg2 == 0) {
1265 tcg_gen_mov_i64(ret, arg1);
1266 } else {
pbrooka7812ae2008-11-17 14:43:54 +00001267 TCGv_i64 t0 = tcg_const_i64(arg2);
bellarde8996ee2008-05-23 17:33:39 +00001268 tcg_gen_sar_i64(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +00001269 tcg_temp_free_i64(t0);
bellard34151a22008-05-22 13:25:14 +00001270 }
bellardc896fe22008-02-01 10:05:41 +00001271}
1272
Richard Henderson8a56e842010-03-19 11:26:05 -07001273static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
1274 TCGv_i64 arg2, int label_index)
bellardc896fe22008-02-01 10:05:41 +00001275{
pbrooka7812ae2008-11-17 14:43:54 +00001276 tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
bellardc896fe22008-02-01 10:05:41 +00001277}
1278
Richard Henderson8a56e842010-03-19 11:26:05 -07001279static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
Aurelien Jarno5105c552010-02-08 12:10:15 +01001280 TCGv_i64 arg1, TCGv_i64 arg2)
1281{
1282 tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1283}
1284
pbrooka7812ae2008-11-17 14:43:54 +00001285static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001286{
pbrooka7812ae2008-11-17 14:43:54 +00001287 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +00001288}
1289
pbrooka7812ae2008-11-17 14:43:54 +00001290static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001291{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001292 if (TCG_TARGET_HAS_div_i64) {
1293 tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1294 } else if (TCG_TARGET_HAS_div2_i64) {
1295 TCGv_i64 t0 = tcg_temp_new_i64();
1296 tcg_gen_sari_i64(t0, arg1, 63);
1297 tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1298 tcg_temp_free_i64(t0);
1299 } else {
1300 int sizemask = 0;
1301 /* Return value and both arguments are 64-bit and signed. */
1302 sizemask |= tcg_gen_sizemask(0, 1, 1);
1303 sizemask |= tcg_gen_sizemask(1, 1, 1);
1304 sizemask |= tcg_gen_sizemask(2, 1, 1);
1305 tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1306 }
bellardc896fe22008-02-01 10:05:41 +00001307}
1308
pbrooka7812ae2008-11-17 14:43:54 +00001309static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001310{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001311 if (TCG_TARGET_HAS_div_i64) {
1312 tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1313 } else if (TCG_TARGET_HAS_div2_i64) {
1314 TCGv_i64 t0 = tcg_temp_new_i64();
1315 tcg_gen_sari_i64(t0, arg1, 63);
1316 tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1317 tcg_temp_free_i64(t0);
1318 } else {
1319 int sizemask = 0;
1320 /* Return value and both arguments are 64-bit and signed. */
1321 sizemask |= tcg_gen_sizemask(0, 1, 1);
1322 sizemask |= tcg_gen_sizemask(1, 1, 1);
1323 sizemask |= tcg_gen_sizemask(2, 1, 1);
1324 tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1325 }
bellardc896fe22008-02-01 10:05:41 +00001326}
1327
pbrooka7812ae2008-11-17 14:43:54 +00001328static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001329{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001330 if (TCG_TARGET_HAS_div_i64) {
1331 tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1332 } else if (TCG_TARGET_HAS_div2_i64) {
1333 TCGv_i64 t0 = tcg_temp_new_i64();
1334 tcg_gen_movi_i64(t0, 0);
1335 tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1336 tcg_temp_free_i64(t0);
1337 } else {
1338 int sizemask = 0;
1339 /* Return value and both arguments are 64-bit and unsigned. */
1340 sizemask |= tcg_gen_sizemask(0, 1, 0);
1341 sizemask |= tcg_gen_sizemask(1, 1, 0);
1342 sizemask |= tcg_gen_sizemask(2, 1, 0);
1343 tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1344 }
bellardc896fe22008-02-01 10:05:41 +00001345}
1346
pbrooka7812ae2008-11-17 14:43:54 +00001347static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +00001348{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001349 if (TCG_TARGET_HAS_div_i64) {
1350 tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1351 } else if (TCG_TARGET_HAS_div2_i64) {
1352 TCGv_i64 t0 = tcg_temp_new_i64();
1353 tcg_gen_movi_i64(t0, 0);
1354 tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1355 tcg_temp_free_i64(t0);
1356 } else {
1357 int sizemask = 0;
1358 /* Return value and both arguments are 64-bit and unsigned. */
1359 sizemask |= tcg_gen_sizemask(0, 1, 0);
1360 sizemask |= tcg_gen_sizemask(1, 1, 0);
1361 sizemask |= tcg_gen_sizemask(2, 1, 0);
1362 tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1363 }
bellardc896fe22008-02-01 10:05:41 +00001364}
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001365#endif /* TCG_TARGET_REG_BITS == 32 */
bellardc896fe22008-02-01 10:05:41 +00001366
pbrooka7812ae2008-11-17 14:43:54 +00001367static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
aurel3263597062008-11-02 08:22:54 +00001368{
1369 /* some cases can be optimized here */
1370 if (arg2 == 0) {
1371 tcg_gen_mov_i64(ret, arg1);
1372 } else {
pbrooka7812ae2008-11-17 14:43:54 +00001373 TCGv_i64 t0 = tcg_const_i64(arg2);
aurel3263597062008-11-02 08:22:54 +00001374 tcg_gen_add_i64(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +00001375 tcg_temp_free_i64(t0);
aurel3263597062008-11-02 08:22:54 +00001376 }
1377}
1378
pbrooka7812ae2008-11-17 14:43:54 +00001379static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
aurel3200457342008-11-02 08:23:04 +00001380{
pbrooka7812ae2008-11-17 14:43:54 +00001381 TCGv_i64 t0 = tcg_const_i64(arg1);
aurel3200457342008-11-02 08:23:04 +00001382 tcg_gen_sub_i64(ret, t0, arg2);
pbrooka7812ae2008-11-17 14:43:54 +00001383 tcg_temp_free_i64(t0);
aurel3200457342008-11-02 08:23:04 +00001384}
1385
pbrooka7812ae2008-11-17 14:43:54 +00001386static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
aurel3263597062008-11-02 08:22:54 +00001387{
1388 /* some cases can be optimized here */
1389 if (arg2 == 0) {
1390 tcg_gen_mov_i64(ret, arg1);
1391 } else {
pbrooka7812ae2008-11-17 14:43:54 +00001392 TCGv_i64 t0 = tcg_const_i64(arg2);
aurel3263597062008-11-02 08:22:54 +00001393 tcg_gen_sub_i64(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +00001394 tcg_temp_free_i64(t0);
aurel3263597062008-11-02 08:22:54 +00001395 }
1396}
Richard Henderson8a56e842010-03-19 11:26:05 -07001397static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1,
1398 int64_t arg2, int label_index)
aurel32f02bb952008-11-03 07:08:26 +00001399{
pbrooka7812ae2008-11-17 14:43:54 +00001400 TCGv_i64 t0 = tcg_const_i64(arg2);
aurel32f02bb952008-11-03 07:08:26 +00001401 tcg_gen_brcond_i64(cond, arg1, t0, label_index);
pbrooka7812ae2008-11-17 14:43:54 +00001402 tcg_temp_free_i64(t0);
aurel32f02bb952008-11-03 07:08:26 +00001403}
1404
Richard Henderson8a56e842010-03-19 11:26:05 -07001405static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1406 TCGv_i64 arg1, int64_t arg2)
Aurelien Jarno5105c552010-02-08 12:10:15 +01001407{
1408 TCGv_i64 t0 = tcg_const_i64(arg2);
1409 tcg_gen_setcond_i64(cond, ret, arg1, t0);
1410 tcg_temp_free_i64(t0);
1411}
1412
pbrooka7812ae2008-11-17 14:43:54 +00001413static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
aurel32f02bb952008-11-03 07:08:26 +00001414{
pbrooka7812ae2008-11-17 14:43:54 +00001415 TCGv_i64 t0 = tcg_const_i64(arg2);
aurel32f02bb952008-11-03 07:08:26 +00001416 tcg_gen_mul_i64(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +00001417 tcg_temp_free_i64(t0);
aurel32f02bb952008-11-03 07:08:26 +00001418}
1419
aurel3263597062008-11-02 08:22:54 +00001420
bellardc896fe22008-02-01 10:05:41 +00001421/***************************************/
1422/* optional operations */
1423
pbrooka7812ae2008-11-17 14:43:54 +00001424static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +00001425{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001426 if (TCG_TARGET_HAS_ext8s_i32) {
1427 tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1428 } else {
1429 tcg_gen_shli_i32(ret, arg, 24);
1430 tcg_gen_sari_i32(ret, ret, 24);
1431 }
bellardc896fe22008-02-01 10:05:41 +00001432}
1433
pbrooka7812ae2008-11-17 14:43:54 +00001434static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +00001435{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001436 if (TCG_TARGET_HAS_ext16s_i32) {
1437 tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1438 } else {
1439 tcg_gen_shli_i32(ret, arg, 16);
1440 tcg_gen_sari_i32(ret, ret, 16);
1441 }
bellardc896fe22008-02-01 10:05:41 +00001442}
1443
pbrooka7812ae2008-11-17 14:43:54 +00001444static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
pbrook86831432008-05-11 12:22:01 +00001445{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001446 if (TCG_TARGET_HAS_ext8u_i32) {
1447 tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1448 } else {
1449 tcg_gen_andi_i32(ret, arg, 0xffu);
1450 }
pbrook86831432008-05-11 12:22:01 +00001451}
1452
pbrooka7812ae2008-11-17 14:43:54 +00001453static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
pbrook86831432008-05-11 12:22:01 +00001454{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001455 if (TCG_TARGET_HAS_ext16u_i32) {
1456 tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1457 } else {
1458 tcg_gen_andi_i32(ret, arg, 0xffffu);
1459 }
pbrook86831432008-05-11 12:22:01 +00001460}
1461
bellardc896fe22008-02-01 10:05:41 +00001462/* Note: we assume the two high bytes are set to zero */
pbrooka7812ae2008-11-17 14:43:54 +00001463static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +00001464{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001465 if (TCG_TARGET_HAS_bswap16_i32) {
1466 tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1467 } else {
1468 TCGv_i32 t0 = tcg_temp_new_i32();
bellardc896fe22008-02-01 10:05:41 +00001469
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001470 tcg_gen_ext8u_i32(t0, arg);
1471 tcg_gen_shli_i32(t0, t0, 8);
1472 tcg_gen_shri_i32(ret, arg, 8);
1473 tcg_gen_or_i32(ret, ret, t0);
1474 tcg_temp_free_i32(t0);
1475 }
bellardc896fe22008-02-01 10:05:41 +00001476}
1477
aurel3266896cb2009-03-13 09:34:48 +00001478static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +00001479{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001480 if (TCG_TARGET_HAS_bswap32_i32) {
1481 tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1482 } else {
1483 TCGv_i32 t0, t1;
1484 t0 = tcg_temp_new_i32();
1485 t1 = tcg_temp_new_i32();
bellardc896fe22008-02-01 10:05:41 +00001486
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001487 tcg_gen_shli_i32(t0, arg, 24);
bellardc896fe22008-02-01 10:05:41 +00001488
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001489 tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1490 tcg_gen_shli_i32(t1, t1, 8);
1491 tcg_gen_or_i32(t0, t0, t1);
bellardc896fe22008-02-01 10:05:41 +00001492
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001493 tcg_gen_shri_i32(t1, arg, 8);
1494 tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1495 tcg_gen_or_i32(t0, t0, t1);
bellardc896fe22008-02-01 10:05:41 +00001496
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001497 tcg_gen_shri_i32(t1, arg, 24);
1498 tcg_gen_or_i32(ret, t0, t1);
1499 tcg_temp_free_i32(t0);
1500 tcg_temp_free_i32(t1);
1501 }
bellardc896fe22008-02-01 10:05:41 +00001502}
1503
1504#if TCG_TARGET_REG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +00001505static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +00001506{
pbrooka7812ae2008-11-17 14:43:54 +00001507 tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1508 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
bellardc896fe22008-02-01 10:05:41 +00001509}
1510
pbrooka7812ae2008-11-17 14:43:54 +00001511static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +00001512{
pbrooka7812ae2008-11-17 14:43:54 +00001513 tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1514 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
bellardc896fe22008-02-01 10:05:41 +00001515}
1516
pbrooka7812ae2008-11-17 14:43:54 +00001517static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +00001518{
pbrooka7812ae2008-11-17 14:43:54 +00001519 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1520 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
bellardc896fe22008-02-01 10:05:41 +00001521}
1522
pbrooka7812ae2008-11-17 14:43:54 +00001523static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
pbrook86831432008-05-11 12:22:01 +00001524{
pbrooka7812ae2008-11-17 14:43:54 +00001525 tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
pbrook86831432008-05-11 12:22:01 +00001526 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1527}
1528
pbrooka7812ae2008-11-17 14:43:54 +00001529static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
pbrook86831432008-05-11 12:22:01 +00001530{
pbrooka7812ae2008-11-17 14:43:54 +00001531 tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
pbrook86831432008-05-11 12:22:01 +00001532 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1533}
1534
pbrooka7812ae2008-11-17 14:43:54 +00001535static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
pbrook86831432008-05-11 12:22:01 +00001536{
pbrooka7812ae2008-11-17 14:43:54 +00001537 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
pbrook86831432008-05-11 12:22:01 +00001538 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1539}
1540
pbrooka7812ae2008-11-17 14:43:54 +00001541static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +00001542{
pbrooka7812ae2008-11-17 14:43:54 +00001543 tcg_gen_mov_i32(ret, TCGV_LOW(arg));
bellardc896fe22008-02-01 10:05:41 +00001544}
1545
pbrooka7812ae2008-11-17 14:43:54 +00001546static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +00001547{
pbrooka7812ae2008-11-17 14:43:54 +00001548 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
pbrookac56dd42008-02-03 19:56:33 +00001549 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
bellardc896fe22008-02-01 10:05:41 +00001550}
1551
pbrooka7812ae2008-11-17 14:43:54 +00001552static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +00001553{
pbrooka7812ae2008-11-17 14:43:54 +00001554 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1555 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
bellardc896fe22008-02-01 10:05:41 +00001556}
1557
aurel329a5c57f2009-03-13 09:35:12 +00001558/* Note: we assume the six high bytes are set to zero */
1559static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1560{
1561 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1562 tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1563}
1564
1565/* Note: we assume the four high bytes are set to zero */
1566static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1567{
1568 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1569 tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1570}
1571
aurel3266896cb2009-03-13 09:34:48 +00001572static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +00001573{
pbrooka7812ae2008-11-17 14:43:54 +00001574 TCGv_i32 t0, t1;
1575 t0 = tcg_temp_new_i32();
1576 t1 = tcg_temp_new_i32();
bellardc896fe22008-02-01 10:05:41 +00001577
aurel3266896cb2009-03-13 09:34:48 +00001578 tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1579 tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
pbrooka7812ae2008-11-17 14:43:54 +00001580 tcg_gen_mov_i32(TCGV_LOW(ret), t1);
pbrookac56dd42008-02-03 19:56:33 +00001581 tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
pbrooka7812ae2008-11-17 14:43:54 +00001582 tcg_temp_free_i32(t0);
1583 tcg_temp_free_i32(t1);
bellardc896fe22008-02-01 10:05:41 +00001584}
1585#else
1586
pbrooka7812ae2008-11-17 14:43:54 +00001587static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +00001588{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001589 if (TCG_TARGET_HAS_ext8s_i64) {
1590 tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1591 } else {
1592 tcg_gen_shli_i64(ret, arg, 56);
1593 tcg_gen_sari_i64(ret, ret, 56);
1594 }
bellardc896fe22008-02-01 10:05:41 +00001595}
1596
pbrooka7812ae2008-11-17 14:43:54 +00001597static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +00001598{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001599 if (TCG_TARGET_HAS_ext16s_i64) {
1600 tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1601 } else {
1602 tcg_gen_shli_i64(ret, arg, 48);
1603 tcg_gen_sari_i64(ret, ret, 48);
1604 }
bellardc896fe22008-02-01 10:05:41 +00001605}
1606
pbrooka7812ae2008-11-17 14:43:54 +00001607static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +00001608{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001609 if (TCG_TARGET_HAS_ext32s_i64) {
1610 tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1611 } else {
1612 tcg_gen_shli_i64(ret, arg, 32);
1613 tcg_gen_sari_i64(ret, ret, 32);
1614 }
bellardc896fe22008-02-01 10:05:41 +00001615}
1616
pbrooka7812ae2008-11-17 14:43:54 +00001617static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
pbrook86831432008-05-11 12:22:01 +00001618{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001619 if (TCG_TARGET_HAS_ext8u_i64) {
1620 tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1621 } else {
1622 tcg_gen_andi_i64(ret, arg, 0xffu);
1623 }
pbrook86831432008-05-11 12:22:01 +00001624}
1625
pbrooka7812ae2008-11-17 14:43:54 +00001626static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
pbrook86831432008-05-11 12:22:01 +00001627{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001628 if (TCG_TARGET_HAS_ext16u_i64) {
1629 tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1630 } else {
1631 tcg_gen_andi_i64(ret, arg, 0xffffu);
1632 }
pbrook86831432008-05-11 12:22:01 +00001633}
1634
pbrooka7812ae2008-11-17 14:43:54 +00001635static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
pbrook86831432008-05-11 12:22:01 +00001636{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001637 if (TCG_TARGET_HAS_ext32u_i64) {
1638 tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1639 } else {
1640 tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1641 }
pbrook86831432008-05-11 12:22:01 +00001642}
1643
bellardc896fe22008-02-01 10:05:41 +00001644/* Note: we assume the target supports move between 32 and 64 bit
pbrookac56dd42008-02-03 19:56:33 +00001645 registers. This will probably break MIPS64 targets. */
pbrooka7812ae2008-11-17 14:43:54 +00001646static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +00001647{
pbrooka7812ae2008-11-17 14:43:54 +00001648 tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
bellardc896fe22008-02-01 10:05:41 +00001649}
1650
1651/* Note: we assume the target supports move between 32 and 64 bit
1652 registers */
pbrooka7812ae2008-11-17 14:43:54 +00001653static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +00001654{
Aurelien Jarnocfc86982009-09-30 23:09:35 +02001655 tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
bellardc896fe22008-02-01 10:05:41 +00001656}
1657
1658/* Note: we assume the target supports move between 32 and 64 bit
1659 registers */
pbrooka7812ae2008-11-17 14:43:54 +00001660static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +00001661{
pbrooka7812ae2008-11-17 14:43:54 +00001662 tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
bellardc896fe22008-02-01 10:05:41 +00001663}
1664
aurel329a5c57f2009-03-13 09:35:12 +00001665/* Note: we assume the six high bytes are set to zero */
1666static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1667{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001668 if (TCG_TARGET_HAS_bswap16_i64) {
1669 tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1670 } else {
1671 TCGv_i64 t0 = tcg_temp_new_i64();
aurel329a5c57f2009-03-13 09:35:12 +00001672
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001673 tcg_gen_ext8u_i64(t0, arg);
1674 tcg_gen_shli_i64(t0, t0, 8);
1675 tcg_gen_shri_i64(ret, arg, 8);
1676 tcg_gen_or_i64(ret, ret, t0);
1677 tcg_temp_free_i64(t0);
1678 }
aurel329a5c57f2009-03-13 09:35:12 +00001679}
1680
1681/* Note: we assume the four high bytes are set to zero */
1682static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1683{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001684 if (TCG_TARGET_HAS_bswap32_i64) {
1685 tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1686 } else {
1687 TCGv_i64 t0, t1;
1688 t0 = tcg_temp_new_i64();
1689 t1 = tcg_temp_new_i64();
aurel329a5c57f2009-03-13 09:35:12 +00001690
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001691 tcg_gen_shli_i64(t0, arg, 24);
1692 tcg_gen_ext32u_i64(t0, t0);
aurel329a5c57f2009-03-13 09:35:12 +00001693
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001694 tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1695 tcg_gen_shli_i64(t1, t1, 8);
1696 tcg_gen_or_i64(t0, t0, t1);
aurel329a5c57f2009-03-13 09:35:12 +00001697
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001698 tcg_gen_shri_i64(t1, arg, 8);
1699 tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1700 tcg_gen_or_i64(t0, t0, t1);
aurel329a5c57f2009-03-13 09:35:12 +00001701
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001702 tcg_gen_shri_i64(t1, arg, 24);
1703 tcg_gen_or_i64(ret, t0, t1);
1704 tcg_temp_free_i64(t0);
1705 tcg_temp_free_i64(t1);
1706 }
aurel329a5c57f2009-03-13 09:35:12 +00001707}
1708
aurel3266896cb2009-03-13 09:34:48 +00001709static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +00001710{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001711 if (TCG_TARGET_HAS_bswap64_i64) {
1712 tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1713 } else {
1714 TCGv_i64 t0 = tcg_temp_new_i64();
1715 TCGv_i64 t1 = tcg_temp_new_i64();
bellardc896fe22008-02-01 10:05:41 +00001716
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001717 tcg_gen_shli_i64(t0, arg, 56);
bellardc896fe22008-02-01 10:05:41 +00001718
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001719 tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1720 tcg_gen_shli_i64(t1, t1, 40);
1721 tcg_gen_or_i64(t0, t0, t1);
bellardc896fe22008-02-01 10:05:41 +00001722
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001723 tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1724 tcg_gen_shli_i64(t1, t1, 24);
1725 tcg_gen_or_i64(t0, t0, t1);
bellardc896fe22008-02-01 10:05:41 +00001726
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001727 tcg_gen_andi_i64(t1, arg, 0xff000000);
1728 tcg_gen_shli_i64(t1, t1, 8);
1729 tcg_gen_or_i64(t0, t0, t1);
bellardc896fe22008-02-01 10:05:41 +00001730
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001731 tcg_gen_shri_i64(t1, arg, 8);
1732 tcg_gen_andi_i64(t1, t1, 0xff000000);
1733 tcg_gen_or_i64(t0, t0, t1);
bellardc896fe22008-02-01 10:05:41 +00001734
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001735 tcg_gen_shri_i64(t1, arg, 24);
1736 tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1737 tcg_gen_or_i64(t0, t0, t1);
bellardc896fe22008-02-01 10:05:41 +00001738
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001739 tcg_gen_shri_i64(t1, arg, 40);
1740 tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1741 tcg_gen_or_i64(t0, t0, t1);
bellardc896fe22008-02-01 10:05:41 +00001742
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001743 tcg_gen_shri_i64(t1, arg, 56);
1744 tcg_gen_or_i64(ret, t0, t1);
1745 tcg_temp_free_i64(t0);
1746 tcg_temp_free_i64(t1);
1747 }
bellardc896fe22008-02-01 10:05:41 +00001748}
1749
1750#endif
1751
pbrooka7812ae2008-11-17 14:43:54 +00001752static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
pbrook390efc52008-05-11 14:35:37 +00001753{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001754 if (TCG_TARGET_HAS_neg_i32) {
1755 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1756 } else {
1757 TCGv_i32 t0 = tcg_const_i32(0);
1758 tcg_gen_sub_i32(ret, t0, arg);
1759 tcg_temp_free_i32(t0);
1760 }
pbrook390efc52008-05-11 14:35:37 +00001761}
1762
pbrooka7812ae2008-11-17 14:43:54 +00001763static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
pbrook390efc52008-05-11 14:35:37 +00001764{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001765 if (TCG_TARGET_HAS_neg_i64) {
1766 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1767 } else {
1768 TCGv_i64 t0 = tcg_const_i64(0);
1769 tcg_gen_sub_i64(ret, t0, arg);
1770 tcg_temp_free_i64(t0);
1771 }
pbrook390efc52008-05-11 14:35:37 +00001772}
1773
pbrooka7812ae2008-11-17 14:43:54 +00001774static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
bellard0b6ce4c2008-05-17 12:40:44 +00001775{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001776 if (TCG_TARGET_HAS_not_i32) {
1777 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1778 } else {
1779 tcg_gen_xori_i32(ret, arg, -1);
1780 }
bellard0b6ce4c2008-05-17 12:40:44 +00001781}
1782
pbrooka7812ae2008-11-17 14:43:54 +00001783static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
bellard0b6ce4c2008-05-17 12:40:44 +00001784{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001785#if TCG_TARGET_REG_BITS == 64
1786 if (TCG_TARGET_HAS_not_i64) {
1787 tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1788 } else {
1789 tcg_gen_xori_i64(ret, arg, -1);
1790 }
1791#else
Richard Hendersona10f9f42010-03-19 12:44:47 -07001792 tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1793 tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
aurel32d2604282009-03-09 22:35:13 +00001794#endif
bellard0b6ce4c2008-05-17 12:40:44 +00001795}
bellard5ff9d6a2008-02-04 00:37:54 +00001796
pbrooka7812ae2008-11-17 14:43:54 +00001797static inline void tcg_gen_discard_i32(TCGv_i32 arg)
bellard5ff9d6a2008-02-04 00:37:54 +00001798{
pbrooka7812ae2008-11-17 14:43:54 +00001799 tcg_gen_op1_i32(INDEX_op_discard, arg);
bellard5ff9d6a2008-02-04 00:37:54 +00001800}
1801
pbrooka7812ae2008-11-17 14:43:54 +00001802static inline void tcg_gen_discard_i64(TCGv_i64 arg)
bellard5ff9d6a2008-02-04 00:37:54 +00001803{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001804#if TCG_TARGET_REG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +00001805 tcg_gen_discard_i32(TCGV_LOW(arg));
bellard5ff9d6a2008-02-04 00:37:54 +00001806 tcg_gen_discard_i32(TCGV_HIGH(arg));
bellard5ff9d6a2008-02-04 00:37:54 +00001807#else
pbrooka7812ae2008-11-17 14:43:54 +00001808 tcg_gen_op1_i64(INDEX_op_discard, arg);
bellard5ff9d6a2008-02-04 00:37:54 +00001809#endif
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001810}
bellard5ff9d6a2008-02-04 00:37:54 +00001811
pbrooka7812ae2008-11-17 14:43:54 +00001812static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
aurel32f24cb332008-10-21 11:28:59 +00001813{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001814 if (TCG_TARGET_HAS_andc_i32) {
1815 tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
1816 } else {
1817 TCGv_i32 t0 = tcg_temp_new_i32();
1818 tcg_gen_not_i32(t0, arg2);
1819 tcg_gen_and_i32(ret, arg1, t0);
1820 tcg_temp_free_i32(t0);
1821 }
aurel32f24cb332008-10-21 11:28:59 +00001822}
1823
pbrooka7812ae2008-11-17 14:43:54 +00001824static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
aurel32f24cb332008-10-21 11:28:59 +00001825{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001826#if TCG_TARGET_REG_BITS == 64
1827 if (TCG_TARGET_HAS_andc_i64) {
1828 tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
1829 } else {
1830 TCGv_i64 t0 = tcg_temp_new_i64();
1831 tcg_gen_not_i64(t0, arg2);
1832 tcg_gen_and_i64(ret, arg1, t0);
1833 tcg_temp_free_i64(t0);
1834 }
1835#else
Richard Henderson241cbed2010-02-16 14:10:13 -08001836 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1837 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
Richard Henderson241cbed2010-02-16 14:10:13 -08001838#endif
aurel32f24cb332008-10-21 11:28:59 +00001839}
1840
pbrooka7812ae2008-11-17 14:43:54 +00001841static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
aurel32f24cb332008-10-21 11:28:59 +00001842{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001843 if (TCG_TARGET_HAS_eqv_i32) {
1844 tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
1845 } else {
1846 tcg_gen_xor_i32(ret, arg1, arg2);
1847 tcg_gen_not_i32(ret, ret);
1848 }
aurel32f24cb332008-10-21 11:28:59 +00001849}
1850
pbrooka7812ae2008-11-17 14:43:54 +00001851static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
aurel32f24cb332008-10-21 11:28:59 +00001852{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001853#if TCG_TARGET_REG_BITS == 64
1854 if (TCG_TARGET_HAS_eqv_i64) {
1855 tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
1856 } else {
1857 tcg_gen_xor_i64(ret, arg1, arg2);
1858 tcg_gen_not_i64(ret, ret);
1859 }
1860#else
Richard Henderson8d625cf2010-03-19 13:02:02 -07001861 tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1862 tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
Richard Henderson8d625cf2010-03-19 13:02:02 -07001863#endif
aurel32f24cb332008-10-21 11:28:59 +00001864}
1865
pbrooka7812ae2008-11-17 14:43:54 +00001866static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
aurel32f24cb332008-10-21 11:28:59 +00001867{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001868 if (TCG_TARGET_HAS_nand_i32) {
1869 tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
1870 } else {
1871 tcg_gen_and_i32(ret, arg1, arg2);
1872 tcg_gen_not_i32(ret, ret);
1873 }
aurel32f24cb332008-10-21 11:28:59 +00001874}
1875
pbrooka7812ae2008-11-17 14:43:54 +00001876static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
aurel32f24cb332008-10-21 11:28:59 +00001877{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001878#if TCG_TARGET_REG_BITS == 64
1879 if (TCG_TARGET_HAS_nand_i64) {
1880 tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
1881 } else {
1882 tcg_gen_and_i64(ret, arg1, arg2);
1883 tcg_gen_not_i64(ret, ret);
1884 }
1885#else
Richard Henderson9940a962010-03-19 13:03:58 -07001886 tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1887 tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
Richard Henderson9940a962010-03-19 13:03:58 -07001888#endif
aurel32f24cb332008-10-21 11:28:59 +00001889}
1890
pbrooka7812ae2008-11-17 14:43:54 +00001891static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
aurel32f24cb332008-10-21 11:28:59 +00001892{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001893 if (TCG_TARGET_HAS_nor_i32) {
1894 tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
1895 } else {
1896 tcg_gen_or_i32(ret, arg1, arg2);
1897 tcg_gen_not_i32(ret, ret);
1898 }
aurel32f24cb332008-10-21 11:28:59 +00001899}
1900
pbrooka7812ae2008-11-17 14:43:54 +00001901static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
aurel32f24cb332008-10-21 11:28:59 +00001902{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001903#if TCG_TARGET_REG_BITS == 64
1904 if (TCG_TARGET_HAS_nor_i64) {
1905 tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
1906 } else {
1907 tcg_gen_or_i64(ret, arg1, arg2);
1908 tcg_gen_not_i64(ret, ret);
1909 }
1910#else
Richard Henderson32d98fb2010-03-19 13:08:56 -07001911 tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1912 tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
Richard Henderson32d98fb2010-03-19 13:08:56 -07001913#endif
aurel32f24cb332008-10-21 11:28:59 +00001914}
1915
pbrooka7812ae2008-11-17 14:43:54 +00001916static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
aurel32f24cb332008-10-21 11:28:59 +00001917{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001918 if (TCG_TARGET_HAS_orc_i32) {
1919 tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
1920 } else {
1921 TCGv_i32 t0 = tcg_temp_new_i32();
1922 tcg_gen_not_i32(t0, arg2);
1923 tcg_gen_or_i32(ret, arg1, t0);
1924 tcg_temp_free_i32(t0);
1925 }
aurel32f24cb332008-10-21 11:28:59 +00001926}
1927
pbrooka7812ae2008-11-17 14:43:54 +00001928static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
aurel32f24cb332008-10-21 11:28:59 +00001929{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001930#if TCG_TARGET_REG_BITS == 64
1931 if (TCG_TARGET_HAS_orc_i64) {
1932 tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
1933 } else {
1934 TCGv_i64 t0 = tcg_temp_new_i64();
1935 tcg_gen_not_i64(t0, arg2);
1936 tcg_gen_or_i64(ret, arg1, t0);
1937 tcg_temp_free_i64(t0);
1938 }
1939#else
Richard Henderson791d1262010-02-16 14:15:28 -08001940 tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1941 tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
Richard Henderson791d1262010-02-16 14:15:28 -08001942#endif
aurel32f24cb332008-10-21 11:28:59 +00001943}
1944
pbrooka7812ae2008-11-17 14:43:54 +00001945static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
aurel3215824572008-11-03 07:08:36 +00001946{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001947 if (TCG_TARGET_HAS_rot_i32) {
1948 tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1949 } else {
1950 TCGv_i32 t0, t1;
aurel3215824572008-11-03 07:08:36 +00001951
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001952 t0 = tcg_temp_new_i32();
1953 t1 = tcg_temp_new_i32();
1954 tcg_gen_shl_i32(t0, arg1, arg2);
1955 tcg_gen_subfi_i32(t1, 32, arg2);
1956 tcg_gen_shr_i32(t1, arg1, t1);
1957 tcg_gen_or_i32(ret, t0, t1);
1958 tcg_temp_free_i32(t0);
1959 tcg_temp_free_i32(t1);
1960 }
aurel3215824572008-11-03 07:08:36 +00001961}
1962
pbrooka7812ae2008-11-17 14:43:54 +00001963static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
aurel3215824572008-11-03 07:08:36 +00001964{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001965 if (TCG_TARGET_HAS_rot_i64) {
1966 tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
1967 } else {
1968 TCGv_i64 t0, t1;
1969 t0 = tcg_temp_new_i64();
1970 t1 = tcg_temp_new_i64();
1971 tcg_gen_shl_i64(t0, arg1, arg2);
1972 tcg_gen_subfi_i64(t1, 64, arg2);
1973 tcg_gen_shr_i64(t1, arg1, t1);
1974 tcg_gen_or_i64(ret, t0, t1);
1975 tcg_temp_free_i64(t0);
1976 tcg_temp_free_i64(t1);
1977 }
aurel3215824572008-11-03 07:08:36 +00001978}
1979
pbrooka7812ae2008-11-17 14:43:54 +00001980static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
aurel3215824572008-11-03 07:08:36 +00001981{
1982 /* some cases can be optimized here */
1983 if (arg2 == 0) {
1984 tcg_gen_mov_i32(ret, arg1);
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001985 } else if (TCG_TARGET_HAS_rot_i32) {
aurel32d42f1832009-03-09 18:50:53 +00001986 TCGv_i32 t0 = tcg_const_i32(arg2);
1987 tcg_gen_rotl_i32(ret, arg1, t0);
1988 tcg_temp_free_i32(t0);
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001989 } else {
pbrooka7812ae2008-11-17 14:43:54 +00001990 TCGv_i32 t0, t1;
1991 t0 = tcg_temp_new_i32();
1992 t1 = tcg_temp_new_i32();
aurel3215824572008-11-03 07:08:36 +00001993 tcg_gen_shli_i32(t0, arg1, arg2);
1994 tcg_gen_shri_i32(t1, arg1, 32 - arg2);
1995 tcg_gen_or_i32(ret, t0, t1);
pbrooka7812ae2008-11-17 14:43:54 +00001996 tcg_temp_free_i32(t0);
1997 tcg_temp_free_i32(t1);
aurel3215824572008-11-03 07:08:36 +00001998 }
1999}
2000
pbrooka7812ae2008-11-17 14:43:54 +00002001static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
aurel3215824572008-11-03 07:08:36 +00002002{
2003 /* some cases can be optimized here */
2004 if (arg2 == 0) {
2005 tcg_gen_mov_i64(ret, arg1);
Richard Henderson25c4d9c2011-08-17 14:11:46 -07002006 } else if (TCG_TARGET_HAS_rot_i64) {
aurel32d42f1832009-03-09 18:50:53 +00002007 TCGv_i64 t0 = tcg_const_i64(arg2);
2008 tcg_gen_rotl_i64(ret, arg1, t0);
2009 tcg_temp_free_i64(t0);
Richard Henderson25c4d9c2011-08-17 14:11:46 -07002010 } else {
pbrooka7812ae2008-11-17 14:43:54 +00002011 TCGv_i64 t0, t1;
2012 t0 = tcg_temp_new_i64();
2013 t1 = tcg_temp_new_i64();
aurel3215824572008-11-03 07:08:36 +00002014 tcg_gen_shli_i64(t0, arg1, arg2);
2015 tcg_gen_shri_i64(t1, arg1, 64 - arg2);
2016 tcg_gen_or_i64(ret, t0, t1);
pbrooka7812ae2008-11-17 14:43:54 +00002017 tcg_temp_free_i64(t0);
2018 tcg_temp_free_i64(t1);
aurel3215824572008-11-03 07:08:36 +00002019 }
2020}
2021
pbrooka7812ae2008-11-17 14:43:54 +00002022static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
aurel3215824572008-11-03 07:08:36 +00002023{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07002024 if (TCG_TARGET_HAS_rot_i32) {
2025 tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
2026 } else {
2027 TCGv_i32 t0, t1;
aurel3215824572008-11-03 07:08:36 +00002028
Richard Henderson25c4d9c2011-08-17 14:11:46 -07002029 t0 = tcg_temp_new_i32();
2030 t1 = tcg_temp_new_i32();
2031 tcg_gen_shr_i32(t0, arg1, arg2);
2032 tcg_gen_subfi_i32(t1, 32, arg2);
2033 tcg_gen_shl_i32(t1, arg1, t1);
2034 tcg_gen_or_i32(ret, t0, t1);
2035 tcg_temp_free_i32(t0);
2036 tcg_temp_free_i32(t1);
2037 }
aurel3215824572008-11-03 07:08:36 +00002038}
2039
pbrooka7812ae2008-11-17 14:43:54 +00002040static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
aurel3215824572008-11-03 07:08:36 +00002041{
Richard Henderson25c4d9c2011-08-17 14:11:46 -07002042 if (TCG_TARGET_HAS_rot_i64) {
2043 tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
2044 } else {
2045 TCGv_i64 t0, t1;
2046 t0 = tcg_temp_new_i64();
2047 t1 = tcg_temp_new_i64();
2048 tcg_gen_shr_i64(t0, arg1, arg2);
2049 tcg_gen_subfi_i64(t1, 64, arg2);
2050 tcg_gen_shl_i64(t1, arg1, t1);
2051 tcg_gen_or_i64(ret, t0, t1);
2052 tcg_temp_free_i64(t0);
2053 tcg_temp_free_i64(t1);
2054 }
aurel3215824572008-11-03 07:08:36 +00002055}
2056
pbrooka7812ae2008-11-17 14:43:54 +00002057static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
aurel3215824572008-11-03 07:08:36 +00002058{
2059 /* some cases can be optimized here */
2060 if (arg2 == 0) {
2061 tcg_gen_mov_i32(ret, arg1);
2062 } else {
2063 tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
2064 }
2065}
2066
pbrooka7812ae2008-11-17 14:43:54 +00002067static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
aurel3215824572008-11-03 07:08:36 +00002068{
2069 /* some cases can be optimized here */
2070 if (arg2 == 0) {
pbrookde3526b2008-11-03 13:30:50 +00002071 tcg_gen_mov_i64(ret, arg1);
aurel3215824572008-11-03 07:08:36 +00002072 } else {
2073 tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
2074 }
2075}
2076
Richard Hendersonb7767f02011-01-10 19:23:42 -08002077static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
Richard Henderson0756e712011-11-01 15:06:43 -07002078 TCGv_i32 arg2, unsigned int ofs,
2079 unsigned int len)
Richard Hendersonb7767f02011-01-10 19:23:42 -08002080{
Richard Hendersondf072772011-10-27 14:15:00 -07002081 uint32_t mask;
2082 TCGv_i32 t1;
2083
Richard Henderson717e7032012-09-21 17:18:15 -07002084 tcg_debug_assert(ofs < 32);
2085 tcg_debug_assert(len <= 32);
2086 tcg_debug_assert(ofs + len <= 32);
2087
Richard Hendersondf072772011-10-27 14:15:00 -07002088 if (ofs == 0 && len == 32) {
2089 tcg_gen_mov_i32(ret, arg2);
2090 return;
2091 }
Jan Kiszkaa4773322011-09-29 18:52:11 +02002092 if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) {
Richard Henderson25c4d9c2011-08-17 14:11:46 -07002093 tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
Richard Hendersondf072772011-10-27 14:15:00 -07002094 return;
2095 }
Richard Hendersonb7767f02011-01-10 19:23:42 -08002096
Richard Hendersondf072772011-10-27 14:15:00 -07002097 mask = (1u << len) - 1;
2098 t1 = tcg_temp_new_i32();
2099
2100 if (ofs + len < 32) {
Richard Henderson25c4d9c2011-08-17 14:11:46 -07002101 tcg_gen_andi_i32(t1, arg2, mask);
2102 tcg_gen_shli_i32(t1, t1, ofs);
Richard Hendersondf072772011-10-27 14:15:00 -07002103 } else {
2104 tcg_gen_shli_i32(t1, arg2, ofs);
Richard Henderson25c4d9c2011-08-17 14:11:46 -07002105 }
Richard Hendersondf072772011-10-27 14:15:00 -07002106 tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
2107 tcg_gen_or_i32(ret, ret, t1);
2108
2109 tcg_temp_free_i32(t1);
Richard Hendersonb7767f02011-01-10 19:23:42 -08002110}
2111
2112static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
Richard Henderson0756e712011-11-01 15:06:43 -07002113 TCGv_i64 arg2, unsigned int ofs,
2114 unsigned int len)
Richard Hendersonb7767f02011-01-10 19:23:42 -08002115{
Richard Hendersondf072772011-10-27 14:15:00 -07002116 uint64_t mask;
2117 TCGv_i64 t1;
2118
Richard Henderson717e7032012-09-21 17:18:15 -07002119 tcg_debug_assert(ofs < 64);
2120 tcg_debug_assert(len <= 64);
2121 tcg_debug_assert(ofs + len <= 64);
2122
Richard Hendersondf072772011-10-27 14:15:00 -07002123 if (ofs == 0 && len == 64) {
2124 tcg_gen_mov_i64(ret, arg2);
2125 return;
2126 }
Jan Kiszkaa4773322011-09-29 18:52:11 +02002127 if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) {
Richard Henderson25c4d9c2011-08-17 14:11:46 -07002128 tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
Richard Hendersondf072772011-10-27 14:15:00 -07002129 return;
2130 }
Richard Hendersonb7767f02011-01-10 19:23:42 -08002131
Richard Hendersondf072772011-10-27 14:15:00 -07002132#if TCG_TARGET_REG_BITS == 32
2133 if (ofs >= 32) {
Richard Henderson2f98c9d2011-11-01 15:06:42 -07002134 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
Richard Hendersondf072772011-10-27 14:15:00 -07002135 tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1),
2136 TCGV_LOW(arg2), ofs - 32, len);
2137 return;
2138 }
2139 if (ofs + len <= 32) {
2140 tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1),
2141 TCGV_LOW(arg2), ofs, len);
Richard Henderson2f98c9d2011-11-01 15:06:42 -07002142 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
Richard Hendersondf072772011-10-27 14:15:00 -07002143 return;
2144 }
2145#endif
2146
2147 mask = (1ull << len) - 1;
2148 t1 = tcg_temp_new_i64();
2149
2150 if (ofs + len < 64) {
Richard Henderson25c4d9c2011-08-17 14:11:46 -07002151 tcg_gen_andi_i64(t1, arg2, mask);
2152 tcg_gen_shli_i64(t1, t1, ofs);
Richard Hendersondf072772011-10-27 14:15:00 -07002153 } else {
2154 tcg_gen_shli_i64(t1, arg2, ofs);
Richard Henderson25c4d9c2011-08-17 14:11:46 -07002155 }
Richard Hendersondf072772011-10-27 14:15:00 -07002156 tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
2157 tcg_gen_or_i64(ret, ret, t1);
2158
2159 tcg_temp_free_i64(t1);
Richard Hendersonb7767f02011-01-10 19:23:42 -08002160}
2161
Richard Henderson77276f62012-09-21 17:18:13 -07002162static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low,
2163 TCGv_i32 high)
2164{
2165#if TCG_TARGET_REG_BITS == 32
2166 tcg_gen_mov_i32(TCGV_LOW(dest), low);
2167 tcg_gen_mov_i32(TCGV_HIGH(dest), high);
2168#else
2169 TCGv_i64 tmp = tcg_temp_new_i64();
2170 /* These extensions are only needed for type correctness.
2171 We may be able to do better given target specific information. */
2172 tcg_gen_extu_i32_i64(tmp, high);
2173 tcg_gen_extu_i32_i64(dest, low);
2174 /* If deposit is available, use it. Otherwise use the extra
2175 knowledge that we have of the zero-extensions above. */
2176 if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) {
2177 tcg_gen_deposit_i64(dest, dest, tmp, 32, 32);
2178 } else {
2179 tcg_gen_shli_i64(tmp, tmp, 32);
2180 tcg_gen_or_i64(dest, dest, tmp);
2181 }
2182 tcg_temp_free_i64(tmp);
2183#endif
2184}
2185
2186static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low,
2187 TCGv_i64 high)
2188{
2189 tcg_gen_deposit_i64(dest, low, high, 32, 32);
2190}
2191
Richard Hendersonffc5ea02012-09-21 10:13:34 -07002192static inline void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret,
2193 TCGv_i32 c1, TCGv_i32 c2,
2194 TCGv_i32 v1, TCGv_i32 v2)
2195{
2196 if (TCG_TARGET_HAS_movcond_i32) {
2197 tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond);
2198 } else {
2199 TCGv_i32 t0 = tcg_temp_new_i32();
2200 TCGv_i32 t1 = tcg_temp_new_i32();
2201 tcg_gen_setcond_i32(cond, t0, c1, c2);
2202 tcg_gen_neg_i32(t0, t0);
2203 tcg_gen_and_i32(t1, v1, t0);
2204 tcg_gen_andc_i32(ret, v2, t0);
2205 tcg_gen_or_i32(ret, ret, t1);
2206 tcg_temp_free_i32(t0);
2207 tcg_temp_free_i32(t1);
2208 }
2209}
2210
2211static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret,
2212 TCGv_i64 c1, TCGv_i64 c2,
2213 TCGv_i64 v1, TCGv_i64 v2)
2214{
Richard Hendersona4631332012-09-24 13:44:59 -07002215#if TCG_TARGET_REG_BITS == 32
2216 TCGv_i32 t0 = tcg_temp_new_i32();
2217 TCGv_i32 t1 = tcg_temp_new_i32();
2218 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0,
2219 TCGV_LOW(c1), TCGV_HIGH(c1),
2220 TCGV_LOW(c2), TCGV_HIGH(c2), cond);
Richard Hendersona4631332012-09-24 13:44:59 -07002221
Richard Hendersona80a6b62012-09-24 13:45:00 -07002222 if (TCG_TARGET_HAS_movcond_i32) {
2223 tcg_gen_movi_i32(t1, 0);
2224 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1,
2225 TCGV_LOW(v1), TCGV_LOW(v2));
2226 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1,
2227 TCGV_HIGH(v1), TCGV_HIGH(v2));
2228 } else {
2229 tcg_gen_neg_i32(t0, t0);
Richard Hendersona4631332012-09-24 13:44:59 -07002230
Richard Hendersona80a6b62012-09-24 13:45:00 -07002231 tcg_gen_and_i32(t1, TCGV_LOW(v1), t0);
2232 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0);
2233 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1);
Richard Hendersona4631332012-09-24 13:44:59 -07002234
Richard Hendersona80a6b62012-09-24 13:45:00 -07002235 tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0);
2236 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0);
2237 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1);
2238 }
Richard Hendersona4631332012-09-24 13:44:59 -07002239 tcg_temp_free_i32(t0);
2240 tcg_temp_free_i32(t1);
2241#else
Richard Hendersonffc5ea02012-09-21 10:13:34 -07002242 if (TCG_TARGET_HAS_movcond_i64) {
2243 tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond);
2244 } else {
2245 TCGv_i64 t0 = tcg_temp_new_i64();
2246 TCGv_i64 t1 = tcg_temp_new_i64();
2247 tcg_gen_setcond_i64(cond, t0, c1, c2);
2248 tcg_gen_neg_i64(t0, t0);
2249 tcg_gen_and_i64(t1, v1, t0);
2250 tcg_gen_andc_i64(ret, v2, t0);
2251 tcg_gen_or_i64(ret, ret, t1);
2252 tcg_temp_free_i64(t0);
2253 tcg_temp_free_i64(t1);
2254 }
Richard Hendersona4631332012-09-24 13:44:59 -07002255#endif
Richard Hendersonffc5ea02012-09-21 10:13:34 -07002256}
2257
bellardc896fe22008-02-01 10:05:41 +00002258/***************************************/
bellardc896fe22008-02-01 10:05:41 +00002259/* QEMU specific operations. Their type depend on the QEMU CPU
2260 type. */
2261#ifndef TARGET_LONG_BITS
2262#error must include QEMU headers
2263#endif
2264
pbrooka7812ae2008-11-17 14:43:54 +00002265#if TARGET_LONG_BITS == 32
2266#define TCGv TCGv_i32
2267#define tcg_temp_new() tcg_temp_new_i32()
2268#define tcg_global_reg_new tcg_global_reg_new_i32
2269#define tcg_global_mem_new tcg_global_mem_new_i32
aurel32df9247b2009-01-01 14:09:05 +00002270#define tcg_temp_local_new() tcg_temp_local_new_i32()
pbrooka7812ae2008-11-17 14:43:54 +00002271#define tcg_temp_free tcg_temp_free_i32
2272#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
2273#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
2274#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
aurel32fe75bcf2009-03-10 08:57:16 +00002275#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
pbrooka7812ae2008-11-17 14:43:54 +00002276#else
2277#define TCGv TCGv_i64
2278#define tcg_temp_new() tcg_temp_new_i64()
2279#define tcg_global_reg_new tcg_global_reg_new_i64
2280#define tcg_global_mem_new tcg_global_mem_new_i64
aurel32df9247b2009-01-01 14:09:05 +00002281#define tcg_temp_local_new() tcg_temp_local_new_i64()
pbrooka7812ae2008-11-17 14:43:54 +00002282#define tcg_temp_free tcg_temp_free_i64
2283#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
2284#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
2285#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
aurel32fe75bcf2009-03-10 08:57:16 +00002286#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
pbrooka7812ae2008-11-17 14:43:54 +00002287#endif
2288
bellard7e4597d2008-05-22 16:56:05 +00002289/* debug info: write the PC of the corresponding QEMU CPU instruction */
2290static inline void tcg_gen_debug_insn_start(uint64_t pc)
2291{
2292 /* XXX: must really use a 32 bit size for TCGArg in all cases */
2293#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
pbrookbcb01262008-05-24 02:24:25 +00002294 tcg_gen_op2ii(INDEX_op_debug_insn_start,
2295 (uint32_t)(pc), (uint32_t)(pc >> 32));
bellard7e4597d2008-05-22 16:56:05 +00002296#else
2297 tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
2298#endif
2299}
2300
bellardc896fe22008-02-01 10:05:41 +00002301static inline void tcg_gen_exit_tb(tcg_target_long val)
2302{
pbrookac56dd42008-02-03 19:56:33 +00002303 tcg_gen_op1i(INDEX_op_exit_tb, val);
bellardc896fe22008-02-01 10:05:41 +00002304}
2305
Richard Henderson0a209d42012-09-21 17:18:16 -07002306static inline void tcg_gen_goto_tb(unsigned idx)
bellardc896fe22008-02-01 10:05:41 +00002307{
Richard Henderson0a209d42012-09-21 17:18:16 -07002308 /* We only support two chained exits. */
2309 tcg_debug_assert(idx <= 1);
2310#ifdef CONFIG_DEBUG_TCG
2311 /* Verify that we havn't seen this numbered exit before. */
2312 tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0);
2313 tcg_ctx.goto_tb_issue_mask |= 1 << idx;
2314#endif
pbrookac56dd42008-02-03 19:56:33 +00002315 tcg_gen_op1i(INDEX_op_goto_tb, idx);
bellardc896fe22008-02-01 10:05:41 +00002316}
2317
2318#if TCG_TARGET_REG_BITS == 32
pbrookac56dd42008-02-03 19:56:33 +00002319static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002320{
2321#if TARGET_LONG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +00002322 tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002323#else
pbrooka7812ae2008-11-17 14:43:54 +00002324 tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
2325 TCGV_HIGH(addr), mem_index);
pbrookac56dd42008-02-03 19:56:33 +00002326 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
bellardc896fe22008-02-01 10:05:41 +00002327#endif
2328}
2329
pbrookac56dd42008-02-03 19:56:33 +00002330static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002331{
2332#if TARGET_LONG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +00002333 tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002334#else
pbrooka7812ae2008-11-17 14:43:54 +00002335 tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
2336 TCGV_HIGH(addr), mem_index);
2337 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
bellardc896fe22008-02-01 10:05:41 +00002338#endif
2339}
2340
pbrookac56dd42008-02-03 19:56:33 +00002341static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002342{
2343#if TARGET_LONG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +00002344 tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002345#else
pbrooka7812ae2008-11-17 14:43:54 +00002346 tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
2347 TCGV_HIGH(addr), mem_index);
pbrookac56dd42008-02-03 19:56:33 +00002348 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
bellardc896fe22008-02-01 10:05:41 +00002349#endif
2350}
2351
pbrookac56dd42008-02-03 19:56:33 +00002352static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002353{
2354#if TARGET_LONG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +00002355 tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002356#else
pbrooka7812ae2008-11-17 14:43:54 +00002357 tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
2358 TCGV_HIGH(addr), mem_index);
2359 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
bellardc896fe22008-02-01 10:05:41 +00002360#endif
2361}
2362
pbrookac56dd42008-02-03 19:56:33 +00002363static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002364{
2365#if TARGET_LONG_BITS == 32
Richard Henderson86feb1c2010-03-19 12:00:26 -07002366 tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002367#else
Richard Henderson86feb1c2010-03-19 12:00:26 -07002368 tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
pbrooka7812ae2008-11-17 14:43:54 +00002369 TCGV_HIGH(addr), mem_index);
pbrookac56dd42008-02-03 19:56:33 +00002370 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
bellardc896fe22008-02-01 10:05:41 +00002371#endif
2372}
2373
pbrookac56dd42008-02-03 19:56:33 +00002374static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002375{
2376#if TARGET_LONG_BITS == 32
Richard Henderson86feb1c2010-03-19 12:00:26 -07002377 tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002378#else
Richard Henderson86feb1c2010-03-19 12:00:26 -07002379 tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
pbrooka7812ae2008-11-17 14:43:54 +00002380 TCGV_HIGH(addr), mem_index);
2381 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
bellardc896fe22008-02-01 10:05:41 +00002382#endif
2383}
2384
pbrooka7812ae2008-11-17 14:43:54 +00002385static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002386{
2387#if TARGET_LONG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +00002388 tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002389#else
pbrooka7812ae2008-11-17 14:43:54 +00002390 tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
2391 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
bellardc896fe22008-02-01 10:05:41 +00002392#endif
2393}
2394
pbrookac56dd42008-02-03 19:56:33 +00002395static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002396{
2397#if TARGET_LONG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +00002398 tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002399#else
pbrooka7812ae2008-11-17 14:43:54 +00002400 tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
2401 TCGV_HIGH(addr), mem_index);
bellardc896fe22008-02-01 10:05:41 +00002402#endif
2403}
2404
pbrookac56dd42008-02-03 19:56:33 +00002405static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002406{
2407#if TARGET_LONG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +00002408 tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002409#else
pbrooka7812ae2008-11-17 14:43:54 +00002410 tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
2411 TCGV_HIGH(addr), mem_index);
bellardc896fe22008-02-01 10:05:41 +00002412#endif
2413}
2414
pbrookac56dd42008-02-03 19:56:33 +00002415static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002416{
2417#if TARGET_LONG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +00002418 tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002419#else
pbrooka7812ae2008-11-17 14:43:54 +00002420 tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
2421 TCGV_HIGH(addr), mem_index);
bellardc896fe22008-02-01 10:05:41 +00002422#endif
2423}
2424
pbrooka7812ae2008-11-17 14:43:54 +00002425static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002426{
2427#if TARGET_LONG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +00002428 tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2429 mem_index);
bellardc896fe22008-02-01 10:05:41 +00002430#else
pbrooka7812ae2008-11-17 14:43:54 +00002431 tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2432 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
bellardc896fe22008-02-01 10:05:41 +00002433#endif
2434}
2435
Peter Maydellebecf362011-05-27 13:12:13 +01002436#define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
2437#define tcg_gen_discard_ptr(A) tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
blueswir1f8422f52008-02-24 07:45:43 +00002438
bellardc896fe22008-02-01 10:05:41 +00002439#else /* TCG_TARGET_REG_BITS == 32 */
2440
pbrookac56dd42008-02-03 19:56:33 +00002441static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002442{
pbrooka7812ae2008-11-17 14:43:54 +00002443 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002444}
2445
pbrookac56dd42008-02-03 19:56:33 +00002446static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002447{
pbrooka7812ae2008-11-17 14:43:54 +00002448 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002449}
2450
pbrookac56dd42008-02-03 19:56:33 +00002451static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002452{
pbrooka7812ae2008-11-17 14:43:54 +00002453 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002454}
2455
pbrookac56dd42008-02-03 19:56:33 +00002456static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002457{
pbrooka7812ae2008-11-17 14:43:54 +00002458 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002459}
2460
pbrookac56dd42008-02-03 19:56:33 +00002461static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002462{
Richard Henderson3e1dbad2010-05-03 16:30:48 -07002463#if TARGET_LONG_BITS == 32
2464 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2465#else
pbrooka7812ae2008-11-17 14:43:54 +00002466 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
Richard Henderson3e1dbad2010-05-03 16:30:48 -07002467#endif
bellardc896fe22008-02-01 10:05:41 +00002468}
2469
pbrookac56dd42008-02-03 19:56:33 +00002470static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002471{
Richard Henderson3e1dbad2010-05-03 16:30:48 -07002472#if TARGET_LONG_BITS == 32
2473 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2474#else
pbrooka7812ae2008-11-17 14:43:54 +00002475 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
Richard Henderson3e1dbad2010-05-03 16:30:48 -07002476#endif
bellardc896fe22008-02-01 10:05:41 +00002477}
2478
pbrooka7812ae2008-11-17 14:43:54 +00002479static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002480{
pbrooka7812ae2008-11-17 14:43:54 +00002481 tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002482}
2483
pbrookac56dd42008-02-03 19:56:33 +00002484static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002485{
pbrooka7812ae2008-11-17 14:43:54 +00002486 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002487}
2488
pbrookac56dd42008-02-03 19:56:33 +00002489static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002490{
pbrooka7812ae2008-11-17 14:43:54 +00002491 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002492}
2493
pbrookac56dd42008-02-03 19:56:33 +00002494static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002495{
pbrooka7812ae2008-11-17 14:43:54 +00002496 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002497}
2498
pbrooka7812ae2008-11-17 14:43:54 +00002499static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +00002500{
pbrooka7812ae2008-11-17 14:43:54 +00002501 tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
bellardc896fe22008-02-01 10:05:41 +00002502}
2503
Peter Maydellebecf362011-05-27 13:12:13 +01002504#define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
2505#define tcg_gen_discard_ptr(A) tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
blueswir1f8422f52008-02-24 07:45:43 +00002506
bellardc896fe22008-02-01 10:05:41 +00002507#endif /* TCG_TARGET_REG_BITS != 32 */
blueswir1f8422f52008-02-24 07:45:43 +00002508
2509#if TARGET_LONG_BITS == 64
blueswir1f8422f52008-02-24 07:45:43 +00002510#define tcg_gen_movi_tl tcg_gen_movi_i64
2511#define tcg_gen_mov_tl tcg_gen_mov_i64
2512#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2513#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2514#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2515#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2516#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2517#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2518#define tcg_gen_ld_tl tcg_gen_ld_i64
2519#define tcg_gen_st8_tl tcg_gen_st8_i64
2520#define tcg_gen_st16_tl tcg_gen_st16_i64
2521#define tcg_gen_st32_tl tcg_gen_st32_i64
2522#define tcg_gen_st_tl tcg_gen_st_i64
2523#define tcg_gen_add_tl tcg_gen_add_i64
2524#define tcg_gen_addi_tl tcg_gen_addi_i64
2525#define tcg_gen_sub_tl tcg_gen_sub_i64
pbrook390efc52008-05-11 14:35:37 +00002526#define tcg_gen_neg_tl tcg_gen_neg_i64
pbrook10460c82008-11-02 13:26:16 +00002527#define tcg_gen_subfi_tl tcg_gen_subfi_i64
blueswir1f8422f52008-02-24 07:45:43 +00002528#define tcg_gen_subi_tl tcg_gen_subi_i64
2529#define tcg_gen_and_tl tcg_gen_and_i64
2530#define tcg_gen_andi_tl tcg_gen_andi_i64
2531#define tcg_gen_or_tl tcg_gen_or_i64
2532#define tcg_gen_ori_tl tcg_gen_ori_i64
2533#define tcg_gen_xor_tl tcg_gen_xor_i64
2534#define tcg_gen_xori_tl tcg_gen_xori_i64
bellard0b6ce4c2008-05-17 12:40:44 +00002535#define tcg_gen_not_tl tcg_gen_not_i64
blueswir1f8422f52008-02-24 07:45:43 +00002536#define tcg_gen_shl_tl tcg_gen_shl_i64
2537#define tcg_gen_shli_tl tcg_gen_shli_i64
2538#define tcg_gen_shr_tl tcg_gen_shr_i64
2539#define tcg_gen_shri_tl tcg_gen_shri_i64
2540#define tcg_gen_sar_tl tcg_gen_sar_i64
2541#define tcg_gen_sari_tl tcg_gen_sari_i64
blueswir10cf767d2008-03-02 18:20:59 +00002542#define tcg_gen_brcond_tl tcg_gen_brcond_i64
pbrookcb636692008-05-24 02:22:00 +00002543#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
Richard Hendersonbe210ac2010-01-07 10:13:31 -08002544#define tcg_gen_setcond_tl tcg_gen_setcond_i64
Aurelien Jarnoadd1e7e2010-02-08 12:06:05 +01002545#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
thsf730fd22008-05-04 08:14:08 +00002546#define tcg_gen_mul_tl tcg_gen_mul_i64
2547#define tcg_gen_muli_tl tcg_gen_muli_i64
aurel32ab364212009-03-29 01:19:22 +00002548#define tcg_gen_div_tl tcg_gen_div_i64
2549#define tcg_gen_rem_tl tcg_gen_rem_i64
aurel32864951a2009-03-29 14:08:54 +00002550#define tcg_gen_divu_tl tcg_gen_divu_i64
2551#define tcg_gen_remu_tl tcg_gen_remu_i64
blueswir1a768e4b2008-03-16 19:16:37 +00002552#define tcg_gen_discard_tl tcg_gen_discard_i64
blueswir1e4290732008-03-22 08:39:04 +00002553#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2554#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2555#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2556#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2557#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2558#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
bellard0b6ce4c2008-05-17 12:40:44 +00002559#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2560#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2561#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2562#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2563#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2564#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
aurel32911d79b2009-03-13 09:35:19 +00002565#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2566#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2567#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
blueswir1945ca822008-09-21 18:32:28 +00002568#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
aurel32f24cb332008-10-21 11:28:59 +00002569#define tcg_gen_andc_tl tcg_gen_andc_i64
2570#define tcg_gen_eqv_tl tcg_gen_eqv_i64
2571#define tcg_gen_nand_tl tcg_gen_nand_i64
2572#define tcg_gen_nor_tl tcg_gen_nor_i64
2573#define tcg_gen_orc_tl tcg_gen_orc_i64
aurel3215824572008-11-03 07:08:36 +00002574#define tcg_gen_rotl_tl tcg_gen_rotl_i64
2575#define tcg_gen_rotli_tl tcg_gen_rotli_i64
2576#define tcg_gen_rotr_tl tcg_gen_rotr_i64
2577#define tcg_gen_rotri_tl tcg_gen_rotri_i64
Richard Hendersonb7767f02011-01-10 19:23:42 -08002578#define tcg_gen_deposit_tl tcg_gen_deposit_i64
blueswir1a98824a2008-03-13 20:46:42 +00002579#define tcg_const_tl tcg_const_i64
aurel32bdffd4a2008-10-21 11:30:45 +00002580#define tcg_const_local_tl tcg_const_local_i64
Richard Hendersonffc5ea02012-09-21 10:13:34 -07002581#define tcg_gen_movcond_tl tcg_gen_movcond_i64
blueswir1f8422f52008-02-24 07:45:43 +00002582#else
blueswir1f8422f52008-02-24 07:45:43 +00002583#define tcg_gen_movi_tl tcg_gen_movi_i32
2584#define tcg_gen_mov_tl tcg_gen_mov_i32
2585#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2586#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2587#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2588#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2589#define tcg_gen_ld32u_tl tcg_gen_ld_i32
2590#define tcg_gen_ld32s_tl tcg_gen_ld_i32
2591#define tcg_gen_ld_tl tcg_gen_ld_i32
2592#define tcg_gen_st8_tl tcg_gen_st8_i32
2593#define tcg_gen_st16_tl tcg_gen_st16_i32
2594#define tcg_gen_st32_tl tcg_gen_st_i32
2595#define tcg_gen_st_tl tcg_gen_st_i32
2596#define tcg_gen_add_tl tcg_gen_add_i32
2597#define tcg_gen_addi_tl tcg_gen_addi_i32
2598#define tcg_gen_sub_tl tcg_gen_sub_i32
pbrook390efc52008-05-11 14:35:37 +00002599#define tcg_gen_neg_tl tcg_gen_neg_i32
aurel3200457342008-11-02 08:23:04 +00002600#define tcg_gen_subfi_tl tcg_gen_subfi_i32
blueswir1f8422f52008-02-24 07:45:43 +00002601#define tcg_gen_subi_tl tcg_gen_subi_i32
2602#define tcg_gen_and_tl tcg_gen_and_i32
2603#define tcg_gen_andi_tl tcg_gen_andi_i32
2604#define tcg_gen_or_tl tcg_gen_or_i32
2605#define tcg_gen_ori_tl tcg_gen_ori_i32
2606#define tcg_gen_xor_tl tcg_gen_xor_i32
2607#define tcg_gen_xori_tl tcg_gen_xori_i32
bellard0b6ce4c2008-05-17 12:40:44 +00002608#define tcg_gen_not_tl tcg_gen_not_i32
blueswir1f8422f52008-02-24 07:45:43 +00002609#define tcg_gen_shl_tl tcg_gen_shl_i32
2610#define tcg_gen_shli_tl tcg_gen_shli_i32
2611#define tcg_gen_shr_tl tcg_gen_shr_i32
2612#define tcg_gen_shri_tl tcg_gen_shri_i32
2613#define tcg_gen_sar_tl tcg_gen_sar_i32
2614#define tcg_gen_sari_tl tcg_gen_sari_i32
blueswir10cf767d2008-03-02 18:20:59 +00002615#define tcg_gen_brcond_tl tcg_gen_brcond_i32
pbrookcb636692008-05-24 02:22:00 +00002616#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
Richard Hendersonbe210ac2010-01-07 10:13:31 -08002617#define tcg_gen_setcond_tl tcg_gen_setcond_i32
Aurelien Jarnoadd1e7e2010-02-08 12:06:05 +01002618#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
thsf730fd22008-05-04 08:14:08 +00002619#define tcg_gen_mul_tl tcg_gen_mul_i32
2620#define tcg_gen_muli_tl tcg_gen_muli_i32
aurel32ab364212009-03-29 01:19:22 +00002621#define tcg_gen_div_tl tcg_gen_div_i32
2622#define tcg_gen_rem_tl tcg_gen_rem_i32
aurel32864951a2009-03-29 14:08:54 +00002623#define tcg_gen_divu_tl tcg_gen_divu_i32
2624#define tcg_gen_remu_tl tcg_gen_remu_i32
blueswir1a768e4b2008-03-16 19:16:37 +00002625#define tcg_gen_discard_tl tcg_gen_discard_i32
blueswir1e4290732008-03-22 08:39:04 +00002626#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2627#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2628#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2629#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2630#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2631#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
bellard0b6ce4c2008-05-17 12:40:44 +00002632#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2633#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2634#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2635#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2636#define tcg_gen_ext32u_tl tcg_gen_mov_i32
2637#define tcg_gen_ext32s_tl tcg_gen_mov_i32
aurel32911d79b2009-03-13 09:35:19 +00002638#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2639#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
blueswir1945ca822008-09-21 18:32:28 +00002640#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
aurel32f24cb332008-10-21 11:28:59 +00002641#define tcg_gen_andc_tl tcg_gen_andc_i32
2642#define tcg_gen_eqv_tl tcg_gen_eqv_i32
2643#define tcg_gen_nand_tl tcg_gen_nand_i32
2644#define tcg_gen_nor_tl tcg_gen_nor_i32
2645#define tcg_gen_orc_tl tcg_gen_orc_i32
aurel3215824572008-11-03 07:08:36 +00002646#define tcg_gen_rotl_tl tcg_gen_rotl_i32
2647#define tcg_gen_rotli_tl tcg_gen_rotli_i32
2648#define tcg_gen_rotr_tl tcg_gen_rotr_i32
2649#define tcg_gen_rotri_tl tcg_gen_rotri_i32
Richard Hendersonb7767f02011-01-10 19:23:42 -08002650#define tcg_gen_deposit_tl tcg_gen_deposit_i32
blueswir1a98824a2008-03-13 20:46:42 +00002651#define tcg_const_tl tcg_const_i32
aurel32bdffd4a2008-10-21 11:30:45 +00002652#define tcg_const_local_tl tcg_const_local_i32
Richard Hendersonffc5ea02012-09-21 10:13:34 -07002653#define tcg_gen_movcond_tl tcg_gen_movcond_i32
blueswir1f8422f52008-02-24 07:45:43 +00002654#endif
pbrook6ddbc6e2008-03-31 03:46:33 +00002655
2656#if TCG_TARGET_REG_BITS == 32
Peter Maydellebecf362011-05-27 13:12:13 +01002657#define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \
2658 TCGV_PTR_TO_NAT(A), \
2659 TCGV_PTR_TO_NAT(B))
2660#define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), \
2661 TCGV_PTR_TO_NAT(A), (B))
2662#define tcg_gen_ext_i32_ptr(R, A) tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
pbrook6ddbc6e2008-03-31 03:46:33 +00002663#else /* TCG_TARGET_REG_BITS == 32 */
Peter Maydellebecf362011-05-27 13:12:13 +01002664#define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), \
2665 TCGV_PTR_TO_NAT(A), \
2666 TCGV_PTR_TO_NAT(B))
2667#define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), \
2668 TCGV_PTR_TO_NAT(A), (B))
2669#define tcg_gen_ext_i32_ptr(R, A) tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
pbrook6ddbc6e2008-03-31 03:46:33 +00002670#endif /* TCG_TARGET_REG_BITS != 32 */